rs6000: Add OPTION_MASK_POWER8 [PR101865]releases/gcc-12

The bug in PR101865 is the _ARCH_PWR8 predefine macro is conditional upon
TARGET_DIRECT_MOVE, which can be false for some -mcpu=power8 compiles if the
-mno-altivec or -mno-vsx options are used.  The solution here is to create
a new OPTION_MASK_POWER8 mask that is true for -mcpu=power8, regardless of
Altivec or VSX enablement.

Unfortunately, the only way to create an OPTION_MASK_* mask is to create
a new option, which we have done here, but marked it as WarnRemoved since
we do not want users using it.  For stage1, we will look into how we can
create ISA mask flags for use in the compiler without the need for explicit
options.

2024-04-12  Will Schmidt  <will_schmidt@linux.ibm.com>
	    Peter Bergner  <bergner@linux.ibm.com>

gcc/
	PR target/101865
	* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
	TARGET_POWER8.
	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use
	OPTION_MASK_POWER8.
	* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_POWER8.
	(ISA_2_7_MASKS_SERVER): Likewise.
	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Update
	comment.  Use OPTION_MASK_POWER8 and TARGET_POWER8.
	* config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
	* config/rs6000/rs6000.md (define_attr "isa"): Add p8.
	(define_attr "enabled"): Handle it.
	(define_insn "prefetch"): Use TARGET_POWER8.
	* config/rs6000/rs6000.opt (mpower8-internal): New.

gcc/testsuite/
	PR target/101865
	* gcc.target/powerpc/predefine-p7-novsx.c: New test.
	* gcc.target/powerpc/predefine-p8-noaltivec-novsx.c: New test.
	* gcc.target/powerpc/predefine-p8-noaltivec.c: New test.
	* gcc.target/powerpc/predefine-p8-novsx.c: New test.
	* gcc.target/powerpc/predefine-p8-pragma-vsx.c: New test.
	* gcc.target/powerpc/predefine-p9-novsx.c: New test.

(cherry picked from commit aa57af93ba22865be747f926e4e5f219e7f8758a)

13 files changed, 245 insertions, 9 deletions

diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 39a07a27c86..ff5830532d2 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -168,7 +168,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode)
     case ENB_P7_64:
       return TARGET_POPCNTD && TARGET_POWERPC64;
     case ENB_P8:
-      return TARGET_DIRECT_MOVE;
+      return TARGET_POWER8;
     case ENB_P8V:
       return TARGET_P8_VECTOR;
     case ENB_P9:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index cc848478a20..77d8de70e7a 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -432,7 +432,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((flags & OPTION_MASK_POPCNTD) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_MASK_P8_VECTOR) != 0)
+  if ((flags & OPTION_MASK_POWER8) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
   if ((flags & OPTION_MASK_MODULO) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 7dc8679ac9d..a052914b246 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,6 +47,7 @@
    fusion here, instead set it in rs6000.cc if we are tuning for a power8
    system.  */
 #define ISA_2_7_MASKS_SERVER	(ISA_2_6_MASKS_SERVER			\
+				 | OPTION_MASK_POWER8			\
 				 | OPTION_MASK_P8_VECTOR		\
 				 | OPTION_MASK_CRYPTO			\
 				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
@@ -137,6 +138,7 @@
 				 | OPTION_MASK_MODULO			\
 				 | OPTION_MASK_MULHW			\
 				 | OPTION_MASK_NO_UPDATE		\
+				 | OPTION_MASK_POWER8			\
 				 | OPTION_MASK_P8_FUSION		\
 				 | OPTION_MASK_P8_VECTOR		\
 				 | OPTION_MASK_P9_MINMAX		\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 34c533dba31..f5db6436dfa 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3826,11 +3826,10 @@ rs6000_option_override_internal (bool global_init_p)
 		 "-mmultiple");
     }
 
-  /* If little-endian, default to -mstrict-align on older processors.
-     Testing for direct_move matches power8 and later.  */
+  /* If little-endian, default to -mstrict-align on older processors.  */
   if (!BYTES_BIG_ENDIAN
       && !(processor_target_table[tune_index].target_enable
-	   & OPTION_MASK_P8_VECTOR))
+	   & OPTION_MASK_POWER8))
     rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
 
   /* Add some warnings for VSX.  */
@@ -3916,7 +3915,7 @@ rs6000_option_override_internal (bool global_init_p)
       else
 	rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
     }
-  else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
+  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
     rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_VSX)
     rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d3c8e7a8ecb..5588a4bae02 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -494,7 +494,7 @@ extern int rs6000_vector_align[];
    memory support.  */
 #define TARGET_SYNC_HI_QI	(TARGET_QUAD_MEMORY			\
 				 || TARGET_QUAD_MEMORY_ATOMIC		\
-				 || TARGET_DIRECT_MOVE)
+				 || TARGET_POWER8)
 
 #define TARGET_SYNC_TI		TARGET_QUAD_MEMORY_ATOMIC
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5cbf25dc76b..2f69c89c689 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -354,7 +354,7 @@
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
 ;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10"
   (const_string "any"))
 
 ;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -379,6 +379,10 @@
 	  (match_test "TARGET_VSX"))
      (const_int 1)
 
+     (and (eq_attr "isa" "p8")
+	  (match_test "TARGET_POWER8"))
+     (const_int 1)
+
      (and (eq_attr "isa" "p8v")
 	  (match_test "TARGET_P8_VECTOR"))
      (const_int 1)
@@ -14063,7 +14067,7 @@
      AIX does not support the dcbtstt and dcbtt extended mnemonics.
      The AIX assembler does not support the three operand form of dcbt
      and dcbtst on Power 7 (-mpwr7).  */
-  int inst_select = INTVAL (operands[2]) || !TARGET_DIRECT_MOVE;
+  int inst_select = INTVAL (operands[2]) || !TARGET_POWER8;
 
   if (REG_P (operands[0]))
     {
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index e8448eb91a0..46f7be748c7 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -474,6 +474,10 @@ Save the TOC in the prologue for indirect calls rather than inline.
 mvsx-timode
 Target RejectNegative Undocumented Ignore
 
+;; This option exists only to create its MASK.  It is not intended for users.
+mpower8-internal
+Target Undocumented Mask(POWER8) Var(rs6000_isa_flags) Warn(Do not use %<-mpower8-internal%>; use %<-mcpu=power8%> instead)
+
 mpower8-fusion
 Target Mask(P8_FUSION) Var(rs6000_isa_flags)
 Fuse certain integer operations together for better performance on power8.
diff --git a/gcc/testsuite/gcc.target/powerpc/predefine-p7-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefine-p7-novsx.c
new file mode 100644
index 00000000000..bebe62d8f48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/predefine-p7-novsx.c
@@ -0,0 +1,22 @@
+/* PR target/101865 */
+/* { dg-do preprocess } */
+/* { dg-options "-mdejagnu-cpu=power7 -mno-vsx" } */
+
+/* Verify we correctly set the correct set of predefined macros
+   for the given set of options.  */
+
+#ifndef _ARCH_PWR7
+#error "_ARCH_PWR7 should be defined for this test"
+#endif
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined for this test"
+#endif
+
+#ifdef _ARCH_PWR8
+#error "_ARCH_PWR8 should not be defined for this test"
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined for this test"
+#endif
diff --git a/gcc/testsuite/gcc.target/powerpc/predefine-p8-noaltivec-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefine-p8-noaltivec-novsx.c
new file mode 100644
index 00000000000..9d118b44fe8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/predefine-p8-noaltivec-novsx.c
@@ -0,0 +1,26 @@
+/* PR target/101865 */
+/* { dg-do preprocess } */
+/* { dg-options "-mdejagnu-cpu=power8 -mno-altivec -mno-vsx" } */
+
+/* Verify _ARCH_PWR8 is defined for -mcpu=power8 and after disabling
+   both altivec and vsx.  */
+
+#ifndef _ARCH_PWR7
+#error "_ARCH_PWR7 should be defined for this test"
+#endif
+
+#ifndef _ARCH_PWR8
+#error "_ARCH_PWR8 should be defined for this test"
+#endif
+
+#ifdef _ARCH_PWR9
+#error "_ARCH_PWR9 should not be defined for this test"
+#endif
+
+#ifdef __ALTIVEC__
+#error "__ALTIVEC__ should not be defined for this test"
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined for this test"
+#endif
diff --git a/gcc/testsuite/gcc.target/powerpc/predefine-p8-noaltivec.c b/gcc/testsuite/gcc.target/powerpc/predefine-p8-noaltivec.c
new file mode 100644
index 00000000000..5d2a7b852b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/predefine-p8-noaltivec.c
@@ -0,0 +1,26 @@
+/* PR target/101865 */
+/* { dg-do preprocess } */
+/* { dg-options "-mdejagnu-cpu=power8 -mno-altivec -w" } */
+
+/* Verify _ARCH_PWR8 is defined for -mcpu=power8 and after disabling altivec.
+   The -w option is used to silence the -mno-altivec disables -mvsx warning.  */
+
+#ifndef _ARCH_PWR7
+#error "_ARCH_PWR7 should be defined for this test"
+#endif
+
+#ifndef _ARCH_PWR8
+#error "_ARCH_PWR8 should be defined for this test"
+#endif
+
+#ifdef _ARCH_PWR9
+#error "_ARCH_PWR9 should not be defined for this test"
+#endif
+
+#ifdef __ALTIVEC__
+#error "__ALTIVEC__ should not be defined for this test"
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined for this test"
+#endif
diff --git a/gcc/testsuite/gcc.target/powerpc/predefine-p8-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefine-p8-novsx.c
new file mode 100644
index 00000000000..5eeadf421b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/predefine-p8-novsx.c
@@ -0,0 +1,26 @@
+/* PR target/101865 */
+/* { dg-do preprocess } */
+/* { dg-options "-mdejagnu-cpu=power8 -mno-vsx" } */
+
+/* Verify _ARCH_PWR8 is defined for -mcpu=power8 and after disabling vsx.
+   This also confirms __ALTIVEC__ remains set when VSX is disabled.  */
+
+#ifndef _ARCH_PWR7
+#error "_ARCH_PWR7 should be defined for this test"
+#endif
+
+#ifndef _ARCH_PWR8
+#error "_ARCH_PWR8 should be defined for this test"
+#endif
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined for this test"
+#endif
+
+#ifdef _ARCH_PWR9
+#error "_ARCH_PWR9 should not be defined for this test"
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined for this test"
+#endif
diff --git a/gcc/testsuite/gcc.target/powerpc/predefine-p8-pragma-vsx.c b/gcc/testsuite/gcc.target/powerpc/predefine-p8-pragma-vsx.c
new file mode 100644
index 00000000000..aed3068f117
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/predefine-p8-pragma-vsx.c
@@ -0,0 +1,101 @@
+/* PR target/101865 */
+/* { dg-do run } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */
+
+/* Verify we correctly set our predefined macros in the face of #pragma usage.  */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+volatile int power8_set;
+volatile int vsx_set;
+
+void
+test_default (void)
+{
+#ifdef _ARCH_PWR8
+  power8_set=1;
+#else
+  power8_set=0;
+#endif
+#ifdef __VSX__
+  vsx_set=1;
+#else
+  vsx_set=0;
+#endif
+}
+
+#pragma GCC target "no-vsx"
+void
+test_no_vsx (void)
+{
+#ifdef _ARCH_PWR8
+  power8_set=1;
+#else
+  power8_set=0;
+#endif
+#ifdef __VSX__
+  vsx_set=1;
+#else
+  vsx_set=0;
+#endif
+}
+
+#pragma GCC reset_options
+void
+test_reset_options (void)
+{
+#ifdef _ARCH_PWR8
+  power8_set=1;
+#else
+  power8_set=0;
+#endif
+#ifdef __VSX__
+  vsx_set=1;
+#else
+  vsx_set=0;
+#endif
+}
+
+int
+main (void)
+{
+  test_default ();
+  if (!power8_set)
+    {
+      printf ("_ARCH_PWR8 is not set.\n");
+      abort ();
+    }
+  if (!vsx_set)
+    {
+      printf ("__VSX__ is not set.\n");
+      abort ();
+    }
+
+  test_no_vsx ();
+  if (!power8_set)
+    {
+      printf ("_ARCH_PWR8 is not set.\n");
+      abort ();
+    }
+  if (vsx_set)
+    {
+      printf ("__VSX__ is unexpectedly set.\n");
+      abort ();
+    }
+
+  test_reset_options ();
+  if (!power8_set)
+    {
+      printf ("_ARCH_PWR8 is not set.\n");
+      abort ();
+    }
+  if (!vsx_set)
+    {
+      printf ("__VSX__ is not set.\n");
+      abort ();
+    }
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/predefine-p9-novsx.c b/gcc/testsuite/gcc.target/powerpc/predefine-p9-novsx.c
new file mode 100644
index 00000000000..d8f12275fd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/predefine-p9-novsx.c
@@ -0,0 +1,26 @@
+/* PR target/101865 */
+/* { dg-do preprocess } */
+/* { dg-options "-mdejagnu-cpu=power9 -mno-vsx" } */
+
+/* Verify _ARCH_PWR8 is defined for -mcpu=power9 and after disabling vsx.
+   This also confirms __ALTIVEC__ remains set when VSX is disabled.  */
+
+#ifndef _ARCH_PWR7
+#error "_ARCH_PWR7 should be defined for this test"
+#endif
+
+#ifndef _ARCH_PWR8
+#error "_ARCH_PWR8 should be defined for this test"
+#endif
+
+#ifndef _ARCH_PWR9
+#error "_ARCH_PWR9 should be defined for this test"
+#endif
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined for this test"
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined for this test"
+#endif