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authorAlexey Volkov <alexey.v.volkov@intel.com>2014-03-13 14:39:18 +0400
committerAlexey Volkov <alexey.v.volkov@intel.com>2014-03-13 16:22:42 +0400
commit3831cbe99734261bb779e4e8c0e33c94958965df (patch)
tree406782dbb6c7b829e2aa6f028ff5a3fa8e37b863
parent791b3deb936c7361ad61dc035256cd01fe3f4138 (diff)
downloadllvm-3831cbe99734261bb779e4e8c0e33c94958965df.tar.gz
Backport llvm svn@r203218
Enable FeatureFastUAMem for Silvermont processor Differential Revision: http://llvm-reviews.chandlerc.com/D2982 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203218 91177308-0d34-0410-b5e6-96231b3b80d8 Change-Id: Ie5f999dde9728adf33df352ebe517ea737b5727a Signed-off-by: Alexey Volkov <alexey.v.volkov@intel.com>
-rw-r--r--lib/Target/X86/X86.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index 65c5552de2a..4057eff3402 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -221,7 +221,7 @@ def : ProcessorModel<"slm", SLMModel, [ProcIntelSLM,
FeaturePCLMUL, FeatureAES,
FeatureCallRegIndirect,
FeaturePRFCHW,
- FeatureSlowBTMem]>;
+ FeatureSlowBTMem, FeatureFastUAMem]>;
// "Arrandale" along with corei3 and corei5
def : ProcessorModel<"corei7", SandyBridgeModel,
[FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,