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| author | Robert Khasanov <rob.khasanov@gmail.com> | 2014-12-18 12:28:22 +0000 |
|---|---|---|
| committer | Robert Khasanov <rob.khasanov@gmail.com> | 2014-12-18 12:28:22 +0000 |
| commit | d25d7bb3728ad775cf6ad3e91101348586deba12 (patch) | |
| tree | 606e8a59024d5df24482317212181a269ad3989f /lib/Target/X86/X86ISelLowering.cpp | |
| parent | e22e2b8798bb55a79be02848767587a765a153ff (diff) | |
| download | llvm-d25d7bb3728ad775cf6ad3e91101348586deba12.tar.gz | |
[AVX512] Enable FP arithmetic lowering for AVX512VL subsets.
Added RegOp2MemOpTable4 to transform 4th operand from register to memory in merge-masked versions of instructions.
Added lowering tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224516 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 6a6b20e81d9..1a0b62970cf 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -6213,7 +6213,8 @@ static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget, if (!IsLoad) return SDValue(); - if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) + if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) || + (Subtarget->hasVLX() && ScalarSize == 64)) return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); // The integer check is needed for the 64-bit into 128-bit so it doesn't match |