diff options
Diffstat (limited to 'plat/arm')
77 files changed, 2051 insertions, 914 deletions
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk index 084532ce2..a14a0d8c0 100644 --- a/plat/arm/board/arm_fpga/platform.mk +++ b/plat/arm/board/arm_fpga/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2021, Arm Limited. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -71,9 +71,9 @@ else lib/cpus/aarch64/cortex_a65.S \ lib/cpus/aarch64/cortex_a65ae.S \ lib/cpus/aarch64/cortex_a510.S \ - lib/cpus/aarch64/cortex_a710.S \ - lib/cpus/aarch64/cortex_makalu.S \ - lib/cpus/aarch64/cortex_makalu_elp_arm.S \ + lib/cpus/aarch64/cortex_a710.S \ + lib/cpus/aarch64/cortex_a715.S \ + lib/cpus/aarch64/cortex_x3.S \ lib/cpus/aarch64/cortex_a78c.S # AArch64/AArch32 cores diff --git a/plat/arm/board/common/board_arm_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c index 66cc3e949..714c444e7 100644 --- a/plat/arm/board/common/board_arm_trusted_boot.c +++ b/plat/arm/board/common/board_arm_trusted_boot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,18 +13,20 @@ #include <drivers/delay_timer.h> #include <lib/cassert.h> #include <lib/fconf/fconf.h> -#include <plat/arm/common/plat_arm.h> -#include <plat/arm/common/fconf_nv_cntr_getter.h> #include <plat/common/common_def.h> #include <plat/common/platform.h> -#include <platform_def.h> - -#if defined(ARM_COT_tbbr) -#include <tools_share/tbbr_oid.h> +#if defined(ARM_COT_cca) +#include <tools_share/cca_oid.h> #elif defined(ARM_COT_dualroot) #include <tools_share/dualroot_oid.h> +#elif defined(ARM_COT_tbbr) +#include <tools_share/tbbr_oid.h> #endif +#include <plat/arm/common/fconf_nv_cntr_getter.h> +#include <plat/arm/common/plat_arm.h> +#include <platform_def.h> + #if !ARM_CRYPTOCELL_INTEG #if !ARM_ROTPK_LOCATION_ID #error "ARM_ROTPK_LOCATION_ID not defined" @@ -181,6 +183,40 @@ int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, return 1; } } + +#elif defined(ARM_COT_cca) + +int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + /* + * Return the right root of trust key hash based on the cookie value: + * - NULL means the primary ROTPK. + * - Otherwise, interpret cookie as the OID of the certificate + * extension containing the key. + */ + if (cookie == NULL) { + return get_rotpk_info(key_ptr, key_len, flags); + } else if (strcmp(cookie, PROT_PK_OID) == 0) { + extern unsigned char arm_protpk_hash[]; + extern unsigned char arm_protpk_hash_end[]; + *key_ptr = arm_protpk_hash; + *key_len = arm_protpk_hash_end - arm_protpk_hash; + *flags = ROTPK_IS_HASH; + return 0; + } else if (strcmp(cookie, SWD_ROT_PK_OID) == 0) { + extern unsigned char arm_swd_rotpk_hash[]; + extern unsigned char arm_swd_rotpk_hash_end[]; + *key_ptr = arm_swd_rotpk_hash; + *key_len = arm_swd_rotpk_hash_end - arm_swd_rotpk_hash; + *flags = ROTPK_IS_HASH; + return 0; + } else { + /* Invalid key ID. */ + return 1; + } +} + #endif /* diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk index 5cdf1bf39..1d0eb136e 100644 --- a/plat/arm/board/common/board_common.mk +++ b/plat/arm/board/common/board_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -38,6 +38,10 @@ endif $(eval $(call add_define,ARM_ROTPK_LOCATION_ID)) +ifeq (${ENABLE_RME}, 1) +COT := cca +endif + # Force generation of the new hash if ROT_KEY is specified ifdef ROT_KEY HASH_PREREQUISITES = $(ROT_KEY) FORCE @@ -49,8 +53,8 @@ $(ARM_ROTPK_HASH) : $(HASH_PREREQUISITES) ifndef ROT_KEY $(error Cannot generate hash: no ROT_KEY defined) endif - openssl ${CRYPTO_ALG} -in $< -pubout -outform DER | openssl dgst \ - -sha256 -binary > $@ + ${OPENSSL_BIN_PATH}/openssl ${CRYPTO_ALG} -in $< -pubout -outform DER | \ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ # Certificate NV-Counters. Use values corresponding to tied off values in # ARM development platforms @@ -88,4 +92,29 @@ $(BUILD_PLAT)/bl1/arm_dev_protpk.o: $(ARM_PROTPK_HASH) $(BUILD_PLAT)/bl2/arm_dev_protpk.o: $(ARM_PROTPK_HASH) endif +ifeq (${COT},cca) +# Platform and Secure World Root of Trust key files. +ARM_PROT_KEY := plat/arm/board/common/protpk/arm_protprivk_rsa.pem +ARM_PROTPK_HASH := plat/arm/board/common/protpk/arm_protpk_rsa_sha256.bin +ARM_SWD_ROT_KEY := plat/arm/board/common/swd_rotpk/arm_swd_rotprivk_rsa.pem +ARM_SWD_ROTPK_HASH := plat/arm/board/common/swd_rotpk/arm_swd_rotpk_rsa_sha256.bin + +# Provide the private keys to cert_create tool. It needs them to sign the images. +PROT_KEY := ${ARM_PROT_KEY} +SWD_ROT_KEY := ${ARM_SWD_ROT_KEY} + +$(eval $(call add_define_val,ARM_PROTPK_HASH,'"$(ARM_PROTPK_HASH)"')) +$(eval $(call add_define_val,ARM_SWD_ROTPK_HASH,'"$(ARM_SWD_ROTPK_HASH)"')) + +BL1_SOURCES += plat/arm/board/common/protpk/arm_dev_protpk.S \ + plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S +BL2_SOURCES += plat/arm/board/common/protpk/arm_dev_protpk.S \ + plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S + +$(BUILD_PLAT)/bl1/arm_dev_protpk.o: $(ARM_PROTPK_HASH) +$(BUILD_PLAT)/bl1/arm_dev_swd_rotpk.o: $(ARM_SWD_ROTPK_HASH) +$(BUILD_PLAT)/bl2/arm_dev_protpk.o: $(ARM_PROTPK_HASH) +$(BUILD_PLAT)/bl2/arm_dev_swd_rotpk.o: $(ARM_SWD_ROTPK_HASH) +endif + endif diff --git a/plat/arm/board/common/swd_rotpk/README b/plat/arm/board/common/swd_rotpk/README new file mode 100644 index 000000000..b628a5fd8 --- /dev/null +++ b/plat/arm/board/common/swd_rotpk/README @@ -0,0 +1,14 @@ +This directory contains some development keys to be used as the secure world +root-of-trust key used in the CCA chain of trust. + +* swd_rotprivk_rsa.pem is a 2K RSA private key in PEM format. It has been + generated using the openssl command line tool: + + openssl genrsa 2048 > arm_swd_rotprivk_rsa.pem + +* swd_rotpk_rsa_sha256.bin is the SHA-256 hash of the DER-encoded public key + associated with the above private key. It has been generated using the openssl + command line tool: + + openssl rsa -in arm_swd_rotprivk_rsa.pem -pubout -outform DER | \ + openssl dgst -sha256 -binary > arm_swd_rotpk_rsa_sha256.bin diff --git a/plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S b/plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S new file mode 100644 index 000000000..ae4f9d271 --- /dev/null +++ b/plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global arm_swd_rotpk_hash + .global arm_swd_rotpk_hash_end + + .section .rodata.arm_swd_rotpk_hash, "a" + +arm_swd_rotpk_hash: + /* DER header. */ + .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 + .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 + /* Key hash. */ + .incbin ARM_SWD_ROTPK_HASH +arm_swd_rotpk_hash_end: diff --git a/plat/arm/board/common/swd_rotpk/arm_swd_rotpk_rsa_sha256.bin b/plat/arm/board/common/swd_rotpk/arm_swd_rotpk_rsa_sha256.bin new file mode 100644 index 000000000..b2f3e60a4 --- /dev/null +++ b/plat/arm/board/common/swd_rotpk/arm_swd_rotpk_rsa_sha256.bin @@ -0,0 +1 @@ +0 (0wIӁ gk
\ No newline at end of file diff --git a/plat/arm/board/common/swd_rotpk/arm_swd_rotprivk_rsa.pem b/plat/arm/board/common/swd_rotpk/arm_swd_rotprivk_rsa.pem new file mode 100644 index 000000000..0de655d4a --- /dev/null +++ b/plat/arm/board/common/swd_rotpk/arm_swd_rotprivk_rsa.pem @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEpQIBAAKCAQEA8igTd5QdZd181kz9vINr7Au34Rr/pQ1jpesfLlc1ZXCNAI9y +/rhQlpw00y8rwOfgZsf18gPwGWWGhDJMsXI7OPem7BEUr8xKumuJuCiOdJh1STcR +/JoFvz8wJPyycj/DOERRGsz+RvFBs6cLjSZHNQdzKDW+DE5vVJpmNWBVkoK7MCRD +Wh/PMZVSoq9PeJOzayYcsipKvifT1+Wo9y2MG5zTDxi28rLr/FBm0CpTepBcRe8L +pmgS7XJKhCQYxdDSzxi/0t/qXAwWuME4jv2HbNxsUZjahiBYpA0BafXanSuxVHly +qpD0BmKAu7PpgKrEnUcPuHpZ2W+a05lNk6zjewIDAQABAoIBAG3twYCcTYgrtvs1 +8k38vyZl33CiKAGOhXkRtpL75fKJ2IizljmKBJOKj/R6ynsFCHrANadLIFj3HMyw +ZN59A+OFkVJDIsf3jsj3/ooKZzkI6N120YSBizBZiAqSaJOy3HWTldn7y0b7SJ88 +quLFyLeLDTzowMCnbqTSfqmmdNJQAn+Q+7RX5sZGyBQUF2pRAA67cOYzc3a5MZ5E +zBOs2u8VboC3ulEq876XWQbcXpRh/ap3eplQ1kAdyy64IPp2WbxqyXW0IQAQqaqh +6oj19ME6mVD5wtELcYscJCDb7pA6WJtPp6nz/og2ifCJE/75T5RJ6fc6eBFMcofQ +STIClGECgYEA/ZC0GX1HTKEKK3c1TiS3Zy0DS5ZoN5KFK7Sp1ZAjPE63iAr1a3z9 +Kepb+L8TBSw50tVD74MF5ChEid/ghF5BrVC3/YJkiiNpM1F51SMLGFeiDPRzJcx5 +KJkSflX7Q36BAXqj85Yz5AjgTPKcBqQRVZ6pNZN1HY99MloMg22WPRECgYEA9HtU +FXmnTplXaNnihdq+vL5Z4/KDM+1f1E95y1PB8vkLI+o1szVNFP+BYz+w42lKtHW+ +c+z40AhFBGZQ0QCx83NOyObCReFjEbP8Nz71BsHe6GyMk9tSPIpzu9XB49Rs+9EO +DAvFM5y2j5bH+lXE0pSyS3oBf51L9ZCPhp/vB8sCgYEAydwB1Gzsbu+hFfs/v2bx +brzh67HgY6VMSP/5WF/3/RG5gB8hQ6HsNQsyjrMmZC7SFarb+3e2H+2CqrREm3wi +EuS4pKPCgEoyfL03HVtZgNZ61o9gf83pAk3h8Bto/VFfSBsnHEsOIlKCph9Z4NuK +RTwa/uDWEmNhyszvO03pldECgYEA2zB7GWnhc1mNgabfLY0JtuSeaPzzXqnyYcID +eyUT3QglUcTY8lvWSP4ufdILgEfVP2fVIdAS30iawDAPQuLxqEf4Gayx/r7s+GE6 +vjlGqxFEDXPMsX9QApFK49voop/AOiCbDHe9DOHy11ei4TDmbrn8BClVkJlxEa/S +ziszvfMCgYEA2V0zXziooI0toaOJEWZlAYhEONS5SG2z28HMLNgbdMcueGNhseaR +NBGgPcu3EQhbL/hD0tBs09u6gjy1WD1i0HYnm1K1YQ1flzfbjUa3BqZETMbNhugd +CM9yv0GEL/udZyOmO401aYl+QGXZX/WwlLQOe7WqQXOXJvW73oSqy7M= +-----END RSA PRIVATE KEY----- diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts index 21a6073a3..4543671a9 100644 --- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts +++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -82,4 +82,8 @@ device_type = "memory"; reg = <0x0 0x6000000 0x2000000>; /* Trusted DRAM */ }; + +#if MEASURED_BOOT +#include "event_log.dtsi" +#endif }; diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts index cf4ef2d02..6fd334d8e 100644 --- a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts +++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,6 +47,9 @@ soc_fw_cfg_uuid = "9979814b-0376-fb46-8c8e-8d267f7859e0"; tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021"; nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9"; + cca_cert_uuid = "36d83d85-761d-4daf-96f1-cd99d6569b00"; + core_swd_cert_uuid = "52222d31-820f-494d-8bbc-ea6825d3c35a"; + plat_cert_uuid = "d43cd902-5b9f-412e-8ac6-92b6d18be60d"; t_key_cert_uuid = "827ee890-f860-e411-a1b4-777a21b4f94c"; scp_fw_key_uuid = "024221a1-f860-e411-8d9b-f33c0e15a014"; soc_fw_key_uuid = "8ab8becc-f960-e411-9ad0-eb4822d8dcf8"; diff --git a/plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts b/plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts new file mode 100644 index 000000000..1587c72b0 --- /dev/null +++ b/plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/dts-v1/; + +#define AFF 00 + +#include "fvp-defs.dtsi" +#undef POST +#define POST \ + }; + +#define S_EL0 (0x1) +#define S_EL1 (0x2) + +/* For consumption by EL3 SPMC. */ +/ { + compatible = "arm,ffa-manifest-1.0"; + #address-cells = <2>; + #size-cells = <1>; + + ffa-version = <0x00010001>; /* 31:16 - Major, 15:0 - Minor */ + id = <0x8001>; + uuid = <0x6b43b460 0x74a24b78 0xade24502 0x40682886>; + messaging-method = <0x3>; /* Direct Messaging Only */ + exception-level = <S_EL1>; + execution-state = <0>; + execution-ctx-count = <8>; + gp-register-num = <0>; + /* Subscribe to CPU_OFF, CPU_SUSPEND and CPU_SUSPEND_RESUME PM Msgs */ + power-management-messages = <0x7>; +}; diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c index fd15b70d3..e938e2419 100644 --- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c +++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c @@ -6,6 +6,7 @@ #include <stdint.h> +#include <common/tbbr/tbbr_img_def.h> #include <drivers/measured_boot/event_log/event_log.h> #include <drivers/measured_boot/rss/rss_measured_boot.h> #include <tools_share/tbbr_oid.h> @@ -31,6 +32,17 @@ const event_log_metadata_t fvp_event_log_metadata[] = { { TOS_FW_CONFIG_ID, EVLOG_TOS_FW_CONFIG_STRING, PCR_0 }, { RMM_IMAGE_ID, EVLOG_RMM_STRING, PCR_0}, +#if defined(SPD_spmd) + { SP_PKG1_ID, EVLOG_SP1_STRING, PCR_0 }, + { SP_PKG2_ID, EVLOG_SP2_STRING, PCR_0 }, + { SP_PKG3_ID, EVLOG_SP3_STRING, PCR_0 }, + { SP_PKG4_ID, EVLOG_SP4_STRING, PCR_0 }, + { SP_PKG5_ID, EVLOG_SP5_STRING, PCR_0 }, + { SP_PKG6_ID, EVLOG_SP6_STRING, PCR_0 }, + { SP_PKG7_ID, EVLOG_SP7_STRING, PCR_0 }, + { SP_PKG8_ID, EVLOG_SP8_STRING, PCR_0 }, +#endif + { CRITICAL_DATA_ID, EVLOG_CRITICAL_DATA_STRING, PCR_1 }, { EVLOG_INVALID_ID, NULL, (unsigned int)(-1) } /* Terminator */ diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index a7028f6cf..f8463f14c 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -17,6 +17,9 @@ #include <lib/xlat_tables/xlat_tables_compat.h> #include <platform_def.h> #include <services/arm_arch_svc.h> +#if ENABLE_RME +#include <services/rmm_core_manifest.h> +#endif #if SPM_MM #include <services/spm_mm_partition.h> #endif @@ -169,6 +172,7 @@ const mmap_region_t plat_arm_mmap[] = { #endif #if ENABLE_RME ARM_MAP_GPT_L1_DRAM, + ARM_MAP_EL3_RMM_SHARED_MEM, #endif {0} }; @@ -512,3 +516,29 @@ int32_t plat_get_soc_revision(void) return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); } + +#if ENABLE_RME +/* + * Get a pointer to the RMM-EL3 Shared buffer and return it + * through the pointer passed as parameter. + * + * This function returns the size of the shared buffer. + */ +size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared) +{ + *shared = (uintptr_t)RMM_SHARED_BASE; + + return (size_t)RMM_SHARED_SIZE; +} + +int plat_rmmd_load_manifest(rmm_manifest_t *manifest) +{ + assert(manifest != NULL); + + manifest->version = RMMD_MANIFEST_VERSION; + manifest->plat_data = (uintptr_t)NULL; + + return 0; +} + +#endif diff --git a/plat/arm/board/fvp/fvp_drtm_addr.c b/plat/arm/board/fvp/fvp_drtm_addr.c new file mode 100644 index 000000000..eeaa3425b --- /dev/null +++ b/plat/arm/board/fvp/fvp_drtm_addr.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <stdint.h> + +#include <plat/common/platform.h> +#include <platform_def.h> + +/******************************************************************************* + * Check passed region is within Non-Secure region of DRAM + ******************************************************************************/ +int plat_drtm_validate_ns_region(uintptr_t region_start, + size_t region_size) +{ + uintptr_t region_end = region_start + region_size - 1; + + if (region_start >= region_end) { + return -1; + } else if ((region_start >= ARM_NS_DRAM1_BASE) && + (region_start < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE)) && + (region_end >= ARM_NS_DRAM1_BASE) && + (region_end < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { + return 0; + } else if ((region_start >= ARM_DRAM2_BASE) && + (region_start < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE)) && + (region_end >= ARM_DRAM2_BASE) && + (region_end < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { + return 0; + } + + return -1; +} diff --git a/plat/arm/board/fvp/fvp_drtm_dma_prot.c b/plat/arm/board/fvp/fvp_drtm_dma_prot.c new file mode 100644 index 000000000..38ff7fe38 --- /dev/null +++ b/plat/arm/board/fvp/fvp_drtm_dma_prot.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <stddef.h> + +#include <drivers/arm/smmu_v3.h> +#include <lib/utils_def.h> +#include <plat/arm/common/arm_config.h> +#include <plat/common/platform.h> + +#include <platform_def.h> + +/** + * Array mentioning number of SMMUs supported by FVP + */ +static const uintptr_t fvp_smmus[] = { + PLAT_FVP_SMMUV3_BASE, +}; + +bool plat_has_non_host_platforms(void) +{ + /* FVP base platforms typically have GPU, as per FVP Reference guide */ + return true; +} + +bool plat_has_unmanaged_dma_peripherals(void) +{ + /* + * FVP Reference guide does not show devices that are described as + * DMA-capable but not managed by an SMMU in the FVP documentation. + * However, the SMMU seems to have only been introduced in the RevC + * revision. + */ + return (arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) == 0; +} + +unsigned int plat_get_total_smmus(void) +{ + if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) { + return ARRAY_SIZE(fvp_smmus); + } else { + return 0; + } +} + +void plat_enumerate_smmus(const uintptr_t **smmus_out, + size_t *smmu_count_out) +{ + if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) { + *smmus_out = fvp_smmus; + *smmu_count_out = ARRAY_SIZE(fvp_smmus); + } else { + *smmus_out = NULL; + *smmu_count_out = 0; + } +} + +/* DRTM DMA Protection Features */ +static const plat_drtm_dma_prot_features_t dma_prot_features = { + .max_num_mem_prot_regions = 0, /* No protection regions are present */ + .dma_protection_support = 0x1 /* Complete DMA protection only */ +}; + +const plat_drtm_dma_prot_features_t *plat_drtm_get_dma_prot_features(void) +{ + return &dma_prot_features; +} + +uint64_t plat_drtm_dma_prot_get_max_table_bytes(void) +{ + return 0U; +} diff --git a/plat/arm/board/fvp/fvp_drtm_err.c b/plat/arm/board/fvp/fvp_drtm_err.c new file mode 100644 index 000000000..95259fa82 --- /dev/null +++ b/plat/arm/board/fvp/fvp_drtm_err.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <plat/common/platform.h> + +int plat_set_drtm_error(uint64_t error_code) +{ + /* TODO: Set DRTM error in NV-storage */ + return 0; +} + +int plat_get_drtm_error(uint64_t *error_code) +{ + /* TODO: Get DRTM error from NV-storage */ + *error_code = 0; + return 0; +} diff --git a/plat/arm/board/fvp/fvp_drtm_measurement.c b/plat/arm/board/fvp/fvp_drtm_measurement.c new file mode 100644 index 000000000..4fbedd8bc --- /dev/null +++ b/plat/arm/board/fvp/fvp_drtm_measurement.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#include <drivers/measured_boot/event_log/event_log.h> +#include <plat/common/platform.h> + +#include <platform_def.h> + +/* DRTM TPM Features */ +static const plat_drtm_tpm_features_t tpm_features = { + /* No TPM-based hashing supported. */ + .tpm_based_hash_support = false, + + /* Set to decided algorithm by Event Log driver */ + .firmware_hash_algorithm = TPM_ALG_ID + +}; + +const plat_drtm_tpm_features_t *plat_drtm_get_tpm_features(void) +{ + return &tpm_features; +} diff --git a/plat/arm/board/fvp/fvp_drtm_stub.c b/plat/arm/board/fvp/fvp_drtm_stub.c new file mode 100644 index 000000000..e2bc5169a --- /dev/null +++ b/plat/arm/board/fvp/fvp_drtm_stub.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#include <stdint.h> + +#include <services/drtm_svc.h> + +/* + * This file contains DRTM platform functions which don't really do anything on + * FVP but are needed for DRTM to function. + */ + +uint64_t plat_drtm_get_min_size_normal_world_dce(void) +{ + return 0ULL; +} + +uint64_t plat_drtm_get_imp_def_dlme_region_size(void) +{ + return 0ULL; +} + +uint64_t plat_drtm_get_tcb_hash_features(void) +{ + return 0ULL; +} + +uint64_t plat_drtm_get_tcb_hash_table_size(void) +{ + return 0ULL; +} diff --git a/plat/arm/board/fvp/fvp_err.c b/plat/arm/board/fvp/fvp_err.c index 1f9f0dd14..244659ab7 100644 --- a/plat/arm/board/fvp/fvp_err.c +++ b/plat/arm/board/fvp/fvp_err.c @@ -29,3 +29,15 @@ __dead2 void plat_arm_error_handler(int err) for (;;) wfi(); } + +void __dead2 plat_arm_system_reset(void) +{ + /* Write the System Configuration Control Register */ + mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, + V2M_CFGCTRL_START | + V2M_CFGCTRL_RW | + V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); + wfi(); + ERROR("FVP System Reset: operation not handled.\n"); + panic(); +} diff --git a/plat/arm/board/fvp/fvp_gicv3.c b/plat/arm/board/fvp/fvp_gicv3.c index 8f3e7b702..e780f21f2 100644 --- a/plat/arm/board/fvp/fvp_gicv3.c +++ b/plat/arm/board/fvp/fvp_gicv3.c @@ -7,6 +7,7 @@ #include <assert.h> #include <platform_def.h> +#include <common/debug.h> #include <common/interrupt_props.h> #include <drivers/arm/gicv3.h> #include <fconf_hw_config_getter.h> diff --git a/plat/arm/board/fvp/fvp_plat_attest_token.c b/plat/arm/board/fvp/fvp_plat_attest_token.c index 5463f3374..4dd37a4eb 100644 --- a/plat/arm/board/fvp/fvp_plat_attest_token.c +++ b/plat/arm/board/fvp/fvp_plat_attest_token.c @@ -10,298 +10,92 @@ /* Using hardcoded token values for AEM FVP */ static uint8_t platform_token[] = { - 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0x98, 0x18, 0xB5, 0x16, 0x9C, 0x21, 0x78, 0xB7, - 0x92, 0xF8, 0x26, 0x82, 0x76, 0x2F, 0x26, 0x45, - 0x21, 0x6D, 0x0C, 0x21, 0x06, 0xF4, 0xB5, 0xE3, - 0xA8, 0x07, 0xD1, 0xD6, 0x8C, 0x73, 0xA5, 0xC8, - 0x16, 0xD8, 0x30, 0x68, 0xC0, 0xA4, 0x77, 0xE2, - 0x1E, 0xD2, 0x17, 0x86, 0xC3, 0x68, 0x82, 0xDD, - 0x21, 0x1B, 0xA3, 0xE2, 0xC7, 0xF7, 0x06, 0x33, - 0xB0, 0x3A + 0xD2, 0x84, 0x40, 0xA0, 0x59, 0x02, 0x46, 0xA9, + 0x19, 0x01, 0x09, 0x78, 0x1C, 0x68, 0x74, 0x74, + 0x70, 0x3A, 0x2F, 0x2F, 0x61, 0x72, 0x6D, 0x2E, + 0x63, 0x6F, 0x6D, 0x2F, 0x43, 0x43, 0x41, 0x2D, + 0x53, 0x53, 0x44, 0x2F, 0x31, 0x2E, 0x30, 0x2E, + 0x30, 0x0A, 0x58, 0x20, 0x07, 0x06, 0x05, 0x04, + 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, + 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, + 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, + 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, 0x5C, 0x58, + 0x40, 0x7F, 0x45, 0x4C, 0x46, 0x02, 0x01, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x3E, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x50, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xA0, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x38, + 0x00, 0x09, 0x00, 0x40, 0x00, 0x1C, 0x00, 0x1B, + 0x00, 0x19, 0x01, 0x00, 0x58, 0x21, 0x01, 0x07, + 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, + 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, + 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, + 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, + 0x09, 0x61, 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, + 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, + 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, + 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, + 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, 0x5B, + 0x19, 0x30, 0x03, 0x19, 0x09, 0x62, 0x67, 0x73, + 0x68, 0x61, 0x2D, 0x32, 0x35, 0x36, 0x19, 0x09, + 0x5F, 0x84, 0xA5, 0x01, 0x62, 0x42, 0x4C, 0x05, + 0x58, 0x20, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, + 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, + 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, + 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, + 0x19, 0x18, 0x04, 0x65, 0x33, 0x2E, 0x34, 0x2E, + 0x32, 0x02, 0x58, 0x20, 0x07, 0x06, 0x05, 0x04, + 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, + 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, + 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, + 0x1B, 0x1A, 0x19, 0x18, 0x06, 0x67, 0x73, 0x68, + 0x61, 0x2D, 0x32, 0x35, 0x36, 0xA4, 0x01, 0x62, + 0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06, 0x05, + 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, + 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, + 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, + 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63, 0x31, + 0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06, 0x05, + 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, + 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, + 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, + 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01, 0x62, + 0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06, 0x05, + 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, + 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, + 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, + 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65, 0x31, + 0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20, 0x07, + 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, + 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, + 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, + 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, + 0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20, 0x07, + 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, + 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, + 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, + 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, + 0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06, 0x05, + 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, + 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, + 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, + 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, 0x60, + 0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76, 0x65, + 0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x40, 0x84, + 0x32, 0x12, 0x5B, 0x92, 0x6B, 0x20, 0xD8, 0x14, + 0xC1, 0xC1, 0x8C, 0x3C, 0x73, 0xB8, 0x29, 0x0F, + 0x42, 0xBC, 0x0B, 0x25, 0x87, 0x5C, 0x4F, 0xA4, + 0xFA, 0xD9, 0xDE, 0xC1, 0x2B, 0x20, 0xED, 0xDF, + 0x1C, 0xDD, 0x1A, 0x09, 0xBD, 0xA0, 0x25, 0x48, + 0xC6, 0xBB, 0x99, 0xA1, 0x30, 0x4F, 0x2C, 0xDC, + 0x89, 0xE8, 0xB7, 0xFF, 0x32, 0xE9, 0x3F, 0xBB, + 0xC6, 0xBF, 0x9D, 0x38, 0x68, 0xE1, 0xB2, }; -int plat_get_cca_attest_token(uintptr_t buf, size_t *len, - uintptr_t hash, size_t hash_size) +int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len, + uintptr_t hash, size_t hash_size) { (void)hash; (void)hash_size; diff --git a/plat/arm/board/fvp/fvp_realm_attest_key.c b/plat/arm/board/fvp/fvp_realm_attest_key.c index b32f557f5..1af1f0d3f 100644 --- a/plat/arm/board/fvp/fvp_realm_attest_key.c +++ b/plat/arm/board/fvp/fvp_realm_attest_key.c @@ -19,7 +19,8 @@ static uint8_t sample_attest_priv_key[] = { 0xEB, 0x1A, 0x41, 0x85, 0xBD, 0x11, 0x7F, 0x68 }; -int plat_get_cca_realm_attest_key(uintptr_t buf, size_t *len, unsigned int type) +int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len, + unsigned int type) { assert(type == ATTEST_KEY_CURVE_ECC_SECP384R1); diff --git a/plat/arm/board/fvp/include/fvp_critical_data.h b/plat/arm/board/fvp/include/fvp_critical_data.h index 3010d2180..04bd5b2ed 100644 --- a/plat/arm/board/fvp/include/fvp_critical_data.h +++ b/plat/arm/board/fvp/include/fvp_critical_data.h @@ -1,8 +1,10 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#ifndef FVP_CRITICAL_DATA_H +#define FVP_CRITICAL_DATA_H #include <common/nv_cntr_ids.h> #include <lib/utils_def.h> @@ -17,3 +19,5 @@ struct fvp_critical_data { /* platform NV counters */ unsigned int nv_ctr[MAX_NV_CTR_IDS]; }; + +#endif /* FVP_CRITICAL_DATA_H */ diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 82bd7c8a5..1ef6c87a2 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -127,11 +127,7 @@ #if defined(IMAGE_BL31) # if SPM_MM # define PLAT_ARM_MMAP_ENTRIES 10 -# if ENABLE_RME -# define MAX_XLAT_TABLES 11 -# else -# define MAX_XLAT_TABLES 9 -# endif +# define MAX_XLAT_TABLES 9 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 # elif SPMC_AT_EL3 @@ -141,13 +137,15 @@ # define PLAT_ARM_MMAP_ENTRIES 9 # if USE_DEBUGFS # if ENABLE_RME -# define MAX_XLAT_TABLES 10 +# define MAX_XLAT_TABLES 9 # else # define MAX_XLAT_TABLES 8 # endif # else # if ENABLE_RME -# define MAX_XLAT_TABLES 9 +# define MAX_XLAT_TABLES 8 +# elif DRTM_SUPPORT +# define MAX_XLAT_TABLES 8 # else # define MAX_XLAT_TABLES 7 # endif @@ -197,6 +195,9 @@ # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) #elif CRYPTO_SUPPORT # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) +#elif ARM_BL31_IN_DRAM +/* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) #else # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) #endif @@ -248,9 +249,17 @@ #elif defined(IMAGE_BL2U) # define PLATFORM_STACK_SIZE UL(0x400) #elif defined(IMAGE_BL31) +# if DRTM_SUPPORT +# define PLATFORM_STACK_SIZE UL(0x1000) +# else # define PLATFORM_STACK_SIZE UL(0x800) +# endif /* DRTM_SUPPORT */ #elif defined(IMAGE_BL32) -# define PLATFORM_STACK_SIZE UL(0x440) +# if SPMC_AT_EL3 +# define PLATFORM_STACK_SIZE UL(0x1000) +# else +# define PLATFORM_STACK_SIZE UL(0x440) +# endif /* SPMC_AT_EL3 */ #elif defined(IMAGE_RMM) # define PLATFORM_STACK_SIZE UL(0x440) #endif @@ -394,4 +403,14 @@ */ #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) +/* + * Maximum size of Event Log buffer used for DRTM + */ +#define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) + +/* + * Number of MMAP entries used by DRTM implementation + */ +#define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES + #endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 54c5e7545..51ba03524 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -132,17 +132,18 @@ else lib/cpus/aarch64/neoverse_n2.S \ lib/cpus/aarch64/neoverse_e1.S \ lib/cpus/aarch64/neoverse_v1.S \ - lib/cpus/aarch64/neoverse_demeter.S \ + lib/cpus/aarch64/neoverse_v2.S \ lib/cpus/aarch64/cortex_a78_ae.S \ lib/cpus/aarch64/cortex_a510.S \ - lib/cpus/aarch64/cortex_a710.S \ - lib/cpus/aarch64/cortex_makalu.S \ - lib/cpus/aarch64/cortex_makalu_elp_arm.S \ + lib/cpus/aarch64/cortex_a710.S \ + lib/cpus/aarch64/cortex_a715.S \ + lib/cpus/aarch64/cortex_x3.S \ lib/cpus/aarch64/cortex_a65.S \ lib/cpus/aarch64/cortex_a65ae.S \ lib/cpus/aarch64/cortex_a78c.S \ lib/cpus/aarch64/cortex_hayes.S \ lib/cpus/aarch64/cortex_hunter.S \ + lib/cpus/aarch64/cortex_hunter_elp_arm.S \ lib/cpus/aarch64/cortex_x2.S \ lib/cpus/aarch64/neoverse_poseidon.S endif @@ -341,10 +342,6 @@ ifeq ($(filter 1,${BL2_AT_EL3} ${ARM_XLAT_TABLES_LIB_V1}),) endif endif -ifeq (${ENABLE_RME},1) - BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC -endif - ifeq (${ALLOW_RO_XLAT_TABLES}, 1) ifeq (${ARCH},aarch32) BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES @@ -375,6 +372,10 @@ ifeq (${MEASURED_BOOT},1) $(info Including ${RSS_MEASURED_BOOT_MK}) include ${RSS_MEASURED_BOOT_MK} + ifneq (${MBOOT_RSS_HASH_ALG}, sha256) + $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) + endif + BL1_SOURCES += ${MEASURED_BOOT_SOURCES} BL2_SOURCES += ${MEASURED_BOOT_SOURCES} endif @@ -391,12 +392,44 @@ BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ plat/arm/board/fvp/fvp_bl2_measured_boot.c \ lib/psa/measured_boot.c +# Note that attestation code does not depend on measured boot interfaces per se, +# but the two features go together - attestation without boot measurements is +# pretty much pointless... +BL31_SOURCES += lib/psa/delegated_attestation.c + PLAT_INCLUDES += -Iinclude/lib/psa # RSS is not supported on FVP right now. Thus, we use the mocked version -# of PSA Measured Boot APIs. They return with success and hard-coded data. +# of the provided PSA APIs. They return with success and hard-coded data. PLAT_RSS_NOT_SUPPORTED := 1 +# Even though RSS is not supported on FVP (see above), we support overriding +# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building +# the code to detect any build regressions. The resulting firmware will not be +# functional. +ifneq (${PLAT_RSS_NOT_SUPPORTED},1) + $(warning "RSS is not supported on FVP. The firmware will not be functional.") + include drivers/arm/rss/rss_comms.mk + BL1_SOURCES += ${RSS_COMMS_SOURCES} + BL2_SOURCES += ${RSS_COMMS_SOURCES} + BL31_SOURCES += ${RSS_COMMS_SOURCES} \ + lib/psa/delegated_attestation.c + + BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 + BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 + BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 +endif + +endif + +ifeq (${DRTM_SUPPORT}, 1) +BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ + plat/arm/board/fvp/fvp_drtm_dma_prot.c \ + plat/arm/board/fvp/fvp_drtm_err.c \ + plat/arm/board/fvp/fvp_drtm_measurement.c \ + plat/arm/board/fvp/fvp_drtm_stub.c \ + plat/arm/common/arm_dyn_cfg.c \ + plat/arm/board/fvp/fvp_err.c endif ifeq (${TRUSTED_BOARD_BOOT}, 1) diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 3265b0b72..409d7a60f 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -196,12 +196,6 @@ # define PLATFORM_STACK_SIZE UL(0x440) #endif -/* - * Since free SRAM space is scant, enable the ASSERTION message size - * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). - */ -#define PLAT_LOG_LEVEL_ASSERT 40 - /* CCI related constants */ #define PLAT_ARM_CCI_BASE UL(0x2c090000) #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 diff --git a/plat/arm/board/morello/morello_bl2_setup.c b/plat/arm/board/morello/morello_bl2_setup.c index 0d4b6d00f..da1f7ae10 100644 --- a/plat/arm/board/morello/morello_bl2_setup.c +++ b/plat/arm/board/morello/morello_bl2_setup.c @@ -1,27 +1,226 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <common/debug.h> +#include <drivers/arm/css/sds.h> +#include <lib/mmio.h> #include <lib/utils.h> #include <plat/arm/common/plat_arm.h> -void bl2_platform_setup(void) -{ +#include "morello_def.h" +#include <platform_def.h> + +#ifdef TARGET_PLATFORM_FVP +/* + * Platform information structure stored in SDS. + * This structure holds information about platform's DDR + * size + * - Local DDR size in bytes, DDR memory in main board + */ +struct morello_plat_info { + uint64_t local_ddr_size; +} __packed; +#else +/* + * Platform information structure stored in SDS. + * This structure holds information about platform's DDR + * size which is an information about multichip setup + * - Local DDR size in bytes, DDR memory in main board + * - Remote DDR size in bytes, DDR memory in remote board + * - remote_chip_count + * - multichip mode + * - scc configuration + */ +struct morello_plat_info { + uint64_t local_ddr_size; + uint64_t remote_ddr_size; + uint8_t remote_chip_count; + bool multichip_mode; + uint32_t scc_config; +} __packed; +#endif + +/* Compile time assertion to ensure the size of structure is 18 bytes */ +CASSERT(sizeof(struct morello_plat_info) == MORELLO_SDS_PLATFORM_INFO_SIZE, + assert_invalid_plat_info_size); + #ifdef TARGET_PLATFORM_SOC - /* - * Morello platform supports RDIMMs with ECC capability. To use the ECC - * capability, the entire DDR memory space has to be zeroed out before - * enabling the ECC bits in DMC-Bing. - * Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF during BL2 stage, - * as BL33 binary cannot be copied to DDR memory before enabling ECC. - * Rest of the DDR memory space is zeroed out during BL31 stage. - */ +/* + * Morello platform supports RDIMMs with ECC capability. To use the ECC + * capability, the entire DDR memory space has to be zeroed out before + * enabling the ECC bits in DMC-Bing. Zeroing out several gigabytes of + * memory from SCP is quite time consuming so the following function + * is added to zero out the DDR memory from application processor which is + * much faster compared to SCP. + */ + +static void dmc_ecc_setup(struct morello_plat_info *plat_info) +{ + uint64_t dram2_size; + uint32_t val; + uint64_t tag_mem_base; + uint64_t usable_mem_size; + + INFO("Total DIMM size: %uGB\n", + (uint32_t)(plat_info->local_ddr_size / 0x40000000)); + + assert(plat_info->local_ddr_size > ARM_DRAM1_SIZE); + dram2_size = plat_info->local_ddr_size - ARM_DRAM1_SIZE; + INFO("Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF\n"); zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); + + INFO("Zeroing DDR memory range 0x%llx - 0x%llx\n", + ARM_DRAM2_BASE, ARM_DRAM2_BASE + dram2_size); + zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); + flush_dcache_range(ARM_DRAM2_BASE, dram2_size); + + /* Clear previous ECC errors while zeroing out the memory */ + val = mmio_read_32(MORELLO_DMC0_ERR2STATUS_REG); + mmio_write_32(MORELLO_DMC0_ERR2STATUS_REG, val); + + val = mmio_read_32(MORELLO_DMC1_ERR2STATUS_REG); + mmio_write_32(MORELLO_DMC1_ERR2STATUS_REG, val); + + /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ + mmio_write_32(MORELLO_DMC0_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_CONFIG); + mmio_write_32(MORELLO_DMC1_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_CONFIG); + + while ((mmio_read_32(MORELLO_DMC0_MEMC_STATUS_REG) & + MORELLO_DMC_MEMC_STATUS_MASK) != + MORELLO_DMC_MEMC_CMD_CONFIG) { + continue; + } + + while ((mmio_read_32(MORELLO_DMC1_MEMC_STATUS_REG) & + MORELLO_DMC_MEMC_STATUS_MASK) != + MORELLO_DMC_MEMC_CMD_CONFIG) { + continue; + } + + /* Configure Bing client/server mode based on SCC configuration */ + if (plat_info->scc_config & MORELLO_SCC_CLIENT_MODE_MASK) { + INFO("Configuring DMC Bing in client mode\n"); + usable_mem_size = plat_info->local_ddr_size - + (plat_info->local_ddr_size / 128ULL); + + /* Linear DDR address */ + tag_mem_base = usable_mem_size; + tag_mem_base = tag_mem_base / 4; + + /* Reverse translation */ + if (tag_mem_base < ARM_DRAM1_BASE) { + tag_mem_base += ARM_DRAM1_BASE; + } else { + tag_mem_base = tag_mem_base - ARM_DRAM1_BASE + + ARM_DRAM2_BASE; + } + + mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x1); + mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x1); + mmio_write_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x1); + mmio_write_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x1); + + if (plat_info->scc_config & MORELLO_SCC_C1_TAG_CACHE_EN_MASK) { + mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x2); + mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x2); + INFO("C1 Tag Cache Enabled\n"); + } + + if (plat_info->scc_config & MORELLO_SCC_C2_TAG_CACHE_EN_MASK) { + mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x4); + mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x4); + INFO("C2 Tag Cache Enabled\n"); + } + + mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL, + (uint32_t)tag_mem_base); + mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL, + (uint32_t)tag_mem_base); + mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL2, + (uint32_t)(tag_mem_base >> 32)); + mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL2, + (uint32_t)(tag_mem_base >> 32)); + + mmio_setbits_32(MORELLO_DMC0_MEM_ACCESS_CTL, + MORELLO_DMC_MEM_ACCESS_DIS); + mmio_setbits_32(MORELLO_DMC1_MEM_ACCESS_CTL, + MORELLO_DMC_MEM_ACCESS_DIS); + + INFO("Tag base set to 0x%lx\n", tag_mem_base); + plat_info->local_ddr_size = usable_mem_size; + } else { + INFO("Configuring DMC Bing in server mode\n"); + mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x0); + mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x0); + } + + INFO("Enabling ECC on DMCs\n"); + /* Enable ECC in DMCs */ + mmio_setbits_32(MORELLO_DMC0_ERR0CTLR0_REG, + MORELLO_DMC_ERR0CTLR0_ECC_EN); + mmio_setbits_32(MORELLO_DMC1_ERR0CTLR0_REG, + MORELLO_DMC_ERR0CTLR0_ECC_EN); + + /* Set DMCs to READY state */ + mmio_write_32(MORELLO_DMC0_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_READY); + mmio_write_32(MORELLO_DMC1_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_READY); + + while ((mmio_read_32(MORELLO_DMC0_MEMC_STATUS_REG) & + MORELLO_DMC_MEMC_STATUS_MASK) != + MORELLO_DMC_MEMC_CMD_READY) { + continue; + } + + while ((mmio_read_32(MORELLO_DMC1_MEMC_STATUS_REG) & + MORELLO_DMC_MEMC_STATUS_MASK) != + MORELLO_DMC_MEMC_CMD_READY) { + continue; + } +} +#endif + +void bl2_platform_setup(void) +{ + int ret; + struct morello_plat_info plat_info; + + ret = sds_init(); + if (ret != SDS_OK) { + ERROR("SDS initialization failed. ret:%d\n", ret); + panic(); + } + + ret = sds_struct_read(MORELLO_SDS_PLATFORM_INFO_STRUCT_ID, + MORELLO_SDS_PLATFORM_INFO_OFFSET, + &plat_info, + MORELLO_SDS_PLATFORM_INFO_SIZE, + SDS_ACCESS_MODE_NON_CACHED); + if (ret != SDS_OK) { + ERROR("Error getting platform info from SDS. ret:%d\n", ret); + panic(); + } + + /* Validate plat_info SDS */ +#ifdef TARGET_PLATFORM_FVP + if (plat_info.local_ddr_size == 0U) { +#else + if ((plat_info.local_ddr_size == 0U) + || (plat_info.local_ddr_size > MORELLO_MAX_DDR_CAPACITY) + || (plat_info.remote_ddr_size > MORELLO_MAX_DDR_CAPACITY) + || (plat_info.remote_chip_count > MORELLO_MAX_REMOTE_CHIP_COUNT) + ) { +#endif + ERROR("platform info SDS is corrupted\n"); + panic(); + } + +#ifdef TARGET_PLATFORM_SOC + dmc_ecc_setup(&plat_info); #endif arm_bl2_platform_setup(); } diff --git a/plat/arm/board/morello/morello_bl31_setup.c b/plat/arm/board/morello/morello_bl31_setup.c index e41851810..a04421200 100644 --- a/plat/arm/board/morello/morello_bl31_setup.c +++ b/plat/arm/board/morello/morello_bl31_setup.c @@ -1,54 +1,16 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#include <common/debug.h> #include <drivers/arm/css/css_mhu_doorbell.h> #include <drivers/arm/css/scmi.h> -#include <drivers/arm/css/sds.h> -#include <lib/cassert.h> -#include <lib/utils.h> #include <plat/arm/common/plat_arm.h> #include "morello_def.h" #include <platform_def.h> -#ifdef TARGET_PLATFORM_FVP -/* - * Platform information structure stored in SDS. - * This structure holds information about platform's DDR - * size - * - Local DDR size in bytes, DDR memory in main board - */ -struct morello_plat_info { - uint64_t local_ddr_size; -} __packed; -#else -/* - * Platform information structure stored in SDS. - * This structure holds information about platform's DDR - * size which is an information about multichip setup - * - Local DDR size in bytes, DDR memory in main board - * - Remote DDR size in bytes, DDR memory in remote board - * - remote_chip_count - * - multichip mode - * - scc configuration - */ -struct morello_plat_info { - uint64_t local_ddr_size; - uint64_t remote_ddr_size; - uint8_t remote_chip_count; - bool multichip_mode; - uint32_t scc_config; -} __packed; -#endif - -/* Compile time assertion to ensure the size of structure is 18 bytes */ -CASSERT(sizeof(struct morello_plat_info) == MORELLO_SDS_PLATFORM_INFO_SIZE, - assert_invalid_plat_info_size); - static scmi_channel_plat_info_t morello_scmi_plat_info = { .scmi_mbx_mem = MORELLO_SCMI_PAYLOAD_BASE, .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, @@ -67,177 +29,7 @@ const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) return css_scmi_override_pm_ops(ops); } -#ifdef TARGET_PLATFORM_SOC -/* - * Morello platform supports RDIMMs with ECC capability. To use the ECC - * capability, the entire DDR memory space has to be zeroed out before - * enabling the ECC bits in DMC-Bing. Zeroing out several gigabytes of - * memory from SCP is quite time consuming so the following function - * is added to zero out the DDR memory from application processor which is - * much faster compared to SCP. - */ - -static void dmc_ecc_setup(struct morello_plat_info *plat_info) -{ - uint64_t dram2_size; - uint32_t val; - uint64_t tag_mem_base; - uint64_t usable_mem_size; - - INFO("Total DIMM size: %uGB\n", - (uint32_t)(plat_info->local_ddr_size / 0x40000000)); - - assert(plat_info->local_ddr_size > ARM_DRAM1_SIZE); - dram2_size = plat_info->local_ddr_size - ARM_DRAM1_SIZE; - - INFO("Zeroing DDR memory range 0x%llx - 0x%llx\n", - ARM_DRAM2_BASE, ARM_DRAM2_BASE + dram2_size); - zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); - flush_dcache_range(ARM_DRAM2_BASE, dram2_size); - - /* Clear previous ECC errors while zeroing out the memory */ - val = mmio_read_32(MORELLO_DMC0_ERR2STATUS_REG); - mmio_write_32(MORELLO_DMC0_ERR2STATUS_REG, val); - - val = mmio_read_32(MORELLO_DMC1_ERR2STATUS_REG); - mmio_write_32(MORELLO_DMC1_ERR2STATUS_REG, val); - - /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ - mmio_write_32(MORELLO_DMC0_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_CONFIG); - mmio_write_32(MORELLO_DMC1_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_CONFIG); - - while ((mmio_read_32(MORELLO_DMC0_MEMC_STATUS_REG) & - MORELLO_DMC_MEMC_STATUS_MASK) != - MORELLO_DMC_MEMC_CMD_CONFIG) { - continue; - } - - while ((mmio_read_32(MORELLO_DMC1_MEMC_STATUS_REG) & - MORELLO_DMC_MEMC_STATUS_MASK) != - MORELLO_DMC_MEMC_CMD_CONFIG) { - continue; - } - - /* Configure Bing client/server mode based on SCC configuration */ - if (plat_info->scc_config & MORELLO_SCC_CLIENT_MODE_MASK) { - INFO("Configuring DMC Bing in client mode\n"); - usable_mem_size = plat_info->local_ddr_size - - (plat_info->local_ddr_size / 128ULL); - - /* Linear DDR address */ - tag_mem_base = usable_mem_size; - tag_mem_base = tag_mem_base / 4; - - /* Reverse translation */ - if (tag_mem_base < ARM_DRAM1_BASE) { - tag_mem_base += ARM_DRAM1_BASE; - } else { - tag_mem_base = tag_mem_base - ARM_DRAM1_BASE + - ARM_DRAM2_BASE; - } - - mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x1); - mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x1); - mmio_write_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x1); - mmio_write_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x1); - - if (plat_info->scc_config & MORELLO_SCC_C1_TAG_CACHE_EN_MASK) { - mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x2); - mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x2); - INFO("C1 Tag Cache Enabled\n"); - } - - if (plat_info->scc_config & MORELLO_SCC_C2_TAG_CACHE_EN_MASK) { - mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x4); - mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x4); - INFO("C2 Tag Cache Enabled\n"); - } - - mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL, - (uint32_t)tag_mem_base); - mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL, - (uint32_t)tag_mem_base); - mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL2, - (uint32_t)(tag_mem_base >> 32)); - mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL2, - (uint32_t)(tag_mem_base >> 32)); - - mmio_setbits_32(MORELLO_DMC0_MEM_ACCESS_CTL, - MORELLO_DMC_MEM_ACCESS_DIS); - mmio_setbits_32(MORELLO_DMC1_MEM_ACCESS_CTL, - MORELLO_DMC_MEM_ACCESS_DIS); - - INFO("Tag base set to 0x%lx\n", tag_mem_base); - plat_info->local_ddr_size = usable_mem_size; - } else { - INFO("Configuring DMC Bing in server mode\n"); - mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x0); - mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x0); - } - - INFO("Enabling ECC on DMCs\n"); - /* Enable ECC in DMCs */ - mmio_setbits_32(MORELLO_DMC0_ERR0CTLR0_REG, - MORELLO_DMC_ERR0CTLR0_ECC_EN); - mmio_setbits_32(MORELLO_DMC1_ERR0CTLR0_REG, - MORELLO_DMC_ERR0CTLR0_ECC_EN); - - /* Set DMCs to READY state */ - mmio_write_32(MORELLO_DMC0_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_READY); - mmio_write_32(MORELLO_DMC1_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_READY); - - while ((mmio_read_32(MORELLO_DMC0_MEMC_STATUS_REG) & - MORELLO_DMC_MEMC_STATUS_MASK) != - MORELLO_DMC_MEMC_CMD_READY) { - continue; - } - - while ((mmio_read_32(MORELLO_DMC1_MEMC_STATUS_REG) & - MORELLO_DMC_MEMC_STATUS_MASK) != - MORELLO_DMC_MEMC_CMD_READY) { - continue; - } -} -#endif - void bl31_platform_setup(void) { - int ret; - struct morello_plat_info plat_info; - - ret = sds_init(); - if (ret != SDS_OK) { - ERROR("SDS initialization failed. ret:%d\n", ret); - panic(); - } - - ret = sds_struct_read(MORELLO_SDS_PLATFORM_INFO_STRUCT_ID, - MORELLO_SDS_PLATFORM_INFO_OFFSET, - &plat_info, - MORELLO_SDS_PLATFORM_INFO_SIZE, - SDS_ACCESS_MODE_NON_CACHED); - if (ret != SDS_OK) { - ERROR("Error getting platform info from SDS. ret:%d\n", ret); - panic(); - } - - /* Validate plat_info SDS */ -#ifdef TARGET_PLATFORM_FVP - if (plat_info.local_ddr_size == 0U) { -#else - if ((plat_info.local_ddr_size == 0U) - || (plat_info.local_ddr_size > MORELLO_MAX_DDR_CAPACITY) - || (plat_info.remote_ddr_size > MORELLO_MAX_DDR_CAPACITY) - || (plat_info.remote_chip_count > MORELLO_MAX_REMOTE_CHIP_COUNT) - ) { -#endif - ERROR("platform info SDS is corrupted\n"); - panic(); - } - arm_bl31_platform_setup(); - -#ifdef TARGET_PLATFORM_SOC - dmc_ecc_setup(&plat_info); -#endif } diff --git a/plat/arm/board/morello/morello_plat.c b/plat/arm/board/morello/morello_plat.c index 42e5171ca..1da0ff96a 100644 --- a/plat/arm/board/morello/morello_plat.c +++ b/plat/arm/board/morello/morello_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,7 +15,7 @@ * Table of regions to map using the MMU. * Replace or extend the below regions as required */ -#if IMAGE_BL1 || IMAGE_BL31 +#if IMAGE_BL1 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, MORELLO_MAP_DEVICE, @@ -25,12 +25,23 @@ const mmap_region_t plat_arm_mmap[] = { {0} }; #endif + +#if IMAGE_BL31 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + MORELLO_MAP_DEVICE, + MORELLO_MAP_NS_SRAM, + {0} +}; +#endif + #if IMAGE_BL2 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, MORELLO_MAP_DEVICE, MORELLO_MAP_NS_SRAM, ARM_MAP_DRAM1, + ARM_MAP_DRAM2, #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3 ARM_MAP_BL1_RW, #endif diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk index 86047e39f..156b7ea2c 100644 --- a/plat/arm/board/morello/platform.mk +++ b/plat/arm/board/morello/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2020-2021, Arm Limited. All rights reserved. +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -83,6 +83,8 @@ override CTX_INCLUDE_AARCH32_REGS := 0 override ARM_PLAT_MT := 1 +override ARM_BL31_IN_DRAM := 1 + # Errata workarounds: ERRATA_N1_1868343 := 1 diff --git a/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts b/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts index f61e30bc5..700b900ef 100644 --- a/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts +++ b/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts @@ -15,7 +15,11 @@ max-size = <0x200>; id = <TB_FW_CONFIG_ID>; }; - + tos_fw-config { + load-address = <0x0 0x4001600>; + max-size = <0x1000>; + id = <TOS_FW_CONFIG_ID>; + }; nt_fw-config { load-address = <0x0 0xFEF00000>; max-size = <0x0100000>; diff --git a/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts b/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts new file mode 100644 index 000000000..ed870803c --- /dev/null +++ b/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/dts-v1/; + +/ { + compatible = "arm,ffa-core-manifest-1.0"; + #address-cells = <2>; + #size-cells = <1>; + + /* + * BL32 image details needed by SPMC + * + * Note: + * binary_size: size of BL32 + TOS_FW_CONFIG + */ + + attribute { + spmc_id = <0x8000>; + maj_ver = <0x1>; + min_ver = <0x0>; + exec_state = <0x0>; + load_address = <0x0 0x08000000>; + entrypoint = <0x0 0x08000000>; + binary_size = <0x2000000>; + }; + +}; diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index c9b81bafa..b3799a7b2 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h @@ -15,8 +15,9 @@ #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 -#define PLAT_ARM_RUN_UART_BASE 0x2A410000 -#define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000 +/* IOFPGA UART0 */ +#define PLAT_ARM_RUN_UART_BASE 0x1C090000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000 #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 @@ -91,7 +92,7 @@ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size * plus a little space for growth. */ -#define PLAT_ARM_MAX_BL1_RW_SIZE 0xE000 +#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 /* * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page @@ -110,12 +111,16 @@ * little space for growth. */ #if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL2_SIZE 0x20000 +# define PLAT_ARM_MAX_BL2_SIZE 0x22000 #else # define PLAT_ARM_MAX_BL2_SIZE 0x14000 #endif -#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) +#define PLAT_ARM_MAX_BL31_SIZE UL(0x40000) + +#define PLAT_ARM_SPMC_BASE U(0x08000000) +#define PLAT_ARM_SPMC_SIZE UL(0x02000000) /* 32 MB */ + /******************************************************************************* * N1SDP topology related constants diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk index 740fb2988..9c0cc022c 100644 --- a/plat/arm/board/n1sdp/platform.mk +++ b/plat/arm/board/n1sdp/platform.mk @@ -68,6 +68,13 @@ $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) # Add the NT_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG})) +N1SDP_SPMC_MANIFEST_DTS := ${N1SDP_BASE}/fdts/${PLAT}_optee_spmc_manifest.dts +FDT_SOURCES += ${N1SDP_SPMC_MANIFEST_DTS} +N1SDP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_optee_spmc_manifest.dtb + +# Add the TOS_FW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${N1SDP_TOS_FW_CONFIG},--tos-fw-config,${N1SDP_TOS_FW_CONFIG})) + # Setting to 0 as no NVCTR in N1SDP N1SDP_FW_NVCTR_VAL := 0 TFW_NVCTR_VAL := ${N1SDP_FW_NVCTR_VAL} diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h index a9b30a41d..69bfd7bcf 100644 --- a/plat/arm/board/rde1edge/include/platform_def.h +++ b/plat/arm/board/rde1edge/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, Arm Limited. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,12 +26,15 @@ #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 +/* Maximum number of address bits used per chip */ +#define CSS_SGI_ADDR_BITS_PER_CHIP U(36) + /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ #ifdef __aarch64__ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) #else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h index a61b0d555..de0190272 100644 --- a/plat/arm/board/rdn1edge/include/platform_def.h +++ b/plat/arm/board/rdn1edge/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,12 +30,17 @@ /* Virtual address used by dynamic mem_protect for chunk_base */ #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) +/* Maximum number of address bits used per chip */ +#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) + /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ #ifdef __aarch64__ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) +#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ + CSS_SGI_CHIP_COUNT) +#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ + CSS_SGI_CHIP_COUNT) #else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk index 22ab312ee..95753aafc 100644 --- a/plat/arm/board/rdn1edge/platform.mk +++ b/plat/arm/board/rdn1edge/platform.mk @@ -4,6 +4,8 @@ # SPDX-License-Identifier: BSD-3-Clause # +$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected) + # GIC-600 configuration GICV3_IMPL_GIC600_MULTICHIP := 1 diff --git a/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts b/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts index bbc36fc14..dd70141de 100644 --- a/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts +++ b/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020 - 2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,5 +18,26 @@ platform-id = <0x0>; config-id = <0x0>; multi-chip-mode = <0x0>; + /* + * First cell pair: Count of isolated CPUs in the list. + * Rest of the cells: MPID list of the isolated CPUs. + */ + isolated-cpu-list = <0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0>; }; }; diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h index e4015f75b..347401626 100644 --- a/plat/arm/board/rdn2/include/platform_def.h +++ b/plat/arm/board/rdn2/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,15 +69,16 @@ */ #ifdef __aarch64__ #if (CSS_SGI_PLATFORM_VARIANT == 2) +#define CSS_SGI_ADDR_BITS_PER_CHIP U(46) /* 64TB */ +#else +#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) /* 4TB */ +#endif + #define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ CSS_SGI_CHIP_COUNT) #define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ CSS_SGI_CHIP_COUNT) #else -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) -#endif -#else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #endif @@ -95,4 +96,8 @@ #define PLAT_ARM_GICR_BASE UL(0x301C0000) #endif +/* Interrupt priority level for shutdown/reboot */ +#define PLAT_REBOOT_PRI GIC_HIGHEST_SEC_PRIORITY +#define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI) + #endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk index b882dc823..7492fe5ce 100644 --- a/plat/arm/board/rdn2/platform.mk +++ b/plat/arm/board/rdn2/platform.mk @@ -1,4 +1,4 @@ -# Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -18,12 +18,16 @@ endif # RD-N2 platform uses GIC-700 which is based on GICv4.1 GIC_ENABLE_V4_EXTN := 1 +GIC_EXT_INTID := 1 #Enable GIC Multichip Extension only for Multichip Platforms ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2) GICV3_IMPL_GIC600_MULTICHIP := 1 endif +override CSS_SYSTEM_GRACEFUL_RESET := 1 +override EL3_EXCEPTION_HANDLING := 1 + include plat/arm/css/sgi/sgi-common.mk RDN2_BASE = plat/arm/board/rdn2 @@ -31,7 +35,7 @@ RDN2_BASE = plat/arm/board/rdn2 PLAT_INCLUDES += -I${RDN2_BASE}/include/ SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \ - lib/cpus/aarch64/neoverse_demeter.S + lib/cpus/aarch64/neoverse_v2.S PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c diff --git a/plat/arm/board/rdn2/rdn2_plat.c b/plat/arm/board/rdn2/rdn2_plat.c index 8cf192972..2506f9da0 100644 --- a/plat/arm/board/rdn2/rdn2_plat.c +++ b/plat/arm/board/rdn2/rdn2_plat.c @@ -47,15 +47,15 @@ static struct gic600_multichip_data rdn2mc_multichip_data __init = { #endif }, .spi_ids = { - {32, 479}, + {32, 511}, #if CSS_SGI_CHIP_COUNT > 1 - {0, 0}, + {512, 991}, #endif #if CSS_SGI_CHIP_COUNT > 2 - {0, 0}, + {4096, 4575}, #endif #if CSS_SGI_CHIP_COUNT > 3 - {0, 0}, + {4576, 5055}, #endif } }; diff --git a/plat/arm/board/rdv1/include/platform_def.h b/plat/arm/board/rdv1/include/platform_def.h index 5b98b4e8c..620fa3e2d 100644 --- a/plat/arm/board/rdv1/include/platform_def.h +++ b/plat/arm/board/rdv1/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,12 +46,15 @@ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) +/* Maximum number of address bits used per chip */ +#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) + /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ #ifdef __aarch64__ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) #else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) diff --git a/plat/arm/board/rdv1mc/include/platform_def.h b/plat/arm/board/rdv1mc/include/platform_def.h index 12ce8063a..367090488 100644 --- a/plat/arm/board/rdv1mc/include/platform_def.h +++ b/plat/arm/board/rdv1mc/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,6 +46,9 @@ /* Virtual address used by dynamic mem_protect for chunk_base */ #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) +/* Remote chip address offset (4TB per chip) */ +#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) + /* Physical and virtual address space limits for MMU in AARCH64 mode */ #define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ CSS_SGI_CHIP_COUNT) diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h index 72d5f7cf0..82a38c549 100644 --- a/plat/arm/board/sgi575/include/platform_def.h +++ b/plat/arm/board/sgi575/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,12 +27,15 @@ #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 +/* Maximum number of address bits used per chip */ +#define CSS_SGI_ADDR_BITS_PER_CHIP U(36) + /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ #ifdef __aarch64__ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) #else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk index 0761b77ef..2f2bf73b4 100644 --- a/plat/arm/board/sgi575/platform.mk +++ b/plat/arm/board/sgi575/platform.mk @@ -4,6 +4,8 @@ # SPDX-License-Identifier: BSD-3-Clause # +$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected) + include plat/arm/css/sgi/sgi-common.mk SGI575_BASE = plat/arm/board/sgi575 diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h index 745d91cab..bc4f25449 100644 --- a/plat/arm/board/tc/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -101,7 +101,7 @@ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size * plus a little space for growth. */ -#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 +#define PLAT_ARM_MAX_BL1_RW_SIZE 0xD000 /* * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page @@ -117,20 +117,19 @@ /* * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a - * little space for growth. + * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT + * and MEASURED_BOOT is enabled. */ -#if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL2_SIZE 0x20000 -#else -# define PLAT_ARM_MAX_BL2_SIZE 0x14000 -#endif +# define PLAT_ARM_MAX_BL2_SIZE 0x26000 + /* * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is * calculated using the current BL31 PROGBITS debug size plus the sizes of - * BL2 and BL1-RW + * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and + * MEASURED_BOOT is enabled. */ -#define PLAT_ARM_MAX_BL31_SIZE 0x3F000 +#define PLAT_ARM_MAX_BL31_SIZE 0x47000 /* * Size of cacheable stacks @@ -159,6 +158,13 @@ # define PLATFORM_STACK_SIZE 0x440 #endif +/* + * In the current implementation the RoT Service request that requires the + * biggest message buffer is the RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The + * maximum required buffer size is calculated based on the platform-specific + * needs of this request. + */ +#define PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE 0x500 #define TC_DEVICE_BASE 0x21000000 #define TC_DEVICE_SIZE 0x5f000000 @@ -177,8 +183,14 @@ #define PLAT_ARM_NSTIMER_FRAME_ID 0 +#if (TARGET_PLATFORM >= 2) +#define PLAT_ARM_TRUSTED_ROM_BASE 0x1000 +#else #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 -#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ +#endif + +/* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ +#define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) #define PLAT_ARM_NSRAM_BASE 0x06000000 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ @@ -214,9 +226,14 @@ #define PLAT_MAX_CPUS_PER_CLUSTER U(8) #define PLAT_MAX_PE_PER_CPU U(1) +/* Message Handling Unit (MHU) base addresses */ #define PLAT_CSS_MHU_BASE UL(0x45400000) #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE +/* TC2: AP<->RSS MHUs */ +#define PLAT_RSS_AP_SND_MHU_BASE UL(0x2A840000) +#define PLAT_RSS_AP_RCV_MHU_BASE UL(0x2A850000) + #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index 3acd88e78..37ba2295c 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -1,14 +1,21 @@ -# Copyright (c) 2021, Arm Limited. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include common/fdt_wrappers.mk -ifeq ($(filter ${TARGET_PLATFORM}, 0 1),) - $(error TARGET_PLATFORM must be 0 or 1) +ifeq ($(TARGET_PLATFORM), 0) +$(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \ +Some of the features might not work as expected) endif +ifeq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0) + $(error TARGET_PLATFORM must be less than or equal to 2) +endif + +$(eval $(call add_define,TARGET_PLATFORM)) + CSS_LOAD_SCP_IMAGES := 1 CSS_USE_SCMI_SDS_DRIVER := 1 @@ -19,7 +26,7 @@ SDEI_SUPPORT := 0 EL3_EXCEPTION_HANDLING := 0 -HANDLE_EA_EL3_FIRST := 0 +HANDLE_EA_EL3_FIRST_NS := 0 # System coherency is managed in hardware HW_ASSISTED_COHERENCY := 1 @@ -61,19 +68,25 @@ TC_BASE = plat/arm/board/tc PLAT_INCLUDES += -I${TC_BASE}/include/ -# Common CPU libraries -TC_CPU_SOURCES := lib/cpus/aarch64/cortex_a510.S - # CPU libraries for TARGET_PLATFORM=0 ifeq (${TARGET_PLATFORM}, 0) -TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a710.S \ +TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \ + lib/cpus/aarch64/cortex_a710.S \ lib/cpus/aarch64/cortex_x2.S endif # CPU libraries for TARGET_PLATFORM=1 ifeq (${TARGET_PLATFORM}, 1) -TC_CPU_SOURCES += lib/cpus/aarch64/cortex_makalu.S \ - lib/cpus/aarch64/cortex_makalu_elp_arm.S +TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \ + lib/cpus/aarch64/cortex_a715.S \ + lib/cpus/aarch64/cortex_x3.S +endif + +# CPU libraries for TARGET_PLATFORM=2 +ifeq (${TARGET_PLATFORM}, 2) +TC_CPU_SOURCES += lib/cpus/aarch64/cortex_hayes.S \ + lib/cpus/aarch64/cortex_hunter.S \ + lib/cpus/aarch64/cortex_hunter_elp_arm.S endif INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c @@ -87,7 +100,6 @@ BL1_SOURCES += ${INTERCONNECT_SOURCES} \ ${TC_BASE}/tc_err.c \ drivers/arm/sbsa/sbsa.c - BL2_SOURCES += ${TC_BASE}/tc_security.c \ ${TC_BASE}/tc_err.c \ ${TC_BASE}/tc_trusted_boot.c \ @@ -155,6 +167,32 @@ override ENABLE_AMU_FCONF := 1 override ENABLE_MPMM := 1 override ENABLE_MPMM_FCONF := 1 +# Include Measured Boot makefile before any Crypto library makefile. +# Crypto library makefile may need default definitions of Measured Boot build +# flags present in Measured Boot makefile. +ifeq (${MEASURED_BOOT},1) + MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk + $(info Including ${MEASURED_BOOT_MK}) + include ${MEASURED_BOOT_MK} + $(info Including rss_comms.mk) + include drivers/arm/rss/rss_comms.mk + + BL1_SOURCES += ${MEASURED_BOOT_SOURCES} \ + plat/arm/board/tc/tc_common_measured_boot.c \ + plat/arm/board/tc/tc_bl1_measured_boot.c \ + lib/psa/measured_boot.c \ + ${RSS_COMMS_SOURCES} + + BL2_SOURCES += ${MEASURED_BOOT_SOURCES} \ + plat/arm/board/tc/tc_common_measured_boot.c \ + plat/arm/board/tc/tc_bl2_measured_boot.c \ + lib/psa/measured_boot.c \ + ${RSS_COMMS_SOURCES} + +PLAT_INCLUDES += -Iinclude/lib/psa + +endif + include plat/arm/common/arm_common.mk include plat/arm/css/common/css_common.mk include plat/arm/soc/common/soc_css.mk diff --git a/plat/arm/board/tc/tc_bl1_measured_boot.c b/plat/arm/board/tc/tc_bl1_measured_boot.c new file mode 100644 index 000000000..0d29c5114 --- /dev/null +++ b/plat/arm/board/tc/tc_bl1_measured_boot.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <drivers/arm/rss_comms.h> +#include <drivers/measured_boot/rss/rss_measured_boot.h> +#include <lib/psa/measured_boot.h> + +#include <plat/arm/common/plat_arm.h> +#include <platform_def.h> + +/* Table with platform specific image IDs and metadata. Intentionally not a + * const struct, some members might set by bootloaders during trusted boot. + */ +struct rss_mboot_metadata tc_rss_mboot_metadata[] = { + { + .id = FW_CONFIG_ID, + .slot = U(6), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_FW_CONFIG_STRING, + .lock_measurement = true }, + { + .id = TB_FW_CONFIG_ID, + .slot = U(7), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_TB_FW_CONFIG_STRING, + .lock_measurement = true }, + { + .id = BL2_IMAGE_ID, + .slot = U(8), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_BL2_STRING, + .lock_measurement = true }, + + { + .id = RSS_MBOOT_INVALID_ID } +}; + +void bl1_plat_mboot_init(void) +{ + /* Initialize the communication channel between AP and RSS */ + (void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, + PLAT_RSS_AP_RCV_MHU_BASE); + + rss_measured_boot_init(); +} + +void bl1_plat_mboot_finish(void) +{ + /* Nothing to do. */ +} diff --git a/plat/arm/board/tc/tc_bl2_measured_boot.c b/plat/arm/board/tc/tc_bl2_measured_boot.c new file mode 100644 index 000000000..7ea2c2ec4 --- /dev/null +++ b/plat/arm/board/tc/tc_bl2_measured_boot.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <drivers/arm/rss_comms.h> +#include <drivers/measured_boot/rss/rss_measured_boot.h> +#include <lib/psa/measured_boot.h> + +#include <plat/common/common_def.h> +#include <platform_def.h> + +/* TC specific table with image IDs and metadata. Intentionally not a + * const struct, some members might set by bootloaders during trusted boot. + */ +struct rss_mboot_metadata tc_rss_mboot_metadata[] = { + { + .id = BL31_IMAGE_ID, + .slot = U(9), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_BL31_STRING, + .lock_measurement = true }, + { + .id = HW_CONFIG_ID, + .slot = U(10), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_HW_CONFIG_STRING, + .lock_measurement = true }, + { + .id = SOC_FW_CONFIG_ID, + .slot = U(11), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_SOC_FW_CONFIG_STRING, + .lock_measurement = true }, + { + .id = RSS_MBOOT_INVALID_ID } +}; + +void bl2_plat_mboot_init(void) +{ + /* Initialize the communication channel between AP and RSS */ + (void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, + PLAT_RSS_AP_RCV_MHU_BASE); + + rss_measured_boot_init(); +} + +void bl2_plat_mboot_finish(void) +{ + /* Nothing to do. */ +} diff --git a/plat/arm/board/tc/tc_common_measured_boot.c b/plat/arm/board/tc/tc_common_measured_boot.c new file mode 100644 index 000000000..fe718995a --- /dev/null +++ b/plat/arm/board/tc/tc_common_measured_boot.c @@ -0,0 +1,35 @@ + +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <stdint.h> + +#include <common/desc_image_load.h> +#include <drivers/measured_boot/rss/rss_measured_boot.h> + +extern struct rss_mboot_metadata tc_rss_mboot_metadata[]; + +struct rss_mboot_metadata *plat_rss_mboot_get_metadata(void) +{ + return tc_rss_mboot_metadata; +} + +int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data) +{ + int err; + + /* Calculate image hash and record data in RSS */ + err = rss_mboot_measure_and_record(image_data->image_base, + image_data->image_size, + image_id); + if (err != 0) { + ERROR("%s%s image id %u (%i)\n", + "Failed to ", "record in RSS", image_id, err); + } + + return err; +} diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c index a9668e117..77db023fd 100644 --- a/plat/arm/board/tc/tc_plat.c +++ b/plat/arm/board/tc/tc_plat.c @@ -135,7 +135,7 @@ const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( } #endif /* SPM_MM && defined(IMAGE_BL31) */ -#if TRUSTED_BOARD_BOOT +#if TRUSTED_BOARD_BOOT || MEASURED_BOOT int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) { assert(heap_addr != NULL); diff --git a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c index 78360b06c..18f1a3798 100644 --- a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c +++ b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c @@ -20,71 +20,72 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { #ifdef SCP_BL2_BASE /* Fill SCP_BL2 related information if it exists */ - { - .image_id = SCP_BL2_IMAGE_ID, + { + .image_id = SCP_BL2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #endif /* SCP_BL2_BASE */ /* Fill BL32 related information */ - { - .image_id = BL32_IMAGE_ID, + { + .image_id = BL32_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL32_BASE, - .ep_info.spsr = SPSR_MODE32(MODE32_mon, SPSR_T_ARM, - SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL32_BASE, + .ep_info.spsr = SPSR_MODE32(MODE32_mon, SPSR_T_ARM, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = BL33_IMAGE_ID, - }, + .next_handoff_image_id = BL33_IMAGE_ID, + }, /* Fill HW_CONFIG related information if it exists */ - { - .image_id = HW_CONFIG_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + { + .image_id = HW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, + NON_SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* Fill BL33 related information */ - { - .image_id = BL33_IMAGE_ID, + { + .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), #ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, + .ep_info.pc = PRELOADED_BL33_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), #else - .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, + .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, - .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE - - PLAT_ARM_NS_IMAGE_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, + .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE + - PLAT_ARM_NS_IMAGE_BASE, #endif /* PRELOADED_BL33_BASE */ - .next_handoff_image_id = INVALID_IMAGE_ID, - } + .next_handoff_image_id = INVALID_IMAGE_ID, + } }; REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c index 0666e57fa..3d7b3613e 100644 --- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c +++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c @@ -20,203 +20,207 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { #ifdef SCP_BL2_BASE /* Fill SCP_BL2 related information if it exists */ - { - .image_id = SCP_BL2_IMAGE_ID, + { + .image_id = SCP_BL2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #endif /* SCP_BL2_BASE */ #ifdef EL3_PAYLOAD_BASE /* Fill EL3 payload related information (BL31 is EL3 payload)*/ - { - .image_id = BL31_IMAGE_ID, + { + .image_id = BL31_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #else /* EL3_PAYLOAD_BASE */ /* Fill BL31 related information */ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), #if DEBUG - .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL, + .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL, #endif - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, # if defined(BL32_BASE) - .next_handoff_image_id = BL32_IMAGE_ID, + .next_handoff_image_id = BL32_IMAGE_ID, # elif ENABLE_RME - .next_handoff_image_id = RMM_IMAGE_ID, + .next_handoff_image_id = RMM_IMAGE_ID, # else - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, # endif - }, + }, /* Fill HW_CONFIG related information */ - { - .image_id = HW_CONFIG_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + { + .image_id = HW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, + NON_SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* Fill SOC_FW_CONFIG related information */ - { - .image_id = SOC_FW_CONFIG_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + { + .image_id = SOC_FW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, # if ENABLE_RME /* Fill RMM related information */ - { - .image_id = RMM_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, EP_REALM | EXECUTABLE), - .ep_info.pc = RMM_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = RMM_BASE, - .image_info.image_max_size = RMM_LIMIT - RMM_BASE, - .next_handoff_image_id = BL33_IMAGE_ID, - }, + { + .image_id = RMM_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, EP_REALM | EXECUTABLE), + .ep_info.pc = RMM_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = RMM_BASE, + .image_info.image_max_size = RMM_LIMIT - RMM_BASE, + .next_handoff_image_id = BL33_IMAGE_ID, + }, # endif # ifdef BL32_BASE /* Fill BL32 related information */ - { - .image_id = BL32_IMAGE_ID, + { + .image_id = BL32_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), - .ep_info.pc = BL32_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, # if ENABLE_RME - .next_handoff_image_id = RMM_IMAGE_ID, + .next_handoff_image_id = RMM_IMAGE_ID, # else - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, # endif - }, + }, /* * Fill BL32 external 1 related information. - * A typical use for extra1 image is with OP-TEE where it is the pager image. + * A typical use for extra1 image is with OP-TEE where it is the pager + * image. */ - { - .image_id = BL32_EXTRA1_IMAGE_ID, + { + .image_id = BL32_EXTRA1_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* * Fill BL32 external 2 related information. - * A typical use for extra2 image is with OP-TEE where it is the paged image. + * A typical use for extra2 image is with OP-TEE where it is the paged + * image. */ - { - .image_id = BL32_EXTRA2_IMAGE_ID, + { + .image_id = BL32_EXTRA2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), #ifdef SPD_opteed - .image_info.image_base = ARM_OPTEE_PAGEABLE_LOAD_BASE, - .image_info.image_max_size = ARM_OPTEE_PAGEABLE_LOAD_SIZE, + .image_info.image_base = ARM_OPTEE_PAGEABLE_LOAD_BASE, + .image_info.image_max_size = ARM_OPTEE_PAGEABLE_LOAD_SIZE, #endif - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* Fill TOS_FW_CONFIG related information */ - { - .image_id = TOS_FW_CONFIG_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + { + .image_id = TOS_FW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, # endif /* BL32_BASE */ /* Fill BL33 related information */ - { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), # ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, + .ep_info.pc = PRELOADED_BL33_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), # else - .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, + .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, - .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE - - PLAT_ARM_NS_IMAGE_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, + .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE + - PLAT_ARM_NS_IMAGE_BASE, # endif /* PRELOADED_BL33_BASE */ - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* Fill NT_FW_CONFIG related information */ - { - .image_id = NT_FW_CONFIG_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - } + { + .image_id = NT_FW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, + NON_SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + } #endif /* EL3_PAYLOAD_BASE */ }; diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index 7a9e04d0c..70002362d 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -11,6 +11,7 @@ #include <arch.h> #include <bl1/bl1.h> #include <common/bl_common.h> +#include <common/debug.h> #include <lib/fconf/fconf.h> #include <lib/fconf/fconf_dyn_cfg_getter.h> #include <lib/utils.h> diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index a6f7df5f4..cf403b161 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -164,6 +164,14 @@ void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_confi bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +#if ENABLE_RME + /* + * Populate entry point information for RMM. + * Only PC needs to be set as other fields are determined by RMMD. + */ + rmm_image_ep_info.pc = RMM_BASE; +#endif /* ENABLE_RME */ + #else /* RESET_TO_BL31 */ /* diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 946b7329f..fc681149e 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -237,3 +237,7 @@ int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) } #endif +const mmap_region_t *plat_get_addr_mmap(void) +{ + return plat_arm_mmap; +} diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 6d7aa2df5..7162ce984 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -73,6 +73,14 @@ ARM_BL31_IN_DRAM := 0 $(eval $(call assert_boolean,ARM_BL31_IN_DRAM)) $(eval $(call add_define,ARM_BL31_IN_DRAM)) +# As per CCA security model, all root firmware must execute from on-chip secure +# memory. This means we must not run BL31 from TZC-protected DRAM. +ifeq (${ARM_BL31_IN_DRAM},1) + ifeq (${ENABLE_RME},1) + $(error "BL31 must not run from DRAM on RME-systems. Please set ARM_BL31_IN_DRAM to 0") + endif +endif + # Process ARM_PLAT_MT flag ARM_PLAT_MT := 0 $(eval $(call assert_boolean,ARM_PLAT_MT)) @@ -106,7 +114,7 @@ ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) endif endif -# Arm Ethos-N NPU SiP service +# Arm(R) Ethos(TM)-N NPU SiP service ARM_ETHOSN_NPU_DRIVER := 0 $(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER)) $(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER)) @@ -187,8 +195,10 @@ endif # Enable CRC instructions via extension for ARMv8-A CPUs. # For ARMv8.1-A, and onwards CRC instructions are default enabled. # Enable HW computed CRC support unconditionally in BL2 component. -ifeq (${ARM_ARCH_MINOR},0) - BL2_CPPFLAGS += -march=armv8-a+crc +ifeq (${ARM_ARCH_MAJOR},8) + ifeq (${ARM_ARCH_MINOR},0) + BL2_CPPFLAGS += -march=armv8-a+crc + endif endif ifeq ($(PSA_FWU_SUPPORT),1) @@ -355,6 +365,10 @@ BL31_SOURCES += plat/common/plat_spmd_manifest.c \ BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} endif +ifeq (${DRTM_SUPPORT},1) +BL31_SOURCES += plat/arm/common/arm_err.c +endif + ifneq (${TRUSTED_BOARD_BOOT},0) # Include common TBB sources @@ -373,6 +387,8 @@ ifneq (${TRUSTED_BOARD_BOOT},0) endif else ifeq (${COT},dualroot) AUTH_SOURCES += drivers/auth/dualroot/cot.c + else ifeq (${COT},cca) + AUTH_SOURCES += drivers/auth/cca/cot.c else $(error Unknown chain of trust ${COT}) endif @@ -396,20 +412,31 @@ endif # Include Measured Boot makefile before any Crypto library makefile. # Crypto library makefile may need default definitions of Measured Boot build # flags present in Measured Boot makefile. -ifeq (${MEASURED_BOOT},1) +ifneq ($(filter 1,${MEASURED_BOOT} ${DRTM_SUPPORT}),) MEASURED_BOOT_MK := drivers/measured_boot/event_log/event_log.mk $(info Including ${MEASURED_BOOT_MK}) include ${MEASURED_BOOT_MK} - BL1_SOURCES += ${EVENT_LOG_SOURCES} - BL2_SOURCES += ${EVENT_LOG_SOURCES} + ifneq (${MBOOT_EL_HASH_ALG}, sha256) + $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) + endif + + ifeq (${MEASURED_BOOT},1) + BL1_SOURCES += ${EVENT_LOG_SOURCES} + BL2_SOURCES += ${EVENT_LOG_SOURCES} + endif + + ifeq (${DRTM_SUPPORT},1) + BL31_SOURCES += ${EVENT_LOG_SOURCES} + endif endif -ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT}),) +ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT} ${DRTM_SUPPORT}),) CRYPTO_SOURCES := drivers/auth/crypto_mod.c \ lib/fconf/fconf_tbbr_getter.c BL1_SOURCES += ${CRYPTO_SOURCES} BL2_SOURCES += ${CRYPTO_SOURCES} + BL31_SOURCES += drivers/auth/crypto_mod.c # We expect to locate the *.mk files under the directories specified below ifeq (${ARM_CRYPTOCELL_INTEG},0) diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c index 83e3f9aa2..c88621e37 100644 --- a/plat/arm/common/arm_dyn_cfg.c +++ b/plat/arm/common/arm_dyn_cfg.c @@ -45,7 +45,7 @@ int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size) assert(heap_addr != NULL); assert(heap_size != NULL); -#if defined(IMAGE_BL1) || BL2_AT_EL3 +#if defined(IMAGE_BL1) || BL2_AT_EL3 || defined(IMAGE_BL31) /* If in BL1 or BL2_AT_EL3 define a heap */ static unsigned char heap[TF_MBEDTLS_HEAP_SIZE]; @@ -131,6 +131,7 @@ void arm_bl2_dyn_cfg_init(void) bl_mem_params_node_t *cfg_mem_params = NULL; uintptr_t image_base; uint32_t image_size; + unsigned int error_config_id = MAX_IMAGE_IDS; const unsigned int config_ids[] = { HW_CONFIG_ID, SOC_FW_CONFIG_ID, @@ -142,17 +143,17 @@ void arm_bl2_dyn_cfg_init(void) /* Iterate through all the fw config IDs */ for (i = 0; i < ARRAY_SIZE(config_ids); i++) { - /* Get the config load address and size from TB_FW_CONFIG */ + /* Get the config load address and size */ cfg_mem_params = get_bl_mem_params_node(config_ids[i]); if (cfg_mem_params == NULL) { - VERBOSE("%sHW_CONFIG in bl_mem_params_node\n", - "Couldn't find "); + VERBOSE("%sconfig_id = %d in bl_mem_params_node\n", + "Couldn't find ", config_ids[i]); continue; } dtb_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, config_ids[i]); if (dtb_info == NULL) { - VERBOSE("%sconfig_id %d load info in TB_FW_CONFIG\n", + VERBOSE("%sconfig_id %d load info in FW_CONFIG\n", "Couldn't find ", config_ids[i]); continue; } @@ -168,17 +169,32 @@ void arm_bl2_dyn_cfg_init(void) if (config_ids[i] != HW_CONFIG_ID) { if (check_uptr_overflow(image_base, image_size)) { + VERBOSE("%s=%d as its %s is overflowing uptr\n", + "skip loading of firmware config", + config_ids[i], + "load-address"); + error_config_id = config_ids[i]; continue; } #ifdef BL31_BASE /* Ensure the configs don't overlap with BL31 */ if ((image_base >= BL31_BASE) && (image_base <= BL31_LIMIT)) { + VERBOSE("%s=%d as its %s is overlapping BL31\n", + "skip loading of firmware config", + config_ids[i], + "load-address"); + error_config_id = config_ids[i]; continue; } #endif /* Ensure the configs are loaded in a valid address */ if (image_base < ARM_BL_RAM_BASE) { + VERBOSE("%s=%d as its %s is invalid\n", + "skip loading of firmware config", + config_ids[i], + "load-address"); + error_config_id = config_ids[i]; continue; } #ifdef BL32_BASE @@ -188,6 +204,11 @@ void arm_bl2_dyn_cfg_init(void) */ if ((image_base >= BL32_BASE) && (image_base <= BL32_LIMIT)) { + VERBOSE("%s=%d as its %s is overlapping BL32\n", + "skip loading of firmware config", + config_ids[i], + "load-address"); + error_config_id = config_ids[i]; continue; } #endif @@ -202,4 +223,9 @@ void arm_bl2_dyn_cfg_init(void) */ cfg_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; } + + if (error_config_id != MAX_IMAGE_IDS) { + ERROR("Invalid config file %u\n", error_config_id); + panic(); + } } diff --git a/plat/arm/common/arm_dyn_cfg_helpers.c b/plat/arm/common/arm_dyn_cfg_helpers.c index 6a2a6f89a..e88ea657f 100644 --- a/plat/arm/common/arm_dyn_cfg_helpers.c +++ b/plat/arm/common/arm_dyn_cfg_helpers.c @@ -6,6 +6,7 @@ #include <assert.h> +#include <common/debug.h> #if MEASURED_BOOT #include <common/desc_image_load.h> #endif diff --git a/plat/arm/common/arm_err.c b/plat/arm/common/arm_err.c index f80ba78c7..fa36e8d3a 100644 --- a/plat/arm/common/arm_err.c +++ b/plat/arm/common/arm_err.c @@ -13,3 +13,8 @@ void __dead2 plat_error_handler(int err) { plat_arm_error_handler(err); } + +void __dead2 plat_system_reset(void) +{ + plat_arm_system_reset(); +} diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index 4a3a22ec0..469e22ade 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -7,6 +7,7 @@ #include <assert.h> #include <platform_def.h> +#include <common/debug.h> #include <common/interrupt_props.h> #include <drivers/arm/gicv3.h> #include <lib/utils.h> diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c index aea2f38d4..6c323312c 100644 --- a/plat/arm/common/fconf/arm_fconf_io.c +++ b/plat/arm/common/fconf/arm_fconf_io.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, ARM Limited. All rights reserved. + * Copyright (c) 2019-2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -72,6 +72,9 @@ const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = { #if TRUSTED_BOARD_BOOT [TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT}, #if !ARM_IO_IN_DTB + [CCA_CONTENT_CERT_ID] = {UUID_CCA_CONTENT_CERT}, + [CORE_SWD_KEY_CERT_ID] = {UUID_CORE_SWD_KEY_CERT}, + [PLAT_KEY_CERT_ID] = {UUID_PLAT_KEY_CERT}, [TRUSTED_KEY_CERT_ID] = {UUID_TRUSTED_KEY_CERT}, [SCP_FW_KEY_CERT_ID] = {UUID_SCP_FW_KEY_CERT}, [SOC_FW_KEY_CERT_ID] = {UUID_SOC_FW_KEY_CERT}, @@ -196,6 +199,21 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { open_fip }, #if !ARM_IO_IN_DTB + [CCA_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[CCA_CONTENT_CERT_ID], + open_fip + }, + [CORE_SWD_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[CORE_SWD_KEY_CERT_ID], + open_fip + }, + [PLAT_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[PLAT_KEY_CERT_ID], + open_fip + }, [TRUSTED_KEY_CERT_ID] = { &fip_dev_handle, (uintptr_t)&arm_uuid_spec[TRUSTED_KEY_CERT_ID], @@ -260,7 +278,7 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { #ifdef IMAGE_BL2 #if TRUSTED_BOARD_BOOT -#define FCONF_ARM_IO_UUID_NUMBER U(21) +#define FCONF_ARM_IO_UUID_NUMBER U(24) #else #define FCONF_ARM_IO_UUID_NUMBER U(10) #endif @@ -286,6 +304,9 @@ static const struct policies_load_info load_info[FCONF_ARM_IO_UUID_NUMBER] = { {TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"}, {NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"}, #if TRUSTED_BOARD_BOOT + {CCA_CONTENT_CERT_ID, "cca_cert_uuid"}, + {CORE_SWD_KEY_CERT_ID, "core_swd_cert_uuid"}, + {PLAT_KEY_CERT_ID, "plat_cert_uuid"}, {TRUSTED_KEY_CERT_ID, "t_key_cert_uuid"}, {SCP_FW_KEY_CERT_ID, "scp_fw_key_uuid"}, {SOC_FW_KEY_CERT_ID, "soc_fw_key_uuid"}, diff --git a/plat/arm/common/fconf/fconf_ethosn_getter.c b/plat/arm/common/fconf/fconf_ethosn_getter.c index 0af1a20fb..0b48a9816 100644 --- a/plat/arm/common/fconf/fconf_ethosn_getter.c +++ b/plat/arm/common/fconf/fconf_ethosn_getter.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,107 +12,341 @@ #include <libfdt.h> #include <plat/arm/common/fconf_ethosn_getter.h> -struct ethosn_config_t ethosn_config = {.num_cores = 0}; +struct ethosn_config_t ethosn_config = {0}; -static uint8_t fdt_node_get_status(const void *fdt, int node) +struct ethosn_sub_allocator_t { + const char *name; + size_t name_len; + uint32_t stream_id; +}; + +static bool fdt_node_is_enabled(const void *fdt, int node) { int len; - uint8_t status = ETHOSN_STATUS_DISABLED; const char *node_status; node_status = fdt_getprop(fdt, node, "status", &len); if (node_status == NULL || (len == 5 && /* Includes null character */ strncmp(node_status, "okay", 4U) == 0)) { - status = ETHOSN_STATUS_ENABLED; + return true; + } + + return false; +} + +static bool fdt_node_has_reserved_memory(const void *fdt, int dev_node) +{ + return fdt_get_property(fdt, dev_node, "memory-region", NULL) != NULL; +} + +static int fdt_node_get_iommus_stream_id(const void *fdt, int node, uint32_t *stream_id) +{ + int err; + uint32_t iommus_array[2] = {0U}; + + err = fdt_read_uint32_array(fdt, node, "iommus", 2U, iommus_array); + if (err) { + return err; + } + + *stream_id = iommus_array[1]; + return 0; +} + +static int fdt_node_populate_sub_allocators(const void *fdt, + int alloc_node, + struct ethosn_sub_allocator_t *sub_allocators, + size_t num_allocs) +{ + int sub_node; + size_t i; + int err = -FDT_ERR_NOTFOUND; + uint32_t found_sub_allocators = 0U; + + fdt_for_each_subnode(sub_node, fdt, alloc_node) { + const char *node_name; + + if (!fdt_node_is_enabled(fdt, sub_node)) { + /* Ignore disabled node */ + continue; + } + + if (fdt_node_check_compatible(fdt, sub_node, "ethosn-memory") != 0) { + continue; + } + + node_name = fdt_get_name(fdt, sub_node, NULL); + for (i = 0U; i < num_allocs; ++i) { + if (strncmp(node_name, sub_allocators[i].name, + sub_allocators[i].name_len) != 0) { + continue; + } + + err = fdt_node_get_iommus_stream_id(fdt, sub_node, + &sub_allocators[i].stream_id); + if (err) { + ERROR("FCONF: Failed to get stream ID from sub-allocator %s\n", + node_name); + return err; + } + + ++found_sub_allocators; + /* Nothing more to do for this node */ + break; + } + + /* Check that at least one of the sub-allocators matched */ + if (i == num_allocs) { + ERROR("FCONF: Unknown sub-allocator %s\n", node_name); + return -FDT_ERR_BADSTRUCTURE; + } + } + + if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) { + ERROR("FCONF: Failed to parse sub-allocators\n"); + return -FDT_ERR_BADSTRUCTURE; + } + + if (err == -FDT_ERR_NOTFOUND) { + ERROR("FCONF: No matching sub-allocator found\n"); + return err; + } + + if (found_sub_allocators != num_allocs) { + ERROR("FCONF: Not all sub-allocators were found\n"); + return -FDT_ERR_BADSTRUCTURE; + } + + return 0; +} + +static int fdt_node_populate_main_allocator(const void *fdt, + int alloc_node, + struct ethosn_main_allocator_t *allocator) +{ + int err; + struct ethosn_sub_allocator_t sub_allocators[] = { + {.name = "firmware", .name_len = 8U}, + {.name = "working_data", .name_len = 12U} + }; + + err = fdt_node_populate_sub_allocators(fdt, alloc_node, sub_allocators, + ARRAY_SIZE(sub_allocators)); + if (err) { + return err; + } + + allocator->firmware.stream_id = sub_allocators[0].stream_id; + allocator->working_data.stream_id = sub_allocators[1].stream_id; + + return 0; +} + +static int fdt_node_populate_asset_allocator(const void *fdt, + int alloc_node, + struct ethosn_asset_allocator_t *allocator) +{ + int err; + struct ethosn_sub_allocator_t sub_allocators[] = { + {.name = "command_stream", .name_len = 14U}, + {.name = "weight_data", .name_len = 11U}, + {.name = "buffer_data", .name_len = 11U}, + {.name = "intermediate_data", .name_len = 17U} + }; + + err = fdt_node_populate_sub_allocators(fdt, alloc_node, sub_allocators, + ARRAY_SIZE(sub_allocators)); + if (err) { + return err; } - return status; + + allocator->command_stream.stream_id = sub_allocators[0].stream_id; + allocator->weight_data.stream_id = sub_allocators[1].stream_id; + allocator->buffer_data.stream_id = sub_allocators[2].stream_id; + allocator->intermediate_data.stream_id = sub_allocators[3].stream_id; + return 0; +} + +static int fdt_node_populate_core(const void *fdt, + int device_node, + int core_node, + bool has_reserved_memory, + uint32_t core_index, + struct ethosn_core_t *core) +{ + int err; + int sub_node; + uintptr_t core_addr; + + err = fdt_get_reg_props_by_index(fdt, device_node, core_index, + &core_addr, NULL); + if (err < 0) { + ERROR("FCONF: Failed to read reg property for NPU core %u\n", + core_index); + return err; + } + + err = -FDT_ERR_NOTFOUND; + fdt_for_each_subnode(sub_node, fdt, core_node) { + + if (!fdt_node_is_enabled(fdt, sub_node)) { + continue; + } + + if (fdt_node_check_compatible(fdt, + sub_node, + "ethosn-main_allocator") != 0) { + continue; + } + + if (has_reserved_memory) { + ERROR("FCONF: Main allocator not supported when using reserved memory\n"); + return -FDT_ERR_BADSTRUCTURE; + } + + if (err != -FDT_ERR_NOTFOUND) { + ERROR("FCONF: NPU core 0x%lx has more than one main allocator\n", + core_addr); + return -FDT_ERR_BADSTRUCTURE; + } + + err = fdt_node_populate_main_allocator(fdt, sub_node, &core->main_allocator); + if (err) { + ERROR("FCONF: Failed to parse main allocator for NPU core 0x%lx\n", + core_addr); + return err; + } + } + + if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) { + ERROR("FCONF: Failed to parse core sub nodes\n"); + return -FDT_ERR_BADSTRUCTURE; + } + + if (!has_reserved_memory && err) { + ERROR("FCONF: Main allocator not found for NPU core 0x%lx\n", + core_addr); + return err; + } + + core->addr = core_addr; + + return 0; } int fconf_populate_ethosn_config(uintptr_t config) { int ethosn_node; + uint32_t dev_count = 0U; const void *hw_conf_dtb = (const void *)config; - /* Find offset to node with 'ethosn' compatible property */ - INFO("Probing Arm Ethos-N NPU\n"); - uint32_t total_core_count = 0U; + INFO("Probing Arm(R) Ethos(TM)-N NPU\n"); fdt_for_each_compatible_node(hw_conf_dtb, ethosn_node, "ethosn") { + struct ethosn_device_t *dev = ðosn_config.devices[dev_count]; + uint32_t dev_asset_alloc_count = 0U; + uint32_t dev_core_count = 0U; + bool has_reserved_memory; int sub_node; - uint8_t ethosn_status; - uint32_t device_core_count = 0U; - /* If the Arm Ethos-N NPU is disabled the core check can be skipped */ - ethosn_status = fdt_node_get_status(hw_conf_dtb, ethosn_node); - if (ethosn_status == ETHOSN_STATUS_DISABLED) { + if (!fdt_node_is_enabled(hw_conf_dtb, ethosn_node)) { continue; } + if (dev_count >= ETHOSN_DEV_NUM_MAX) { + ERROR("FCONF: Reached max number of NPUs\n"); + return -FDT_ERR_BADSTRUCTURE; + } + + has_reserved_memory = fdt_node_has_reserved_memory(hw_conf_dtb, ethosn_node); fdt_for_each_subnode(sub_node, hw_conf_dtb, ethosn_node) { int err; - uintptr_t core_addr; - uint8_t core_status; - if (total_core_count >= ETHOSN_CORE_NUM_MAX) { - ERROR("FCONF: Reached max number of Arm Ethos-N NPU cores\n"); - return -FDT_ERR_BADSTRUCTURE; + if (!fdt_node_is_enabled(hw_conf_dtb, sub_node)) { + /* Ignore disabled sub node */ + continue; } - /* Check that the sub node is "ethosn-core" compatible */ if (fdt_node_check_compatible(hw_conf_dtb, sub_node, - "ethosn-core") != 0) { - /* Ignore incompatible sub node */ - continue; - } + "ethosn-core") == 0) { - core_status = fdt_node_get_status(hw_conf_dtb, sub_node); - if (core_status == ETHOSN_STATUS_DISABLED) { - continue; - } + if (dev_core_count >= ETHOSN_DEV_CORE_NUM_MAX) { + ERROR("FCONF: Reached max number of NPU cores for NPU %u\n", + dev_count); + return -FDT_ERR_BADSTRUCTURE; + } - err = fdt_get_reg_props_by_index(hw_conf_dtb, - ethosn_node, - device_core_count, - &core_addr, - NULL); - if (err < 0) { - ERROR( - "FCONF: Failed to read reg property for Arm Ethos-N NPU core %u\n", - device_core_count); - return err; - } + err = fdt_node_populate_core(hw_conf_dtb, + ethosn_node, + sub_node, + has_reserved_memory, + dev_core_count, + &(dev->cores[dev_core_count])); + if (err) { + return err; + } + ++dev_core_count; + } else if (fdt_node_check_compatible(hw_conf_dtb, + sub_node, + "ethosn-asset_allocator") == 0) { + + if (dev_asset_alloc_count >= + ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX) { + ERROR("FCONF: Reached max number of asset allocators for NPU %u\n", + dev_count); + return -FDT_ERR_BADSTRUCTURE; + } + + if (has_reserved_memory) { + ERROR("FCONF: Asset allocator not supported when using reserved memory\n"); + return -FDT_ERR_BADSTRUCTURE; + } - INFO("NPU core probed at address 0x%lx\n", core_addr); - ethosn_config.core[total_core_count].addr = core_addr; - total_core_count++; - device_core_count++; + err = fdt_node_populate_asset_allocator(hw_conf_dtb, + sub_node, + &(dev->asset_allocators[dev_asset_alloc_count])); + if (err) { + ERROR("FCONF: Failed to parse asset allocator for NPU %u\n", + dev_count); + return err; + } + ++dev_asset_alloc_count; + } } if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) { - ERROR("FCONF: Failed to parse sub nodes\n"); + ERROR("FCONF: Failed to parse sub nodes for NPU %u\n", + dev_count); + return -FDT_ERR_BADSTRUCTURE; + } + + if (dev_core_count == 0U) { + ERROR("FCONF: NPU %u must have at least one enabled core\n", + dev_count); return -FDT_ERR_BADSTRUCTURE; } - if (device_core_count == 0U) { - ERROR( - "FCONF: Enabled Arm Ethos-N NPU device must have at least one enabled core\n"); + if (!has_reserved_memory && dev_asset_alloc_count == 0U) { + ERROR("FCONF: NPU %u must have at least one asset allocator\n", + dev_count); return -FDT_ERR_BADSTRUCTURE; } + + dev->num_cores = dev_core_count; + dev->num_allocators = dev_asset_alloc_count; + dev->has_reserved_memory = has_reserved_memory; + ++dev_count; } - if (total_core_count == 0U) { + if (dev_count == 0U) { ERROR("FCONF: Can't find 'ethosn' compatible node in dtb\n"); return -FDT_ERR_BADSTRUCTURE; } - ethosn_config.num_cores = total_core_count; - - INFO("%d NPU core%s probed\n", - ethosn_config.num_cores, - ethosn_config.num_cores > 1 ? "s" : ""); + ethosn_config.num_devices = dev_count; return 0; } diff --git a/plat/arm/common/trp/arm_trp.mk b/plat/arm/common/trp/arm_trp.mk index 997111f99..204c14ac1 100644 --- a/plat/arm/common/trp/arm_trp.mk +++ b/plat/arm/common/trp/arm_trp.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -8,3 +8,5 @@ RMM_SOURCES += plat/arm/common/trp/arm_trp_setup.c \ plat/arm/common/arm_topology.c \ plat/common/aarch64/platform_mp_stack.S + +INCLUDES += -Iinclude/services/trp diff --git a/plat/arm/common/trp/arm_trp_setup.c b/plat/arm/common/trp/arm_trp_setup.c index 8e4829344..59b4c06e9 100644 --- a/plat/arm/common/trp/arm_trp_setup.c +++ b/plat/arm/common/trp/arm_trp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,33 +8,65 @@ #include <common/debug.h> #include <drivers/arm/pl011.h> #include <drivers/console.h> +#include <services/rmm_core_manifest.h> +#include <services/rmmd_svc.h> +#include <services/trp/platform_trp.h> +#include <trp_helpers.h> + #include <plat/arm/common/plat_arm.h> #include <platform_def.h> /******************************************************************************* + * Received from boot manifest and populated here + ******************************************************************************/ +extern uint32_t trp_boot_manifest_version; + +/******************************************************************************* * Initialize the UART ******************************************************************************/ static console_t arm_trp_runtime_console; -void arm_trp_early_platform_setup(void) +static int arm_trp_process_manifest(rmm_manifest_t *manifest) +{ + /* Verify the Boot Manifest Version. Only the Major is considered */ + if (RMMD_MANIFEST_VERSION_MAJOR != + RMMD_GET_MANIFEST_VERSION_MAJOR(manifest->version)) { + return E_RMM_BOOT_MANIFEST_VERSION_NOT_SUPPORTED; + } + + trp_boot_manifest_version = manifest->version; + flush_dcache_range((uintptr_t)manifest, sizeof(rmm_manifest_t)); + + return 0; +} + +void arm_trp_early_platform_setup(rmm_manifest_t *manifest) { + int rc; + + rc = arm_trp_process_manifest(manifest); + if (rc != 0) { + trp_boot_abort(rc); + } + /* * Initialize a different console than already in use to display * messages from trp */ - int rc = console_pl011_register(PLAT_ARM_TRP_UART_BASE, - PLAT_ARM_TRP_UART_CLK_IN_HZ, - ARM_CONSOLE_BAUDRATE, - &arm_trp_runtime_console); + rc = console_pl011_register(PLAT_ARM_TRP_UART_BASE, + PLAT_ARM_TRP_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE, + &arm_trp_runtime_console); if (rc == 0) { panic(); } console_set_scope(&arm_trp_runtime_console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); + } -void trp_early_platform_setup(void) +void trp_early_platform_setup(rmm_manifest_t *manifest) { - arm_trp_early_platform_setup(); + arm_trp_early_platform_setup(manifest); } diff --git a/plat/arm/css/common/css_common.mk b/plat/arm/css/common/css_common.mk index 2fbbe4560..1e4851cd4 100644 --- a/plat/arm/css/common/css_common.mk +++ b/plat/arm/css/common/css_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -35,6 +35,7 @@ BL31_SOURCES += drivers/arm/css/mhu/css_mhu_doorbell.c \ drivers/arm/css/scmi/scmi_common.c \ drivers/arm/css/scmi/scmi_pwr_dmn_proto.c \ drivers/arm/css/scmi/scmi_sys_pwr_proto.c \ + drivers/delay_timer/delay_timer.c \ drivers/arm/css/scp/css_pm_scmi.c endif @@ -88,3 +89,9 @@ CSS_NON_SECURE_UART := 0 $(eval $(call assert_boolean,CSS_NON_SECURE_UART)) $(eval $(call add_define,CSS_NON_SECURE_UART)) +# Process CSS_SYSTEM_GRACEFUL_RESET flag +# This build option can be used on CSS platforms that require all the CPUs +# to execute the CPU specific power down sequence to complete a warm reboot +# sequence in which only the CPUs are power cycled. +CSS_SYSTEM_GRACEFUL_RESET := 0 +$(eval $(call add_define,CSS_SYSTEM_GRACEFUL_RESET)) diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c index 926b8ec7c..9b2639c35 100644 --- a/plat/arm/css/common/css_pm.c +++ b/plat/arm/css/common/css_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,10 +9,14 @@ #include <platform_def.h> #include <arch_helpers.h> +#include <bl31/interrupt_mgmt.h> #include <common/debug.h> #include <drivers/arm/css/css_scp.h> #include <lib/cassert.h> #include <plat/arm/common/plat_arm.h> + +#include <plat/common/platform.h> + #include <plat/arm/css/common/css_pm.h> /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ @@ -110,6 +114,9 @@ void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state) /* Enable the gic cpu interface */ plat_arm_gic_cpuif_enable(); + + /* Setup the CPU power down request interrupt for secondary core(s) */ + css_setup_cpu_pwr_down_intr(); } /******************************************************************************* @@ -331,6 +338,52 @@ static int css_translate_power_state_by_mpidr(u_register_t mpidr, return arm_validate_power_state(power_state, output_state); } +/* + * Setup the SGI interrupt that will be used trigger the execution of power + * down sequence for all the secondary cores. This interrupt is setup to be + * handled in EL3 context at a priority defined by the platform. + */ +void css_setup_cpu_pwr_down_intr(void) +{ +#if CSS_SYSTEM_GRACEFUL_RESET + plat_ic_set_interrupt_type(CSS_CPU_PWR_DOWN_REQ_INTR, INTR_TYPE_EL3); + plat_ic_set_interrupt_priority(CSS_CPU_PWR_DOWN_REQ_INTR, + PLAT_REBOOT_PRI); + plat_ic_enable_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR); +#endif +} + +/* + * For a graceful shutdown/reboot, each CPU in the system should do their power + * down sequence. On a PSCI shutdown/reboot request, only one CPU gets an + * opportunity to do the powerdown sequence. To achieve graceful reset, of all + * cores in the system, the CPU gets the opportunity raise warm reboot SGI to + * rest of the CPUs which are online. Add handler for the reboot SGI where the + * rest of the CPU execute the powerdown sequence. + */ +int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags, + void *handle, void *cookie) +{ + assert(intr_raw == CSS_CPU_PWR_DOWN_REQ_INTR); + + /* Deactivate warm reboot SGI */ + plat_ic_end_of_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR); + + /* + * Disable GIC CPU interface to prevent pending interrupt from waking + * up the AP from WFI. + */ + plat_arm_gic_cpuif_disable(); + plat_arm_gic_redistif_off(); + + psci_pwrdown_cpu(PLAT_MAX_PWR_LVL); + + dmbsy(); + + wfi(); + return 0; +} + /******************************************************************************* * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard * platform will take care of registering the handlers with PSCI. diff --git a/plat/arm/css/common/sp_min/css_sp_min.mk b/plat/arm/css/common/sp_min/css_sp_min.mk index 6523a164b..ae489fdf8 100644 --- a/plat/arm/css/common/sp_min/css_sp_min.mk +++ b/plat/arm/css/common/sp_min/css_sp_min.mk @@ -15,6 +15,7 @@ BL32_SOURCES += drivers/arm/css/mhu/css_mhu.c \ else BL32_SOURCES += drivers/arm/css/mhu/css_mhu_doorbell.c \ drivers/arm/css/scp/css_pm_scmi.c \ + drivers/delay_timer/delay_timer.c \ drivers/arm/css/scmi/scmi_common.c \ drivers/arm/css/scmi/scmi_pwr_dmn_proto.c \ drivers/arm/css/scmi/scmi_sys_pwr_proto.c diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index c9c8c0463..c1fadc654 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,10 +19,11 @@ CSS_SGI_MAX_CPUS_PER_CLUSTER * \ CSS_SGI_MAX_PE_PER_CPU) -#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ +#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ -/* Remote chip address offset (4TB per chip) */ -#define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) ((ULL(1) << 42) * (n)) +/* Remote chip address offset */ +#define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) \ + ((ULL(1) << CSS_SGI_ADDR_BITS_PER_CHIP) * (n)) /* * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the @@ -35,8 +36,8 @@ # if SPM_MM # define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) -# define PLAT_SP_IMAGE_MMAP_REGIONS 9 -# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 11 +# define PLAT_SP_IMAGE_MMAP_REGIONS 10 +# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 # else # define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) @@ -67,7 +68,7 @@ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size * plus a little space for growth. */ -#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 +#define PLAT_ARM_MAX_BL1_RW_SIZE (64 * 1024) /* 64 KB */ /* * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page @@ -98,10 +99,16 @@ /* * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is - * calculated using the current BL31 PROGBITS debug size plus the sizes of - * BL2 and BL1-RW + * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2 + * and BL1-RW. CSS_SGI_BL31_SIZE - is tuned with respect to the actual BL31 + * PROGBITS size which is around 64-68KB at the time this change is being made. + * A buffer of ~35KB is added to account for future expansion of the image, + * making it a total of 100KB. */ -#define PLAT_ARM_MAX_BL31_SIZE 0x3B000 +#define CSS_SGI_BL31_SIZE (100 * 1024) /* 100 KB */ +#define PLAT_ARM_MAX_BL31_SIZE (CSS_SGI_BL31_SIZE + \ + PLAT_ARM_MAX_BL2_SIZE + \ + PLAT_ARM_MAX_BL1_RW_SIZE) /* * Size of cacheable stacks @@ -130,6 +137,21 @@ # define PLATFORM_STACK_SIZE 0x440 #endif +/* PL011 UART related constants */ +#define SOC_CSS_SEC_UART_BASE UL(0x2A410000) +#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000) +#define SOC_CSS_UART_SIZE UL(0x10000) +#define SOC_CSS_UART_CLK_IN_HZ UL(7372800) + +/* UART related constants */ +#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ + +#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ + +#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ #define PLAT_ARM_NSTIMER_FRAME_ID 0 @@ -258,4 +280,21 @@ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \ ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} +#if SPM_MM + +/* + * Stand-alone MM logs would be routed via secure UART. Define page table + * entry for secure UART which would be common to all platforms. + */ +#define SOC_PLATFORM_SECURE_UART MAP_REGION_FLAT( \ + SOC_CSS_SEC_UART_BASE, \ + SOC_CSS_UART_SIZE, \ + MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER) + +#endif + +/* SDS ID for unusable CPU MPID list structure */ +#define SDS_ISOLATED_CPU_LIST_ID U(128) + #endif /* SGI_BASE_PLATFORM_DEF_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def.h b/plat/arm/css/sgi/include/sgi_soc_css_def.h new file mode 100644 index 000000000..f78b45a28 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_soc_css_def.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_SOC_CSS_DEF_H +#define SGI_SOC_CSS_DEF_H + +#include <lib/utils_def.h> +#include <plat/arm/board/common/v2m_def.h> +#include <plat/arm/soc/common/soc_css_def.h> +#include <plat/common/common_def.h> + +/* + * Definitions common to all ARM CSSv1-based development platforms + */ + +/* Platform ID address */ +#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x7ffe00e0) + +/* Platform ID related accessors */ +#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f +#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 +#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 + +#ifndef __ASSEMBLER__ + +#include <lib/mmio.h> + +#define BOARD_CSS_GET_PLAT_TYPE(addr) \ + ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ + >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) + +#endif /* __ASSEMBLER__ */ + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/* Reserve the last block of flash for PSCI MEM PROTECT flag */ +#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE +#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +#endif /* SGI_SOC_CSS_DEF_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h index 639b687f1..acf31ebba 100644 --- a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h +++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,17 +24,10 @@ #define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000) -/* PL011 UART related constants */ -#define SOC_CSS_UART1_BASE UL(0x0ef80000) -#define SOC_CSS_UART0_BASE UL(0x0ef70000) - /* Memory controller */ #define SOC_MEMCNTRL_BASE UL(0x10000000) #define SOC_MEMCNTRL_SIZE UL(0x10000000) -#define SOC_CSS_UART0_CLK_IN_HZ UL(7372800) -#define SOC_CSS_UART1_CLK_IN_HZ UL(7372800) - /* SoC NIC-400 Global Programmers View (GPV) */ #define SOC_CSS_NIC400_BASE UL(0x0ED00000) @@ -206,17 +199,4 @@ #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) -/* UART related constants */ -#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE -#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ - -#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE -#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ - -#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE -#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ - -#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE -#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ - #endif /* SGI_SOC_CSS_DEF_V2_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_platform_def.h b/plat/arm/css/sgi/include/sgi_soc_platform_def.h index 405d62f12..3b8d9c664 100644 --- a/plat/arm/css/sgi/include/sgi_soc_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_soc_platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +7,10 @@ #ifndef SGI_SOC_PLATFORM_DEF_H #define SGI_SOC_PLATFORM_DEF_H -#include <sgi_base_platform_def.h> -#include <plat/arm/board/common/board_css_def.h> #include <plat/arm/board/common/v2m_def.h> #include <plat/arm/soc/common/soc_css_def.h> +#include <sgi_base_platform_def.h> +#include <sgi_soc_css_def.h> /* Map the System registers to access from S-EL0 */ #define CSS_SYSTEMREG_DEVICE_BASE (0x1C010000) diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h index 41467f7de..223ac3ecc 100644 --- a/plat/arm/css/sgi/include/sgi_variant.h +++ b/plat/arm/css/sgi/include/sgi_variant.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,9 +23,9 @@ /* SID Version values for RD-N2 variants */ #define RD_N2_CFG1_SID_VER_PART_NUM 0x07B6 -/* SID Version values for RD-Edmunds */ -#define RD_EDMUNDS_SID_VER_PART_NUM 0x07F2 -#define RD_EDMUNDS_CONFIG_ID 0x1 +/* SID Version values for RD-V2 */ +#define RD_V2_SID_VER_PART_NUM 0x07F2 +#define RD_V2_CONFIG_ID 0x1 /* Structure containing SGI platform variant information */ typedef struct sgi_platform_info { diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk index 76c8025ba..282a5f080 100644 --- a/plat/arm/css/sgi/sgi-common.mk +++ b/plat/arm/css/sgi/sgi-common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -14,7 +14,7 @@ SDEI_SUPPORT := 0 EL3_EXCEPTION_HANDLING := 0 -HANDLE_EA_EL3_FIRST := 0 +HANDLE_EA_EL3_FIRST_NS := 0 CSS_SGI_CHIP_COUNT := 1 @@ -44,7 +44,8 @@ PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/aarch64/sgi_helper.S BL1_SOURCES += ${INTERCONNECT_SOURCES} \ drivers/arm/sbsa/sbsa.c -BL2_SOURCES += ${CSS_ENT_BASE}/sgi_image_load.c +BL2_SOURCES += ${CSS_ENT_BASE}/sgi_image_load.c \ + drivers/arm/css/sds/sds.c BL31_SOURCES += ${INTERCONNECT_SOURCES} \ ${ENT_GIC_SOURCES} \ @@ -68,7 +69,6 @@ $(eval $(call add_define,CSS_SGI_PLATFORM_VARIANT)) override CSS_LOAD_SCP_IMAGES := 0 override NEED_BL2U := no -override ARM_BL31_IN_DRAM := 1 override ARM_PLAT_MT := 1 override PSCI_EXTENDED_STATE_ID := 1 override ARM_RECOM_STATE_ID_ENC := 1 diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c index 99f2f2002..27cf18346 100644 --- a/plat/arm/css/sgi/sgi_bl31_setup.c +++ b/plat/arm/css/sgi/sgi_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,8 +13,11 @@ #include <drivers/arm/css/css_mhu_doorbell.h> #include <drivers/arm/css/scmi.h> #include <plat/arm/common/plat_arm.h> + #include <plat/common/platform.h> +#include <plat/arm/css/common/css_pm.h> + #include <sgi_ras.h> #include <sgi_variant.h> @@ -76,7 +79,7 @@ scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id) if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM || sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM || sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM || - sgi_plat_info.platform_id == RD_EDMUNDS_SID_VER_PART_NUM || + sgi_plat_info.platform_id == RD_V2_SID_VER_PART_NUM || sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) { if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info)) panic(); @@ -105,6 +108,15 @@ void sgi_bl31_common_platform_setup(void) #if RAS_EXTENSION sgi_ras_intr_handler_setup(); #endif + + /* Configure the warm reboot SGI for primary core */ + css_setup_cpu_pwr_down_intr(); + +#if CSS_SYSTEM_GRACEFUL_RESET + /* Register priority level handlers for reboot */ + ehf_register_priority_handler(PLAT_REBOOT_PRI, + css_reboot_interrupt_handler); +#endif } const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) diff --git a/plat/arm/css/sgi/sgi_image_load.c b/plat/arm/css/sgi/sgi_image_load.c index 09f3b728d..ac4bfd292 100644 --- a/plat/arm/css/sgi/sgi_image_load.c +++ b/plat/arm/css/sgi/sgi_image_load.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,16 +9,68 @@ #include <arch_helpers.h> #include <common/debug.h> #include <common/desc_image_load.h> +#include <drivers/arm/css/sds.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> +#include <platform_def.h> +#include <sgi_base_platform_def.h> #include <sgi_variant.h> +/* + * Information about the isolated CPUs obtained from SDS. + */ +struct isolated_cpu_mpid_list { + uint64_t num_entries; /* Number of entries in the list */ + uint64_t mpid_list[PLATFORM_CORE_COUNT]; /* List of isolated CPU MPIDs */ +}; + +/* Function to read isolated CPU MPID list from SDS. */ +void plat_arm_sgi_get_isolated_cpu_list(struct isolated_cpu_mpid_list *list) +{ + int ret; + + ret = sds_init(); + if (ret != SDS_OK) { + ERROR("SDS initialization failed, error: %d\n", ret); + panic(); + } + + ret = sds_struct_read(SDS_ISOLATED_CPU_LIST_ID, 0, &list->num_entries, + sizeof(list->num_entries), SDS_ACCESS_MODE_CACHED); + if (ret != SDS_OK) { + INFO("SDS CPU num elements read failed, error: %d\n", ret); + list->num_entries = 0; + return; + } + + if (list->num_entries > PLATFORM_CORE_COUNT) { + ERROR("Isolated CPU list count %ld greater than max" + " number supported %d\n", + list->num_entries, PLATFORM_CORE_COUNT); + panic(); + } else if (list->num_entries == 0) { + INFO("SDS isolated CPU list is empty\n"); + return; + } + + ret = sds_struct_read(SDS_ISOLATED_CPU_LIST_ID, + sizeof(list->num_entries), + &list->mpid_list, + sizeof(list->mpid_list[0]) * list->num_entries, + SDS_ACCESS_MODE_CACHED); + if (ret != SDS_OK) { + ERROR("SDS CPU list read failed. error: %d\n", ret); + panic(); + } +} + /******************************************************************************* * This function inserts Platform information via device tree nodes as, * system-id { * platform-id = <0>; * config-id = <0>; + * isolated-cpu-list = <0> * } ******************************************************************************/ static int plat_sgi_append_config_node(void) @@ -27,6 +79,7 @@ static int plat_sgi_append_config_node(void) void *fdt; int nodeoffset, err; unsigned int platid = 0, platcfg = 0; + struct isolated_cpu_mpid_list cpu_mpid_list = {0}; mem_params = get_bl_mem_params_node(NT_FW_CONFIG_ID); if (mem_params == NULL) { @@ -69,6 +122,18 @@ static int plat_sgi_append_config_node(void) return -1; } + plat_arm_sgi_get_isolated_cpu_list(&cpu_mpid_list); + if (cpu_mpid_list.num_entries > 0) { + err = fdt_setprop(fdt, nodeoffset, "isolated-cpu-list", + &cpu_mpid_list, + (sizeof(cpu_mpid_list.num_entries) * + (cpu_mpid_list.num_entries + 1))); + if (err < 0) { + ERROR("Failed to set isolated-cpu-list, error: %d\n", + err); + } + } + flush_dcache_range((uintptr_t)fdt, mem_params->image_info.image_size); return 0; diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c index 20c52e9c5..a0199c348 100644 --- a/plat/arm/css/sgi/sgi_plat.c +++ b/plat/arm/css/sgi/sgi_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -89,6 +89,7 @@ const mmap_region_t plat_arm_mmap[] = { const mmap_region_t plat_arm_secure_partition_mmap[] = { PLAT_ARM_SECURE_MAP_SYSTEMREG, PLAT_ARM_SECURE_MAP_NOR2, + SOC_PLATFORM_SECURE_UART, PLAT_ARM_SECURE_MAP_DEVICE, ARM_SP_IMAGE_MMAP, ARM_SP_IMAGE_NS_BUF_MMAP, diff --git a/plat/arm/css/sgi/sgi_plat_v2.c b/plat/arm/css/sgi/sgi_plat_v2.c index 1a2a96629..cef5345cd 100644 --- a/plat/arm/css/sgi/sgi_plat_v2.c +++ b/plat/arm/css/sgi/sgi_plat_v2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -83,6 +83,7 @@ const mmap_region_t plat_arm_mmap[] = { const mmap_region_t plat_arm_secure_partition_mmap[] = { PLAT_ARM_SECURE_MAP_SYSTEMREG, PLAT_ARM_SECURE_MAP_NOR2, + SOC_PLATFORM_SECURE_UART, SOC_PLATFORM_PERIPH_MAP_DEVICE_USER, ARM_SP_IMAGE_MMAP, ARM_SP_IMAGE_NS_BUF_MMAP, |