Merge branch 'p-ti-u-boot-2016.05' of git://git.omapzoom.org/repo/u-boot into 6AM.1.3-rvc-video6AM.1.3-rvc-video-j6e-aug6AM.1.3-rvc-video

* 'p-ti-u-boot-2016.05' of git://git.omapzoom.org/repo/u-boot: (62 commits)
  am57x: android: add vendor partition
  arm: omap: enable high speed mode support in SPL for the eMMC on DRA76x
  ARM: dts: dra76-evm: add higher speed MMC/SD modes
  ARM: dts: dra76-evm: shift to using common IOdelay data
  ARM: dts: dra76x: create a common file with MMC/SD IOdelay data
  ARM: DRA72x: Add support for detection of DRA71x SR 2.1
  dra7xx: android: add vendor partition
  fastboot: sparse: remove session-id logic
  ARM: dts: dra76-evm: Add initial support
  ARM: dts: dra7-evm: sync DT with Linux
  configs: ti_omap5_common: Select dtb name for dra76
  board: ti: dra76-evm: Add support for powering on mmc ldo
  board: ti: dra76-evm: Add the pinmux data
  board: ti: dra76-evm: Add DDR data
  board: ti: dra76-evm: Add the pmic data
  board: ti: dra76-evm: Add epprom support
  arm: dra76: Add support for ES1.0 detection
  configs: dra7xx: Enable LP87565 related configs
  power: regulator: palmas: Add smps12 dual regulator for tps65917
  power: regulator: lp87565: add regulator support
  ...

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

91 files changed, 2981 insertions, 984 deletions

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 4618470bad..8cc4e65809 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -105,7 +105,7 @@ static const struct gpio_bank gpio_bank_am33xx[] = {
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 #endif
 
-#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_OMAP_HSMMC)
 int cpu_mmc_init(bd_t *bis)
 {
 	int ret;
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 4e50a68b58..b308859104 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -209,22 +209,6 @@ void spl_board_init(void)
 #endif
 }
 
-int board_mmc_init(bd_t *bis)
-{
-	switch (spl_boot_device()) {
-	case BOOT_DEVICE_MMC1:
-		omap_mmc_init(0, 0, 0, -1, -1);
-		break;
-	case BOOT_DEVICE_MMC2:
-	case BOOT_DEVICE_MMC2_2:
-	case BOOT_DEVICE_SPI:
-		omap_mmc_init(0, 0, 0, -1, -1);
-		omap_mmc_init(1, 0, 0, -1, -1);
-		break;
-	}
-	return 0;
-}
-
 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
 	typedef void __noreturn (*image_entry_noargs_t)(u32 *);
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 0716f51931..06b0414469 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -28,17 +28,6 @@ struct vcores_data const **omap_vcores =
 struct omap_sys_ctrl_regs const **ctrl =
 	(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
 
-/* OPP HIGH FREQUENCY for ES2.0 */
-static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
-	{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
-};
-
 /* OPP NOM FREQUENCY for ES1.0 */
 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
 	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
@@ -50,28 +39,6 @@ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
 	{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
 };
 
-/* OPP LOW FREQUENCY for ES1.0 */
-static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
-	{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
-};
-
-/* OPP LOW FREQUENCY for ES2.0 */
-static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
-	{499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
-};
-
 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
 	{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
@@ -116,28 +83,6 @@ static const struct dpll_params
 	{277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 38.4 MHz */
 };
 
-static const struct dpll_params
-			core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
-	{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 16.8 MHz */
-	{277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 19.2 MHz */
-	{368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}		/* 38.4 MHz */
-};
-
-static const struct dpll_params
-			core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
-	{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 16.8 MHz */
-	{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 19.2 MHz */
-	{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}		/* 38.4 MHz */
-};
-
 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
 	{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
@@ -168,6 +113,16 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 	{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 38.4 MHz */
 };
 
+static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
+	{32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 12 MHz   */
+	{96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 16.8 MHz */
+	{20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 19.2 MHz */
+	{192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 38.4 MHz */
+};
+
 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
 	{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
@@ -188,6 +143,7 @@ static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
 	{91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
 };
 
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 /* ABE M & N values with sys_clk as source */
 static const struct dpll_params
 		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
@@ -199,11 +155,14 @@ static const struct dpll_params
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
 	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
 };
+#endif
 
+#ifndef CONFIG_SYS_OMAP_ABE_SYSCK
 /* ABE M & N values with 32K clock as source */
 static const struct dpll_params abe_dpll_params_32k_196608khz = {
 	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
 };
+#endif
 
 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
 static const struct dpll_params
@@ -285,6 +244,17 @@ struct dplls omap5_dplls_es2 = {
 	.ddr = NULL
 };
 
+struct dplls dra76x_dplls = {
+	.mpu = mpu_dpll_params_1ghz,
+	.core = core_dpll_params_2128mhz_dra7xx,
+	.per = per_dpll_params_768mhz_dra76x,
+	.abe = abe_dpll_params_sysclk2_361267khz,
+	.iva = iva_dpll_params_2330mhz_dra7xx,
+	.usb = usb_dpll_params_1920mhz,
+	.ddr =	ddr_dpll_params_2664mhz,
+	.gmac = gmac_dpll_params_2000mhz,
+};
+
 struct dplls dra7xx_dplls = {
 	.mpu = mpu_dpll_params_1ghz,
 	.core = core_dpll_params_2128mhz_dra7xx,
@@ -336,6 +306,22 @@ struct pmic_data tps659038 = {
 	.gpio_en = 0,
 };
 
+/* The LP87565*/
+struct pmic_data lp87565 = {
+	.base_offset = LP873X_BUCK_BASE_VOLT_UV,
+	.step = 5000, /* 5 mV represented in uV */
+	/*
+	 * Offset codes 0 - 0x13 Invalid.
+	 * Offset codes 0x14 0x17 give 10mV steps
+	 * Offset codes 0x17 through 0x9D give 5mV steps
+	 * So let us start with our operating range from .73V
+	 */
+	.start_code = 0x17,
+	.i2c_slave_addr = 0x60,
+	.pmic_bus_init  = gpi2c_init,
+	.pmic_write     = palmas_i2c_write_u8,
+};
+
 /* The LP8732 and LP8733 are software-compatible, use common struct */
 struct pmic_data lp8733 = {
 	.base_offset = LP873X_BUCK_BASE_VOLT_UV,
@@ -753,6 +739,12 @@ void __weak hw_data_init(void)
 	*ctrl = &omap5_ctrl;
 	break;
 
+	case DRA762_ES1_0:
+	*prcm = &dra7xx_prcm;
+	*dplls_data = &dra76x_dplls;
+	*ctrl = &dra7xx_ctrl;
+	break;
+
 	case DRA752_ES1_0:
 	case DRA752_ES1_1:
 	case DRA752_ES2_0:
@@ -763,6 +755,7 @@ void __weak hw_data_init(void)
 
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra72x_dplls;
 	*ctrl = &dra7xx_ctrl;
@@ -791,12 +784,14 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 	case DRA752_ES1_0:
 	case DRA752_ES1_1:
 	case DRA752_ES2_0:
+	case DRA762_ES1_0:
 		*regs = &ioregs_dra7xx_es1;
 		break;
 	case DRA722_ES1_0:
 		*regs = &ioregs_dra72x_es1;
 		break;
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		*regs = &ioregs_dra72x_es2;
 		break;
 
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 839d79d102..03e50ba891 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -362,6 +362,9 @@ void init_omap_revision(void)
 	case OMAP5432_CONTROL_ID_CODE_ES2_0:
 		*omap_si_rev = OMAP5432_ES2_0;
 		break;
+	case DRA762_CONTROL_ID_CODE_ES1_0:
+		*omap_si_rev = DRA762_ES1_0;
+		break;
 	case DRA752_CONTROL_ID_CODE_ES1_0:
 		*omap_si_rev = DRA752_ES1_0;
 		break;
@@ -377,6 +380,9 @@ void init_omap_revision(void)
 	case DRA722_CONTROL_ID_CODE_ES2_0:
 		*omap_si_rev = DRA722_ES2_0;
 		break;
+	case DRA722_CONTROL_ID_CODE_ES2_1:
+		*omap_si_rev = DRA722_ES2_1;
+		break;
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}
@@ -454,10 +460,14 @@ void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
 }
 
 #if defined(CONFIG_PALMAS_POWER)
+__weak void board_mmc_poweron_ldo(uint voltage)
+{
+	palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
+}
+
 void vmmc_pbias_config(uint voltage)
 {
 	u32 value = 0;
-	struct vcores_data const *vcores = *omap_vcores;
 
 	value = readl((*ctrl)->control_pbias);
 	value &= ~SDCARD_PWRDNZ;
@@ -466,15 +476,7 @@ void vmmc_pbias_config(uint voltage)
 	value &= ~SDCARD_BIAS_PWRDNZ;
 	writel(value, (*ctrl)->control_pbias);
 
-	if (vcores->core.pmic->i2c_slave_addr == 0x60) {
-		if (voltage == LDO_VOLT_3V0)
-			voltage = 0x19;
-		else if (voltage == LDO_VOLT_1V8)
-			voltage = 0xa;
-		lp873x_mmc1_poweron_ldo(voltage);
-	} else {
-		palmas_mmc1_poweron_ldo(voltage);
-	}
+	board_mmc_poweron_ldo(voltage);
 
 	value = readl((*ctrl)->control_pbias);
 	value |= SDCARD_BIAS_PWRDNZ;
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7712923d85..8fb962e39d 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -480,7 +480,9 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
 		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
 		break;
+	case DRA762_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
 		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
 		break;
@@ -709,11 +711,13 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
 		*iterations = sizeof(omap5_bug_00339_regs)/
 			     sizeof(omap5_bug_00339_regs[0]);
 		break;
+	case DRA762_ES1_0:
 	case DRA752_ES1_0:
 	case DRA752_ES1_1:
 	case DRA752_ES2_0:
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		bug_00339_regs_ptr = dra_bug_00339_regs;
 		*iterations = sizeof(dra_bug_00339_regs)/
 			     sizeof(dra_bug_00339_regs[0]);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0c87fa4492..fa81de1152 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -108,7 +108,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_sr1500.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb	\
-	dra72-evm-revc.dtb dra71-evm.dtb
+	dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
 dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
 	am572x-idk.dtb	\
 	am571x-idk.dtb
diff --git a/arch/arm/dts/dra7-evm-common.dtsi b/arch/arm/dts/dra7-evm-common.dtsi
new file mode 100644
index 0000000000..78ffafd143
--- /dev/null
+++ b/arch/arm/dts/dra7-evm-common.dtsi
@@ -0,0 +1,190 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+		tick-timer = &timer2;
+	};
+
+	extcon_usb1: extcon_usb1 {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+	};
+
+	extcon_usb2: extcon_usb2 {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led@0 {
+			label = "dra7:usr1";
+			gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led@1 {
+			label = "dra7:usr2";
+			gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "dra7:usr3";
+			gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "dra7:usr4";
+			gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		USER1 {
+			label = "btnUser1";
+			linux,code = <BTN_0>;
+			gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
+		};
+
+		USER2 {
+			label = "btnUser2";
+			linux,code = <BTN_1>;
+			gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&dra7_pmx_core {
+	dcan1_pins_default: dcan1_pins_default {
+		pinctrl-single,pins = <
+			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+			0x418   (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+		>;
+	};
+
+	dcan1_pins_sleep: dcan1_pins_sleep {
+		pinctrl-single,pins = <
+			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
+			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
+		>;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+	clock-frequency = <400000>;
+};
+
+&mcspi1 {
+	status = "okay";
+};
+
+&mcspi2 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+			      <&dra7_pmx_core 0x3e0>;
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+
+&qspi {
+	status = "okay";
+
+	spi-max-frequency = <76800000>;
+	m25p80@0 {
+		compatible = "s25fl256s1";
+		spi-max-frequency = <76800000>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* MTD partition table.
+		 * The ROM checks the first four physical blocks
+		 * for a valid file to boot and the flash here is
+		 * 64KiB block size.
+		 */
+		partition@0 {
+			label = "QSPI.SPL";
+			reg = <0x00000000 0x000040000>;
+		};
+		partition@1 {
+			label = "QSPI.u-boot";
+			reg = <0x00040000 0x00100000>;
+		};
+		partition@2 {
+			label = "QSPI.u-boot-spl-os";
+			reg = <0x00140000 0x00080000>;
+		};
+		partition@3 {
+			label = "QSPI.u-boot-env";
+			reg = <0x001c0000 0x00010000>;
+		};
+		partition@4 {
+			label = "QSPI.u-boot-env.backup1";
+			reg = <0x001d0000 0x0010000>;
+		};
+		partition@5 {
+			label = "QSPI.kernel";
+			reg = <0x001e0000 0x0800000>;
+		};
+		partition@6 {
+			label = "QSPI.file-system";
+			reg = <0x009e0000 0x01620000>;
+		};
+	};
+};
+
+&omap_dwc3_1 {
+	extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+	extcon = <&extcon_usb2>;
+};
+
+&usb1 {
+	dr_mode = "peripheral";
+};
+
+&usb2 {
+	dr_mode = "host";
+};
+
+&dcan1 {
+	status = "ok";
+	pinctrl-names = "default", "sleep", "active";
+	pinctrl-0 = <&dcan1_pins_sleep>;
+	pinctrl-1 = <&dcan1_pins_sleep>;
+	pinctrl-2 = <&dcan1_pins_default>;
+};
diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index ecfaf6052d..ceee1a76b5 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -8,17 +8,14 @@
 /dts-v1/;
 
 #include "dra74x.dtsi"
+#include "dra7-evm-common.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "TI DRA742";
 	compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
 
-	chosen {
-		stdout-path = &uart1;
-		tick-timer = &timer2;
-	};
-
 	memory {
 		device_type = "memory";
 		reg = <0x80000000 0x60000000>; /* 1536 MB */
@@ -33,23 +30,34 @@
 		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
 	};
 
-	mmc2_3v3: fixedregulator-mmc2 {
+	evm_3v3_sw: fixedregulator-evm_3v3_sw {
 		compatible = "regulator-fixed";
-		regulator-name = "mmc2_3v3";
+		regulator-name = "evm_3v3_sw";
+		vin-supply = <&sysen1>;
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
 
-	extcon_usb1: extcon_usb1 {
-		compatible = "linux,extcon-usb-gpio";
-		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+	aic_dvdd: fixedregulator-aic_dvdd {
+		/* TPS77018DBVT */
+		compatible = "regulator-fixed";
+		regulator-name = "aic_dvdd";
+		vin-supply = <&evm_3v3_sw>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
 	};
 
-	extcon_usb2: extcon_usb2 {
-		compatible = "linux,extcon-usb-gpio";
-		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+	vmmcwl_fixed: fixedregulator-mmcwl {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmcwl_fixed";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio5 8 0>;	/* gpio5_8 */
+		startup-delay-us = <70000>;
+		enable-active-high;
 	};
 
+
 	vtt_fixed: fixedregulator-vtt {
 		compatible = "regulator-fixed";
 		regulator-name = "vtt_fixed";
@@ -58,234 +66,30 @@
 		regulator-always-on;
 		regulator-boot-on;
 		enable-active-high;
+		vin-supply = <&sysen2>;
 		gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
 	};
 };
 
 &dra7_pmx_core {
-	pinctrl-names = "default";
-	pinctrl-0 = <&vtt_pin>;
-
-	vtt_pin: pinmux_vtt_pin {
-		pinctrl-single,pins = <
-			0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
-		>;
-	};
-
-	i2c1_pins: pinmux_i2c1_pins {
-		pinctrl-single,pins = <
-			0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
-			0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
-		>;
-	};
-
-	i2c2_pins: pinmux_i2c2_pins {
-		pinctrl-single,pins = <
-			0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
-			0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
-		>;
-	};
-
-	i2c3_pins: pinmux_i2c3_pins {
-		pinctrl-single,pins = <
-			0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
-			0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
-		>;
-	};
-
-	mcspi1_pins: pinmux_mcspi1_pins {
-		pinctrl-single,pins = <
-			0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
-			0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
-			0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
-			0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
-			0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
-			0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
-		>;
-	};
-
-	mcspi2_pins: pinmux_mcspi2_pins {
-		pinctrl-single,pins = <
-			0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
-			0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
-			0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
-			0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
-		>;
-	};
-
-	uart1_pins: pinmux_uart1_pins {
-		pinctrl-single,pins = <
-			0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
-			0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
-			0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
-			0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
-		>;
-	};
-
-	uart2_pins: pinmux_uart2_pins {
-		pinctrl-single,pins = <
-			0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
-			0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
-			0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
-			0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
-		>;
-	};
-
-	uart3_pins: pinmux_uart3_pins {
+	hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
 		pinctrl-single,pins = <
-			0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
-			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
+			/* this pin is used as a GPIO via mcasp */
+			0x2fc   (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
 		>;
 	};
 
-	qspi1_pins: pinmux_qspi1_pins {
+	hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
 		pinctrl-single,pins = <
-			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
-			0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
-			0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
-			0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
-			0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
-			0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
-			0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
-			0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
-			0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
-			0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
+			0x408   (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
+			0x40c   (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
 		>;
 	};
 
-	usb1_pins: pinmux_usb1_pins {
-                pinctrl-single,pins = <
-			0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
-                >;
-        };
-
-	usb2_pins: pinmux_usb2_pins {
-                pinctrl-single,pins = <
-			0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
-                >;
-        };
-
-	nand_flash_x16: nand_flash_x16 {
-		/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
-		 * So NAND flash requires following switch settings:
-		 * SW5.9 (GPMC_WPN) = LOW
-		 * SW5.1 (NAND_BOOTn) = HIGH */
+	hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
 		pinctrl-single,pins = <
-			0x0 	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad0	*/
-			0x4 	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad1	*/
-			0x8 	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad2	*/
-			0xc 	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad3	*/
-			0x10	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad4	*/
-			0x14	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad5	*/
-			0x18	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad6	*/
-			0x1c	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad7	*/
-			0x20	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad8	*/
-			0x24	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad9	*/
-			0x28	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad10	*/
-			0x2c	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad11	*/
-			0x30	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad12	*/
-			0x34	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad13	*/
-			0x38	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad14	*/
-			0x3c	(PIN_INPUT  | MUX_MODE0)	/* gpmc_ad15	*/
-			0xd8	(PIN_INPUT_PULLUP  | MUX_MODE0)	/* gpmc_wait0	*/
-			0xcc	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_wen	*/
-			0xb4	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_csn0	*/
-			0xc4	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_advn_ale */
-			0xc8	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_oen_ren	 */
-			0xd0	(PIN_OUTPUT | MUX_MODE0)	/* gpmc_be0n_cle */
-		>;
-	};
-
-	cpsw_default: cpsw_default {
-		pinctrl-single,pins = <
-			/* Slave 1 */
-			0x250 (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_txc.rgmii0_txc */
-			0x254 (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_txctl.rgmii0_txctl */
-			0x258 (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_td3.rgmii0_txd3 */
-			0x25c (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_txd2.rgmii0_txd2 */
-			0x260 (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_txd1.rgmii0_txd1 */
-			0x264 (PIN_OUTPUT | MUX_MODE0)	/* rgmii0_txd0.rgmii0_txd0 */
-			0x268 (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxc.rgmii0_rxc */
-			0x26c (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxctl.rgmii0_rxctl */
-			0x270 (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxd3.rgmii0_rxd3 */
-			0x274 (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxd2.rgmii0_rxd2 */
-			0x278 (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxd1.rgmii0_rxd1 */
-			0x27c (PIN_INPUT | MUX_MODE0)	/* rgmii0_rxd0.rgmii0_rxd0 */
-
-			/* Slave 2 */
-			0x198 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d12.rgmii1_txc */
-			0x19c (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d13.rgmii1_tctl */
-			0x1a0 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d14.rgmii1_td3 */
-			0x1a4 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d15.rgmii1_td2 */
-			0x1a8 (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d16.rgmii1_td1 */
-			0x1ac (PIN_OUTPUT | MUX_MODE3)	/* vin2a_d17.rgmii1_td0 */
-			0x1b0 (PIN_INPUT | MUX_MODE3)	/* vin2a_d18.rgmii1_rclk */
-			0x1b4 (PIN_INPUT | MUX_MODE3)	/* vin2a_d19.rgmii1_rctl */
-			0x1b8 (PIN_INPUT | MUX_MODE3)	/* vin2a_d20.rgmii1_rd3 */
-			0x1bc (PIN_INPUT | MUX_MODE3)	/* vin2a_d21.rgmii1_rd2 */
-			0x1c0 (PIN_INPUT | MUX_MODE3)	/* vin2a_d22.rgmii1_rd1 */
-			0x1c4 (PIN_INPUT | MUX_MODE3)	/* vin2a_d23.rgmii1_rd0 */
-		>;
-
-	};
-
-	cpsw_sleep: cpsw_sleep {
-		pinctrl-single,pins = <
-			/* Slave 1 */
-			0x250 (MUX_MODE15)
-			0x254 (MUX_MODE15)
-			0x258 (MUX_MODE15)
-			0x25c (MUX_MODE15)
-			0x260 (MUX_MODE15)
-			0x264 (MUX_MODE15)
-			0x268 (MUX_MODE15)
-			0x26c (MUX_MODE15)
-			0x270 (MUX_MODE15)
-			0x274 (MUX_MODE15)
-			0x278 (MUX_MODE15)
-			0x27c (MUX_MODE15)
-
-			/* Slave 2 */
-			0x198 (MUX_MODE15)
-			0x19c (MUX_MODE15)
-			0x1a0 (MUX_MODE15)
-			0x1a4 (MUX_MODE15)
-			0x1a8 (MUX_MODE15)
-			0x1ac (MUX_MODE15)
-			0x1b0 (MUX_MODE15)
-			0x1b4 (MUX_MODE15)
-			0x1b8 (MUX_MODE15)
-			0x1bc (MUX_MODE15)
-			0x1c0 (MUX_MODE15)
-			0x1c4 (MUX_MODE15)
-		>;
-	};
-
-	davinci_mdio_default: davinci_mdio_default {
-		pinctrl-single,pins = <
-			0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mdio_d.mdio_d */
-			0x240 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mdio_clk.mdio_clk */
-		>;
-	};
-
-	davinci_mdio_sleep: davinci_mdio_sleep {
-		pinctrl-single,pins = <
-			0x23c (MUX_MODE15)
-			0x240 (MUX_MODE15)
-		>;
-	};
-
-	dcan1_pins_default: dcan1_pins_default {
-		pinctrl-single,pins = <
-			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
-			0x418   (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
-		>;
-	};
-
-	dcan1_pins_sleep: dcan1_pins_sleep {
-		pinctrl-single,pins = <
-			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
-			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
+			0x408   (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
+			0x40c   (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
 		>;
 	};
 
@@ -623,8 +427,6 @@
 
 &i2c1 {
 	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
 	clock-frequency = <400000>;
 
 	tps659038: tps659038@58 {
@@ -648,7 +450,7 @@
 					/* VDD_DSPEVE */
 					regulator-name = "smps45";
 					regulator-min-microvolt = < 850000>;
-					regulator-max-microvolt = <1150000>;
+					regulator-max-microvolt = <1250000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};
@@ -666,7 +468,7 @@
 					/* CORE_VDD */
 					regulator-name = "smps7";
 					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1060000>;
+					regulator-max-microvolt = <1150000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};
@@ -694,6 +496,7 @@
 					regulator-name = "ldo1";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
 					regulator-boot-on;
 				};
 
@@ -723,6 +526,7 @@
 					regulator-max-microvolt = <1050000>;
 					regulator-always-on;
 					regulator-boot-on;
+					regulator-allow-bypass;
 				};
 
 				ldoln_reg: ldoln {
@@ -741,10 +545,46 @@
 					regulator-max-microvolt = <3300000>;
 					regulator-boot-on;
 				};
+
+				/* REGEN1 is unused */
+
+				regen2: regen2 {
+					/* Needed for PMIC internal resources */
+					regulator-name = "regen2";
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				/* REGEN3 is unused */
+
+				sysen1: sysen1 {
+					/* PMIC_REGEN_3V3 */
+					regulator-name = "sysen1";
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				sysen2: sysen2 {
+					/* PMIC_REGEN_DDR */
+					regulator-name = "sysen2";
+					regulator-boot-on;
+					regulator-always-on;
+				};
 			};
 		};
 	};
 
+	pcf_lcd: gpio@20 {
+		compatible = "nxp,pcf8575";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	pcf_gpio_21: gpio@21 {
 		compatible = "ti,pcf8575";
 		reg = <0x21>;
@@ -757,52 +597,39 @@
 		#interrupt-cells = <2>;
 	};
 
-};
+	tlv320aic3106: tlv320aic3106@19 {
+		#sound-dai-cells = <0>;
+		compatible = "ti,tlv320aic3106";
+		reg = <0x19>;
+		adc-settle-ms = <40>;
+		ai3x-micbias-vg = <1>;		/* 2.0V */
+		status = "okay";
 
-&i2c2 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins>;
-	clock-frequency = <400000>;
+		/* Regulators */
+		AVDD-supply = <&evm_3v3_sw>;
+		IOVDD-supply = <&evm_3v3_sw>;
+		DRVDD-supply = <&evm_3v3_sw>;
+		DVDD-supply = <&aic_dvdd>;
+	};
 };
 
-&i2c3 {
+&i2c2 {
 	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c3_pins>;
 	clock-frequency = <400000>;
-};
-
-&mcspi1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcspi1_pins>;
-};
-
-&mcspi2 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcspi2_pins>;
-};
-
-&uart1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
-			      <&dra7_pmx_core 0x3e0>;
-};
 
-&uart2 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-};
-
-&uart3 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins>;
+	pcf_hdmi: gpio@26 {
+		compatible = "nxp,pcf8575";
+		reg = <0x26>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		p1 {
+			/* vin6_sel_s0: high: VIN6, low: audio */
+			gpio-hog;
+			gpios = <1 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "vin6_sel_s0";
+		};
+	};
 };
 
 &mmc1 {
@@ -830,7 +657,7 @@
 
 &mmc2 {
 	status = "okay";
-	vmmc-supply = <&mmc2_3v3>;
+	vmmc-supply = <&evm_3v3_sw>;
 	bus-width = <8>;
 	max-frequency = <192000000>;
 	pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
@@ -846,97 +673,12 @@
 	cpu0-supply = <&smps123_reg>;
 };
 
-&qspi {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&qspi1_pins>;
-
-	spi-max-frequency = <64000000>;
-	m25p80@0 {
-		compatible = "s25fl256s1","spi-flash";
-		spi-max-frequency = <76800000>;
-		reg = <0>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <4>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* MTD partition table.
-		 * The ROM checks the first four physical blocks
-		 * for a valid file to boot and the flash here is
-		 * 64KiB block size.
-		 */
-		partition@0 {
-			label = "QSPI.SPL";
-			reg = <0x00000000 0x000010000>;
-		};
-		partition@1 {
-			label = "QSPI.SPL.backup1";
-			reg = <0x00010000 0x00010000>;
-		};
-		partition@2 {
-			label = "QSPI.SPL.backup2";
-			reg = <0x00020000 0x00010000>;
-		};
-		partition@3 {
-			label = "QSPI.SPL.backup3";
-			reg = <0x00030000 0x00010000>;
-		};
-		partition@4 {
-			label = "QSPI.u-boot";
-			reg = <0x00040000 0x00100000>;
-		};
-		partition@5 {
-			label = "QSPI.u-boot-spl-os";
-			reg = <0x00140000 0x00080000>;
-		};
-		partition@6 {
-			label = "QSPI.u-boot-env";
-			reg = <0x001c0000 0x00010000>;
-		};
-		partition@7 {
-			label = "QSPI.u-boot-env.backup1";
-			reg = <0x001d0000 0x0010000>;
-		};
-		partition@8 {
-			label = "QSPI.kernel";
-			reg = <0x001e0000 0x0800000>;
-		};
-		partition@9 {
-			label = "QSPI.file-system";
-			reg = <0x009e0000 0x01620000>;
-		};
-	};
-};
-
-&omap_dwc3_1 {
-	extcon = <&extcon_usb1>;
-};
-
-&omap_dwc3_2 {
-	extcon = <&extcon_usb2>;
-};
-
-&usb1 {
-	dr_mode = "peripheral";
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb1_pins>;
-};
-
-&usb2 {
-	dr_mode = "host";
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb2_pins>;
-};
-
 &elm {
 	status = "okay";
 };
 
 &gpmc {
 	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&nand_flash_x16>;
 	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
 	nand@0,0 {
 		reg = <0 0 4>;		/* device IO registers */
@@ -1028,9 +770,6 @@
 
 &mac {
 	status = "okay";
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&cpsw_default>;
-	pinctrl-1 = <&cpsw_sleep>;
 	dual_emac;
 };
 
@@ -1045,17 +784,3 @@
 	phy-mode = "rgmii";
 	dual_emac_res_vlan = <2>;
 };
-
-&davinci_mdio {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&davinci_mdio_default>;
-	pinctrl-1 = <&davinci_mdio_sleep>;
-};
-
-&dcan1 {
-	status = "ok";
-	pinctrl-names = "default", "sleep", "active";
-	pinctrl-0 = <&dcan1_pins_sleep>;
-	pinctrl-1 = <&dcan1_pins_sleep>;
-	pinctrl-2 = <&dcan1_pins_default>;
-};
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index ec8de7a116..e9eb8f0986 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -146,6 +146,7 @@
 					#address-cells = <1>;
 					#size-cells = <0>;
 					#interrupt-cells = <1>;
+					#pinctrl-cells = <1>;
 					interrupt-controller;
 					pinctrl-single,register-width = <32>;
 					pinctrl-single,function-mask = <0x3fffffff>;
@@ -302,6 +303,7 @@
 			reg = <0x4844a000 0x0d1c>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#pinctrl-cells = <1>;
 		};
 
 		sdma: dma-controller@4a056000 {
diff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts
new file mode 100644
index 0000000000..1a149fa5fe
--- /dev/null
+++ b/arch/arm/dts/dra76-evm.dts
@@ -0,0 +1,388 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra76x.dtsi"
+#include "dra7-evm-common.dtsi"
+#include "dra76x-mmc-iodelay.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	model = "TI DRA762 EVM";
+	compatible = "ti,dra76-evm", "ti,dra76", "ti,dra7";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+	vsys_12v0: fixedregulator-vsys12v0 {
+		/* main supply */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_12v0";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_5v0: fixedregulator-vsys5v0 {
+		/* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vsys_12v0>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_3v3: fixedregulator-vsys3v3 {
+		/* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vsys_12v0>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vio_3v3: fixedregulator-vio_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vio_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vsys_3v3>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vio_3v3_sd: fixedregulator-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vio_3v3_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vio_3v3>;
+		enable-active-high;
+		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+	};
+
+	vio_1v8: fixedregulator-vio_1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vio_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&smps5_reg>;
+	};
+
+	vtt_fixed: fixedregulator-vtt {
+		compatible = "regulator-fixed";
+		regulator-name = "vtt_fixed";
+		regulator-min-microvolt = <1350000>;
+		regulator-max-microvolt = <1350000>;
+		vin-supply = <&vsys_3v3>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	aic_dvdd: fixedregulator-aic_dvdd {
+		/* TPS77018DBVT */
+		compatible = "regulator-fixed";
+		regulator-name = "aic_dvdd";
+		vin-supply = <&vio_3v3>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps65917: tps65917@58 {
+		compatible = "ti,tps65917";
+		reg = <0x58>;
+		ti,system-power-controller;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		tps65917_pmic {
+			compatible = "ti,tps65917-pmic";
+
+			smps12-in-supply = <&vsys_3v3>;
+			smps3-in-supply = <&vsys_3v3>;
+			smps4-in-supply = <&vsys_3v3>;
+			smps5-in-supply = <&vsys_3v3>;
+			ldo1-in-supply = <&vsys_3v3>;
+			ldo2-in-supply = <&vsys_3v3>;
+			ldo3-in-supply = <&vsys_5v0>;
+			ldo4-in-supply = <&vsys_5v0>;
+			ldo5-in-supply = <&vsys_3v3>;
+
+			tps65917_regulators: regulators {
+				smps12_reg: smps12 {
+					/* VDD_DSPEVE */
+					regulator-name = "smps12";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps3_reg: smps3 {
+					/* VDD_CORE */
+					regulator-name = "smps3";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				smps4_reg: smps4 {
+					/* VDD_IVA */
+					regulator-name = "smps4";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps5_reg: smps5 {
+					/* VDDS1V8 */
+					regulator-name = "smps5";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo1_reg: ldo1 {
+					/* LDO1_OUT --> VDA_PHY1_1V8  */
+					regulator-name = "ldo1";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-allow-bypass;
+				};
+
+				ldo2_reg: ldo2 {
+					/* LDO2_OUT --> VDA_PHY2_1V8 */
+					regulator-name = "ldo2";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-allow-bypass;
+					regulator-always-on;
+				};
+
+				ldo3_reg: ldo3 {
+					/* VDA_USB_3V3 */
+					regulator-name = "ldo3";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo5_reg: ldo5 {
+					/* VDDA_1V8_PLL */
+					regulator-name = "ldo5";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo4_reg: ldo4 {
+					/* VDD_SDIO_DV */
+					regulator-name = "ldo4";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+			};
+		};
+
+		tps65917_power_button {
+			compatible = "ti,palmas-pwrbutton";
+			interrupt-parent = <&tps65917>;
+			interrupts = <1 IRQ_TYPE_NONE>;
+			wakeup-source;
+			ti,palmas-long-press-seconds = <6>;
+		};
+	};
+
+	lp87565: lp87565@60 {
+		compatible = "ti,lp87565-q1";
+		reg = <0x60>;
+
+		buck10-in-supply =<&vsys_3v3>;
+		buck23-in-supply =<&vsys_3v3>;
+
+		regulators: regulators {
+			buck10_reg: buck10 {
+				/*VDD_MPU*/
+				regulator-name = "buck10";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1250000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck23_reg: buck23 {
+				/* VDD_GPU*/
+				regulator-name = "buck23";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1250000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+
+	pcf_lcd: pcf8757@20 {
+		compatible = "ti,pcf8575", "nxp,pcf8575";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+	};
+
+	pcf_gpio_21: pcf8757@21 {
+		compatible = "ti,pcf8575", "nxp,pcf8575";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	pcf_hdmi: pcf8575@26 {
+		compatible = "ti,pcf8575", "nxp,pcf8575";
+		reg = <0x26>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		p1 {
+			/* vin6_sel_s0: high: VIN6, low: audio */
+			gpio-hog;
+			gpios = <1 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "vin6_sel_s0";
+		};
+	};
+
+	tlv320aic3106: tlv320aic3106@19 {
+		#sound-dai-cells = <0>;
+		compatible = "ti,tlv320aic3106";
+		reg = <0x19>;
+		adc-settle-ms = <40>;
+		ai3x-micbias-vg = <1>;		/* 2.0V */
+		status = "okay";
+
+		/* Regulators */
+		AVDD-supply = <&vio_3v3>;
+		IOVDD-supply = <&vio_3v3>;
+		DRVDD-supply = <&vio_3v3>;
+		DVDD-supply = <&aic_dvdd>;
+	};
+};
+
+&cpu0 {
+	vdd-supply = <&buck10_reg>;
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&vio_3v3_sd>;
+	vmmc_aux-supply = <&ldo4_reg>;
+	bus-width = <4>;
+	/*
+	 * SDCD signal is not being used here - using the fact that GPIO mode
+	 * is always hardwired.
+	 */
+	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
+	max-frequency = <192000000>;
+	pinctrl-names = "default", "hs";
+	pinctrl-0 = <&mmc1_pins_default>;
+	pinctrl-1 = <&mmc1_pins_hs>;
+};
+
+&mmc2 {
+	status = "okay";
+	vmmc-supply = <&vio_1v8>;
+	bus-width = <8>;
+	max-frequency = <192000000>;
+	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
+	pinctrl-0 = <&mmc2_pins_default>;
+	pinctrl-1 = <&mmc2_pins_hs>;
+	pinctrl-2 = <&mmc2_pins_ddr>;
+	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
+};
+
+/* No RTC on this device */
+&rtc {
+	status = "disabled";
+};
+
+&mac {
+	status = "okay";
+
+	dual_emac;
+};
+
+&cpsw_emac0 {
+	phy-handle = <&dp83867_0>;
+	phy-mode = "rgmii-id";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy-handle = <&dp83867_1>;
+	phy-mode = "rgmii-id";
+	dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+	dp83867_0: ethernet-phy@2 {
+		reg = <2>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+		ti,min-output-impedance;
+	};
+
+	dp83867_1: ethernet-phy@3 {
+		reg = <3>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&usb2_phy1 {
+	phy-supply = <&ldo3_reg>;
+};
+
+&usb2_phy2 {
+	phy-supply = <&ldo3_reg>;
+};
+
+&qspi {
+	spi-max-frequency = <96000000>;
+	m25p80@0 {
+		spi-max-frequency = <96000000>;
+	};
+};
diff --git a/arch/arm/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/dts/dra76x-mmc-iodelay.dtsi
new file mode 100644
index 0000000000..ff578843eb
--- /dev/null
+++ b/arch/arm/dts/dra76x-mmc-iodelay.dtsi
@@ -0,0 +1,244 @@
+/*
+ * MMC IOdelay values for TI's DRA76x and AM576x SoCs.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ *    Datamanual revision that was used should be updated in comment below.
+ *    If there is no update to datamanual, do not update the values. If you
+ *    need to use values different from that recommended by the datamanual
+ *    for your design, then you should consider adding values to the device-
+ *    -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ *    if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ *    we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ *    a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
+ *    'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ *    to curb naming creativity and achieve consistency.
+ *
+ * Datamanual Revisions:
+ *
+ * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
+ *
+ */
+
+&dra7_pmx_core {
+	mmc1_pins_default: mmc1_pins_default {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_sdr12: mmc1_pins_sdr12 {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_hs: mmc1_pins_hs {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_sdr25: mmc1_pins_sdr25 {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_sdr50: mmc1_pins_sdr50 {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_ddr50: mmc1_pins_ddr50 {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc1_pins_sdr104: mmc1_pins_sdr104 {
+		pinctrl-single,pins = <
+			0x354 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_clk.clk */
+			0x358 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_cmd.cmd */
+			0x35c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat0.dat0 */
+			0x360 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat1.dat1 */
+			0x364 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat2.dat2 */
+			0x368 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc2_pins_default: mmc2_pins_default {
+		pinctrl-single,pins = <
+			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+		>;
+	};
+
+	mmc2_pins_hs: mmc2_pins_hs {
+		pinctrl-single,pins = <
+			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+		>;
+	};
+
+	mmc2_pins_ddr: mmc2_pins_ddr {
+		pinctrl-single,pins = <
+			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+		>;
+	};
+
+	mmc2_pins_hs200: mmc2_pins_hs200 {
+		pinctrl-single,pins = <
+			0x9c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+			0xb0 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+			0xa0 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+			0xa4 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+			0xa8 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+			0xac (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+			0x8c (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+			0x90 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+			0x94 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+			0x98 (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+		>;
+	};
+};
+
+&dra7_iodelay_core {
+
+	/* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+	mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf {
+		pinctrl-single,pins = <
+			0x618 (A_DELAY(489) | G_DELAY(0))	/* CFG_MMC1_CLK_IN */
+			0x624 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_CMD_IN */
+			0x630 (A_DELAY(374) | G_DELAY(0))	/* CFG_MMC1_DAT0_IN */
+			0x63c (A_DELAY(31) | G_DELAY(0))	/* CFG_MMC1_DAT1_IN */
+			0x648 (A_DELAY(56) | G_DELAY(0))	/* CFG_MMC1_DAT2_IN */
+			0x654 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT3_IN */
+			0x620 (A_DELAY(1355) | G_DELAY(0))	/* CFG_MMC1_CLK_OUT */
+			0x628 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_CMD_OEN */
+			0x62c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
+			0x634 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT0_OEN */
+			0x638 (A_DELAY(0) | G_DELAY(4))	/* CFG_MMC1_DAT0_OUT */
+			0x640 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT1_OEN */
+			0x644 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT1_OUT */
+			0x64c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT2_OEN */
+			0x650 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT2_OUT */
+			0x658 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT3_OEN */
+			0x65c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT3_OUT */
+		>;
+	};
+
+	/* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+	mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
+		pinctrl-single,pins = <
+			0x620 (A_DELAY(892) | G_DELAY(0))	/* CFG_MMC1_CLK_OUT */
+			0x628 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_CMD_OEN */
+			0x62c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
+			0x634 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT0_OEN */
+			0x638 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT0_OUT */
+			0x640 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT1_OEN */
+			0x644 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT1_OUT */
+			0x64c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT2_OEN */
+			0x650 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT2_OUT */
+			0x658 (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT3_OEN */
+			0x65c (A_DELAY(0) | G_DELAY(0))	/* CFG_MMC1_DAT3_OUT */
+		>;
+	};
+
+	/* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+	mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
+		pinctrl-single,pins = <
+			0x190 (A_DELAY(384) | G_DELAY(0))       /* CFG_GPMC_A19_OEN */
+			0x194 (A_DELAY(0) | G_DELAY(174))       /* CFG_GPMC_A19_OUT */
+			0x1a8 (A_DELAY(410) | G_DELAY(0))       /* CFG_GPMC_A20_OEN */
+			0x1ac (A_DELAY(85) | G_DELAY(0))        /* CFG_GPMC_A20_OUT */
+			0x1b4 (A_DELAY(468) | G_DELAY(0))       /* CFG_GPMC_A21_OEN */
+			0x1b8 (A_DELAY(139) | G_DELAY(0))       /* CFG_GPMC_A21_OUT */
+			0x1c0 (A_DELAY(676) | G_DELAY(0))       /* CFG_GPMC_A22_OEN */
+			0x1c4 (A_DELAY(69) | G_DELAY(0))        /* CFG_GPMC_A22_OUT */
+			0x1d0 (A_DELAY(1062) | G_DELAY(154))	/* CFG_GPMC_A23_OUT */
+			0x1d8 (A_DELAY(640) | G_DELAY(0))       /* CFG_GPMC_A24_OEN */
+			0x1dc (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A24_OUT */
+			0x1e4 (A_DELAY(356) | G_DELAY(0))       /* CFG_GPMC_A25_OEN */
+			0x1e8 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A25_OUT */
+			0x1f0 (A_DELAY(579) | G_DELAY(0))       /* CFG_GPMC_A26_OEN */
+			0x1f4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A26_OUT */
+			0x1fc (A_DELAY(435) | G_DELAY(0))       /* CFG_GPMC_A27_OEN */
+			0x200 (A_DELAY(36) | G_DELAY(0))        /* CFG_GPMC_A27_OUT */
+			0x364 (A_DELAY(759) | G_DELAY(0))       /* CFG_GPMC_CS1_OEN */
+			0x368 (A_DELAY(72) | G_DELAY(0))        /* CFG_GPMC_CS1_OUT */
+	      >;
+	};
+};
diff --git a/arch/arm/dts/dra76x.dtsi b/arch/arm/dts/dra76x.dtsi
new file mode 100644
index 0000000000..0176ce4da9
--- /dev/null
+++ b/arch/arm/dts/dra76x.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "dra74x.dtsi"
+
+/ {
+	compatible = "ti,dra76", "ti,dra7";
+};
+
+&abb_mpu {
+	ti,abb_info = <
+	/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
+	1060000		0	0x0	0 0x02000000 0x01F00000
+	1160000		0	0x4	0 0x02000000 0x01F00000
+	1210000		0	0x8	0 0x02000000 0x01F00000
+	1250000		0	0xC	0 0x02000000 0x01F00000
+	>;
+};
+
+&mmc3 {
+	max-frequency = <96000000>;
+};
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 724e252946..5a2ea8faef 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -21,8 +21,8 @@
 /*
  * OMAP HSMMC register definitions
  */
-#define OMAP_HSMMC1_BASE		0x48060100
-#define OMAP_HSMMC2_BASE		0x481D8100
+#define OMAP_HSMMC1_BASE		0x48060000
+#define OMAP_HSMMC2_BASE		0x481D8000
 
 #if defined(CONFIG_TI814X)
 #undef MMC_CLOCK_REFERENCE
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
index 9c8ccb6c83..d06779956f 100644
--- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -31,8 +31,8 @@
  * OMAP HSMMC register definitions
  */
 
-#define OMAP_HSMMC1_BASE	0x4809C100
-#define OMAP_HSMMC2_BASE	0x480B4100
-#define OMAP_HSMMC3_BASE	0x480AD100
+#define OMAP_HSMMC1_BASE	0x4809C000
+#define OMAP_HSMMC2_BASE	0x480B4000
+#define OMAP_HSMMC3_BASE	0x480AD000
 
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 4c0e890194..489815e644 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -341,6 +341,9 @@
 /* Offset is 0.73V for LP873x */
 #define LP873X_BUCK_BASE_VOLT_UV		730000
 
+/* Offset is 0.73V for LP87565 */
+#define LP87565_BUCK_BASE_VOLT_UV		730000
+
 /* TPS659038 */
 #define TPS659038_I2C_SLAVE_ADDR		0x58
 #define TPS659038_REG_ADDR_SMPS12		0x23
@@ -354,6 +357,7 @@
 #define TPS65917_REG_ADDR_SMPS1		0x23
 #define TPS65917_REG_ADDR_SMPS2		0x27
 #define TPS65917_REG_ADDR_SMPS3		0x2F
+#define TPS65917_REG_ADDR_SMPS4		0x33
 
 /* LP873X */
 #define LP873X_I2C_SLAVE_ADDR		0x60
@@ -361,6 +365,11 @@
 #define LP873X_REG_ADDR_BUCK1		0x7
 #define LP873X_REG_ADDR_LDO1		0xA
 
+/* LP87565 */
+#define LP87565_I2C_SLAVE_ADDR		0x61
+#define LP87565_REG_ADDR_BUCK01		0xA
+#define LP87565_REG_ADDR_BUCK23		0xE
+
 /* TPS */
 #define TPS62361_I2C_SLAVE_ADDR		0x60
 #define TPS62361_REG_ADDR_SET0		0x0
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
index 9c8ccb6c83..d06779956f 100644
--- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -31,8 +31,8 @@
  * OMAP HSMMC register definitions
  */
 
-#define OMAP_HSMMC1_BASE	0x4809C100
-#define OMAP_HSMMC2_BASE	0x480B4100
-#define OMAP_HSMMC3_BASE	0x480AD100
+#define OMAP_HSMMC1_BASE	0x4809C000
+#define OMAP_HSMMC2_BASE	0x480B4000
+#define OMAP_HSMMC3_BASE	0x480AD000
 
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index b5e5519fbd..0fd3d85d29 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -58,11 +58,13 @@
 #define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
 #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
+#define DRA762_CONTROL_ID_CODE_ES1_0		0x0BB5002F
 #define DRA752_CONTROL_ID_CODE_ES1_0		0x0B99002F
 #define DRA752_CONTROL_ID_CODE_ES1_1		0x1B99002F
 #define DRA752_CONTROL_ID_CODE_ES2_0		0x2B99002F
 #define DRA722_CONTROL_ID_CODE_ES1_0		0x0B9BC02F
 #define DRA722_CONTROL_ID_CODE_ES2_0		0x1B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_1		0x2B9BC02F
 
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index c870a72980..fb563ee542 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -35,6 +35,13 @@ struct pad_conf_entry {
 	u32 val;
 };
 
+struct omap_hsmmc_pinctrl_state {
+	struct pad_conf_entry *padconf;
+	int npads;
+	struct iodelay_cfg_entry *iodelay;
+	int niodelays;
+};
+
 struct omap_sysinfo {
 	char *board_string;
 };
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 3e178be954..951a407515 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -602,6 +602,7 @@ extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
 
 extern struct pmic_data tps659038;
 extern struct pmic_data lp8733;
+extern struct pmic_data lp87565;
 
 void hw_data_init(void);
 
@@ -702,6 +703,7 @@ static inline u8 is_omap54xx(void)
 
 #define DRA7XX		0x07000000
 #define DRA72X		0x07200000
+#define DRA76X		0x07600000
 
 static inline u8 is_dra7xx(void)
 {
@@ -714,6 +716,12 @@ static inline u8 is_dra72x(void)
 	extern u32 *const omap_si_rev;
 	return (*omap_si_rev & 0xFFF00000) == DRA72X;
 }
+
+static inline u8 is_dra76x(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xFFF00000) == DRA76X;
+}
 #endif
 
 /*
@@ -741,11 +749,13 @@ static inline u8 is_dra72x(void)
 #define OMAP5432_ES2_0  0x54320200
 
 /* DRA7XX */
+#define DRA762_ES1_0	0x07620100
 #define DRA752_ES1_0	0x07520100
 #define DRA752_ES1_1	0x07520110
 #define DRA752_ES2_0	0x07520200
 #define DRA722_ES1_0	0x07220100
 #define DRA722_ES2_0	0x07220200
+#define DRA722_ES2_1	0x07220210
 
 /*
  * SRAM scratch space entries
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 767f8ec50a..abfdc2ef4f 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -26,7 +26,7 @@
 #define OMAP_MMC_H_
 
 struct hsmmc {
-#ifdef CONFIG_DM_MMC
+#ifndef CONFIG_OMAP34XX
 	unsigned int hl_rev;
 	unsigned int hl_hwinfo;
 	unsigned int hl_sysconfig;
@@ -225,7 +225,9 @@ struct hsmmc {
 
 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 		int wp_gpio);
-
 int platform_fixup_disable_uhs_mode(void);
+struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
+	(struct hsmmc *base, const char *mode);
 void vmmc_pbias_config(uint voltage);
+void board_mmc_poweron_ldo(uint voltage);
 #endif /* OMAP_MMC_H_ */
diff --git a/arch/arm/mach-keystone/include/mach/mmc_host_def.h b/arch/arm/mach-keystone/include/mach/mmc_host_def.h
index a5050ac0f1..b8eed7d29b 100644
--- a/arch/arm/mach-keystone/include/mach/mmc_host_def.h
+++ b/arch/arm/mach-keystone/include/mach/mmc_host_def.h
@@ -16,7 +16,7 @@
  * OMAP HSMMC register definitions
  */
 
-#define OMAP_HSMMC1_BASE	0x23000100
-#define OMAP_HSMMC2_BASE	0x23100100
+#define OMAP_HSMMC1_BASE	0x23000000
+#define OMAP_HSMMC2_BASE	0x23100000
 
 #endif /* K2G_MMC_HOST_DEF_H */
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index ce4acc13e0..677e043797 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -684,7 +684,7 @@ int board_eth_init(bd_t *bis)
 	return rv;
 }
 #endif /* defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) */
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(1, 0, 0, -1, -1);
diff --git a/board/amazon/kc1/kc1.c b/board/amazon/kc1/kc1.c
index 469a83eeef..b3fa7896c5 100644
--- a/board/amazon/kc1/kc1.c
+++ b/board/amazon/kc1/kc1.c
@@ -166,12 +166,10 @@ int fb_set_reboot_flag(void)
 	return omap_reboot_mode_store("b");
 }
 
-#ifndef CONFIG_SPL_BUILD
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(1, 0, 0, -1, -1);
 }
-#endif
 
 void board_mmc_power_init(void)
 {
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 189d903b6e..d3f11a7376 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -372,7 +372,7 @@ void set_muxconf_regs(void)
 		cm_t3730_set_muxconf();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 #define SB_T35_WP_GPIO 59
 
 int board_mmc_getcd(struct mmc *mmc)
diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c
index 8aae248042..d9da6d00d6 100644
--- a/board/compulab/cm_t3517/cm_t3517.c
+++ b/board/compulab/cm_t3517/cm_t3517.c
@@ -115,7 +115,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 #define SB_T35_CD_GPIO 144
 #define SB_T35_WP_GPIO 59
 
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c
index b4f5d40654..7b58fcd21f 100644
--- a/board/compulab/cm_t54/cm_t54.c
+++ b/board/compulab/cm_t54/cm_t54.c
@@ -96,7 +96,7 @@ uint mmc_get_env_part(struct mmc *mmc)
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 #define SB_T54_CD_GPIO 228
 #define SB_T54_WP_GPIO 229
 
diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
index 0009452651..029f20b86c 100644
--- a/board/corscience/tricorder/tricorder.c
+++ b/board/corscience/tricorder/tricorder.c
@@ -140,7 +140,7 @@ void set_muxconf_regs(void)
 	MUX_TRICORDER();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD))
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c
index 9671c5aa54..f35c77ba5a 100644
--- a/board/gumstix/duovero/duovero.c
+++ b/board/gumstix/duovero/duovero.c
@@ -110,17 +110,19 @@ void set_muxconf_regs(void)
 		   sizeof(struct pad_conf_entry));
 }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 
+#if !defined(CONFIG_SPL_BUILD)
 void board_mmc_power_init(void)
 {
 	twl6030_power_mmc_init(0);
 }
 #endif
+#endif
 
 #if defined(CONFIG_CMD_NET)
 
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
index 4330cf0ddb..06510b2008 100644
--- a/board/htkw/mcx/mcx.c
+++ b/board/htkw/mcx/mcx.c
@@ -100,7 +100,7 @@ void set_muxconf_regs(void)
 	MUX_MCX();
 }
 
-#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_OMAP_HSMMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index d1a6a6f56f..ec340e038f 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -140,7 +140,7 @@ static void setup_net_chip(void)
 static inline void setup_net_chip(void) {}
 #endif
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c
index 0662449c38..3c0a6db81a 100644
--- a/board/lg/sniper/sniper.c
+++ b/board/lg/sniper/sniper.c
@@ -178,12 +178,10 @@ int fb_set_reboot_flag(void)
 	return omap_reboot_mode_store("b");
 }
 
-#ifndef CONFIG_SPL_BUILD
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(1, 0, 0, -1, -1);
 }
-#endif
 
 void board_mmc_power_init(void)
 {
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index 1f1e5aedb0..5819aa582f 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -152,7 +152,7 @@ void set_muxconf_regs(void)
 	MUX_AM3517EVM();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index 51d2987566..adba90dbb1 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -252,7 +252,7 @@ int board_late_init(void)
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
index 77e4482906..555f5c0e01 100644
--- a/board/quipos/cairo/cairo.c
+++ b/board/quipos/cairo/cairo.c
@@ -62,7 +62,7 @@ void set_muxconf_regs(void)
 	MUX_CAIRO();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
index d51b5d940c..cba48d48fc 100644
--- a/board/technexion/tao3530/tao3530.c
+++ b/board/technexion/tao3530/tao3530.c
@@ -179,7 +179,7 @@ void set_muxconf_regs(void)
 #endif
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
index 48d207fbd4..70c4ce5b8d 100644
--- a/board/technexion/twister/twister.c
+++ b/board/technexion/twister/twister.c
@@ -130,8 +130,7 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
-#if defined(CONFIG_OMAP_HSMMC) && \
-	!defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_OMAP_HSMMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
index c2de1fec62..9307258cba 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -291,8 +291,7 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
-#if defined(CONFIG_OMAP_HSMMC) && \
-	!defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_OMAP_HSMMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
index 8d1c390e5d..faa95d7da8 100644
--- a/board/ti/am3517crane/am3517crane.c
+++ b/board/ti/am3517crane/am3517crane.c
@@ -63,7 +63,7 @@ void set_muxconf_regs(void)
 	MUX_AM3517CRANE();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 00f05986b4..72c4312837 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -712,7 +712,7 @@ err:
 }
 #endif
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0, 0, 0, -1, -1);
@@ -721,6 +721,67 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#if defined(CONFIG_IODELAY_RECALIBRATION) && \
+	(defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
+
+struct pinctrl_desc {
+	const char *name;
+	struct omap_hsmmc_pinctrl_state *pinctrl;
+};
+
+static struct pinctrl_desc pinctrl_descs_hsmmc1[] = {
+	{"default", &hsmmc1_default},
+	{"hs", &hsmmc1_default},
+	{NULL}
+};
+
+static struct pinctrl_desc pinctrl_descs_hsmmc2_am572[] = {
+	{"default", &hsmmc2_default_hs},
+	{"hs", &hsmmc2_default_hs},
+	{"ddr_1_8v", &hsmmc2_ddr_am572},
+	{NULL}
+};
+
+static struct pinctrl_desc pinctrl_descs_hsmmc2_am571[] = {
+	{"default", &hsmmc2_default_hs},
+	{"hs", &hsmmc2_default_hs},
+	{"ddr_1_8v", &hsmmc2_ddr_am571},
+	{NULL}
+};
+
+struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
+				  (struct hsmmc *base, const char *mode)
+{
+	struct pinctrl_desc *p = NULL;
+
+	switch ((uint32_t)base) {
+	case OMAP_HSMMC1_BASE:
+		p = pinctrl_descs_hsmmc1;
+		break;
+	case OMAP_HSMMC2_BASE:
+		if (is_dra72x())
+			p = pinctrl_descs_hsmmc2_am571;
+		else
+			p = pinctrl_descs_hsmmc2_am572;
+		break;
+	default:
+		break;
+	}
+
+	if (!p) {
+		printf("%s no pinctrl defined for MMC@%p\n", __func__,
+		       base);
+		return NULL;
+	}
+	while (p->name) {
+		if (strcmp(mode, p->name) == 0)
+			return p->pinctrl;
+		p++;
+	}
+	return NULL;
+}
+#endif
+
 #ifdef CONFIG_OMAP_HSMMC
 int platform_fixup_disable_uhs_mode(void)
 {
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index aff274c74f..3c99905dd2 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -985,4 +985,136 @@ const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
 };
 
 #endif
+
+#if defined(CONFIG_IODELAY_RECALIBRATION) && \
+	(defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
+
+static struct iodelay_cfg_entry mmc2_iodelay_ddr_am572[] = {
+	{0x18c, 270, 0	/* CFG_GPMC_A19_IN */},
+	{0x1a4, 0, 0	/* CFG_GPMC_A20_IN */},
+	{0x1b0, 170, 0	/* CFG_GPMC_A21_IN */},
+	{0x1bc, 758, 0	/* CFG_GPMC_A22_IN */},
+	{0x1c8, 0, 0	/* CFG_GPMC_A23_IN */},
+	{0x1d4, 81, 0	/* CFG_GPMC_A24_IN */},
+	{0x1e0, 286, 0	/* CFG_GPMC_A25_IN */},
+	{0x1ec, 0, 0	/* CFG_GPMC_A26_IN */},
+	{0x1f8, 123, 0	/* CFG_GPMC_A27_IN */},
+	{0x360, 346, 0	/* CFG_GPMC_CS1_IN */},
+	{0x190, 0, 0	/* CFG_GPMC_A19_OEN */},
+	{0x194, 55, 0	/* CFG_GPMC_A19_OUT */},
+	{0x1a8, 0, 0	/* CFG_GPMC_A20_OEN */},
+	{0x1ac, 422, 0	/* CFG_GPMC_A20_OUT */},
+	{0x1b4, 642, 0	/* CFG_GPMC_A21_OEN */},
+	{0x1b8, 0, 0	/* CFG_GPMC_A21_OUT */},
+	{0x1c0, 0, 0	/* CFG_GPMC_A22_OEN */},
+	{0x1c4, 128, 0	/* CFG_GPMC_A22_OUT */},
+	{0x1d0, 0, 0	/* CFG_GPMC_A23_OUT */},
+	{0x1d8, 0, 0	/* CFG_GPMC_A24_OEN */},
+	{0x1dc, 395, 0	/* CFG_GPMC_A24_OUT */},
+	{0x1e4, 0, 0	/* CFG_GPMC_A25_OEN */},
+	{0x1e8, 0, 0	/* CFG_GPMC_A25_OUT */},
+	{0x1f0, 623, 0	/* CFG_GPMC_A26_OEN */},
+	{0x1f4, 0, 0	/* CFG_GPMC_A26_OUT */},
+	{0x1fc, 54, 0	/* CFG_GPMC_A27_OEN */},
+	{0x200, 0, 0	/* CFG_GPMC_A27_OUT */},
+	{0x364, 0, 0	/* CFG_GPMC_CS1_OEN */},
+	{0x368, 0, 0	/* CFG_GPMC_CS1_OUT */},
+};
+
+static struct iodelay_cfg_entry mmc2_iodelay_ddr_am571[] = {
+	{0x18c, 0, 0,	/* CFG_GPMC_A19_IN */},
+	{0x1a4, 121, 0,	/* CFG_GPMC_A20_IN */},
+	{0x1b0, 0, 0,	/* CFG_GPMC_A21_IN */},
+	{0x1bc, 20, 0,	/* CFG_GPMC_A22_IN */},
+	{0x1c8, 108, 0,	/* CFG_GPMC_A23_IN */},
+	{0x1d4, 31, 0,	/* CFG_GPMC_A24_IN */},
+	{0x1e0, 0, 0,	/* CFG_GPMC_A25_IN */},
+	{0x1ec, 24, 0,	/* CFG_GPMC_A26_IN */},
+	{0x1f8, 0, 0,	/* CFG_GPMC_A27_IN */},
+	{0x360, 0, 0,	/* CFG_GPMC_CS1_IN */},
+	{0x194, 152, 0,	/* CFG_GPMC_A19_OUT */},
+	{0x1ac, 206, 0,	/* CFG_GPMC_A20_OUT */},
+	{0x1b8, 78, 0,	/* CFG_GPMC_A21_OUT */},
+	{0x1c4, 2, 0,	/* CFG_GPMC_A22_OUT */},
+	{0x1d0, 266, 0,	/* CFG_GPMC_A23_OUT */},
+	{0x1dc, 0, 0,	/* CFG_GPMC_A24_OUT */},
+	{0x1e8, 0, 0,	/* CFG_GPMC_A25_OUT */},
+	{0x1f4, 43, 0,	/* CFG_GPMC_A26_OUT */},
+	{0x200, 0, 0,	/* CFG_GPMC_A27_OUT */},
+	{0x368, 0, 0,	/* CFG_GPMC_CS1_OUT */},
+	{0x190, 0, 0,	/* CFG_GPMC_A19_OEN */},
+	{0x1a8, 0, 0,	/* CFG_GPMC_A20_OEN */},
+	{0x1b4, 0, 0,	/* CFG_GPMC_A21_OEN */},
+	{0x1c0, 0, 0,	/* CFG_GPMC_A22_OEN */},
+	{0x1d8, 0, 0,	/* CFG_GPMC_A24_OEN */},
+	{0x1e4, 0, 0,	/* CFG_GPMC_A25_OEN */},
+	{0x1f0, 0, 0,	/* CFG_GPMC_A26_OEN */},
+	{0x1fc, 0, 0,	/* CFG_GPMC_A27_OEN */},
+	{0x364, 0, 0,	/* CFG_GPMC_CS1_OEN */},
+};
+
+static struct pad_conf_entry hsmmc1_default_padconf[] = {
+	{MMC1_CLK,  (M0 | PIN_INPUT_PULLUP) /* mmc1_clk.clk */},
+	{MMC1_CMD,  (M0 | PIN_INPUT_PULLUP) /* mmc1_cmd.cmd */},
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat0.dat0 */},
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat1.dat1 */},
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat2.dat2 */},
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat3.dat3 */},
+};
+
+static struct pad_conf_entry mmc2_pins_ddr[] = {
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a23.mmc2_clk */},
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_cs1.mmc2_cmd */},
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a24.mmc2_dat0 */},
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a25.mmc2_dat1 */},
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a26.mmc2_dat2 */},
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a27.mmc2_dat3 */},
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a19.mmc2_dat4 */},
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a20.mmc2_dat5 */},
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a21.mmc2_dat6 */},
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a22.mmc2_dat7 */},
+};
+
+static struct pad_conf_entry mmc2_pins_default_hs[] = {
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP) /* g pmc_a23.mmc2_clk */},
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP) /* gpmc_cs1.mmc2_cmd */},
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP) /* gpmc_a24.mmc2_dat0 */},
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP) /* gpmc_a25.mmc2_dat1 */},
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP) /* gpmc_a26.mmc2_dat2 */},
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP) /* gpmc_a27.mmc2_dat3 */},
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP) /* gpmc_a19.mmc2_dat4 */},
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP) /* gpmc_a20.mmc2_dat5 */},
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP) /* gpmc_a21.mmc2_dat6 */},
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP) /* gpmc_a22.mmc2_dat7 */},
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc1_default = {
+	.padconf = hsmmc1_default_padconf,
+	.npads = ARRAY_SIZE(hsmmc1_default_padconf),
+	.iodelay = NULL,
+	.niodelays = 0,
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_default_hs = {
+	.padconf = mmc2_pins_default_hs,
+	.npads = ARRAY_SIZE(mmc2_pins_default_hs),
+	.iodelay = NULL,
+	.niodelays = 0,
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_am572 = {
+	.padconf = mmc2_pins_ddr,
+	.npads = ARRAY_SIZE(mmc2_pins_ddr),
+	.iodelay = mmc2_iodelay_ddr_am572,
+	.niodelays = ARRAY_SIZE(mmc2_iodelay_ddr_am572),
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_am571 = {
+	.padconf = mmc2_pins_ddr,
+	.npads = ARRAY_SIZE(mmc2_pins_ddr),
+	.iodelay = mmc2_iodelay_ddr_am571,
+	.niodelays = ARRAY_SIZE(mmc2_iodelay_ddr_am571),
+};
+
+#endif
 #endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 0ed4f52771..ddcfe7d46d 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -523,7 +523,7 @@ void set_muxconf_regs(void)
 	MUX_BEAGLE();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 1b8c898c19..145f044f88 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -35,6 +35,7 @@
 #include "mux_data.h"
 #include "../common/board_detect.h"
 
+#define board_is_dra76x_evm()		board_ti_is("DRA76/7x")
 #define board_is_dra74x_evm()		board_ti_is("5777xCPU")
 #define board_is_dra72x_evm()		board_ti_is("DRA72x-T")
 #define board_is_dra71x_evm()		board_ti_is("DRA79x,D")
@@ -210,6 +211,56 @@ const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
 	.emif_rd_wr_exec_thresh         = 0x00000305
 };
 
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
+	.sdram_config_init              = 0x61862B32,
+	.sdram_config                   = 0x61862B32,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl                       = 0x0000514C,
+	.ref_ctrl_final			= 0x0000144A,
+	.sdram_tim1                     = 0xD113783C,
+	.sdram_tim2                     = 0x30B47FE3,
+	.sdram_tim3                     = 0x409F8AD8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x5007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0824400D,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400D,
+	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
+	.emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
+	.emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
+	.emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
+	.sdram_config_init              = 0x61862B32,
+	.sdram_config                   = 0x61862B32,
+	.sdram_config2			= 0x00000000,
+	.ref_ctrl                       = 0x0000514C,
+	.ref_ctrl_final			= 0x0000144A,
+	.sdram_tim1                     = 0xD113781C,
+	.sdram_tim2                     = 0x30B47FE3,
+	.sdram_tim3                     = 0x409F8AD8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x5007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0824400D,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400D,
+	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
+	.emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
+	.emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
+	.emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 {
 	u64 ram_size;
@@ -235,8 +286,15 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 			break;
 		}
 		break;
+	case DRA762_ES1_0:
+		if (emif_nr == 1)
+			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
+		else
+			*regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
+		break;
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		if (ram_size < CONFIG_MAX_MEM_MAPPED)
 			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 		else
@@ -290,6 +348,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	ram_size = board_ti_get_emif_size();
 
 	switch (omap_revision()) {
+	case DRA762_ES1_0:
 	case DRA752_ES1_0:
 	case DRA752_ES1_1:
 	case DRA752_ES2_0:
@@ -300,6 +359,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 		break;
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 	default:
 		if (ram_size < CONFIG_MAX_MEM_MAPPED)
 			*dmm_lisa_regs = &lisa_map_2G_x_2;
@@ -357,6 +417,54 @@ struct vcores_data dra752_volts = {
 	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 };
 
+struct vcores_data dra76x_volts = {
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.mpu.addr	= LP87565_REG_ADDR_BUCK01,
+	.mpu.pmic	= &lp87565,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr	= TPS65917_REG_ADDR_SMPS1,
+	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr	= LP87565_REG_ADDR_BUCK23,
+	.gpu.pmic	= &lp87565,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= TPS65917_REG_ADDR_SMPS3,
+	.core.pmic	= &tps659038,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr	= TPS65917_REG_ADDR_SMPS4,
+	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
 struct vcores_data dra722_volts = {
 	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
 	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
@@ -439,14 +547,18 @@ struct vcores_data dra718_volts = {
 	 * and are powered by BUCK1 of LP873X PMIC
 	 */
 	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
 	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.eve.addr	= LP873X_REG_ADDR_BUCK1,
 	.eve.pmic	= &lp8733,
 	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
 	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
 	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
 	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.iva.addr	= LP873X_REG_ADDR_BUCK1,
 	.iva.pmic	= &lp8733,
@@ -457,27 +569,44 @@ int get_voltrail_opp(int rail_offset)
 {
 	int opp;
 
-	/*
-	 * DRA71x supports only OPP_NOM.
-	 */
-	if (board_is_dra71x_evm())
-		return OPP_NOM;
-
 	switch (rail_offset) {
 	case VOLT_MPU:
 		opp = DRA7_MPU_OPP;
+		/* DRA71x supports only OPP_NOM for MPU */
+		if (board_is_dra71x_evm())
+			opp = OPP_NOM;
 		break;
 	case VOLT_CORE:
 		opp = DRA7_CORE_OPP;
+		/* DRA71x supports only OPP_NOM for CORE */
+		if (board_is_dra71x_evm())
+			opp = OPP_NOM;
 		break;
 	case VOLT_GPU:
 		opp = DRA7_GPU_OPP;
+		/* DRA71x supports only OPP_NOM for GPU */
+		if (board_is_dra71x_evm())
+			opp = OPP_NOM;
 		break;
 	case VOLT_EVE:
 		opp = DRA7_DSPEVE_OPP;
+		/*
+		 * DRA71x does not support OPP_OD for EVE.
+		 * If OPP_OD is selected by menuconfig, fallback
+		 * to OPP_NOM.
+		 */
+		if (board_is_dra71x_evm() && opp == OPP_OD)
+			opp = OPP_NOM;
 		break;
 	case VOLT_IVA:
 		opp = DRA7_IVA_OPP;
+		/*
+		 * DRA71x does not support OPP_OD for IVA.
+		 * If OPP_OD is selected by menuconfig, fallback
+		 * to OPP_NOM.
+		 */
+		if (board_is_dra71x_evm() && opp == OPP_OD)
+			opp = OPP_NOM;
 		break;
 	default:
 		opp = OPP_NOM;
@@ -538,6 +667,8 @@ int board_late_init(void)
 			name = "dra71x";
 		else
 			name = "dra72x";
+	} else if (is_dra76x()) {
+		name = "dra76x";
 	} else {
 		name = "dra7xx";
 	}
@@ -586,6 +717,8 @@ void do_board_detect(void)
 		bname = "DRA72x EVM";
 	} else if (board_is_dra71x_evm()) {
 		bname = "DRA71x EVM";
+	} else if (board_is_dra76x_evm()) {
+		bname = "DRA76x EVM";
 	} else {
 		/* If EEPROM is not populated */
 		if (is_dra72x())
@@ -608,6 +741,8 @@ void vcores_update(void)
 		*omap_vcores = &dra722_volts;
 	} else if (board_is_dra71x_evm()) {
 		*omap_vcores = &dra718_volts;
+	} else if (board_is_dra76x_evm()) {
+		*omap_vcores = &dra76x_volts;
 	} else {
 		/* If EEPROM is not populated */
 		if (is_dra72x())
@@ -634,6 +769,7 @@ void recalibrate_iodelay(void)
 	switch (omap_revision()) {
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		pads = dra72x_core_padconf_array_common;
 		npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 		if (board_is_dra71x_evm()) {
@@ -662,6 +798,12 @@ void recalibrate_iodelay(void)
 		iodelay = dra742_es1_1_iodelay_cfg_array;
 		niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 		break;
+	case DRA762_ES1_0:
+		pads = dra76x_core_padconf_array;
+		npads = ARRAY_SIZE(dra76x_core_padconf_array);
+		iodelay = dra76x_es1_0_iodelay_cfg_array;
+		niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
+		break;
 	default:
 	case DRA752_ES2_0:
 		pads = dra74x_core_padconf_array;
@@ -694,16 +836,115 @@ err:
 }
 #endif
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0, 0, 0, -1, -1);
 	omap_mmc_init(1, 0, 0, -1, -1);
 	return 0;
 }
+
+void board_mmc_poweron_ldo(uint voltage)
+{
+	if (board_is_dra71x_evm()) {
+		if (voltage == LDO_VOLT_3V0)
+			voltage = 0x19;
+		else if (voltage == LDO_VOLT_1V8)
+			voltage = 0xa;
+		lp873x_mmc1_poweron_ldo(voltage);
+	} else if (board_is_dra76x_evm()) {
+		palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
+	} else {
+		palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
+	}
+}
 #endif
 
 #ifdef CONFIG_OMAP_HSMMC
+#if defined(CONFIG_IODELAY_RECALIBRATION) && \
+	(defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC))
+
+struct pinctrl_desc {
+	const char *name;
+	struct omap_hsmmc_pinctrl_state *pinctrl;
+};
+
+static struct pinctrl_desc pinctrl_descs_hsmmc1[] = {
+	{"default", &hsmmc1_default},
+	{"hs", &hsmmc1_default},
+	{NULL}
+};
+
+static struct pinctrl_desc pinctrl_descs_hsmmc2_rev20[] = {
+	{"default", &hsmmc2_default_hs},
+	{"hs", &hsmmc2_default_hs},
+	{"ddr_1_8v", &hsmmc2_ddr_1v8_rev20},
+	{"hs200_1_8v", &hsmmc2_hs200_1v8_rev20},
+	{NULL}
+};
+
+static struct pinctrl_desc pinctrl_descs_hsmmc2_rev11[] = {
+	{"default", &hsmmc2_default_hs},
+	{"hs", &hsmmc2_default_hs},
+	{"ddr_1_8v", &hsmmc2_ddr_1v8_rev11},
+	{"hs200_1_8v", &hsmmc2_hs200_1v8_rev11},
+	{NULL}
+};
+
+static struct pinctrl_desc pinctrl_descs_hsmmc2_dra72x[] = {
+	{"default", &hsmmc2_default_hs},
+	{"hs", &hsmmc2_default_hs},
+	{"ddr_1_8v", &hsmmc2_ddr_1v8_dra72},
+	{"hs200_1_8v", &hsmmc2_hs200_1v8_dra72},
+	{NULL}
+};
+
+static struct pinctrl_desc pinctrl_descs_hsmmc2_dra76x[] = {
+	{"default", &hsmmc2_default_hs},
+	{"hs", &hsmmc2_default_hs},
+	{"ddr_1_8v", &hsmmc2_default_hs},
+	{"hs200_1_8v", &hsmmc2_hs200_1v8_dra76},
+	{NULL}
+};
+
+struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
+				  (struct hsmmc *base, const char *mode)
+{
+	struct pinctrl_desc *p = NULL;
+
+	switch ((uint32_t)base) {
+	case OMAP_HSMMC1_BASE:
+		p = pinctrl_descs_hsmmc1;
+		break;
+	case OMAP_HSMMC2_BASE:
+		if ((omap_revision() == DRA752_ES1_0) ||
+		    (omap_revision() == DRA752_ES1_1))
+			p = pinctrl_descs_hsmmc2_rev11;
+		else if (is_dra72x())
+			p = pinctrl_descs_hsmmc2_dra72x;
+		else if (is_dra76x())
+			p = pinctrl_descs_hsmmc2_dra76x;
+		else if (is_dra7xx())
+			p = pinctrl_descs_hsmmc2_rev20;
+		break;
+	default:
+		break;
+	}
+
+	if (!p) {
+		printf("%s no pinctrl defined for MMC@%p\n", __func__,
+		       base);
+		return NULL;
+	}
+	while (p->name) {
+		if (strcmp(mode, p->name) == 0)
+			return p->pinctrl;
+		p++;
+	}
+	return NULL;
+}
+#endif
+
 int platform_fixup_disable_uhs_mode(void)
 {
 	return omap_revision() == DRA752_ES1_1;
@@ -942,8 +1183,8 @@ static inline void vtt_regulator_enable(void)
 	if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 		return;
 
-	/* Do not enable VTT for DRA722 */
-	if (is_dra72x())
+	/* Do not enable VTT for DRA722 or DRA76x */
+	if (is_dra72x() || is_dra76x())
 		return;
 
 	/*
@@ -974,7 +1215,9 @@ int board_fit_config_name_match(const char *name)
 		} else if (!strcmp(name, "dra72-evm")) {
 			return 0;
 		}
-	} else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
+	} else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
+		return 0;
+	} else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
 		return 0;
 	}
 
diff --git a/board/ti/dra7xx/lateattach.c b/board/ti/dra7xx/lateattach.c
index f294806fd3..14e152e8d1 100644
--- a/board/ti/dra7xx/lateattach.c
+++ b/board/ti/dra7xx/lateattach.c
@@ -171,6 +171,11 @@
 #define DRA7_PGTBL_BASE_DSP1                 0xbfc10000
 #define DRA7_PGTBL_BASE_DSP2                 0xbfc18000
 
+#define DRA7_PGTBL_BASE_IPU1                 0xbfc00000
+#define DRA7_PGTBL_BASE_IPU2                 0xbfc08000
+#define DRA7_PGTBL_BASE_DSP1                 0xbfc10000
+#define DRA7_PGTBL_BASE_DSP2                 0xbfc18000
+
 /*
  * The page table (32 KB) is placed at the end of the CMA reserved area.
  * It's possible that this location is needed by the firmware (in which
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 731c5521af..3fe52b19b2 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -448,6 +448,26 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = {
 	{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_scl.hdmi1_ddc_sda */
 	{WAKEUP0, (M15 | PULL_UP)},	/* Wakeup0.safe for dcan1_rx */
 	{WAKEUP3, (M1 | PULL_ENA | PULL_UP)},	/* Wakeup3.sys_nirq1 */
+#ifdef CONFIG_DRA7XX_JAMR3
+	{XREF_CLK1, (M5 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.atl_clk1 */
+	{XREF_CLK3, (M14 | PIN_INPUT)},		/* xref_clk3.gpio6_20 */
+	{MCASP1_AXR8, (M1 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},	/* mcasp1_axr8.mcasp6_axr0 */
+	{MCASP1_AXR9, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr9.mcasp6_axr1 */
+	{MCASP1_AXR10, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr10.mcasp6_aclkx */
+	{MCASP1_AXR11, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr11.mcasp6_fsx */
+	{MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)},	/* mcasp2_aclkx.mcasp2_aclkx */
+	{MCASP2_FSX, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)},		/* mcasp2_fsx.mcasp2_fsx */
+	{MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)},	/* mcasp2_axr0.mcasp2_axr0 */
+	{MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)},	/* mcasp2_axr1.mcasp2_axr1 */
+	{MCASP2_AXR2, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)},		/* mcasp2_axr2.mcasp2_axr2 */
+	{MCASP2_AXR3, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)},		/* mcasp2_axr3.mcasp2_axr3 */
+	{MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)},	/* mcasp2_axr4.mcasp2_axr4 */
+	{MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)},	/* mcasp2_axr5.mcasp2_axr5 */
+	{MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)},	/* mcasp2_axr6.mcasp2_axr6 */
+	{MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)},	/* mcasp2_axr7.mcasp2_axr7 */
+	{MCASP4_ACLKX, (M4 | PIN_INPUT_PULLUP)},/* mcasp4_aclkx.i2c4_sda */
+	{MCASP4_FSX, (M4 | PIN_INPUT_PULLUP)},	/* mcasp4_fsx.i2c4_scl */
+#endif
 };
 
 const struct pad_conf_entry early_padconf[] = {
@@ -846,6 +866,194 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = {
 
 };
 
+const struct pad_conf_entry dra76x_core_padconf_array[] = {
+	{GPMC_AD0, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad0.vout3_d0 */
+	{GPMC_AD1, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad1.vout3_d1 */
+	{GPMC_AD2, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad2.vout3_d2 */
+	{GPMC_AD3, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad3.vout3_d3 */
+	{GPMC_AD4, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad4.vout3_d4 */
+	{GPMC_AD5, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad5.vout3_d5 */
+	{GPMC_AD6, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad6.vout3_d6 */
+	{GPMC_AD7, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad7.vout3_d7 */
+	{GPMC_AD8, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad8.vout3_d8 */
+	{GPMC_AD9, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad9.vout3_d9 */
+	{GPMC_AD10, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad10.vout3_d10 */
+	{GPMC_AD11, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad11.vout3_d11 */
+	{GPMC_AD12, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad12.vout3_d12 */
+	{GPMC_AD13, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad13.vout3_d13 */
+	{GPMC_AD14, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad14.vout3_d14 */
+	{GPMC_AD15, (M3 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad15.vout3_d15 */
+	{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a0.vout3_d16 */
+	{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a1.vout3_d17 */
+	{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a2.vout3_d18 */
+	{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a3.vout3_d19 */
+	{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a4.vout3_d20 */
+	{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a5.vout3_d21 */
+	{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a6.vout3_d22 */
+	{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a7.vout3_d23 */
+	{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a8.vout3_hsync */
+	{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a9.vout3_vsync */
+	{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a10.vout3_de */
+	{GPMC_A11, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a11.gpio2_1 */
+	{GPMC_A12, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a12.gpio2_2 */
+	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLDOWN)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS0, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_cs0.gpmc_cs0 */
+	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{GPMC_CS3, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_cs3.vout3_clk */
+	{GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_advn_ale.gpmc_advn_ale */
+	{GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_oen_ren.gpmc_oen_ren */
+	{GPMC_WEN, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_wen.gpmc_wen */
+	{GPMC_BEN0, (M0 | PIN_INPUT_PULLUP)},	/* gpmc_ben0.gpmc_ben0 */
+	{GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* gpmc_wait0.gpmc_wait0 */
+	{VIN1A_FLD0, (M14 | PIN_INPUT_PULLUP)},	/* vin1a_fld0.gpio3_1 */
+	{VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_clk0.vin2a_clk0 */
+	{VIN2A_DE0, (M15 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_de0.Driveroff */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_hsync0.vin2a_hsync0 */
+	{VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_vsync0.vin2a_vsync0 */
+	{VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d0.vin2a_d0 */
+	{VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d1.vin2a_d1 */
+	{VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d2.vin2a_d2 */
+	{VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d3.vin2a_d3 */
+	{VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d4.vin2a_d4 */
+	{VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d5.vin2a_d5 */
+	{VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d6.vin2a_d6 */
+	{VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d7.vin2a_d7 */
+	{VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d8.vin2a_d8 */
+	{VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d9.vin2a_d9 */
+	{VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d10.vin2a_d10 */
+	{VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d11.vin2a_d11 */
+	{VIN2A_D12, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_de.vout1_de */
+	{VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)},	/* vout1_fld.gpio4_21 */
+	{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RGMII0_TXC, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_14.i2c3_sda */
+	{GPIO6_15, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_15.i2c3_scl */
+	{GPIO6_16, (M0 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.atl_clk2 */
+	{MCASP1_ACLKX, (M14 | 0x00070000)},	/* mcasp1_aclkx.gpio7_31 */
+	{MCASP1_FSX, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_fsx.gpio7_30 */
+	{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.i2c5_sda */
+	{MCASP1_AXR1, (M10 | 0x000f0000)},	/* mcasp1_axr1.i2c5_scl */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr15.mcasp7_fsx */
+	{MCASP2_ACLKR, (M15 | PIN_INPUT_PULLUP)},	/* mcasp2_aclkr.Driveroff */
+	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
+	{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mmc1_sdcd.mmc1_sdcd */
+	{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)},	/* mmc1_sdwp.gpio6_28 */
+	{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.spi1_sclk */
+	{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.spi1_d1 */
+	{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.spi1_d0 */
+	{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)},	/* spi1_cs0.spi1_cs0 */
+	{SPI1_CS2, (M6 | 0x000f0000)},	/* spi1_cs2.hdmi1_hpd */
+	{SPI1_CS3, (M6 | 0x000f0000)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.uart3_rxd */
+	{SPI2_D1, (M1 | PIN_INPUT_SLEW)},	/* spi2_d1.uart3_txd */
+	{SPI2_D0, (M1 | PIN_INPUT_SLEW)},	/* spi2_d0.uart3_ctsn */
+	{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.uart3_rtsn */
+	{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
+	{DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.dcan1_rx */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_ctsn.mmc4_clk */
+	{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_rtsn.mmc4_cmd */
+	{UART2_RXD, (M3 | PIN_INPUT_PULLUP)},	/* N/A.mmc4_dat0 */
+	{UART2_TXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_txd.mmc4_dat1 */
+	{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.mmc4_dat2 */
+	{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rtsn.mmc4_dat3 */
+	{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M14 | PIN_OUTPUT)},	/* N/A.gpio1_0 */
+	{WAKEUP1, (M14 | PIN_OUTPUT)},	/* N/A.gpio1_1 */
+	{WAKEUP2, (M1 | PIN_OUTPUT)},	/* N/A.sys_nirq2 */
+	{WAKEUP3, (M1 | PIN_OUTPUT)},	/* N/A.sys_nirq1 */
+};
+
 #ifdef CONFIG_IODELAY_RECALIBRATION
 const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
 	{0x06F0, 480, 0},	/* CFG_RGMII0_RXC_IN */
@@ -1057,6 +1265,402 @@ const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
 #endif
 
 };
+
+const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = {
+	{0x011C, 787, 0},	/* CFG_GPMC_A0_OUT */
+	{0x0128, 1181, 0},	/* CFG_GPMC_A10_OUT */
+	{0x0144, 0, 0},	/* CFG_GPMC_A13_IN */
+	{0x0150, 2149, 1052},	/* CFG_GPMC_A14_IN */
+	{0x015C, 2121, 997},	/* CFG_GPMC_A15_IN */
+	{0x0168, 2159, 1134},	/* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 2135, 1085},	/* CFG_GPMC_A17_IN */
+	{0x0188, 0, 0},	/* CFG_GPMC_A18_OUT */
+	{0x01A0, 592, 0},	/* CFG_GPMC_A1_OUT */
+	{0x020C, 641, 0},	/* CFG_GPMC_A2_OUT */
+	{0x0218, 1481, 0},	/* CFG_GPMC_A3_OUT */
+	{0x0224, 1775, 0},	/* CFG_GPMC_A4_OUT */
+	{0x0230, 785, 0},	/* CFG_GPMC_A5_OUT */
+	{0x023C, 848, 0},	/* CFG_GPMC_A6_OUT */
+	{0x0248, 851, 0},	/* CFG_GPMC_A7_OUT */
+	{0x0254, 1783, 0},	/* CFG_GPMC_A8_OUT */
+	{0x0260, 951, 0},	/* CFG_GPMC_A9_OUT */
+	{0x026C, 1091, 0},	/* CFG_GPMC_AD0_OUT */
+	{0x0278, 1027, 0},	/* CFG_GPMC_AD10_OUT */
+	{0x0284, 824, 0},	/* CFG_GPMC_AD11_OUT */
+	{0x0290, 1196, 0},	/* CFG_GPMC_AD12_OUT */
+	{0x029C, 754, 0},	/* CFG_GPMC_AD13_OUT */
+	{0x02A8, 665, 0},	/* CFG_GPMC_AD14_OUT */
+	{0x02B4, 1027, 0},	/* CFG_GPMC_AD15_OUT */
+	{0x02C0, 937, 0},	/* CFG_GPMC_AD1_OUT */
+	{0x02CC, 1168, 0},	/* CFG_GPMC_AD2_OUT */
+	{0x02D8, 872, 0},	/* CFG_GPMC_AD3_OUT */
+	{0x02E4, 1092, 0},	/* CFG_GPMC_AD4_OUT */
+	{0x02F0, 576, 0},	/* CFG_GPMC_AD5_OUT */
+	{0x02FC, 1113, 0},	/* CFG_GPMC_AD6_OUT */
+	{0x0308, 943, 0},	/* CFG_GPMC_AD7_OUT */
+	{0x0314, 0, 0},	/* CFG_GPMC_AD8_OUT */
+	{0x0320, 0, 0},	/* CFG_GPMC_AD9_OUT */
+	{0x0374, 0, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x0380, 1801, 948},	/* CFG_GPMC_CS3_OUT */
+	{0x06F0, 451, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 127, 1571},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 165, 1178},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 136, 1302},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 0, 1520},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 28, 1690},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 121, 0},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 60, 0},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 153, 0},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 35, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 0},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 172, 0},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A38, 0, 0},	/* CFG_VIN2A_CLK0_IN */
+	{0x0A44, 2180, 0},	/* CFG_VIN2A_D0_IN */
+	{0x0A50, 2297, 110},	/* CFG_VIN2A_D10_IN */
+	{0x0A5C, 1938, 0},	/* CFG_VIN2A_D11_IN */
+	{0x0A70, 147, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 110, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 18, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 82, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 33, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 0, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 417, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 156, 843},	/* CFG_VIN2A_D19_IN */
+	{0x0AC8, 2326, 309},	/* CFG_VIN2A_D1_IN */
+	{0x0AD4, 223, 1413},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 169, 1415},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 43, 1150},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1210},	/* CFG_VIN2A_D23_IN */
+	{0x0B04, 2057, 0},	/* CFG_VIN2A_D2_IN */
+	{0x0B10, 2440, 257},	/* CFG_VIN2A_D3_IN */
+	{0x0B1C, 2142, 0},	/* CFG_VIN2A_D4_IN */
+	{0x0B28, 2455, 252},	/* CFG_VIN2A_D5_IN */
+	{0x0B34, 1883, 0},	/* CFG_VIN2A_D6_IN */
+	{0x0B40, 2229, 0},	/* CFG_VIN2A_D7_IN */
+	{0x0B4C, 2250, 151},	/* CFG_VIN2A_D8_IN */
+	{0x0B58, 2279, 27},	/* CFG_VIN2A_D9_IN */
+	{0x0B7C, 2233, 0},	/* CFG_VIN2A_HSYNC0_IN */
+	{0x0B88, 1936, 0},	/* CFG_VIN2A_VSYNC0_IN */
+	{0x0B9C, 1281, 497},	/* CFG_VOUT1_CLK_OUT */
+	{0x0BA8, 379, 0},	/* CFG_VOUT1_D0_OUT */
+	{0x0BB4, 441, 0},	/* CFG_VOUT1_D10_OUT */
+	{0x0BC0, 461, 0},	/* CFG_VOUT1_D11_OUT */
+	{0x0BCC, 1189, 0},	/* CFG_VOUT1_D12_OUT */
+	{0x0BD8, 312, 0},	/* CFG_VOUT1_D13_OUT */
+	{0x0BE4, 298, 0},	/* CFG_VOUT1_D14_OUT */
+	{0x0BF0, 284, 0},	/* CFG_VOUT1_D15_OUT */
+	{0x0BFC, 152, 0},	/* CFG_VOUT1_D16_OUT */
+	{0x0C08, 216, 0},	/* CFG_VOUT1_D17_OUT */
+	{0x0C14, 408, 0},	/* CFG_VOUT1_D18_OUT */
+	{0x0C20, 519, 0},	/* CFG_VOUT1_D19_OUT */
+	{0x0C2C, 475, 0},	/* CFG_VOUT1_D1_OUT */
+	{0x0C38, 316, 0},	/* CFG_VOUT1_D20_OUT */
+	{0x0C44, 59, 0},	/* CFG_VOUT1_D21_OUT */
+	{0x0C50, 221, 0},	/* CFG_VOUT1_D22_OUT */
+	{0x0C5C, 96, 0},	/* CFG_VOUT1_D23_OUT */
+	{0x0C68, 264, 0},	/* CFG_VOUT1_D2_OUT */
+	{0x0C74, 421, 0},	/* CFG_VOUT1_D3_OUT */
+	{0x0C80, 1257, 0},	/* CFG_VOUT1_D4_OUT */
+	{0x0C8C, 432, 0},	/* CFG_VOUT1_D5_OUT */
+	{0x0C98, 436, 0},	/* CFG_VOUT1_D6_OUT */
+	{0x0CA4, 440, 0},	/* CFG_VOUT1_D7_OUT */
+	{0x0CB0, 81, 100},	/* CFG_VOUT1_D8_OUT */
+	{0x0CBC, 471, 0},	/* CFG_VOUT1_D9_OUT */
+	{0x0CC8, 0, 0},	/* CFG_VOUT1_DE_OUT */
+	{0x0CE0, 0, 0},	/* CFG_VOUT1_HSYNC_OUT */
+	{0x0CEC, 815, 0},	/* CFG_VOUT1_VSYNC_OUT */
+};
+#endif
+
+
+#if defined(CONFIG_IODELAY_RECALIBRATION) && \
+	(defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC)) && \
+	defined(CONFIG_OMAP_HSMMC)
+
+static struct pad_conf_entry hsmmc1_default_padconf[] = {
+	{MMC1_CLK,  (M0 | PIN_INPUT_PULLUP) /* mmc1_clk.clk */},
+	{MMC1_CMD,  (M0 | PIN_INPUT_PULLUP) /* mmc1_cmd.cmd */},
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat0.dat0 */},
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat1.dat1 */},
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat2.dat2 */},
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP) /* mmc1_dat3.dat3 */},
+};
+
+static struct pad_conf_entry mmc2_pins_default_hs[] = {
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP) /* g pmc_a23.mmc2_clk */},
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP) /* gpmc_cs1.mmc2_cmd */},
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP) /* gpmc_a24.mmc2_dat0 */},
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP) /* gpmc_a25.mmc2_dat1 */},
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP) /* gpmc_a26.mmc2_dat2 */},
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP) /* gpmc_a27.mmc2_dat3 */},
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP) /* gpmc_a19.mmc2_dat4 */},
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP) /* gpmc_a20.mmc2_dat5 */},
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP) /* gpmc_a21.mmc2_dat6 */},
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP) /* gpmc_a22.mmc2_dat7 */},
+};
+
+static struct pad_conf_entry mmc2_pins_ddr_hs200_1_8v[] = {
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a23.mmc2_clk */},
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_cs1.mmc2_cmd */},
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a24.mmc2_dat0 */},
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a25.mmc2_dat1 */},
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a26.mmc2_dat2 */},
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a27.mmc2_dat3 */},
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a19.mmc2_dat4 */},
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a20.mmc2_dat5 */},
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a21.mmc2_dat6 */},
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE) /* gpmc_a22.mmc2_dat7 */},
+};
+
+static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_rev11_conf[] = {
+	{0x190, 621, 600	/* CFG_GPMC_A19_OEN */},
+	{0x194, 300, 0		/* CFG_GPMC_A19_OUT */},
+	{0x1a8, 739, 600	/* CFG_GPMC_A20_OEN */},
+	{0x1ac, 240, 0		/* CFG_GPMC_A20_OUT */},
+	{0x1b4, 812, 600	/* CFG_GPMC_A21_OEN */},
+	{0x1b8, 240, 0		/* CFG_GPMC_A21_OUT */},
+	{0x1c0, 954, 600	/* CFG_GPMC_A22_OEN */},
+	{0x1c4, 60, 0		/* CFG_GPMC_A22_OUT */},
+	{0x1d0, 1340, 420	/* CFG_GPMC_A23_OUT */},
+	{0x1d8, 935, 600	/* CFG_GPMC_A24_OEN */},
+	{0x1dc, 0, 0		/* CFG_GPMC_A24_OUT */},
+	{0x1e4, 525, 600	/* CFG_GPMC_A25_OEN */},
+	{0x1e8, 120, 0		/* CFG_GPMC_A25_OUT */},
+	{0x1f0, 767, 600	/* CFG_GPMC_A26_OEN */},
+	{0x1f4, 225, 0		/* CFG_GPMC_A26_OUT */},
+	{0x1fc, 565, 600	/* CFG_GPMC_A27_OEN */},
+	{0x200, 60, 0		/* CFG_GPMC_A27_OUT */},
+	{0x364, 969, 600	/* CFG_GPMC_CS1_OEN */},
+	{0x368, 180, 0		/* CFG_GPMC_CS1_OUT */},
+};
+
+static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_rev20_conf[] = {
+	{0x190, 274, 0  /* CFG_GPMC_A19_OEN */},
+	{0x194, 162, 0  /* CFG_GPMC_A19_OUT */},
+	{0x1a8, 401, 0  /* CFG_GPMC_A20_OEN */},
+	{0x1ac, 73, 0   /* CFG_GPMC_A20_OUT */},
+	{0x1b4, 465, 0  /* CFG_GPMC_A21_OEN */},
+	{0x1b8, 115, 0  /* CFG_GPMC_A21_OUT */},
+	{0x1c0, 633, 0  /* CFG_GPMC_A22_OEN */},
+	{0x1c4, 47, 0   /* CFG_GPMC_A22_OUT */},
+	{0x1d0, 935, 280 /* CFG_GPMC_A23_OUT */},
+	{0x1d8, 621, 0  /* CFG_GPMC_A24_OEN */},
+	{0x1dc, 0, 0    /* CFG_GPMC_A24_OUT */},
+	{0x1e4, 183, 0  /* CFG_GPMC_A25_OEN */},
+	{0x1e8, 0, 0    /* CFG_GPMC_A25_OUT */},
+	{0x1f0, 467, 0  /* CFG_GPMC_A26_OEN */},
+	{0x1f4, 0, 0    /* CFG_GPMC_A26_OUT */},
+	{0x1fc, 262, 0  /* CFG_GPMC_A27_OEN */},
+	{0x200, 46, 0   /* CFG_GPMC_A27_OUT */},
+	{0x364, 684, 0  /* CFG_GPMC_CS1_OEN */},
+	{0x368, 76, 0   /* CFG_GPMC_CS1_OUT */},
+};
+
+static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_rev11_conf[] = {
+	{0x18c, 0, 0		/* CFG_GPMC_A19_IN */},
+	{0x1a4, 274, 240	/* CFG_GPMC_A20_IN */},
+	{0x1b0, 0, 60		/* CFG_GPMC_A21_IN */},
+	{0x1bc, 0, 60		/* CFG_GPMC_A22_IN */},
+	{0x1c8, 514, 360	/* CFG_GPMC_A23_IN */},
+	{0x1d4, 187, 120	/* CFG_GPMC_A24_IN */},
+	{0x1e0, 0, 0		/* CFG_GPMC_A25_IN */},
+	{0x1ec, 0, 60		/* CFG_GPMC_A26_IN */},
+	{0x1f8, 121, 60		/* CFG_GPMC_A27_IN */},
+	{0x360, 0, 0		/* CFG_GPMC_CS1_IN */},
+	{0x190, 0, 0		/* CFG_GPMC_A19_OEN */},
+	{0x194, 174, 0		/* CFG_GPMC_A19_OUT */},
+	{0x1a8, 0, 0		/* CFG_GPMC_A20_OEN */},
+	{0x1ac, 168, 0		/* CFG_GPMC_A20_OUT */},
+	{0x1b4, 0, 0		/* CFG_GPMC_A21_OEN */},
+	{0x1b8, 136, 0		/* CFG_GPMC_A21_OUT */},
+	{0x1c0, 0, 0		/* CFG_GPMC_A22_OEN */},
+	{0x1c4, 0, 0		/* CFG_GPMC_A22_OUT */},
+	{0x1d0, 879, 0		/* CFG_GPMC_A23_OUT */},
+	{0x1d8, 0, 0		/* CFG_GPMC_A24_OEN */},
+	{0x1dc, 0, 0		/* CFG_GPMC_A24_OUT */},
+	{0x1e4, 0, 0		/* CFG_GPMC_A25_OEN */},
+	{0x1e8, 34, 0		/* CFG_GPMC_A25_OUT */},
+	{0x1f0, 0, 0		/* CFG_GPMC_A26_OEN */},
+	{0x1f4, 120, 0		/* CFG_GPMC_A26_OUT */},
+	{0x1fc, 0, 0		/* CFG_GPMC_A27_OEN */},
+	{0x200, 0, 0		/* CFG_GPMC_A27_OUT */},
+	{0x364, 0, 0		/* CFG_GPMC_CS1_OEN */},
+	{0x368, 11, 0		/* CFG_GPMC_CS1_OUT */},
+};
+
+static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_rev20_conf[] = {
+	{0x18c, 270, 0	/* CFG_GPMC_A19_IN */},
+	{0x1a4, 0, 0	/* CFG_GPMC_A20_IN */},
+	{0x1b0, 170, 0	/* CFG_GPMC_A21_IN */},
+	{0x1bc, 758, 0	/* CFG_GPMC_A22_IN */},
+	{0x1c8, 0, 0	/* CFG_GPMC_A23_IN */},
+	{0x1d4, 81, 0	/* CFG_GPMC_A24_IN */},
+	{0x1e0, 286, 0	/* CFG_GPMC_A25_IN */},
+	{0x1ec, 0, 0	/* CFG_GPMC_A26_IN */},
+	{0x1f8, 123, 0	/* CFG_GPMC_A27_IN */},
+	{0x360, 346, 0	/* CFG_GPMC_CS1_IN */},
+	{0x190, 0, 0	/* CFG_GPMC_A19_OEN */},
+	{0x194, 55, 0	/* CFG_GPMC_A19_OUT */},
+	{0x1a8, 0, 0	/* CFG_GPMC_A20_OEN */},
+	{0x1ac, 422, 0	/* CFG_GPMC_A20_OUT */},
+	{0x1b4, 642, 0	/* CFG_GPMC_A21_OEN */},
+	{0x1b8, 0, 0	/* CFG_GPMC_A21_OUT */},
+	{0x1c0, 0, 0	/* CFG_GPMC_A22_OEN */},
+	{0x1c4, 128, 0	/* CFG_GPMC_A22_OUT */},
+	{0x1d0, 0, 0	/* CFG_GPMC_A23_OUT */},
+	{0x1d8, 0, 0	/* CFG_GPMC_A24_OEN */},
+	{0x1dc, 395, 0	/* CFG_GPMC_A24_OUT */},
+	{0x1e4, 0, 0	/* CFG_GPMC_A25_OEN */},
+	{0x1e8, 0, 0	/* CFG_GPMC_A25_OUT */},
+	{0x1f0, 623, 0	/* CFG_GPMC_A26_OEN */},
+	{0x1f4, 0, 0	/* CFG_GPMC_A26_OUT */},
+	{0x1fc, 54, 0	/* CFG_GPMC_A27_OEN */},
+	{0x200, 0, 0	/* CFG_GPMC_A27_OUT */},
+	{0x364, 0, 0	/* CFG_GPMC_CS1_OEN */},
+	{0x368, 0, 0	/* CFG_GPMC_CS1_OUT */},
+};
+
+static struct iodelay_cfg_entry mmc2_iodelay_ddr_1_8v_dra72_conf[] = {
+	{0x18c, 0, 0,	/* CFG_GPMC_A19_IN */},
+	{0x1a4, 121, 0,	/* CFG_GPMC_A20_IN */},
+	{0x1b0, 0, 0,	/* CFG_GPMC_A21_IN */},
+	{0x1bc, 20, 0,	/* CFG_GPMC_A22_IN */},
+	{0x1c8, 108, 0,	/* CFG_GPMC_A23_IN */},
+	{0x1d4, 31, 0,	/* CFG_GPMC_A24_IN */},
+	{0x1e0, 0, 0,	/* CFG_GPMC_A25_IN */},
+	{0x1ec, 24, 0,	/* CFG_GPMC_A26_IN */},
+	{0x1f8, 0, 0,	/* CFG_GPMC_A27_IN */},
+	{0x360, 0, 0,	/* CFG_GPMC_CS1_IN */},
+	{0x194, 152, 0,	/* CFG_GPMC_A19_OUT */},
+	{0x1ac, 206, 0,	/* CFG_GPMC_A20_OUT */},
+	{0x1b8, 78, 0,	/* CFG_GPMC_A21_OUT */},
+	{0x1c4, 2, 0,	/* CFG_GPMC_A22_OUT */},
+	{0x1d0, 266, 0,	/* CFG_GPMC_A23_OUT */},
+	{0x1dc, 0, 0,	/* CFG_GPMC_A24_OUT */},
+	{0x1e8, 0, 0,	/* CFG_GPMC_A25_OUT */},
+	{0x1f4, 43, 0,	/* CFG_GPMC_A26_OUT */},
+	{0x200, 0, 0,	/* CFG_GPMC_A27_OUT */},
+	{0x368, 0, 0,	/* CFG_GPMC_CS1_OUT */},
+	{0x190, 0, 0,	/* CFG_GPMC_A19_OEN */},
+	{0x1a8, 0, 0,	/* CFG_GPMC_A20_OEN */},
+	{0x1b4, 0, 0,	/* CFG_GPMC_A21_OEN */},
+	{0x1c0, 0, 0,	/* CFG_GPMC_A22_OEN */},
+	{0x1d8, 0, 0,	/* CFG_GPMC_A24_OEN */},
+	{0x1e4, 0, 0,	/* CFG_GPMC_A25_OEN */},
+	{0x1f0, 0, 0,	/* CFG_GPMC_A26_OEN */},
+	{0x1fc, 0, 0,	/* CFG_GPMC_A27_OEN */},
+	{0x364, 0, 0,	/* CFG_GPMC_CS1_OEN */},
+};
+
+static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_dra72_conf[] = {
+	{0x194, 150 , 95	/* CFG_GPMC_A19_OUT */},
+	{0x1AC, 250 , 0		/* CFG_GPMC_A20_OUT */},
+	{0x1B8, 125 , 0		/* CFG_GPMC_A21_OUT */},
+	{0x1C4, 100 , 0		/* CFG_GPMC_A22_OUT */},
+	{0x1D0, 870 , 415	/* CFG_GPMC_A23_OUT */},
+	{0x1DC, 30  , 0		/* CFG_GPMC_A24_OUT */},
+	{0x1E8, 200 , 0		/* CFG_GPMC_A25_OUT */},
+	{0x1F4, 200 , 0		/* CFG_GPMC_A26_OUT */},
+	{0x200, 0   , 0		/* CFG_GPMC_A27_OUT */},
+	{0x368, 240 , 0		/* CFG_GPMC_CS1_OUT */},
+	{0x190, 695 , 0		/* CFG_GPMC_A19_OEN */},
+	{0x1A8, 924 , 0		/* CFG_GPMC_A20_OEN */},
+	{0x1B4, 719 , 0		/* CFG_GPMC_A21_OEN */},
+	{0x1C0, 824 , 0		/* CFG_GPMC_A22_OEN */},
+	{0x1D8, 877 , 0		/* CFG_GPMC_A24_OEN */},
+	{0x1E4, 446 , 0		/* CFG_GPMC_A25_OEN */},
+	{0x1F0, 847 , 0		/* CFG_GPMC_A26_OEN */},
+	{0x1FC, 586 , 0		/* CFG_GPMC_A27_OEN */},
+	{0x364, 1039 , 0	/* CFG_GPMC_CS1_OEN */},
+};
+
+static struct iodelay_cfg_entry mmc2_iodelay_hs200_1_8v_dra76_conf[] = {
+	{0x190, 384 , 0		/* CFG_GPMC_A19_OEN */},
+	{0x194, 0   , 174	/* CFG_GPMC_A19_OUT */},
+	{0x1A8, 410 , 0		/* CFG_GPMC_A20_OEN */},
+	{0x1AC, 85  , 0		/* CFG_GPMC_A20_OUT */},
+	{0x1B4, 468 , 0		/* CFG_GPMC_A21_OEN */},
+	{0x1B8, 139 , 0		/* CFG_GPMC_A21_OUT */},
+	{0x1C0, 676 , 0		/* CFG_GPMC_A22_OEN */},
+	{0x1C4, 69  , 0		/* CFG_GPMC_A22_OUT */},
+	{0x1D0, 1062, 154	/* CFG_GPMC_A23_OUT */},
+	{0x1D8, 640 , 0		/* CFG_GPMC_A24_OEN */},
+	{0x1DC, 0   , 0		/* CFG_GPMC_A24_OUT */},
+	{0x1E4, 356 , 0		/* CFG_GPMC_A25_OEN */},
+	{0x1E8, 0   , 0		/* CFG_GPMC_A25_OUT */},
+	{0x1F0, 579 , 0		/* CFG_GPMC_A26_OEN */},
+	{0x1F4, 0   , 0		/* CFG_GPMC_A26_OUT */},
+	{0x1FC, 435 , 0		/* CFG_GPMC_A27_OEN */},
+	{0x200, 36  , 0		/* CFG_GPMC_A27_OUT */},
+	{0x364, 759 , 0		/* CFG_GPMC_CS1_OEN */},
+	{0x368, 72  , 0		/* CFG_GPMC_CS1_OUT */},
+};
+
+#define dimof(t) (sizeof(t) / sizeof(t[0]))
+static struct omap_hsmmc_pinctrl_state hsmmc1_default = {
+	.padconf = hsmmc1_default_padconf,
+	.npads = dimof(hsmmc1_default_padconf),
+	.iodelay = NULL,
+	.niodelays = 0,
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_default_hs = {
+	.padconf = mmc2_pins_default_hs,
+	.npads = dimof(mmc2_pins_default_hs),
+	.iodelay = NULL,
+	.niodelays = 0,
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_rev11 = {
+	.padconf = mmc2_pins_ddr_hs200_1_8v,
+	.npads = dimof(mmc2_pins_ddr_hs200_1_8v),
+	.iodelay = mmc2_iodelay_ddr_1_8v_rev11_conf,
+	.niodelays = dimof(mmc2_iodelay_ddr_1_8v_rev11_conf),
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_rev20 = {
+	.padconf = mmc2_pins_ddr_hs200_1_8v,
+	.npads = dimof(mmc2_pins_ddr_hs200_1_8v),
+	.iodelay = mmc2_iodelay_ddr_1_8v_rev20_conf,
+	.niodelays = dimof(mmc2_iodelay_ddr_1_8v_rev20_conf),
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_rev11 = {
+	.padconf = mmc2_pins_ddr_hs200_1_8v,
+	.npads = dimof(mmc2_pins_ddr_hs200_1_8v),
+	.iodelay = mmc2_iodelay_hs200_1_8v_rev11_conf,
+	.niodelays = dimof(mmc2_iodelay_hs200_1_8v_rev11_conf),
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_rev20 = {
+	.padconf = mmc2_pins_ddr_hs200_1_8v,
+	.npads = dimof(mmc2_pins_ddr_hs200_1_8v),
+	.iodelay = mmc2_iodelay_hs200_1_8v_rev20_conf,
+	.niodelays = dimof(mmc2_iodelay_hs200_1_8v_rev20_conf),
+};
+
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_ddr_1v8_dra72 = {
+	.padconf = mmc2_pins_ddr_hs200_1_8v,
+	.npads = dimof(mmc2_pins_ddr_hs200_1_8v),
+	.iodelay = mmc2_iodelay_ddr_1_8v_dra72_conf,
+	.niodelays = dimof(mmc2_iodelay_ddr_1_8v_dra72_conf),
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_dra72 = {
+	.padconf = mmc2_pins_ddr_hs200_1_8v,
+	.npads = dimof(mmc2_pins_ddr_hs200_1_8v),
+	.iodelay = mmc2_iodelay_hs200_1_8v_dra72_conf,
+	.niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra72_conf),
+};
+
+static struct omap_hsmmc_pinctrl_state hsmmc2_hs200_1v8_dra76 = {
+	.padconf = mmc2_pins_ddr_hs200_1_8v,
+	.npads = dimof(mmc2_pins_ddr_hs200_1_8v),
+	.iodelay = mmc2_iodelay_hs200_1_8v_dra76_conf,
+	.niodelays = dimof(mmc2_iodelay_hs200_1_8v_dra76_conf),
+};
 #endif
 
 #endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index ff3971dda8..4f132e5107 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -259,7 +259,7 @@ int board_eth_init(bd_t *bis)
 }
 #endif /* CONFIG_CMD_NET */
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index c6fab08e3b..79e6830ba7 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -103,7 +103,7 @@ s16 divn_val[16] = {
 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 };
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	if (psc_enable_module(KS2_LPSC_MMC)) {
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 50da4109bb..55089ec8d3 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -211,7 +211,7 @@ void set_muxconf_regs(void)
 		   sizeof(struct pad_conf_entry));
 }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 13b5dafe82..187ff3cff4 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -287,17 +287,19 @@ void set_muxconf_regs(void)
 			   sizeof(struct pad_conf_entry));
 }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 
+#if !defined(CONFIG_SPL_BUILD)
 void board_mmc_power_init(void)
 {
 	twl6030_power_mmc_init(0);
 }
 #endif
+#endif
 
 #ifdef CONFIG_USB_EHCI
 
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index 6037cdd6c1..0eb60e4271 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -73,7 +73,7 @@ void set_muxconf_regs(void)
 				 sizeof(struct pad_conf_entry));
 }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0, 0, 0, -1, -1);
@@ -81,12 +81,14 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 
+#if !defined(CONFIG_SPL_BUILD)
 void board_mmc_power_init(void)
 {
 	twl6030_power_mmc_init(0);
 	twl6030_power_mmc_init(1);
 }
 #endif
+#endif
 
 /*
  * get_board_rev() - get board revision
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index e406dabfc0..e85794c60e 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -111,7 +111,7 @@ int board_init(void)
 	return 0;
 }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(1, 0, 0, -1, -1);
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index 965252f18d..c9857f2fc9 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -130,7 +130,7 @@ void set_muxconf_regs(void)
 	MUX_DEVKIT8000();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/common/env_ext4.c b/common/env_ext4.c
index ce748ed8c7..54d897278a 100644
--- a/common/env_ext4.c
+++ b/common/env_ext4.c
@@ -42,6 +42,10 @@ int env_init(void)
 	gd->env_addr = (ulong)&default_environment[0];
 	gd->env_valid = 1;
 
+	/* intialize the MMC sub-system if env is stored on a MMC*/
+	if (!strcmp(EXT4_ENV_INTERFACE, "mmc"))
+		mmc_initialize(NULL);
+
 	return 0;
 }
 
diff --git a/common/env_fat.c b/common/env_fat.c
index 75616d4c5b..1ed1ff6166 100644
--- a/common/env_fat.c
+++ b/common/env_fat.c
@@ -31,6 +31,10 @@ int env_init(void)
 	gd->env_addr = (ulong)&default_environment[0];
 	gd->env_valid = 1;
 
+	/* intialize the MMC sub-system if env is stored on a MMC*/
+	if (!strcmp(FAT_ENV_INTERFACE, "mmc"))
+		mmc_initialize(NULL);
+
 	return 0;
 }
 
diff --git a/common/env_mmc.c b/common/env_mmc.c
index 303920d418..d2b1a29259 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -64,6 +64,11 @@ int env_init(void)
 	/* use default */
 	gd->env_addr	= (ulong)&default_environment[0];
 	gd->env_valid	= 1;
+	/*
+	 * intialize the MMC sub-system. This will probe the
+	 * MMC controllers if not already done
+	 */
+	mmc_initialize(NULL);
 
 	return 0;
 }
@@ -82,10 +87,6 @@ static int mmc_set_env_part(struct mmc *mmc)
 	int dev = mmc_get_env_dev();
 	int ret = 0;
 
-#ifdef CONFIG_SPL_BUILD
-	dev = 0;
-#endif
-
 	env_mmc_orig_hwpart = mmc->block_dev.hwpart;
 	ret = mmc_select_hwpart(dev, part);
 	if (ret)
@@ -116,9 +117,6 @@ static void fini_mmc_for_env(struct mmc *mmc)
 #ifdef CONFIG_SYS_MMC_ENV_PART
 	int dev = mmc_get_env_dev();
 
-#ifdef CONFIG_SPL_BUILD
-	dev = 0;
-#endif
 	mmc_select_hwpart(dev, env_mmc_orig_hwpart);
 #endif
 }
@@ -223,10 +221,6 @@ void env_relocate_spec(void)
 	ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env1, 1);
 	ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env2, 1);
 
-#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_ENV_SUPPORT)
-	dev = 0;
-#endif
-
 	mmc = find_mmc_device(dev);
 
 	errmsg = init_mmc_for_env(mmc);
@@ -306,10 +300,6 @@ void env_relocate_spec(void)
 	int dev = mmc_get_env_dev();
 	const char *errmsg;
 
-#ifdef CONFIG_SPL_BUILD
-	dev = 0;
-#endif
-
 	mmc = find_mmc_device(dev);
 
 	errmsg = init_mmc_for_env(mmc);
diff --git a/common/env_sf.c b/common/env_sf.c
index 273098ceb6..a41c0e89e3 100644
--- a/common/env_sf.c
+++ b/common/env_sf.c
@@ -19,16 +19,16 @@
 #include <dm/device-internal.h>
 
 #ifndef CONFIG_ENV_SPI_BUS
-# define CONFIG_ENV_SPI_BUS	0
+# define CONFIG_ENV_SPI_BUS	CONFIG_SF_DEFAULT_BUS
 #endif
 #ifndef CONFIG_ENV_SPI_CS
-# define CONFIG_ENV_SPI_CS	0
+# define CONFIG_ENV_SPI_CS	CONFIG_SF_DEFAULT_CS
 #endif
 #ifndef CONFIG_ENV_SPI_MAX_HZ
-# define CONFIG_ENV_SPI_MAX_HZ	1000000
+# define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
 #endif
 #ifndef CONFIG_ENV_SPI_MODE
-# define CONFIG_ENV_SPI_MODE	SPI_MODE_3
+# define CONFIG_ENV_SPI_MODE	CONFIG_SF_DEFAULT_MODE
 #endif
 
 #ifdef CONFIG_ENV_OFFSET_REDUND
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 8e2b92ce96..9e53adba5e 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -97,9 +97,8 @@ static void write_raw_image(struct blk_desc *dev_desc, disk_partition_t *info,
 	fastboot_okay(response_str, "");
 }
 
-void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
-			void *download_buffer, unsigned int download_bytes,
-			char *response)
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+			unsigned int download_bytes, char *response)
 {
 	struct blk_desc *dev_desc;
 	disk_partition_t info;
@@ -141,7 +140,6 @@ void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
 	if (is_sparse_image(download_buffer)) {
 		struct fb_mmc_sparse sparse_priv;
 		sparse_storage_t sparse;
-		int ret;
 
 		sparse_priv.dev_desc = dev_desc;
 
@@ -154,15 +152,7 @@ void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
 		printf("Flashing sparse image at offset " LBAFU "\n",
 		       info.start);
 
-		ret = store_sparse_image(&sparse, &sparse_priv, session_id,
-				   download_buffer);
-		if (ret) {
-			printf("%s: writing sparse image failed: %d\n",
-					__func__, ret);
-			fastboot_fail(response_str,
-					"writing sparse image failed");
-			return;
-		}
+		store_sparse_image(&sparse, &sparse_priv, download_buffer);
 	} else {
 		write_raw_image(dev_desc, &info, cmd, download_buffer,
 				download_bytes);
diff --git a/common/fb_nand.c b/common/fb_nand.c
index 9ca8602a73..896ed6df6c 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -126,7 +126,7 @@ static int fb_nand_sparse_write(struct sparse_storage *storage,
 	return written / storage->block_sz;
 }
 
-void fb_nand_flash_write(const char *partname, unsigned int session_id,
+void fb_nand_flash_write(const char *partname,
 			 void *download_buffer, unsigned int download_bytes,
 			 char *response)
 {
@@ -161,7 +161,7 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id,
 		sparse.name = part->name;
 		sparse.write = fb_nand_sparse_write;
 
-		ret = store_sparse_image(&sparse, &sparse_priv, session_id,
+		ret = store_sparse_image(&sparse, &sparse_priv,
 					 download_buffer);
 	} else {
 		printf("Flashing raw image at offset 0x%llx\n",
diff --git a/common/image-sparse.c b/common/image-sparse.c
index 2bf737b46c..893c68b35f 100644
--- a/common/image-sparse.c
+++ b/common/image-sparse.c
@@ -52,8 +52,6 @@ typedef struct sparse_buffer {
 	u16	type;
 } sparse_buffer_t;
 
-static uint32_t last_offset;
-
 static unsigned int sparse_get_chunk_data_size(sparse_header_t *sparse,
 					       chunk_header_t *chunk)
 {
@@ -267,8 +265,8 @@ static void sparse_put_data_buffer(sparse_buffer_t *buffer)
 	free(buffer);
 }
 
-int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
-		       unsigned int session_id, void *data)
+int store_sparse_image(sparse_storage_t *storage,
+		       void *storage_priv, void *data)
 {
 	unsigned int chunk, offset;
 	sparse_header_t *sparse_header;
@@ -303,19 +301,10 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
 		return -EINVAL;
 	}
 
-	/*
-	 * If it's a new flashing session, start at the beginning of
-	 * the partition. If not, then simply resume where we were.
-	 */
-	if (session_id > 0)
-		start = last_offset;
-	else
-		start = storage->start;
-
-	printf("Flashing sparse image on partition %s at offset 0x%x (ID: %d)\n",
-	       storage->name, start * storage->block_sz, session_id);
+	puts("Flashing Sparse Image\n");
 
 	/* Start processing chunks */
+	start = storage->start;
 	for (chunk = 0; chunk < sparse_header->total_chunks; chunk++) {
 		uint32_t blkcnt;
 
@@ -390,7 +379,5 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
 		return -EIO;
 	}
 
-	last_offset = start + total_blocks;
-
 	return 0;
 }
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 7ded395e9a..28b8da73d1 100755
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -59,7 +59,7 @@ __weak int spl_start_uboot(void)
 
 void spl_fixup_fdt(void)
 {
-#ifdef CONFIG_SPL_OF_LIBFDT
+#if defined(CONFIG_SPL_OF_LIBFDT) && defined(CONFIG_SYS_SPL_ARGS_ADDR)
 	void *fdt_blob = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
 	int err;
 
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index b0d577df32..8bd57cd8a7 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -37,6 +37,8 @@ CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PMIC_LP87565=y
+CONFIG_DM_REGULATOR_LP87565=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
@@ -49,12 +51,12 @@ CONFIG_USB_DWC3_PHY_OMAP=y
 CONFIG_USB_GADGET=y
 CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
-CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
 CONFIG_DM_ETH=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_PMIC_LP873X=y
-CONFIG_SPL_LOAD_FIT=y
 CONFIG_DISK=y
 CONFIG_DWC_AHCI=y
 CONFIG_DM_MMC=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 59776f7daf..1b68c49feb 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_TI_SECURE_EMIF_REGION_START=0xbe000000
+CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
 CONFIG_DM_SERIAL=y
@@ -41,6 +41,8 @@ CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PMIC_LP87565=y
+CONFIG_DM_REGULATOR_LP87565=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
@@ -55,7 +57,7 @@ CONFIG_FIT=y
 CONFIG_SPL_OF_LIBFDT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_PANIC_ON_NON_FIT_IMAGE=y
-CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
+CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
 CONFIG_DM_ETH=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PALMAS=y
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 0670b16a2e..82a023190b 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -386,7 +386,7 @@ static int mmc_go_idle(struct mmc *mmc)
 
 static int mmc_host_uhs(struct mmc *mmc)
 {
-	return mmc->cfg->host_caps &
+	return mmc->host_ok_caps &
 	(MMC_MODE_UHS_SDR12 | MMC_MODE_UHS_SDR25 |
 	MMC_MODE_UHS_SDR50 | MMC_MODE_UHS_SDR104 |
 	MMC_MODE_UHS_DDR50);
@@ -663,7 +663,7 @@ static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 
 static void mmc_select_card_type(struct mmc *mmc, char card_type)
 {
-	u32 caps = mmc->cfg->host_caps;
+	u32 caps = mmc->host_ok_caps;
 	uint hs_max_dtr = mmc->tran_speed;
 
 	if (caps & MMC_MODE_HS &&
@@ -1094,7 +1094,7 @@ static int mmc_app_set_bus_width(struct mmc *mmc, int width)
 
 static void sd_update_bus_speed_mode(struct mmc *mmc)
 {
-	u32 caps = mmc->cfg->host_caps;
+	u32 caps = mmc->host_ok_caps;
 	/*
 	 * If the host doesn't support any of the UHS-I modes, fallback on
 	 * default speed.
@@ -1238,8 +1238,8 @@ static int mmc_sd_switch_hs(struct mmc *mmc)
 	 * This can avoid furthur problem when the card runs in different
 	 * mode between the host.
 	 */
-	if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
-	      (mmc->cfg->host_caps & MMC_MODE_HS)))
+	if (!((mmc->host_ok_caps & MMC_MODE_HS_52MHz) &&
+	      (mmc->host_ok_caps & MMC_MODE_HS)))
 		return -EINVAL;
 
 	if (!(mmc->card_caps & MMC_MODE_HS))
@@ -1350,7 +1350,7 @@ retry_scr:
 		mmc->card_caps |= MMC_MODE_HS;
 
 	/* Restrict card's capabilities by what the host can do */
-	mmc->card_caps &= mmc->cfg->host_caps;
+	mmc->card_caps &= mmc->host_ok_caps;
 
 	if (mmc->ocr & OCR_S18R) {
 		mmc_sd_init_uhs_card(mmc);
@@ -1513,16 +1513,15 @@ static int mmc_select_bus_width(struct mmc *mmc)
 		MMC_BUS_WIDTH_8,
 		MMC_BUS_WIDTH_4,
 	};
-	const struct mmc_config *cfg = mmc->cfg;
 	ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
 	ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
 	unsigned idx = 0, bus_width = 0;
 	int err = 0;
 
-	if (!(cfg->host_caps & (MMC_MODE_8BIT | MMC_MODE_4BIT)))
+	if (!(mmc->host_ok_caps & (MMC_MODE_8BIT | MMC_MODE_4BIT)))
 		return 0;
 
-	idx = (cfg->host_caps & MMC_MODE_8BIT) ? 0 : 1;
+	idx = (mmc->host_ok_caps & MMC_MODE_8BIT) ? 0 : 1;
 
 	err = mmc_send_ext_csd(mmc, ext_csd);
 	if (err)
@@ -1887,16 +1886,22 @@ static int mmc_startup(struct mmc *mmc)
 		if (mmc->timing == MMC_TIMING_MMC_HS200) {
 			err = mmc->cfg->ops->execute_tuning(mmc,
 						MMC_SEND_TUNING_BLOCK_HS200);
-			if (err)
-				return err;
+			if (err) {
+				printf("Tuning failed, dropping HS200 mode.\n");
+				mmc->host_ok_caps &= ~MMC_MODE_HS200;
+				return -EAGAIN;
+			}
 		} else if (mmc->timing == MMC_TIMING_MMC_HS) {
 			err = mmc_select_bus_width(mmc);
 			if (err)
 				return err;
 
 			err = mmc_select_hs_ddr(mmc);
-			if (err)
-				return err;
+			if (err) {
+				printf("dropping DDR52 mode.\n");
+				mmc->host_ok_caps &= ~MMC_MODE_DDR_52MHz;
+				return -EAGAIN;
+			}
 		}
 	}
 
@@ -2161,19 +2166,26 @@ static int mmc_complete_init(struct mmc *mmc)
 int mmc_init(struct mmc *mmc)
 {
 	int err = 0;
-	unsigned start;
+	int retries = 0;
+	__maybe_unused unsigned start;
 
 	if (mmc->has_init)
 		return 0;
 
+	mmc->host_ok_caps = mmc->cfg->host_caps;
 	start = get_timer(0);
 
-	if (!mmc->init_in_progress)
-		err = mmc_start_init(mmc);
+	do {
+		retries++;
+		if (!mmc->init_in_progress)
+			err = mmc_start_init(mmc);
 
-	if (!err)
-		err = mmc_complete_init(mmc);
-	debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
+		if (!err)
+			err = mmc_complete_init(mmc);
+	} while (err == -EAGAIN);
+
+	debug("%s: %d, time %lu (retries %d)\n", __func__, err,
+	      get_timer(start), retries - 1);
 	return err;
 }
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 2849519a58..0162be44ad 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -59,13 +59,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SYSCTL_SRC	(1 << 25)
 #define SYSCTL_SRD	(1 << 26)
 
-#ifdef CONFIG_IODELAY_RECALIBRATION
-struct omap_hsmmc_pinctrl_state {
-	struct pad_conf_entry *padconf;
-	int npads;
-	struct iodelay_cfg_entry *iodelay;
-	int niodelays;
-};
+#ifndef CONFIG_OMAP34XX
+#define SUPPORTS_ADMA
 #endif
 
 struct omap_hsmmc_data {
@@ -83,18 +78,22 @@ struct omap_hsmmc_data {
 	int wp_gpio;
 #endif
 #endif
-#ifdef CONFIG_DM_MMC
-	uint iov;
-	uint timing;
+
+#ifdef SUPPORTS_ADMA
 	u8 controller_flags;
 	struct omap_hsmmc_adma_desc *adma_desc_table;
 	uint desc_slot;
-	int node;
+#endif
+	ushort last_cmd;
+	uint iov;
+	uint timing;
 	char *version;
+
+#ifdef CONFIG_DM_MMC
+	int node;
 	struct udevice *vmmc_supply;
 	struct udevice *vmmc_aux_supply;
-	ushort last_cmd;
-	uint signal_voltage;
+#endif
 #ifdef CONFIG_IODELAY_RECALIBRATION
 	struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 	struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
@@ -106,10 +105,10 @@ struct omap_hsmmc_data {
 	struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 	struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 #endif
-#endif
+	uint signal_voltage;
 };
 
-#ifdef CONFIG_DM_MMC
+#ifdef SUPPORTS_ADMA
 struct omap_hsmmc_adma_desc {
 	u8 attr;
 	u8 reserved;
@@ -245,8 +244,51 @@ void mmc_init_stream(struct hsmmc *mmc_base)
 	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 }
 
-#ifdef CONFIG_DM_MMC
 #ifdef CONFIG_IODELAY_RECALIBRATION
+#ifdef DEBUG
+static inline void show_mmc_timing(struct mmc *mmc)
+{
+	const char *str;
+	switch (mmc->timing) {
+	case MMC_TIMING_MMC_HS200:
+		str = "HS200";
+		break;
+	case MMC_TIMING_UHS_SDR104:
+		str = "SDR104";
+		break;
+	case MMC_TIMING_UHS_DDR50:
+		str = "DDR50";
+		break;
+	case MMC_TIMING_UHS_SDR50:
+		str = "SDR50";
+		break;
+	case MMC_TIMING_UHS_SDR25:
+		str = "SDR25";
+		break;
+	case MMC_TIMING_UHS_SDR12:
+		str = "SDR12";
+		break;
+	case MMC_TIMING_SD_HS:
+		str = "HS(sd)";
+		break;
+	case MMC_TIMING_MMC_HS:
+		str = "HS(mmc)";
+		break;
+	case MMC_TIMING_MMC_DDR52:
+		str = "DDR52";
+		break;
+	default:
+		str = "std";
+		break;
+	}
+	printf("mmc %d mode %s\n", mmc->block_dev.devnum + 1, str);
+}
+#else
+static inline void show_mmc_timing(struct mmc *mmc)
+{
+}
+#endif
+
 static void omap_hsmmc_set_timing(struct mmc *mmc)
 {
 	u32 val;
@@ -317,6 +359,7 @@ static void omap_hsmmc_set_timing(struct mmc *mmc)
 
 	omap_hsmmc_start_clock(mmc_base);
 	priv->timing = mmc->timing;
+	show_mmc_timing(mmc);
 }
 #endif
 
@@ -428,7 +471,7 @@ static int omap_hsmmc_card_busy(struct mmc *mmc)
 	return ret;
 }
 
-#ifdef CONFIG_DM_REGULATOR
+#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC)
 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int uV)
 {
 	int ret;
@@ -474,10 +517,12 @@ static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 		writel(val, &mmc_base->ac12);
 
 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
-#ifdef CONFIG_DM_REGULATOR
+#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC)
 		return omap_hsmmc_set_io_regulator(mmc, 3000000);
 #else
-		vmmc_pbias_config(LDO_VOLT_3V0);
+		/* PBIAS config needed for MMC1 only */
+		if ((uint32_t) mmc_base == OMAP_HSMMC1_BASE)
+			vmmc_pbias_config(LDO_VOLT_3V0);
 #endif
 #endif
 	} else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
@@ -492,10 +537,12 @@ static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 		writel(val, &mmc_base->ac12);
 
 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
-#ifdef CONFIG_DM_REGULATOR
+#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC)
 		return omap_hsmmc_set_io_regulator(mmc, 1800000);
 #else
-		vmmc_pbias_config(LDO_VOLT_1V8);
+		/* PBIAS config needed for MMC1 only */
+		if ((uint32_t) mmc_base == OMAP_HSMMC1_BASE)
+			vmmc_pbias_config(LDO_VOLT_1V8);
 #endif
 #endif
 	} else {
@@ -505,6 +552,7 @@ static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 	return 0;
 }
 
+#if defined(CONFIG_DM_MMC)
 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
 {
 	struct hsmmc *mmc_base;
@@ -533,6 +581,7 @@ static void omap_hsmmc_set_capabilities(struct mmc *mmc)
 
 	writel(val, &mmc_base->capa);
 }
+#endif
 
 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 {
@@ -650,7 +699,7 @@ tuning_error:
 	return ret;
 }
 
-#ifdef CONFIG_DM_REGULATOR
+#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC)
 static int omap_hsmmc_set_vdd(struct mmc *mmc, int enable)
 {
 	struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
@@ -666,7 +715,6 @@ static int omap_hsmmc_set_vdd(struct mmc *mmc, int enable)
 	return 0;
 }
 #endif
-#endif
 
 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 {
@@ -694,11 +742,9 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
 	unsigned int reg_val;
 	unsigned int dsor;
 	ulong start;
-#ifdef CONFIG_DM_MMC
 	struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
-#endif
 
-	mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
+	mmc_base = priv->base_addr;
 	mmc_board_init(mmc);
 
 	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
@@ -720,12 +766,15 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
 		}
 	}
 
-#ifdef CONFIG_DM_MMC
-	omap_hsmmc_set_capabilities(mmc);
-	omap_hsmmc_conf_bus_power(mmc, priv->iov);
+#ifdef SUPPORTS_ADMA
 	reg_val = readl(&mmc_base->hl_hwinfo);
 	if (reg_val & MADMA_EN)
 		priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
+#endif
+
+#ifdef CONFIG_DM_MMC
+	omap_hsmmc_set_capabilities(mmc);
+	omap_hsmmc_conf_bus_power(mmc, priv->iov);
 #else
 	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
@@ -810,7 +859,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 	}
 }
 
-#ifdef CONFIG_DM_MMC
+#ifdef SUPPORTS_ADMA
 static int omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 {
 	struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
@@ -927,7 +976,7 @@ static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	struct hsmmc *mmc_base;
 	unsigned int flags, mmc_stat;
 	ulong start;
-#ifdef CONFIG_DM_MMC
+#ifdef SUPPORTS_ADMA
 	struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
 	priv->last_cmd = cmd->cmdidx;
 #endif
@@ -1006,7 +1055,7 @@ static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		else
 			flags |= (DP_DATA | DDIR_WRITE);
 
-#ifdef CONFIG_DM_MMC
+#ifdef SUPPORTS_ADMA
 		if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
 		    cmd->cmdidx != MMC_SEND_TUNING_BLOCK_HS200) {
 			omap_hsmmc_prepare_data(mmc, data);
@@ -1051,7 +1100,7 @@ static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		}
 	}
 
-#ifdef CONFIG_DM_MMC
+#ifdef SUPPORTS_ADMA
 	if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
 	    cmd->cmdidx != MMC_SEND_TUNING_BLOCK_HS200) {
 		if (mmc_stat & IE_ADMAE) {
@@ -1286,14 +1335,12 @@ static int omap_hsmmc_set_ios(struct mmc *mmc)
 	else
 		omap_hsmmc_start_clock(mmc_base);
 
-#ifdef CONFIG_DM_MMC
-#ifdef CONFIG_IODELAY_RECALIBRATION
+#if defined(CONFIG_IODELAY_RECALIBRATION)
 	if (priv_data->timing != mmc->timing)
 		omap_hsmmc_set_timing(mmc);
 #endif
 	if (priv_data->signal_voltage != mmc->signal_voltage)
 		ret = omap_hsmmc_set_signal_voltage(mmc);
-#endif
 
 	return ret;
 }
@@ -1365,104 +1412,35 @@ static const struct mmc_ops omap_hsmmc_ops = {
 	.getcd		= omap_hsmmc_getcd,
 	.getwp		= omap_hsmmc_getwp,
 #endif
-#ifdef CONFIG_DM_MMC
 	.execute_tuning = omap_hsmmc_execute_tuning,
 	.card_busy = omap_hsmmc_card_busy,
-#ifdef CONFIG_DM_REGULATOR
+#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC)
 	.set_vdd	= omap_hsmmc_set_vdd,
 #endif
-#endif
 };
 
-#ifndef CONFIG_DM_MMC
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
-		int wp_gpio)
+#ifdef CONFIG_IODELAY_RECALIBRATION
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_MMC)
+__weak struct omap_hsmmc_pinctrl_state *platform_fixup_get_pinctrl_by_mode
+				(struct hsmmc *base, const char *mode)
 {
-	struct mmc *mmc;
-	struct omap_hsmmc_data *priv_data;
-	struct mmc_config *cfg;
-	uint host_caps_val;
-
-	priv_data = malloc(sizeof(*priv_data));
-	if (priv_data == NULL)
-		return -1;
-
-	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
-
-	switch (dev_index) {
-	case 0:
-		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
-		break;
-#ifdef OMAP_HSMMC2_BASE
-	case 1:
-		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
-#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
-	defined(CONFIG_DRA7XX) || \
-	defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
-		defined(CONFIG_HSMMC2_8BIT)
-		/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
-		host_caps_val |= MMC_MODE_8BIT;
-#endif
-		break;
-#endif
-#ifdef OMAP_HSMMC3_BASE
-	case 2:
-		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
-#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
-		/* Enable 8-bit interface for eMMC on DRA7XX */
-		host_caps_val |= MMC_MODE_8BIT;
-#endif
-		break;
-#endif
-	default:
-		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
-		return 1;
-	}
-#ifdef OMAP_HSMMC_USE_GPIO
-	/* on error gpio values are set to -1, which is what we want */
-	priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
-	priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
-#endif
-
-	cfg = &priv_data->cfg;
-
-	cfg->name = "OMAP SD/MMC";
-	cfg->ops = &omap_hsmmc_ops;
-
-	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-	cfg->host_caps = host_caps_val & ~host_caps_mask;
-
-	cfg->f_min = 400000;
-
-	if (f_max != 0)
-		cfg->f_max = f_max;
-	else {
-		if (cfg->host_caps & MMC_MODE_HS) {
-			if (cfg->host_caps & MMC_MODE_HS_52MHz)
-				cfg->f_max = 52000000;
-			else
-				cfg->f_max = 26000000;
-		} else
-			cfg->f_max = 20000000;
-	}
-
-	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+	static struct omap_hsmmc_pinctrl_state empty = {
+		.padconf = NULL,
+		.npads = 0,
+		.iodelay = NULL,
+		.niodelays = 0,
+	};
+	return &empty;
+}
 
-#if defined(CONFIG_OMAP34XX)
-	/*
-	 * Silicon revs 2.1 and older do not support multiblock transfers.
-	 */
-	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
-		cfg->b_max = 1;
-#endif
-	mmc = mmc_create(cfg, priv_data);
-	if (mmc == NULL)
-		return -1;
+static struct omap_hsmmc_pinctrl_state *
+omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
+{
+	struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
 
-	return 0;
+	return platform_fixup_get_pinctrl_by_mode(priv->base_addr, mode);
 }
 #else
-#ifdef CONFIG_IODELAY_RECALIBRATION
 static struct pad_conf_entry *
 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
 {
@@ -1476,9 +1454,9 @@ omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
 	}
 
 	while (index < count) {
-		padconf[index].offset = fdt32_to_cpu(pinctrl[index]);
-		padconf[index].val = fdt32_to_cpu(pinctrl[index + 1]);
-		index += 2;
+		padconf[index].offset = fdt32_to_cpu(*pinctrl++);
+		padconf[index].val = fdt32_to_cpu(*pinctrl++);
+		index++;
 	}
 
 	return padconf;
@@ -1497,17 +1475,37 @@ omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
 	}
 
 	while (index < count) {
-		iodelay[index].offset = fdt32_to_cpu(pinctrl[index]);
-		iodelay[index].a_delay = fdt32_to_cpu(pinctrl[index + 1])
-						      & 0xFFFF;
-		iodelay[index].g_delay = (fdt32_to_cpu(pinctrl[index + 1])
+		iodelay[index].offset = fdt32_to_cpu(*pinctrl++);
+		iodelay[index].a_delay = fdt32_to_cpu(*pinctrl) & 0xFFFF;
+		iodelay[index].g_delay = (fdt32_to_cpu(*pinctrl++)
 					  & 0xFFFF0000) >> 16;
-		index += 2;
+		index++;
 	}
 
 	return iodelay;
 }
 
+static int omap_hsmmc_get_pinctrl_entry_size(uint32_t phandle)
+{
+	const void *fdt = gd->fdt_blob;
+	int offset;
+
+	offset = fdt_node_offset_by_phandle(fdt, phandle);
+	if (offset < 0) {
+		printf("failed to get pinctrl node offset %s.\n",
+		       fdt_strerror(offset));
+		return -EINVAL;
+	}
+
+	offset = fdt_parent_offset(fdt, offset);
+	if (offset < 0) {
+		printf("failed to get pinctrl parent node offset %s.\n",
+		       fdt_strerror(offset));
+		return -EINVAL;
+	}
+	return fdt_pinctrl_cells(fdt, offset);
+}
+
 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(uint32_t phandle, int *len)
 {
 	const void *fdt = gd->fdt_blob;
@@ -1576,7 +1574,7 @@ static struct pad_conf_entry *
 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
 {
 	int len;
-	int count;
+	int count, size;
 	struct pad_conf_entry *padconf;
 	uint32_t phandle;
 	const fdt32_t *pinctrl;
@@ -1589,7 +1587,11 @@ omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
 	if (!pinctrl)
 		return ERR_PTR(-EINVAL);
 
-	count = len / sizeof(*pinctrl);
+	size = omap_hsmmc_get_pinctrl_entry_size(phandle);
+	if (size <= 0)
+		return ERR_PTR(size);
+
+	count = (len / sizeof(*pinctrl)) / size;
 	padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
 	if (!padconf)
 		return ERR_PTR(-EINVAL);
@@ -1603,7 +1605,7 @@ static struct iodelay_cfg_entry *
 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
 {
 	int len;
-	int count;
+	int count, size;
 	struct iodelay_cfg_entry *iodelay;
 	uint32_t phandle;
 	const fdt32_t *pinctrl;
@@ -1617,7 +1619,11 @@ omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
 	if (!pinctrl)
 		return ERR_PTR(-EINVAL);
 
-	count = len / sizeof(*pinctrl);
+	size = omap_hsmmc_get_pinctrl_entry_size(phandle);
+	if (size <= 0)
+		return ERR_PTR(size);
+
+	count = (len / sizeof(*pinctrl)) / size;
 	iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
 	if (!iodelay)
 		return ERR_PTR(-EINVAL);
@@ -1642,13 +1648,18 @@ omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
 	pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
 			 malloc(sizeof(*pinctrl_state));
 	if (!pinctrl_state) {
-		printf("failed to allocate memory\n");
+		printf("%s: failed to allocate memory\n",
+		       fdt_get_name(fdt, node, NULL));
 		return 0;
 	}
 
 	index = fdt_find_string(fdt, node, "pinctrl-names", mode);
-	if (index < 0)
+	if (index < 0) {
+		printf("%s: fail to find %s mode %s\n",
+		       fdt_get_name(fdt, node, NULL),
+		       mode, fdt_strerror(index));
 		goto err_pinctrl_state;
+	}
 
 	sprintf(prop_name, "pinctrl-%d", index);
 
@@ -1673,6 +1684,7 @@ err_pinctrl_state:
 	kfree(pinctrl_state);
 	return 0;
 }
+#endif
 
 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode)				\
 	do {								\
@@ -1726,6 +1738,133 @@ static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
 }
 #endif
 
+__weak int platform_fixup_disable_uhs_mode(void)
+{
+	return 0;
+}
+
+static int omap_hsmmc_platform_fixup(struct mmc *mmc)
+{
+	struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
+	struct mmc_config *cfg = &priv->cfg;
+
+	priv->version = NULL;
+
+	if (platform_fixup_disable_uhs_mode()) {
+		priv->version = "rev11";
+		cfg->host_caps &= ~(MMC_MODE_HS200 | MMC_MODE_UHS_SDR104
+				    | MMC_MODE_UHS_SDR50);
+	}
+
+	return 0;
+}
+
+#ifndef CONFIG_DM_MMC
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
+		int wp_gpio)
+{
+	struct mmc *mmc;
+	struct omap_hsmmc_data *priv_data;
+	struct mmc_config *cfg;
+	uint host_caps_val;
+#ifdef CONFIG_IODELAY_RECALIBRATION
+	int ret;
+#endif
+
+	priv_data = malloc(sizeof(*priv_data));
+	if (priv_data == NULL)
+		return -1;
+
+	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
+#if defined(CONFIG_OMAP54XX)
+	host_caps_val |= MMC_MODE_DDR_52MHz | MMC_MODE_HS200;
+	priv_data->controller_flags |= OMAP_HSMMC_REQUIRE_IODELAY;
+#endif
+	switch (dev_index) {
+	case 0:
+		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
+		break;
+#ifdef OMAP_HSMMC2_BASE
+	case 1:
+		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
+#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
+	defined(CONFIG_DRA7XX) || \
+	defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
+		defined(CONFIG_HSMMC2_8BIT)
+		/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
+		host_caps_val |= MMC_MODE_8BIT;
+#endif
+		break;
+#endif
+#ifdef OMAP_HSMMC3_BASE
+	case 2:
+		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
+#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
+		/* Enable 8-bit interface for eMMC on DRA7XX */
+		host_caps_val |= MMC_MODE_8BIT;
+#endif
+		break;
+#endif
+	default:
+		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
+		return 1;
+	}
+#ifdef OMAP_HSMMC_USE_GPIO
+	/* on error gpio values are set to -1, which is what we want */
+	priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
+	priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
+#endif
+
+	cfg = &priv_data->cfg;
+
+	cfg->name = "OMAP SD/MMC";
+	cfg->ops = &omap_hsmmc_ops;
+
+	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+	cfg->host_caps = host_caps_val & ~host_caps_mask;
+
+
+	cfg->f_min = 400000;
+
+	if (f_max != 0) {
+		cfg->f_max = f_max;
+	} else {
+		if (cfg->host_caps & MMC_MODE_HS200)
+			cfg->f_max = 200000000;
+		else if (cfg->host_caps & MMC_MODE_DDR_52MHz)
+			cfg->f_max = 52000000;
+		else if (cfg->host_caps & MMC_MODE_HS_52MHz)
+			cfg->f_max = 52000000;
+		else if (cfg->host_caps & MMC_MODE_HS)
+			cfg->f_max = 26000000;
+		else
+			cfg->f_max = 20000000;
+	}
+
+	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
+#if defined(CONFIG_OMAP34XX)
+	/*
+	 * Silicon revs 2.1 and older do not support multiblock transfers.
+	 */
+	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
+		cfg->b_max = 1;
+#endif
+	mmc = mmc_create(cfg, priv_data);
+	if (mmc == NULL)
+		return -1;
+
+	omap_hsmmc_platform_fixup(mmc);
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+	ret = omap_hsmmc_get_pinctrl_state(mmc);
+	if (ret < 0)
+		return ret;
+#endif
+
+	return 0;
+}
+#else
 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
 {
 	struct omap_hsmmc_data *priv = dev_get_priv(dev);
@@ -1758,27 +1897,6 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
 	return 0;
 }
 
-__weak int platform_fixup_disable_uhs_mode(void)
-{
-	return 0;
-}
-
-static int omap_hsmmc_platform_fixup(struct mmc *mmc)
-{
-	struct omap_hsmmc_data *priv = (struct omap_hsmmc_data *)mmc->priv;
-	struct mmc_config *cfg = &priv->cfg;
-
-	priv->version = NULL;
-
-	if (platform_fixup_disable_uhs_mode()) {
-		priv->version = "rev11";
-		cfg->host_caps &= ~(MMC_MODE_HS200 | MMC_MODE_UHS_SDR104
-				    | MMC_MODE_UHS_SDR50);
-	}
-
-	return 0;
-}
-
 static int omap_hsmmc_probe(struct udevice *dev)
 {
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
@@ -1800,7 +1918,7 @@ static int omap_hsmmc_probe(struct udevice *dev)
 
 	omap_hsmmc_platform_fixup(mmc);
 
-#ifdef CONFIG_DM_REGULATOR
+#if CONFIG_IS_ENABLED(DM_REGULATOR) && defined(CONFIG_DM_MMC)
 	device_get_supply_regulator(dev, "vmmc-supply", &priv->vmmc_supply);
 	device_get_supply_regulator(dev, "vmmc_aux-supply",
 				    &priv->vmmc_aux_supply);
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index 23a5dc7580..64278866f1 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -41,7 +41,7 @@ int lp873x_mmc1_poweron_ldo(uint voltage)
 }
 #endif
 
-int palmas_mmc1_poweron_ldo(uint voltage)
+int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage)
 {
 	u8 val = 0;
 
@@ -50,13 +50,13 @@ int palmas_mmc1_poweron_ldo(uint voltage)
 	 * Currently valid for the dra7xx_evm board:
 	 * Set TPS659038 LDO1 to 3.0 V
 	 */
-	if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, voltage)) {
+	if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, ldo_volt, voltage)) {
 		printf("tps65903x: could not set LDO1 voltage.\n");
 		return 1;
 	}
 	/* TURN ON LDO1 */
 	val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
-	if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_CTRL, val)) {
+	if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, ldo_ctrl, val)) {
 		printf("tps65903x: could not turn on LDO1.\n");
 		return 1;
 	}
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 00fcacbdd3..aa56efc66f 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -149,3 +149,10 @@ config PMIC_LP873X
 	---help---
 	The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
 	This driver binds the pmic children.
+
+config PMIC_LP87565
+	bool "Enable driver for Texas Instruments LP87565 PMIC"
+	depends on DM_PMIC
+	---help---
+	The LP87565 is a PMIC containing a bunch of SMPS.
+	This driver binds the pmic children.
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 334a24fdb7..b953c03a14 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
 obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
 obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
+obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
 
 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
 obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
diff --git a/drivers/power/pmic/lp87565.c b/drivers/power/pmic/lp87565.c
new file mode 100644
index 0000000000..a5f29d7760
--- /dev/null
+++ b/drivers/power/pmic/lp87565.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2017 Texas Instruments Incorporated, <www.ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/lp87565.h>
+#include <dm/device.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+	{ .prefix = "buck", .driver = LP87565_BUCK_DRIVER },
+	{ },
+};
+
+static int lp87565_write(struct udevice *dev, uint reg, const uint8_t *buff,
+			  int len)
+{
+	int ret;
+
+	ret = dm_i2c_write(dev, reg, buff, len);
+	if (ret)
+		error("write error to device: %p register: %#x!", dev, reg);
+
+	return ret;
+}
+
+static int lp87565_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+	int ret;
+
+	ret = dm_i2c_read(dev, reg, buff, len);
+	if (ret)
+		error("read error from device: %p register: %#x!", dev, reg);
+
+	return ret;
+}
+
+static int lp87565_bind(struct udevice *dev)
+{
+	int regulators_node;
+	const void *blob = gd->fdt_blob;
+	int children;
+	int node = dev->of_offset;
+
+	regulators_node = fdt_subnode_offset(blob, node, "regulators");
+	if (regulators_node <= 0) {
+		debug("%s: %s regulators subnode not found!", __func__,
+		      dev->name);
+		return -ENXIO;
+	}
+
+	debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+	children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+	if (!children)
+		printf("%s: %s - no child found\n", __func__, dev->name);
+
+	/* Always return success for this device */
+	return 0;
+}
+
+static struct dm_pmic_ops lp87565_ops = {
+	.read = lp87565_read,
+	.write = lp87565_write,
+};
+
+static const struct udevice_id lp87565_ids[] = {
+	{ .compatible = "ti,lp87565", .data = LP87565 },
+	{ .compatible = "ti,lp87565-q1", .data = LP87565_Q1 },
+	{ }
+};
+
+U_BOOT_DRIVER(pmic_lp87565) = {
+	.name = "lp87565_pmic",
+	.id = UCLASS_PMIC,
+	.of_match = lp87565_ids,
+	.bind = lp87565_bind,
+	.ops = &lp87565_ops,
+};
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 35af579cba..8696d7dce7 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -139,3 +139,13 @@ config DM_REGULATOR_LP873X
 	This enables implementation of driver-model regulator uclass
 	features for REGULATOR LP873X and the family of LP873X PMICs.
 	The driver implements get/set api for: value and enable.
+
+config DM_REGULATOR_LP87565
+	bool "Enable driver for LP87565 PMIC regulators"
+        depends on PMIC_LP87565
+	---help---
+	This enables implementation of driver-model regulator uclass
+	features for REGULATOR LP87565 and the family of LP87565 PMICs.
+	LP87565 series of PMICs have 4 single phase BUCKs that can also
+	be configured in multi phase modes. The driver implements
+	get/set api for value and enable.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 2d350cb2fe..2862bcc1b1 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
 obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
diff --git a/drivers/power/regulator/lp87565_regulator.c b/drivers/power/regulator/lp87565_regulator.c
new file mode 100644
index 0000000000..2a0b8ca642
--- /dev/null
+++ b/drivers/power/regulator/lp87565_regulator.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2017
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/lp87565.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char lp87565_buck_ctrl1[LP87565_BUCK_NUM] = {0x2, 0x4, 0x6, 0x8, 0x2, 0x6};
+static const char lp87565_buck_vout[LP87565_BUCK_NUM] = {0xA, 0xC, 0xE, 0x10, 0xA, 0xE };
+
+static int lp87565_buck_enable(struct udevice *dev, int op, bool *enable)
+{
+	int ret;
+	unsigned int adr;
+	struct dm_regulator_uclass_platdata *uc_pdata;
+
+	uc_pdata = dev_get_uclass_platdata(dev);
+	adr = uc_pdata->ctrl_reg;
+
+	ret = pmic_reg_read(dev->parent, adr);
+	if (ret < 0)
+		return ret;
+
+	if (op == PMIC_OP_GET) {
+		ret &= LP87565_BUCK_MODE_MASK;
+
+		if (ret)
+			*enable = true;
+		else
+			*enable = false;
+
+		return 0;
+	} else if (op == PMIC_OP_SET) {
+		if (*enable)
+			ret |= LP87565_BUCK_MODE_MASK;
+		else
+			ret &= ~LP87565_BUCK_MODE_MASK;
+		ret = pmic_reg_write(dev->parent, adr, ret);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int lp87565_buck_volt2val(int uV)
+{
+	if (uV > LP87565_BUCK_VOLT_MAX)
+		return -EINVAL;
+	else if (uV > 1400000)
+		return (uV - 1420000) / 20000 + 0x9E;
+	else if (uV > 730000)
+		return (uV - 735000) / 5000 + 0x18;
+	else if (uV >= 500000)
+		return (uV - 500000) / 10000;
+	else
+		return -EINVAL;
+}
+
+static int lp87565_buck_val2volt(int val)
+{
+	if (val > LP87565_BUCK_VOLT_MAX_HEX)
+		return -EINVAL;
+	else if (val > 0x9D)
+		return 1400000 + (val - 0x9D) * 20000;
+	else if (val > 0x17)
+		return 730000 + (val - 0x17) * 5000;
+	else if (val >= 0x0)
+		return 500000 + val * 10000;
+	else
+		return -EINVAL;
+}
+
+static int lp87565_buck_val(struct udevice *dev, int op, int *uV)
+{
+	unsigned int hex, adr;
+	int ret;
+	struct dm_regulator_uclass_platdata *uc_pdata;
+
+	uc_pdata = dev_get_uclass_platdata(dev);
+
+	if (op == PMIC_OP_GET)
+		*uV = 0;
+
+	adr = uc_pdata->volt_reg;
+
+	ret = pmic_reg_read(dev->parent, adr);
+	if (ret < 0)
+		return ret;
+
+	if (op == PMIC_OP_GET) {
+		ret &= LP87565_BUCK_VOLT_MASK;
+		ret = lp87565_buck_val2volt(ret);
+		if (ret < 0)
+			return ret;
+		*uV = ret;
+
+		return 0;
+	}
+
+	hex = lp87565_buck_volt2val(*uV);
+	if (hex < 0)
+		return hex;
+
+	ret &= 0x0;
+	ret = hex;
+
+	ret = pmic_reg_write(dev->parent, adr, ret);
+
+	return ret;
+}
+
+static int lp87565_buck_probe(struct udevice *dev)
+{
+	struct dm_regulator_uclass_platdata *uc_pdata;
+	int idx;
+
+	uc_pdata = dev_get_uclass_platdata(dev);
+	uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+	idx = dev->driver_data;
+	if (idx == 0 || idx == 1 || idx == 2 || idx == 3) {
+		debug("Single phase regulator\n");
+	} else if (idx == 23) {
+		idx = 5;
+	} else if (idx == 10) {
+		idx = 4;
+	} else {
+		printf("Wrong ID for regulator\n");
+		return -EINVAL;
+	}
+
+	uc_pdata->ctrl_reg = lp87565_buck_ctrl1[idx];
+	uc_pdata->volt_reg = lp87565_buck_vout[idx];
+
+	return 0;
+}
+
+static int buck_get_value(struct udevice *dev)
+{
+	int uV;
+	int ret;
+
+	ret = lp87565_buck_val(dev, PMIC_OP_GET, &uV);
+	if (ret)
+		return ret;
+
+	return uV;
+}
+
+static int buck_set_value(struct udevice *dev, int uV)
+{
+	return lp87565_buck_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool buck_get_enable(struct udevice *dev)
+{
+	bool enable = false;
+	int ret;
+
+
+	ret = lp87565_buck_enable(dev, PMIC_OP_GET, &enable);
+	if (ret)
+		return ret;
+
+	return enable;
+}
+
+static int buck_set_enable(struct udevice *dev, bool enable)
+{
+	return lp87565_buck_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static const struct dm_regulator_ops lp87565_buck_ops = {
+	.get_value  = buck_get_value,
+	.set_value  = buck_set_value,
+	.get_enable = buck_get_enable,
+	.set_enable = buck_set_enable,
+};
+
+U_BOOT_DRIVER(lp87565_buck) = {
+	.name = LP87565_BUCK_DRIVER,
+	.id = UCLASS_REGULATOR,
+	.ops = &lp87565_buck_ops,
+	.probe = lp87565_buck_probe,
+};
diff --git a/drivers/power/regulator/palmas_regulator.c b/drivers/power/regulator/palmas_regulator.c
index cce7cd2fc2..b40bad2042 100644
--- a/drivers/power/regulator/palmas_regulator.c
+++ b/drivers/power/regulator/palmas_regulator.c
@@ -377,7 +377,11 @@ static int palmas_smps_probe(struct udevice *dev)
 			uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
 			uc_pdata->volt_reg = palmas_smps_volt[type][idx];
 			break;
-
+		case 12:
+			idx = 0;
+			uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
+			uc_pdata->volt_reg = palmas_smps_volt[type][idx];
+			break;
 		default:
 			printf("Wrong ID for regulator\n");
 		}
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index ceaa0bd0b1..ea0f3b8424 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -16,6 +16,7 @@
 #include <asm/omap_gpio.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -117,21 +118,18 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 	if (!hz)
 		clk_div = 0;
 	else
-		clk_div = (priv->fclk / hz) - 1;
+		clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
+
+	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
+	if (clk_div > QSPI_CLK_DIV_MAX)
+		clk_div = QSPI_CLK_DIV_MAX;
 
 	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 
 	/* disable SCLK */
 	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 	       &priv->base->clk_ctrl);
-
-	/* assign clk_div values */
-	if (clk_div < 0)
-		clk_div = 0;
-	else if (clk_div > QSPI_CLK_DIV_MAX)
-		clk_div = QSPI_CLK_DIV_MAX;
-
-	/* enable SCLK */
+	/* enable SCLK and program the clk divider */
 	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 }
 
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 1c9ecb7ecd..f6f3c3b326 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -61,7 +61,6 @@ static inline struct f_fastboot *func_to_fastboot(struct usb_function *f)
 }
 
 static struct f_fastboot *fastboot_func;
-static unsigned int fastboot_flash_session_id;
 static unsigned int download_size;
 static unsigned int download_bytes;
 static char f_cmdbuf[MAX_CMDS][32];
@@ -452,15 +451,6 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
 
 		sprintf(str_num, "0x%08x", CONFIG_FASTBOOT_BUF_SIZE);
 		strncat(response, str_num, chars_left);
-
-		/*
-		 * This also indicates the start of a new flashing
-		 * "session", in which we could have 1-N buffers to
-		 * write to a partition.
-		 *
-		 * Reset our session counter.
-		 */
-		fastboot_flash_session_id = 0;
 	} else if (!strcmp_l1("serialno", cmd)) {
 		s = getenv("serial#");
 		if (s)
@@ -804,16 +794,14 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req)
 	}
 
 #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
-	fb_mmc_flash_write(cmd, fastboot_flash_session_id,
-			   (void *)CONFIG_FASTBOOT_BUF_ADDR,
+	fb_mmc_flash_write(cmd, (void *)CONFIG_FASTBOOT_BUF_ADDR,
 			   download_bytes, response);
 #endif
 #ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV
-	fb_nand_flash_write(cmd, fastboot_flash_session_id,
+	fb_nand_flash_write(cmd,
 			    (void *)CONFIG_FASTBOOT_BUF_ADDR,
 			    download_bytes, response);
 #endif
-	fastboot_flash_session_id++;
 	fastboot_tx_write_str(response);
 }
 #endif
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 600a90e309..a44749f6fe 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -282,7 +282,7 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size)
 	if ((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1)) {
 		ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
 
-		printf("FAT: Misaligned buffer address (%p)\n", buffer);
+		debug("FAT: misaligned buffer address (%p)\n", buffer);
 
 		while (size >= mydata->sect_size) {
 			ret = disk_read(startsect++, 1, tmpbuf);
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index eb3a916948..b39fb58b86 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -568,7 +568,7 @@ set_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer,
 	if ((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1)) {
 		ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
 
-		printf("FAT: Misaligned buffer address (%p)\n", buffer);
+		debug("FAT: Misaligned buffer address (%p)\n", buffer);
 
 		while (size >= mydata->sect_size) {
 			memcpy(tmpbuf, buffer, mydata->sect_size);
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 02d3bccca7..80e9baf42e 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -17,6 +17,7 @@
 #define __CONFIG_AM335X_EVM_H
 
 #include <configs/ti_am335x_common.h>
+#include <environment/ti/dfu.h>
 
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_TIMESTAMP
@@ -326,40 +327,10 @@
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
-#define DFU_ALT_INFO_MMC \
-	"dfu_alt_info_mmc=" \
-	"boot part 0 1;" \
-	"rootfs part 0 2;" \
-	"MLO fat 0 1;" \
-	"MLO.raw raw 0x100 0x100;" \
-	"u-boot.img.raw raw 0x300 0x400;" \
-	"spl-os-args.raw raw 0x80 0x80;" \
-	"spl-os-image.raw raw 0x900 0x2000;" \
-	"spl-os-args fat 0 1;" \
-	"spl-os-image fat 0 1;" \
-	"u-boot.img fat 0 1;" \
-	"uEnv.txt fat 0 1\0"
 #ifdef CONFIG_NAND
 #define CONFIG_DFU_NAND
-#define DFU_ALT_INFO_NAND \
-	"dfu_alt_info_nand=" \
-	"SPL part 0 1;" \
-	"SPL.backup1 part 0 2;" \
-	"SPL.backup2 part 0 3;" \
-	"SPL.backup3 part 0 4;" \
-	"u-boot part 0 5;" \
-	"u-boot-spl-os part 0 6;" \
-	"kernel part 0 8;" \
-	"rootfs part 0 9\0"
-#else
-#define DFU_ALT_INFO_NAND ""
 #endif
 #define CONFIG_DFU_RAM
-#define DFU_ALT_INFO_RAM \
-	"dfu_alt_info_ram=" \
-	"kernel ram 0x80200000 0xD80000;" \
-	"fdt ram 0x80F80000 0x80000;" \
-	"ramdisk ram 0x81000000 0x4000000\0"
 #define DFUARGS \
 	"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
 	DFU_ALT_INFO_MMC \
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index f805c21f26..10458d07b8 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -15,6 +15,7 @@
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 21)	/* 2GB */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 
+#include <environment/ti/dfu.h>
 #include <asm/arch/omap.h>
 
 /* NS16550 Configuration */
@@ -154,46 +155,14 @@
 /* USB Device Firmware Update support */
 #define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_RAM
-
 #define CONFIG_DFU_MMC
-#define DFU_ALT_INFO_MMC \
-	"dfu_alt_info_mmc=" \
-	"boot part 0 1;" \
-	"rootfs part 0 2;" \
-	"MLO fat 0 1;" \
-	"spl-os-args fat 0 1;" \
-	"spl-os-image fat 0 1;" \
-	"u-boot.img fat 0 1;" \
-	"uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
-	"dfu_alt_info_emmc=" \
-	"MLO raw 0x100 0x100 mmcpart 0;" \
-	"u-boot.img raw 0x300 0x1000 mmcpart 0\0"
-
-#define CONFIG_DFU_RAM
-#define DFU_ALT_INFO_RAM \
-	"dfu_alt_info_ram=" \
-	"kernel ram 0x80200000 0x4000000;" \
-	"fdt ram 0x80f80000 0x80000;" \
-	"ramdisk ram 0x81000000 0x4000000\0"
-
 #define CONFIG_DFU_SF
-#define DFU_ALT_INFO_QSPI \
-	"dfu_alt_info_qspi=" \
-	"u-boot.bin raw 0x0 0x080000;" \
-	"u-boot.backup raw 0x080000 0x080000;" \
-	"u-boot-spl-os raw 0x100000 0x010000;" \
-	"u-boot-env raw 0x110000 0x010000;" \
-	"u-boot-env.backup raw 0x120000 0x010000;" \
-	"kernel raw 0x130000 0x800000\0"
-
 #define DFUARGS \
 	"dfu_bufsiz=0x10000\0" \
 	DFU_ALT_INFO_MMC \
 	DFU_ALT_INFO_EMMC \
 	DFU_ALT_INFO_RAM \
-	DFU_ALT_INFO_QSPI
+	DFU_ALT_INFO_QSPI_XIP
 #else
 #define DFUARGS
 #endif
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index b5dde5ab73..c3ae8c2779 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -48,9 +48,9 @@
 	/* Android partitions */ \
 	"partitions_android=" \
 	"uuid_disk=${uuid_gpt_disk};" \
-	"name=xloader,start=128K,size=128K,uuid=${uuid_gpt_xloader};" \
-	"name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \
-	"name=environment,size=128K,uuid=${uuid_gpt_environment};" \
+	"name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
+	"name=bootloader,size=2304K,uuid=${uuid_gpt_bootloader};" \
+	"name=environment,size=256K,uuid=${uuid_gpt_environment};" \
 	"name=misc,size=128K,uuid=${uuid_gpt_misc};" \
 	"name=reserved,size=384K,uuid=${uuid_gpt_reserved};" \
 	"name=efs,size=16M,uuid=${uuid_gpt_efs};" \
@@ -58,6 +58,7 @@
 	"name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \
 	"name=boot,size=10M,uuid=${uuid_gpt_boot};" \
 	"name=system,size=768M,uuid=${uuid_gpt_system};" \
+	"name=vendor,size=256M,uuid=${uuid_gpt_vendor};" \
 	"name=cache,size=256M,uuid=${uuid_gpt_cache};" \
 	"name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \
 	"name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
@@ -78,50 +79,6 @@
 					"androidboot.console=ttyS2 " \
 					"androidboot.hardware=am57xevmboard"
 
-#define DFU_ALT_INFO_MMC \
-	"dfu_alt_info_mmc=" \
-	"boot part 0 1;" \
-	"rootfs part 0 2;" \
-	"MLO fat 0 1;" \
-	"MLO.raw raw 0x100 0x100;" \
-	"u-boot.img.raw raw 0x300 0x400;" \
-	"spl-os-args.raw raw 0x80 0x80;" \
-	"spl-os-image.raw raw 0x900 0x2000;" \
-	"spl-os-args fat 0 1;" \
-	"spl-os-image fat 0 1;" \
-	"u-boot.img fat 0 1;" \
-	"uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
-	"dfu_alt_info_emmc=" \
-	"rawemmc raw 0 3751936;" \
-	"boot part 1 1;" \
-	"rootfs part 1 2;" \
-	"MLO fat 1 1;" \
-	"MLO.raw raw 0x100 0x100;" \
-	"u-boot.img.raw raw 0x300 0x400;" \
-	"spl-os-args.raw raw 0x80 0x80;" \
-	"spl-os-image.raw raw 0x900 0x2000;" \
-	"spl-os-args fat 1 1;" \
-	"spl-os-image fat 1 1;" \
-	"u-boot.img fat 1 1;" \
-	"uEnv.txt fat 1 1\0"
-
-#define DFU_ALT_INFO_QSPI \
-	"dfu_alt_info_qspi=" \
-	"MLO raw 0x0 0x040000;" \
-	"u-boot.img raw 0x040000 0x0100000;" \
-	"u-boot-spl-os raw 0x140000 0x080000;" \
-	"u-boot-env raw 0x1C0000 0x010000;" \
-	"u-boot-env.backup raw 0x1D0000 0x010000;" \
-	"kernel raw 0x1E0000 0x800000\0"
-
-#define DFU_ALT_INFO_RAM \
-	"dfu_alt_info_ram=" \
-	"kernel ram 0x80200000 0x4000000;" \
-	"fdt ram 0x80f80000 0x80000;" \
-	"ramdisk ram 0x81000000 0x4000000\0"
-
 #define DFUARGS \
 	"dfu_bufsiz=0x10000\0" \
 	DFU_ALT_INFO_MMC \
@@ -129,6 +86,7 @@
 	DFU_ALT_INFO_QSPI \
 	DFU_ALT_INFO_RAM
 
+#include <environment/ti/dfu.h>
 #include <configs/ti_omap5_common.h>
 
 /* Enhance our eMMC support / experience. */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 436750614a..627bca6e18 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -12,6 +12,8 @@
 #ifndef __CONFIG_DRA7XX_EVM_H
 #define __CONFIG_DRA7XX_EVM_H
 
+#include <environment/ti/dfu.h>
+
 #define CONFIG_DRA7XX
 #define CONFIG_BOARD_EARLY_INIT_F
 
@@ -28,7 +30,7 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
 #define CONFIG_ENV_SIZE			(128 << 10)
-#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #endif
@@ -54,9 +56,9 @@
 	/* Android partitions */ \
 	"partitions_android=" \
 	"uuid_disk=${uuid_gpt_disk};" \
-	"name=xloader,start=128K,size=128K,uuid=${uuid_gpt_xloader};" \
-	"name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \
-	"name=environment,size=128K,uuid=${uuid_gpt_environment};" \
+	"name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
+	"name=bootloader,size=2304K,uuid=${uuid_gpt_bootloader};" \
+	"name=environment,size=256K,uuid=${uuid_gpt_environment};" \
 	"name=misc,size=128K,uuid=${uuid_gpt_misc};" \
 	"name=reserved,size=384K,uuid=${uuid_gpt_reserved};" \
 	"name=efs,size=16M,uuid=${uuid_gpt_efs};" \
@@ -74,50 +76,6 @@
 	"name=videodata,size=5K,uuid=${uuid_gpt_videodata};" \
 	"name=userdata,size=-,uuid=${uuid_gpt_userdata}"
 
-#define DFU_ALT_INFO_MMC \
-	"dfu_alt_info_mmc=" \
-	"boot part 0 1;" \
-	"rootfs part 0 2;" \
-	"MLO fat 0 1;" \
-	"MLO.raw raw 0x100 0x100;" \
-	"u-boot.img.raw raw 0x300 0x400;" \
-	"spl-os-args.raw raw 0x80 0x80;" \
-	"spl-os-image.raw raw 0x900 0x2000;" \
-	"spl-os-args fat 0 1;" \
-	"spl-os-image fat 0 1;" \
-	"u-boot.img fat 0 1;" \
-	"uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
-	"dfu_alt_info_emmc=" \
-	"rawemmc raw 0 3751936;" \
-	"boot part 1 1;" \
-	"rootfs part 1 2;" \
-	"MLO fat 1 1;" \
-	"MLO.raw raw 0x100 0x100;" \
-	"u-boot.img.raw raw 0x300 0x400;" \
-	"spl-os-args.raw raw 0x80 0x80;" \
-	"spl-os-image.raw raw 0x900 0x2000;" \
-	"spl-os-args fat 1 1;" \
-	"spl-os-image fat 1 1;" \
-	"u-boot.img fat 1 1;" \
-	"uEnv.txt fat 1 1\0"
-
-#define DFU_ALT_INFO_RAM \
-	"dfu_alt_info_ram=" \
-	"kernel ram 0x80200000 0x4000000;" \
-	"fdt ram 0x80f80000 0x80000;" \
-	"ramdisk ram 0x81000000 0x4000000\0"
-
-#define DFU_ALT_INFO_QSPI \
-	"dfu_alt_info_qspi=" \
-	"MLO raw 0x0 0x040000;" \
-	"u-boot.img raw 0x040000 0x0100000;" \
-	"u-boot-spl-os raw 0x140000 0x080000;" \
-	"u-boot-env raw 0x1C0000 0x010000;" \
-	"u-boot-env.backup raw 0x1D0000 0x010000;" \
-	"kernel raw 0x1E0000 0x800000\0"
-
 #define DFUARGS \
 	"dfu_bufsiz=0x10000\0" \
 	DFU_ALT_INFO_MMC \
@@ -148,11 +106,6 @@
 #define CONFIG_SPL_HASH_SUPPORT
 
 #ifdef CONFIG_SPL_LOAD_FIT
-#define DFU_ALT_INFO_RAM \
-	"dfu_alt_info_ram=" \
-	"kernel ram 0x80200000 0x4000000;" \
-	"fdt ram 0x80f80000 0x80000;" \
-	"ramdisk ram 0x81000000 0x4000000\0"
 #define DFUARGS \
 	"dfu_bufsiz=0x10000\0" \
 	DFU_ALT_INFO_RAM
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 86cefa3b8f..e166669f8b 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -12,6 +12,8 @@
 #ifndef __CONFIG_OMAP5_EVM_H
 #define __CONFIG_OMAP5_EVM_H
 
+#include <environment/ti/dfu.h>
+
 #ifndef CONFIG_SPL_BUILD
 /* Define the default GPT table for eMMC */
 #define PARTS_DEFAULT \
@@ -19,41 +21,6 @@
 	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
 #endif
 
-#define DFU_ALT_INFO_MMC \
-	"dfu_alt_info_mmc=" \
-	"boot part 0 1;" \
-	"rootfs part 0 2;" \
-	"MLO fat 0 1;" \
-	"MLO.raw raw 0x100 0x100;" \
-	"u-boot.img.raw raw 0x300 0x400;" \
-	"spl-os-args.raw raw 0x80 0x80;" \
-	"spl-os-image.raw raw 0x900 0x2000;" \
-	"spl-os-args fat 0 1;" \
-	"spl-os-image fat 0 1;" \
-	"u-boot.img fat 0 1;" \
-	"uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
-	"dfu_alt_info_emmc=" \
-	"rawemmc raw 0 3751936;" \
-	"boot part 1 1;" \
-	"rootfs part 1 2;" \
-	"MLO fat 1 1;" \
-	"MLO.raw raw 0x100 0x100;" \
-	"u-boot.img.raw raw 0x300 0x400;" \
-	"spl-os-args.raw raw 0x80 0x80;" \
-	"spl-os-image.raw raw 0x900 0x2000;" \
-	"spl-os-args fat 1 1;" \
-	"spl-os-image fat 1 1;" \
-	"u-boot.img fat 1 1;" \
-	"uEnv.txt fat 1 1\0"
-
-#define DFU_ALT_INFO_RAM \
-	"dfu_alt_info_ram=" \
-	"kernel ram 0x80200000 0x4000000;" \
-	"fdt ram 0x80f80000 0x80000;" \
-	"ramdisk ram 0x81000000 0x4000000\0"
-
 #define DFUARGS \
 	"dfu_bufsiz=0x10000\0" \
 	DFU_ALT_INFO_MMC \
@@ -71,7 +38,7 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
 #define CONFIG_ENV_SIZE			(128 << 10)
-#define CONFIG_ENV_OFFSET		0xE0000
+#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index bba511ab99..0e5716459e 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -282,8 +282,8 @@
 #endif
 
 /* RAW SD card / eMMC locations. */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x200	/* address 0x40000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x300	/* 384 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300	/* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x1000	/* 2048 KB */
 
 /* FAT sd card locations. */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
@@ -295,9 +295,10 @@
 #define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
 
 /* RAW SD card / eMMC */
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x1700  /* address 0x2E0000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x1500  /* address 0x2A0000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x200   /* 256KiB */
+
 
 /* spl export command */
 #define CONFIG_CMD_SPL
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 171cc9aa36..975679c238 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -128,6 +128,8 @@
 			"setenv fdtfile dra72-evm.dtb; fi;" \
 		"if test $board_name = dra71x; then " \
 			"setenv fdtfile dra71-evm.dtb; fi;" \
+		"if test $board_name = dra76x; then " \
+			"setenv fdtfile dra76-evm.dtb; fi;" \
 		"if test $board_name = beagle_x15; then " \
 			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
 		"if test $board_name = beagle_x15_revb1; then " \
diff --git a/include/environment/ti/dfu.h b/include/environment/ti/dfu.h
new file mode 100644
index 0000000000..c9f61a577e
--- /dev/null
+++ b/include/environment/ti/dfu.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for DFU on TI boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define DFU_ALT_INFO_MMC \
+	"dfu_alt_info_mmc=" \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"MLO fat 0 1;" \
+	"MLO.raw raw 0x100 0x100;" \
+	"u-boot.img.raw raw 0x300 0x1000;" \
+	"u-env.raw raw 0x1300 0x200;" \
+	"spl-os-args.raw raw 0x1500 0x200;" \
+	"spl-os-image.raw raw 0x1700 0x6900;" \
+	"spl-os-args fat 0 1;" \
+	"spl-os-image fat 0 1;" \
+	"u-boot.img fat 0 1;" \
+	"uEnv.txt fat 0 1\0"
+
+#define DFU_ALT_INFO_EMMC \
+	"dfu_alt_info_emmc=" \
+	"rawemmc raw 0 3751936;" \
+	"boot part 1 1;" \
+	"rootfs part 1 2;" \
+	"MLO fat 1 1;" \
+	"MLO.raw raw 0x100 0x100;" \
+	"u-boot.img.raw raw 0x300 0x1000;" \
+	"u-env.raw raw 0x1300 0x200;" \
+	"spl-os-args.raw raw 0x1500 0x200;" \
+	"spl-os-image.raw raw 0x1700 0x6900;" \
+	"spl-os-args fat 1 1;" \
+	"spl-os-image fat 1 1;" \
+	"u-boot.img fat 1 1;" \
+	"uEnv.txt fat 1 1\0"
+
+#ifdef CONFIG_NAND
+#define DFU_ALT_INFO_NAND \
+	"dfu_alt_info_nand=" \
+	"SPL part 0 1;" \
+	"SPL.backup1 part 0 2;" \
+	"SPL.backup2 part 0 3;" \
+	"SPL.backup3 part 0 4;" \
+	"u-boot part 0 5;" \
+	"u-boot-spl-os part 0 6;" \
+	"kernel part 0 8;" \
+	"rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
+#endif
+
+#define DFU_ALT_INFO_RAM \
+	"dfu_alt_info_ram=" \
+	"kernel ram 0x80200000 0x4000000;" \
+	"fdt ram 0x80f80000 0x80000;" \
+	"ramdisk ram 0x81000000 0x4000000\0"
+
+#define DFU_ALT_INFO_QSPI_XIP \
+	"dfu_alt_info_qspi=" \
+	"u-boot.bin raw 0x0 0x080000;" \
+	"u-boot.backup raw 0x080000 0x080000;" \
+	"u-boot-spl-os raw 0x100000 0x010000;" \
+	"u-boot-env raw 0x110000 0x010000;" \
+	"u-boot-env.backup raw 0x120000 0x010000;" \
+	"kernel raw 0x130000 0x800000\0"
+
+#define DFU_ALT_INFO_QSPI \
+	"dfu_alt_info_qspi=" \
+	"MLO raw 0x0 0x040000;" \
+	"u-boot.img raw 0x040000 0x0100000;" \
+	"u-boot-spl-os raw 0x140000 0x080000;" \
+	"u-boot-env raw 0x1C0000 0x010000;" \
+	"u-boot-env.backup raw 0x1D0000 0x010000;" \
+	"kernel raw 0x1E0000 0x800000\0"
diff --git a/include/fb_mmc.h b/include/fb_mmc.h
index 978a1395a1..402ba9b1b4 100644
--- a/include/fb_mmc.h
+++ b/include/fb_mmc.h
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
-			void *download_buffer, unsigned int download_bytes,
-			char *response);
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+			unsigned int download_bytes, char *response);
 void fb_mmc_erase(const char *cmd, char *response);
diff --git a/include/fb_nand.h b/include/fb_nand.h
index 80ddef5656..88bdf3690d 100644
--- a/include/fb_nand.h
+++ b/include/fb_nand.h
@@ -5,7 +5,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-void fb_nand_flash_write(const char *cmd, unsigned int session_id,
-			 void *download_buffer, unsigned int download_bytes,
-			 char *response);
+void fb_nand_flash_write(const char *cmd, void *download_buffer,
+			 unsigned int download_bytes, char *response);
 void fb_nand_erase(const char *cmd, char *response);
diff --git a/include/image-sparse.h b/include/image-sparse.h
index 0382f5bd26..a2b0694190 100644
--- a/include/image-sparse.h
+++ b/include/image-sparse.h
@@ -32,4 +32,4 @@ static inline int is_sparse_image(void *buf)
 }
 
 int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
-		       unsigned int session_id, void *data);
+		       void *data);
diff --git a/include/libfdt.h b/include/libfdt.h
index 74b1d149c2..ba1bf4c214 100644
--- a/include/libfdt.h
+++ b/include/libfdt.h
@@ -990,6 +990,27 @@ int fdt_address_cells(const void *fdt, int nodeoffset);
  */
 int fdt_size_cells(const void *fdt, int nodeoffset);
 
+#define DEF_PINCTRL_LEN (2) /* index + value */
+
+/**
+ * fdt_pinctrl_cells - retrieve pinctrl entry size using the nodeoffset
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to find the pinctrl-cells value for
+ *
+ * When the node has a valid #pinctrl-cells property, returns its value.
+ *
+ * returns:
+ *	0 <= n < FDT_MAX_NCELLS, on success
+ *       DEF_PINCTRL_LEN, if the node has no #pinctrl-cells property
+ *      -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid
+ *		#pinctrl-cells property
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_pinctrl_cells(const void *fdt, int nodeoffset);
 
 /**********************************************************************/
 /* Write-in-place functions                                           */
diff --git a/include/mmc.h b/include/mmc.h
index 8cdad5a800..c7aeb74b49 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -450,6 +450,7 @@ struct mmc {
 	struct blk_desc block_dev;
 	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
 	char init_in_progress;	/* 1 if we have done mmc_start_init() */
+	uint host_ok_caps;	/* host caps that are not yet proven wrong */
 	char preinit;		/* start init as early as possible */
 	int ddr_mode;
 	unsigned int sd_bus_speed;
diff --git a/include/palmas.h b/include/palmas.h
index 96ba8ed566..5addf97eca 100644
--- a/include/palmas.h
+++ b/include/palmas.h
@@ -35,6 +35,10 @@
 #define LDO2_CTRL		0x52
 #define LDO2_VOLTAGE		0x53
 
+/* LDO2 control/voltage */
+#define LDO4_CTRL		0x5e
+#define LDO4_VOLTAGE		0x5f
+
 /* LDO9 control/voltage */
 #define LDO9_CTRL		0x60
 #define LDO9_VOLTAGE		0x61
@@ -126,7 +130,7 @@ static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
 }
 
 void palmas_init_settings(void);
-int palmas_mmc1_poweron_ldo(uint voltage);
+int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage);
 int lp873x_mmc1_poweron_ldo(uint voltage);
 int twl603x_mmc1_set_ldo9(u8 vsel);
 int twl603x_audio_power(u8 on);
diff --git a/include/power/lp87565.h b/include/power/lp87565.h
new file mode 100644
index 0000000000..5160f5df6c
--- /dev/null
+++ b/include/power/lp87565.h
@@ -0,0 +1,12 @@
+#define LP87565	0x0
+#define LP87565_Q1	0x1
+
+#define LP87565_BUCK_NUM		6
+
+/* Drivers name */
+#define LP87565_BUCK_DRIVER	"lp87565_buck"
+
+#define LP87565_BUCK_VOLT_MASK		0xFF
+#define LP87565_BUCK_VOLT_MAX_HEX	0xFF
+#define LP87565_BUCK_VOLT_MAX		3360000
+#define LP87565_BUCK_MODE_MASK		0x80
diff --git a/lib/libfdt/fdt_addresses.c b/lib/libfdt/fdt_addresses.c
index 76054d98e5..4d9809c14c 100644
--- a/lib/libfdt/fdt_addresses.c
+++ b/lib/libfdt/fdt_addresses.c
@@ -53,3 +53,24 @@ int fdt_size_cells(const void *fdt, int nodeoffset)
 
 	return val;
 }
+
+int fdt_pinctrl_cells(const void *fdt, int nodeoffset)
+{
+	const fdt32_t *sc;
+	int val;
+	int len;
+
+	sc = fdt_getprop(fdt, nodeoffset, "#pinctrl-cells", &len);
+	if (!sc)
+		return DEF_PINCTRL_LEN;
+
+	if (len != sizeof(*sc))
+		return -FDT_ERR_BADNCELLS;
+
+	val = fdt32_to_cpu(*sc);
+	if ((val < 0) || (val > FDT_MAX_NCELLS))
+		return -FDT_ERR_BADNCELLS;
+
+	/* pinctrl-cells doesn't count the index. So, increment by one */
+	return val + 1;
+}