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| author | Travis Geiselbrecht <geist@foobox.com> | 2022-07-17 13:14:56 -0700 |
|---|---|---|
| committer | Travis Geiselbrecht <geist@foobox.com> | 2022-07-17 13:21:31 -0700 |
| commit | a007f66728cdb02df516a86f84d18f9fd51ffa74 (patch) | |
| tree | a6b523815b45426c6a1e2fc3163214a13a4f2a89 /arch | |
| parent | be0ba2ca14a30973b192d38586d1b4a06fc47b7b (diff) | |
| download | lk-a007f66728cdb02df516a86f84d18f9fd51ffa74.tar.gz | |
[arch][arm64] update some comments in assembly
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/cache-ops.S | 6 | ||||
| -rw-r--r-- | arch/arm64/start.S | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/cache-ops.S b/arch/arm64/cache-ops.S index de7658df..240208d1 100644 --- a/arch/arm64/cache-ops.S +++ b/arch/arm64/cache-ops.S @@ -14,6 +14,10 @@ .text +// Routines to flush the cache by address on the local cpu. +// NOTE: the following routines do not touch the stack and only use x0-x3 +// so can be safely called from assembly that is aware of this. + .macro cache_range_op, cache op add x2, x0, x1 // calculate the end address bic x3, x0, #(CACHE_LINE-1) // align the start with a cache line @@ -52,6 +56,8 @@ END_FUNCTION(arch_sync_cache_range) // Below are 3 variants of cache flushing routines by way/set for // an individual cpu. +// NOTE: does not touch the stack but trashes most of the temporary +// registers. // void arm64_local_invalidate_cache_all() FUNCTION(arm64_local_invalidate_cache_all) diff --git a/arch/arm64/start.S b/arch/arm64/start.S index fdeffcc3..ac00cb5e 100644 --- a/arch/arm64/start.S +++ b/arch/arm64/start.S @@ -65,6 +65,7 @@ arm_reset: add page_table0, page_table0, #:lo12:tt_trampoline #if WITH_SMP + /* if the cpu id is != 0 it's a secondary cpu */ mrs cpuid, mpidr_el1 ubfx cpuid, cpuid, #0, #SMP_CPU_ID_BITS cbnz cpuid, .Lmmu_enable_secondary |