intel/brw: Remove automatic_exec_sizes

As Ken describes: "This was only used by legacy SF/Clip/FFGS programs."

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>

5 files changed, 0 insertions, 37 deletions

diff --git a/src/intel/compiler/brw_asm_tool.c b/src/intel/compiler/brw_asm_tool.c
index 8b203b0ae62..e5a0dc9c186 100644
--- a/src/intel/compiler/brw_asm_tool.c
+++ b/src/intel/compiler/brw_asm_tool.c
@@ -307,7 +307,6 @@ int main(int argc, char **argv)
 
    p = rzalloc(NULL, struct brw_codegen);
    brw_init_codegen(&isa, p, p);
-   p->automatic_exec_sizes = false;
 
    err = yyparse();
    if (err || errors)
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index e29efe66235..46e0deba54e 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -278,7 +278,6 @@ brw_init_codegen(const struct brw_isa_info *isa,
 
    p->isa = isa;
    p->devinfo = isa->devinfo;
-   p->automatic_exec_sizes = true;
    /*
     * Set the initial instruction store array size to 1024, if found that
     * isn't enough, then it will double the store size at brw_next_insn()
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 9278bc68e70..6df4d1c10bb 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -100,16 +100,6 @@ struct brw_codegen {
    struct brw_insn_state stack[BRW_EU_MAX_INSN_STACK];
    struct brw_insn_state *current;
 
-   /** Whether or not the user wants automatic exec sizes
-    *
-    * If true, codegen will try to automatically infer the exec size of an
-    * instruction from the width of the destination register.  If false, it
-    * will take whatever is set by brw_set_default_exec_size verbatim.
-    *
-    * This is set to true by default in brw_init_codegen.
-    */
-   bool automatic_exec_sizes;
-
    const struct brw_isa_info *isa;
    const struct intel_device_info *devinfo;
 
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ef6de5c0785..14e3834af8c 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -125,25 +125,6 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
          }
       }
    }
-
-   /* Generators should set a default exec_size of either 8 (SIMD4x2 or SIMD8)
-    * or 16 (SIMD16), as that's normally correct.  However, when dealing with
-    * small registers, it can be useful for us to automatically reduce it to
-    * match the register size.
-    */
-   if (p->automatic_exec_sizes) {
-      /*
-       * In platforms that support fp64 we can emit instructions with a width
-       * of 4 that need two SIMD8 registers and an exec_size of 8 or 16. In
-       * these cases we need to make sure that these instructions have their
-       * exec sizes set properly when they are emitted and we can't rely on
-       * this code to fix it.
-       */
-      bool fix_exec_size = dest.width < BRW_EXECUTE_4;
-
-      if (fix_exec_size)
-         brw_inst_set_exec_size(devinfo, inst, dest.width);
-   }
 }
 
 void
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index f228b8f85a0..861b24da7b5 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -139,12 +139,6 @@ fs_generator::fs_generator(const struct brw_compiler *compiler,
 {
    p = rzalloc(mem_ctx, struct brw_codegen);
    brw_init_codegen(&compiler->isa, p, mem_ctx);
-
-   /* In the FS code generator, we are very careful to ensure that we always
-    * set the right execution size so we don't need the EU code to "help" us
-    * by trying to infer it.  Sometimes, it infers the wrong thing.
-    */
-   p->automatic_exec_sizes = false;
 }
 
 fs_generator::~fs_generator()