Added some shortcuts for VG_(message)(), and used them in a few places (but

certainly not all).



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@9367 a5019735-40e9-0310-863c-91ae7b9d1cf9

2 files changed, 92 insertions, 115 deletions

diff --git a/cachegrind/cg-x86.c b/cachegrind/cg-x86.c
index f9fa15ba7..be5eb82ec 100644
--- a/cachegrind/cg-x86.c
+++ b/cachegrind/cg-x86.c
@@ -42,12 +42,10 @@
 
 static void micro_ops_warn(Int actual_size, Int used_size, Int line_size)
 {
-   VG_(message)(Vg_DebugMsg, 
-      "warning: Pentium 4 with %d KB micro-op instruction trace cache", 
-      actual_size);
-   VG_(message)(Vg_DebugMsg, 
-      "         Simulating a %d KB I-cache with %d B lines", 
-      used_size, line_size);
+   VG_DMSG("warning: Pentium 4 with %d KB micro-op instruction trace cache", 
+           actual_size);
+   VG_DMSG("         Simulating a %d KB I-cache with %d B lines", 
+           used_size, line_size);
 }
 
 /* Intel method is truly wretched.  We have to do an insane indexing into an
@@ -67,9 +65,7 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c)
    Bool  L2_found = False;
 
    if (level < 2) {
-      VG_(message)(Vg_DebugMsg, 
-         "warning: CPUID level < 2 for Intel processor (%d)", 
-         level);
+      VG_DMSG("warning: CPUID level < 2 for Intel processor (%d)", level);
       return -1;
    }
 
@@ -85,9 +81,8 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c)
    info[0] = 0x0;           /* reset AL */
 
    if (0 != trials) {
-      VG_(message)(Vg_DebugMsg, 
-         "warning: non-zero CPUID trials for Intel processor (%d)",
-         trials);
+      VG_DMSG("warning: non-zero CPUID trials for Intel processor (%d)",
+              trials);
       return -1;
    }
 
@@ -124,8 +119,7 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c)
 
       case 0x22: case 0x23: case 0x25: case 0x29:
       case 0x46: case 0x47: case 0x4a: case 0x4b: case 0x4c: case 0x4d:
-          VG_(message)(Vg_DebugMsg,
-             "warning: L3 cache detected but ignored");
+          VG_DMSG("warning: L3 cache detected but ignored");
           break;
 
       /* These are sectored, whatever that means */
@@ -148,8 +142,7 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c)
       case 0x49:
 	  if ((family == 15) && (model == 6))
 	      /* On Xeon MP (family F, model 6), this is for L3 */
-	      VG_(message)(Vg_DebugMsg, 
-			   "warning: L3 cache detected but ignored");
+	      VG_DMSG("warning: L3 cache detected but ignored");
 	  else
 	      *L2c = (cache_t) { 4096, 16, 64 }; L2_found = True;
 	  break;
@@ -200,19 +193,17 @@ Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c)
 
       /* Ignore prefetch information */
       case 0xf0: case 0xf1:
-          break;
+         break;
 
       default:
-          VG_(message)(Vg_DebugMsg, 
-             "warning: Unknown Intel cache config value "
-             "(0x%x), ignoring", info[i]);
-          break;
+         VG_DMSG("warning: Unknown Intel cache config value (0x%x), ignoring",
+                 info[i]);
+         break;
       }
    }
 
    if (!L2_found)
-      VG_(message)(Vg_DebugMsg, 
-         "warning: L2 cache not installed, ignore L2 results.");
+      VG_DMSG("warning: L2 cache not installed, ignore L2 results.");
 
    return 0;
 }
@@ -251,9 +242,8 @@ Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c)
    VG_(cpuid)(0x80000000, &ext_level, &dummy, &dummy, &dummy);
 
    if (0 == (ext_level & 0x80000000) || ext_level < 0x80000006) {
-      VG_(message)(Vg_UserMsg, 
-         "warning: ext_level < 0x80000006 for AMD processor (0x%x)", 
-         ext_level);
+      VG_DMSG("warning: ext_level < 0x80000006 for AMD processor (0x%x)", 
+              ext_level);
       return -1;
    }
 
@@ -264,8 +254,7 @@ Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c)
 
    /* Check for Duron bug */
    if (model == 0x630) {
-      VG_(message)(Vg_UserMsg,
-         "Buggy Duron stepping A0. Assuming L2 size=65536 bytes");
+      VG_DMSG("warning: Buggy Duron stepping A0. Assuming L2 size=65536 bytes");
       L2i = (64 << 16) | (L2i & 0xffff);
    }
 
@@ -291,7 +280,7 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c)
    Char vendor_id[13];
 
    if (!VG_(has_cpuid)()) {
-      VG_(message)(Vg_DebugMsg, "CPUID instruction not supported");
+      VG_DMSG("CPUID instruction not supported");
       return -1;
    }
 
@@ -300,7 +289,7 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c)
    vendor_id[12] = '\0';
 
    if (0 == level) {
-      VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?");
+      VG_DMSG("CPUID level is 0, early Pentium?");
       return -1;
    }
 
@@ -325,8 +314,7 @@ Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c)
       ret = 0;
 
    } else {
-      VG_(message)(Vg_DebugMsg, "CPU vendor ID not recognised (%s)",
-                   vendor_id);
+      VG_DMSG("CPU vendor ID not recognised (%s)", vendor_id);
       return -1;
    }
 
@@ -354,9 +342,8 @@ void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
 
    // Warn if CPUID failed and config not completely specified from cmd line.
    if (res != 0 && !all_caches_clo_defined) {
-      VG_(message)(Vg_DebugMsg, 
-                   "Warning: Couldn't auto-detect cache config, using one "
-                   "or more defaults ");
+      VG_DMSG("Warning: Couldn't auto-detect cache config, using one "
+              "or more defaults ");
    }
 }
 
diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c
index ec21b4969..cfaf53aef 100644
--- a/cachegrind/cg_main.c
+++ b/cachegrind/cg_main.c
@@ -1161,16 +1161,13 @@ void check_cache(cache_t* cache, Char *name)
    /* Simulator requires line size and set count to be powers of two */
    if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
        (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
-      VG_(message)(Vg_UserMsg,
-         "error: %s set count not a power of two; aborting.",
-         name);
+      VG_UMSG("error: %s set count not a power of two; aborting.", name);
       VG_(exit)(1);
    }
 
    if (-1 == VG_(log2)(cache->line_size)) {
-      VG_(message)(Vg_UserMsg,
-         "error: %s line size of %dB not a power of two; aborting.",
-         name, cache->line_size);
+      VG_UMSG("error: %s line size of %dB not a power of two; aborting.",
+              name, cache->line_size);
       VG_(exit)(1);
    }
 
@@ -1178,24 +1175,22 @@ void check_cache(cache_t* cache, Char *name)
    // straddle three cache lines, which breaks a simulation assertion and is
    // stupid anyway.
    if (cache->line_size < MIN_LINE_SIZE) {
-      VG_(message)(Vg_UserMsg,
-         "error: %s line size of %dB too small; aborting.", 
-         name, cache->line_size);
+      VG_UMSG("error: %s line size of %dB too small; aborting.", 
+              name, cache->line_size);
       VG_(exit)(1);
    }
 
    /* Then check cache size > line size (causes seg faults if not). */
    if (cache->size <= cache->line_size) {
-      VG_(message)(Vg_UserMsg,
-         "error: %s cache size of %dB <= line size of %dB; aborting.",
-         name, cache->size, cache->line_size);
+      VG_UMSG("error: %s cache size of %dB <= line size of %dB; aborting.",
+              name, cache->size, cache->line_size);
       VG_(exit)(1);
    }
 
    /* Then check assoc <= (size / line size) (seg faults otherwise). */
    if (cache->assoc > (cache->size / cache->line_size)) {
-      VG_(message)(Vg_UserMsg,
-         "warning: %s associativity > (size / line size); aborting.", name);
+      VG_UMSG("warning: %s associativity > (size / line size); aborting.",
+              name);
       VG_(exit)(1);
    }
 }
@@ -1226,14 +1221,14 @@ void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* L2c)
    check_cache(D1c, "D1");
    check_cache(L2c, "L2");
 
-   if (VG_(clo_verbosity) > 1) {
-      VG_(message)(Vg_UserMsg, "Cache configuration used:");
-      VG_(message)(Vg_UserMsg, "  I1: %dB, %d-way, %dB lines",
-                               I1c->size, I1c->assoc, I1c->line_size);
-      VG_(message)(Vg_UserMsg, "  D1: %dB, %d-way, %dB lines",
-                               D1c->size, D1c->assoc, D1c->line_size);
-      VG_(message)(Vg_UserMsg, "  L2: %dB, %d-way, %dB lines",
-                               L2c->size, L2c->assoc, L2c->line_size);
+   if (VG_(clo_verbosity) >= 2) {
+      VG_UMSG("Cache configuration used:");
+      VG_UMSG("  I1: %dB, %d-way, %dB lines",
+              I1c->size, I1c->assoc, I1c->line_size);
+      VG_UMSG("  D1: %dB, %d-way, %dB lines",
+              D1c->size, D1c->assoc, D1c->line_size);
+      VG_UMSG("  L2: %dB, %d-way, %dB lines",
+              L2c->size, L2c->assoc, L2c->line_size);
    }
 #undef CMD_LINE_DEFINED
 }
@@ -1270,11 +1265,9 @@ static void fprint_CC_table_and_calc_totals(void)
    if (sres.isError) {
       // If the file can't be opened for whatever reason (conflict
       // between multiple cachegrinded processes?), give up now.
-      VG_(message)(Vg_UserMsg,
-         "error: can't open cache simulation output file '%s'",
-         cachegrind_out_file );
-      VG_(message)(Vg_UserMsg,
-         "       ... so simulation results will be missing.");
+      VG_UMSG("error: can't open cache simulation output file '%s'",
+              cachegrind_out_file );
+      VG_UMSG("       ... so simulation results will be missing.");
       VG_(free)(cachegrind_out_file);
       return;
    } else {
@@ -1484,23 +1477,23 @@ static void cg_fini(Int exitcode)
    VG_(sprintf)(fmt, "%%s %%,%dllu", l1);
 
    /* Always print this */
-   VG_(message)(Vg_UserMsg, fmt, "I   refs:     ", Ir_total.a);
+   VG_UMSG(fmt, "I   refs:     ", Ir_total.a);
 
    /* If cache profiling is enabled, show D access numbers and all
       miss numbers */
    if (clo_cache_sim) {
-      VG_(message)(Vg_UserMsg, fmt, "I1  misses:   ", Ir_total.m1);
-      VG_(message)(Vg_UserMsg, fmt, "L2i misses:   ", Ir_total.m2);
+      VG_UMSG(fmt, "I1  misses:   ", Ir_total.m1);
+      VG_UMSG(fmt, "L2i misses:   ", Ir_total.m2);
 
       p = 100;
 
       if (0 == Ir_total.a) Ir_total.a = 1;
       VG_(percentify)(Ir_total.m1, Ir_total.a, 2, l1+1, buf1);
-      VG_(message)(Vg_UserMsg, "I1  miss rate: %s", buf1);
+      VG_UMSG("I1  miss rate: %s", buf1);
 
       VG_(percentify)(Ir_total.m2, Ir_total.a, 2, l1+1, buf1);
-      VG_(message)(Vg_UserMsg, "L2i miss rate: %s", buf1);
-      VG_(message)(Vg_UserMsg, "");
+      VG_UMSG("L2i miss rate: %s", buf1);
+      VG_UMSG("");
 
       /* D cache results.  Use the D_refs.rd and D_refs.wr values to
        * determine the width of columns 2 & 3. */
@@ -1511,12 +1504,12 @@ static void cg_fini(Int exitcode)
       /* Make format string, getting width right for numbers */
       VG_(sprintf)(fmt, "%%s %%,%dllu  (%%,%dllu rd   + %%,%dllu wr)", l1, l2, l3);
 
-      VG_(message)(Vg_UserMsg, fmt, "D   refs:     ", 
-                               D_total.a, Dr_total.a, Dw_total.a);
-      VG_(message)(Vg_UserMsg, fmt, "D1  misses:   ",
-                               D_total.m1, Dr_total.m1, Dw_total.m1);
-      VG_(message)(Vg_UserMsg, fmt, "L2d misses:   ",
-                               D_total.m2, Dr_total.m2, Dw_total.m2);
+      VG_UMSG(fmt, "D   refs:     ", 
+                   D_total.a, Dr_total.a, Dw_total.a);
+      VG_UMSG(fmt, "D1  misses:   ",
+                   D_total.m1, Dr_total.m1, Dw_total.m1);
+      VG_UMSG(fmt, "L2d misses:   ",
+                   D_total.m2, Dr_total.m2, Dw_total.m2);
 
       p = 10;
 
@@ -1526,32 +1519,32 @@ static void cg_fini(Int exitcode)
       VG_(percentify)( D_total.m1,  D_total.a, 1, l1+1, buf1);
       VG_(percentify)(Dr_total.m1, Dr_total.a, 1, l2+1, buf2);
       VG_(percentify)(Dw_total.m1, Dw_total.a, 1, l3+1, buf3);
-      VG_(message)(Vg_UserMsg, "D1  miss rate: %s (%s     + %s  )", buf1, buf2,buf3);
+      VG_UMSG("D1  miss rate: %s (%s     + %s  )", buf1, buf2,buf3);
 
       VG_(percentify)( D_total.m2,  D_total.a, 1, l1+1, buf1);
       VG_(percentify)(Dr_total.m2, Dr_total.a, 1, l2+1, buf2);
       VG_(percentify)(Dw_total.m2, Dw_total.a, 1, l3+1, buf3);
-      VG_(message)(Vg_UserMsg, "L2d miss rate: %s (%s     + %s  )", buf1, buf2,buf3);
-      VG_(message)(Vg_UserMsg, "");
+      VG_UMSG("L2d miss rate: %s (%s     + %s  )", buf1, buf2,buf3);
+      VG_UMSG("");
 
       /* L2 overall results */
 
       L2_total   = Dr_total.m1 + Dw_total.m1 + Ir_total.m1;
       L2_total_r = Dr_total.m1 + Ir_total.m1;
       L2_total_w = Dw_total.m1;
-      VG_(message)(Vg_UserMsg, fmt, "L2 refs:      ",
-                               L2_total, L2_total_r, L2_total_w);
+      VG_UMSG(fmt, "L2 refs:      ",
+                   L2_total, L2_total_r, L2_total_w);
 
       L2_total_m  = Dr_total.m2 + Dw_total.m2 + Ir_total.m2;
       L2_total_mr = Dr_total.m2 + Ir_total.m2;
       L2_total_mw = Dw_total.m2;
-      VG_(message)(Vg_UserMsg, fmt, "L2 misses:    ",
-                               L2_total_m, L2_total_mr, L2_total_mw);
+      VG_UMSG(fmt, "L2 misses:    ",
+                   L2_total_m, L2_total_mr, L2_total_mw);
 
       VG_(percentify)(L2_total_m,  (Ir_total.a + D_total.a),  1, l1+1, buf1);
       VG_(percentify)(L2_total_mr, (Ir_total.a + Dr_total.a), 1, l2+1, buf2);
       VG_(percentify)(L2_total_mw, Dw_total.a,                1, l3+1, buf3);
-      VG_(message)(Vg_UserMsg, "L2 miss rate:  %s (%s     + %s  )", buf1, buf2,buf3);
+      VG_UMSG("L2 miss rate:  %s (%s     + %s  )", buf1, buf2,buf3);
    }
 
    /* If branch profiling is enabled, show branch overall results. */
@@ -1564,18 +1557,18 @@ static void cg_fini(Int exitcode)
       B_total.b  = Bc_total.b  + Bi_total.b;
       B_total.mp = Bc_total.mp + Bi_total.mp;
 
-      VG_(message)(Vg_UserMsg, "");
-      VG_(message)(Vg_UserMsg, fmt, "Branches:     ",
-                               B_total.b, Bc_total.b, Bi_total.b);
+      VG_UMSG("");
+      VG_UMSG(fmt, "Branches:     ",
+                   B_total.b, Bc_total.b, Bi_total.b);
 
-      VG_(message)(Vg_UserMsg, fmt, "Mispredicts:  ",
-                               B_total.mp, Bc_total.mp, Bi_total.mp);
+      VG_UMSG(fmt, "Mispredicts:  ",
+                   B_total.mp, Bc_total.mp, Bi_total.mp);
 
       VG_(percentify)(B_total.mp,  B_total.b,  1, l1+1, buf1);
       VG_(percentify)(Bc_total.mp, Bc_total.b, 1, l2+1, buf2);
       VG_(percentify)(Bi_total.mp, Bi_total.b, 1, l3+1, buf3);
 
-      VG_(message)(Vg_UserMsg, "Mispred rate:  %s (%s     + %s   )", buf1, buf2,buf3);
+      VG_UMSG("Mispred rate:  %s (%s     + %s   )", buf1, buf2,buf3);
    }
 
    // Various stats
@@ -1583,32 +1576,32 @@ static void cg_fini(Int exitcode)
       Int debug_lookups = full_debugs      + fn_debugs +
                           file_line_debugs + no_debugs;
 
-      VG_(message)(Vg_DebugMsg, "");
-      VG_(message)(Vg_DebugMsg, "cachegrind: distinct files: %d", distinct_files);
-      VG_(message)(Vg_DebugMsg, "cachegrind: distinct fns:   %d", distinct_fns);
-      VG_(message)(Vg_DebugMsg, "cachegrind: distinct lines: %d", distinct_lines);
-      VG_(message)(Vg_DebugMsg, "cachegrind: distinct instrs:%d", distinct_instrs);
-      VG_(message)(Vg_DebugMsg, "cachegrind: debug lookups      : %d", debug_lookups);
+      VG_DMSG("");
+      VG_DMSG("cachegrind: distinct files: %d", distinct_files);
+      VG_DMSG("cachegrind: distinct fns:   %d", distinct_fns);
+      VG_DMSG("cachegrind: distinct lines: %d", distinct_lines);
+      VG_DMSG("cachegrind: distinct instrs:%d", distinct_instrs);
+      VG_DMSG("cachegrind: debug lookups      : %d", debug_lookups);
       
       VG_(percentify)(full_debugs,      debug_lookups, 1, 6, buf1);
       VG_(percentify)(file_line_debugs, debug_lookups, 1, 6, buf2);
       VG_(percentify)(fn_debugs,        debug_lookups, 1, 6, buf3);
       VG_(percentify)(no_debugs,        debug_lookups, 1, 6, buf4);
-      VG_(message)(Vg_DebugMsg, "cachegrind: with full      info:%s (%d)", 
-                   buf1, full_debugs);
-      VG_(message)(Vg_DebugMsg, "cachegrind: with file/line info:%s (%d)", 
-                   buf2, file_line_debugs);
-      VG_(message)(Vg_DebugMsg, "cachegrind: with fn name   info:%s (%d)", 
-                   buf3, fn_debugs);
-      VG_(message)(Vg_DebugMsg, "cachegrind: with zero      info:%s (%d)", 
-                   buf4, no_debugs);
-
-      VG_(message)(Vg_DebugMsg, "cachegrind: string table size: %lu",
-                   VG_(OSetGen_Size)(stringTable));
-      VG_(message)(Vg_DebugMsg, "cachegrind: CC table size: %lu",
-                   VG_(OSetGen_Size)(CC_table));
-      VG_(message)(Vg_DebugMsg, "cachegrind: InstrInfo table size: %lu",
-                   VG_(OSetGen_Size)(instrInfoTable));
+      VG_DMSG("cachegrind: with full      info:%s (%d)", 
+              buf1, full_debugs);
+      VG_DMSG("cachegrind: with file/line info:%s (%d)", 
+              buf2, file_line_debugs);
+      VG_DMSG("cachegrind: with fn name   info:%s (%d)", 
+              buf3, fn_debugs);
+      VG_DMSG("cachegrind: with zero      info:%s (%d)", 
+              buf4, no_debugs);
+
+      VG_DMSG("cachegrind: string table size: %lu",
+              VG_(OSetGen_Size)(stringTable));
+      VG_DMSG("cachegrind: CC table size: %lu",
+              VG_(OSetGen_Size)(CC_table));
+      VG_DMSG("cachegrind: InstrInfo table size: %lu",
+              VG_(OSetGen_Size)(instrInfoTable));
    }
 }
 
@@ -1664,8 +1657,7 @@ static void parse_cache_opt ( cache_t* cache, Char* opt )
    return;
 
   overflow:
-   VG_(message)(Vg_UserMsg,
-                "one of the cache parameters was too large and overflowed\n");
+   VG_UMSG("one of the cache parameters was too large and overflowed\n");
   bad:
    // XXX: this omits the "--I1/D1/L2=" part from the message, but that's
    // not a big deal.
@@ -1744,10 +1736,8 @@ static void cg_post_clo_init(void)
 
    /* Can't disable both cache and branch profiling */
    if ((!clo_cache_sim) && (!clo_branch_sim)) {
-      VG_(message)(Vg_DebugMsg,
-                   "ERROR: --cache-sim=no --branch-sim=no is not allowed.");
-      VG_(message)(Vg_DebugMsg,
-                   "You must select cache profiling, or branch profiling, or both.");
+      VG_UMSG("ERROR: --cache-sim=no --branch-sim=no is not allowed.");
+      VG_UMSG("You must select cache profiling, or branch profiling, or both.");
       VG_(exit)(2);
    }