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-rw-r--r--libhwc2.1/ExynosHWCModule.h47
-rw-r--r--libhwc2.1/ExynosResourceRestriction.h20
-rw-r--r--libhwc2.1/libmaindisplay/ExynosPrimaryDisplayModule.cpp13
-rw-r--r--libhwc2.1/libresource/ExynosMPPModule.cpp11
-rw-r--r--libhwc2.1/libresource/ExynosMPPModule.h1
-rw-r--r--libhwc2.1/libresource/ExynosResourceManagerModule.cpp7
-rw-r--r--libhwc2.1/libresource/ExynosResourceManagerModule.h3
7 files changed, 54 insertions, 48 deletions
diff --git a/libhwc2.1/ExynosHWCModule.h b/libhwc2.1/ExynosHWCModule.h
index c4c5886..95c91a9 100644
--- a/libhwc2.1/ExynosHWCModule.h
+++ b/libhwc2.1/ExynosHWCModule.h
@@ -20,13 +20,26 @@
#include "ExynosHWC.h"
#include "DeconHeader.h"
+/* TODO: Those definitions should be removed */
+#define USE_SW_VSYNC
+#define DISABLE_M2M_MPPS
+#define FORCE_GPU_COMPOSITION
+#define FIX_BASE_WINDOW_INDEX 5
+#define DISABLE_READ_RESTRICTIONS
+
#define HWC_VERSION HWC_DEVICE_API_VERSION_1_5
#define VSYNC_DEV_PREFIX "/sys/devices/"
#define VSYNC_DEV_MIDDLE "platform/"
-#define VSYNC_DEV_NAME "19030000.decon_f/vsync"
+#ifdef USE_SW_VSYNC
+/* Those are invalid vsync path */
+#define VSYNC_DEV_NAME ""
+#define PSR_DEV_NAME ""
+#else
+#define VSYNC_DEV_NAME "1c300000.decon_f/vsync"
+#define PSR_DEV_NAME "1c300000.decon_f/psr_info"
+#endif
#define VSYNC_DEV_NAME_EXT "19050000.decon_t/vsync"
-#define PSR_DEV_NAME "19030000.decon_f/psr_info"
#define DP_LINK_NAME "130b0000.displayport"
#define DP_UEVENT_NAME "change@/devices/platform/%s/extcon/extcon0"
#define DP_CABLE_STATE_NAME "/sys/devices/platform/%s/extcon/extcon0/cable.0/state"
@@ -51,13 +64,14 @@ struct exynos_mpp_t {
const dpp_channel_map_t IDMA_CHANNEL_MAP[] = {
/* GF physical index is switched to change assign order */
- {MPP_DPP_GF, 1, IDMA_GF0, IDMA(0)},
- {MPP_DPP_VGRFS, 0, IDMA_VGRFS0,IDMA(1)},
- {MPP_DPP_GF, 0, IDMA_GF1, IDMA(2)},
- {MPP_DPP_VGF, 0, IDMA_VGF0, IDMA(3)},
- {MPP_DPP_VG, 0, IDMA_VG0, IDMA(4)},
- {MPP_DPP_VGS, 0, IDMA_VGS0, IDMA(5)},
- {MPP_P_TYPE_MAX, 0, ODMA_WB, IDMA(6)}, // not idma but..
+ /* DECON_IDMA is not used */
+ {MPP_DPP_GF, 0, IDMA(0), IDMA(0)},
+ {MPP_DPP_VGRFS, 0, IDMA(1), IDMA(1)},
+ {MPP_DPP_GF, 1, IDMA(2), IDMA(2)},
+ {MPP_DPP_VGRFS, 1, IDMA(3), IDMA(3)},
+ {MPP_DPP_GF, 2, IDMA(4), IDMA(4)},
+ {MPP_DPP_VGRFS, 2, IDMA(5), IDMA(5)},
+ {MPP_P_TYPE_MAX, 0, IDMA(6), IDMA(6)}, // not idma but..
{static_cast<mpp_phycal_type_t>(MAX_DECON_DMA_TYPE), 0, MAX_DECON_DMA_TYPE, IDMA(7)}
};
@@ -89,22 +103,23 @@ enum {
};
const exynos_mpp_t AVAILABLE_OTF_MPP_UNITS[] = {
- {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF1", 0, 0, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT},
- {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF0", 1, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT},
- {MPP_DPP_VG, MPP_LOGICAL_DPP_VG, "DPP_VG0", 0, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT},
- {MPP_DPP_VGS, MPP_LOGICAL_DPP_VGS, "DPP_VGS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT},
- {MPP_DPP_VGF, MPP_LOGICAL_DPP_VGF, "DPP_VGF0", 0, 0, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT},
- {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}
+ {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF0", 0, 0, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT},
+ {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF1", 1, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT},
+ {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF2", 2, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT},
+ {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT},
+ {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT},
+ {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}
};
const exynos_mpp_t AVAILABLE_M2M_MPP_UNITS[] = {
- {MPP_MSC, MPP_LOGICAL_MSC, "MSC0_PRI", 0, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT},
+#ifndef DISABLE_M2M_MPPS
{MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT},
{MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 1, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT},
{MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_EXT", 0, 2, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT},
{MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_PRI", 0, 3, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT},
{MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_EXT", 0, 4, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT},
{MPP_G2D, MPP_LOGICAL_G2D_COMBO, "G2D0-COMBO_VIR", 0, 5, HWC_DISPLAY_VIRTUAL_BIT|EXTERNAL_MAIN_DISPLAY_VIRTUAL_BIT}
+#endif
};
#endif
diff --git a/libhwc2.1/ExynosResourceRestriction.h b/libhwc2.1/ExynosResourceRestriction.h
index b401b7a..3907a7f 100644
--- a/libhwc2.1/ExynosResourceRestriction.h
+++ b/libhwc2.1/ExynosResourceRestriction.h
@@ -123,22 +123,6 @@ const restriction_key_t restriction_format_table[] =
{MPP_DPP_VGRFS, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SPN_S10B, 0},
{MPP_DPP_VGRFS, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_P010_M, 0},
{MPP_DPP_VGRFS, NODE_NONE, HAL_PIXEL_FORMAT_YCBCR_P010, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SP_M, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SP_M_PRIV, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SP_M_TILED, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCrCb_420_SP_M, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCrCb_420_SP_M_FULL, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SPN, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SP_M_S10B, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SPN_S10B, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_P010_M, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_YCBCR_P010, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_YCrCb_420_SP, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_YV12, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YV12_M, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_P_M, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_PN, 0},
- {MPP_MSC, NODE_NONE, HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SPN_TILED, 0},
{MPP_G2D, NODE_NONE, HAL_PIXEL_FORMAT_RGB_565, 0},
{MPP_G2D, NODE_NONE, HAL_PIXEL_FORMAT_RGB_888, 0},
{MPP_G2D, NODE_NONE, HAL_PIXEL_FORMAT_RGBA_8888, 0},
@@ -197,8 +181,6 @@ const restriction_size_element restriction_size_table_yuv[] =
{ 1, 1, 65534, 8190, 32, 32, 2, 2, 4096, 4096, 32, 32, 2, 2, 2, 2}},
{{MPP_DPP_VGRFS, NODE_SRC, HAL_PIXEL_FORMAT_NONE, 0},
{ 2, 8, 65534, 8190, 32, 32, 2, 2, 4096, 4096, 32, 32, 2, 2, 2, 2}},
- {{MPP_MSC, NODE_SRC, HAL_PIXEL_FORMAT_NONE, 0},
- { 16, 64, 8192, 8192, 16, 16, 2, 2, 4096, 4096, 16, 16, 2, 2, 2, 2}},
/* MPP_G2D maxUpScale = max crop size / min crop size */
{{MPP_G2D, NODE_SRC, HAL_PIXEL_FORMAT_NONE, 0},
{ 4, 8192, 8192, 8192, 2, 2, 2, 2, 8192, 8192, 1, 1, 1, 1, 1, 1}},
@@ -212,8 +194,6 @@ const restriction_size_element restriction_size_table_yuv[] =
{ 1, 1, 65535, 8191, 16, 16, 1, 1, 4096, 4096, 16, 16, 1, 1, 1, 1}},
{{MPP_DPP_VGRFS, NODE_DST, HAL_PIXEL_FORMAT_NONE, 0},
{ 2, 8, 65535, 8191, 16, 16, 1, 1, 4096, 4096, 16, 16, 1, 1, 1, 1}},
- {{MPP_MSC, NODE_DST, HAL_PIXEL_FORMAT_NONE, 0},
- { 16, 64, 8192, 8192, 4, 4, 2, 2, 8192, 8192, 4, 4, 2, 2, 2, 2}},
/* MPP_G2D maxUpScale = max crop size / min crop size */
{{MPP_G2D, NODE_DST, HAL_PIXEL_FORMAT_NONE, 0},
{ 8192, 8192, 8192, 8192, 2, 2, 2, 2, 8192, 8192, 2, 2, 2, 2, 2, 2}}
diff --git a/libhwc2.1/libmaindisplay/ExynosPrimaryDisplayModule.cpp b/libhwc2.1/libmaindisplay/ExynosPrimaryDisplayModule.cpp
index 2a5792f..21d1a44 100644
--- a/libhwc2.1/libmaindisplay/ExynosPrimaryDisplayModule.cpp
+++ b/libhwc2.1/libmaindisplay/ExynosPrimaryDisplayModule.cpp
@@ -17,6 +17,10 @@
#include "ExynosPrimaryDisplayModule.h"
#include "ExynosHWCDebug.h"
+#ifdef FORCE_GPU_COMPOSITION
+extern exynos_hwc_control exynosHWCControl;
+#endif
+
mpp_phycal_type_t getMPPTypeFromDPPChannel(uint32_t channel) {
for (int i=0; i < MAX_DECON_DMA_TYPE; i++){
@@ -30,6 +34,9 @@ mpp_phycal_type_t getMPPTypeFromDPPChannel(uint32_t channel) {
ExynosPrimaryDisplayModule::ExynosPrimaryDisplayModule(uint32_t __unused type, ExynosDevice *device)
: ExynosPrimaryDisplay(HWC_DISPLAY_PRIMARY, device)
{
+#ifdef FORCE_GPU_COMPOSITION
+ exynosHWCControl.forceGpu = true;
+#endif
}
ExynosPrimaryDisplayModule::~ExynosPrimaryDisplayModule () {
@@ -37,6 +44,12 @@ ExynosPrimaryDisplayModule::~ExynosPrimaryDisplayModule () {
void ExynosPrimaryDisplayModule::usePreDefinedWindow(bool use)
{
+#ifdef FIX_BASE_WINDOW_INDEX
+ /* Use fixed base window index */
+ mBaseWindowIndex = FIX_BASE_WINDOW_INDEX;
+ return;
+#endif
+
if (use) {
mBaseWindowIndex = PRIMARY_DISP_BASE_WIN[mDevice->mDisplayMode];
mMaxWindowNum = NUM_HW_WINDOWS - PRIMARY_DISP_BASE_WIN[mDevice->mDisplayMode];
diff --git a/libhwc2.1/libresource/ExynosMPPModule.cpp b/libhwc2.1/libresource/ExynosMPPModule.cpp
index bd90414..9096a1e 100644
--- a/libhwc2.1/libresource/ExynosMPPModule.cpp
+++ b/libhwc2.1/libresource/ExynosMPPModule.cpp
@@ -36,16 +36,6 @@ uint32_t ExynosMPPModule::getSrcXOffsetAlign(struct exynos_image &src)
return mSrcSizeRestrictions[idx].cropXAlign;
}
-uint32_t ExynosMPPModule::getDstWidthAlign(struct exynos_image &dst)
-{
- if (((dst.format == HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SPN_S10B) ||
- (dst.format == HAL_PIXEL_FORMAT_EXYNOS_YCbCr_420_SP_M_S10B)) &&
- (mPhysicalType == MPP_MSC))
- return 4;
-
- return ExynosMPP::getDstWidthAlign(dst);
-}
-
bool ExynosMPPModule::isSupportedCompression(struct exynos_image &src)
{
if (src.compressed) {
@@ -121,7 +111,6 @@ bool ExynosMPPModule::isSupportedTransform(struct exynos_image &src)
ExynosMPP *sharedMPP = NULL;
switch (mPhysicalType)
{
- case MPP_MSC:
case MPP_G2D:
return true;
case MPP_DPP_G:
diff --git a/libhwc2.1/libresource/ExynosMPPModule.h b/libhwc2.1/libresource/ExynosMPPModule.h
index a48a5d6..146ccdd 100644
--- a/libhwc2.1/libresource/ExynosMPPModule.h
+++ b/libhwc2.1/libresource/ExynosMPPModule.h
@@ -28,7 +28,6 @@ class ExynosMPPModule : public ExynosMPP {
virtual bool isSupportedTransform(struct exynos_image &src);
virtual bool isSupportedCompression(struct exynos_image &src);
virtual uint32_t getSrcXOffsetAlign(struct exynos_image &src);
- virtual uint32_t getDstWidthAlign(struct exynos_image &dst);
virtual uint32_t getSrcMaxCropSize(struct exynos_image &src);
public:
uint32_t mChipId;
diff --git a/libhwc2.1/libresource/ExynosResourceManagerModule.cpp b/libhwc2.1/libresource/ExynosResourceManagerModule.cpp
index 997a5d0..dbd9a97 100644
--- a/libhwc2.1/libresource/ExynosResourceManagerModule.cpp
+++ b/libhwc2.1/libresource/ExynosResourceManagerModule.cpp
@@ -62,3 +62,10 @@ ExynosResourceManagerModule::ExynosResourceManagerModule(ExynosDevice* device)
ExynosResourceManagerModule::~ExynosResourceManagerModule()
{
}
+
+#ifdef DISABLE_READ_RESTRICTIONS
+bool ExynosResourceManagerModule::makeDPURestrictions(int fd)
+{
+ return false;
+}
+#endif
diff --git a/libhwc2.1/libresource/ExynosResourceManagerModule.h b/libhwc2.1/libresource/ExynosResourceManagerModule.h
index 19da403..04f0d7e 100644
--- a/libhwc2.1/libresource/ExynosResourceManagerModule.h
+++ b/libhwc2.1/libresource/ExynosResourceManagerModule.h
@@ -22,6 +22,9 @@ class ExynosResourceManagerModule : public ExynosResourceManager {
public:
ExynosResourceManagerModule(ExynosDevice* device);
~ExynosResourceManagerModule();
+#ifdef DISABLE_READ_RESTRICTIONS
+ virtual bool makeDPURestrictions(int fd);
+#endif
};
#endif // _EXYNOS_RESOURCE_MANAGER_MODULE_H
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 01:28:21 +0000