diff options
Diffstat (limited to 'libhwc2.1/ExynosHWCModule.h')
| -rw-r--r-- | libhwc2.1/ExynosHWCModule.h | 47 |
1 files changed, 31 insertions, 16 deletions
diff --git a/libhwc2.1/ExynosHWCModule.h b/libhwc2.1/ExynosHWCModule.h index c4c5886..95c91a9 100644 --- a/libhwc2.1/ExynosHWCModule.h +++ b/libhwc2.1/ExynosHWCModule.h @@ -20,13 +20,26 @@ #include "ExynosHWC.h" #include "DeconHeader.h" +/* TODO: Those definitions should be removed */ +#define USE_SW_VSYNC +#define DISABLE_M2M_MPPS +#define FORCE_GPU_COMPOSITION +#define FIX_BASE_WINDOW_INDEX 5 +#define DISABLE_READ_RESTRICTIONS + #define HWC_VERSION HWC_DEVICE_API_VERSION_1_5 #define VSYNC_DEV_PREFIX "/sys/devices/" #define VSYNC_DEV_MIDDLE "platform/" -#define VSYNC_DEV_NAME "19030000.decon_f/vsync" +#ifdef USE_SW_VSYNC +/* Those are invalid vsync path */ +#define VSYNC_DEV_NAME "" +#define PSR_DEV_NAME "" +#else +#define VSYNC_DEV_NAME "1c300000.decon_f/vsync" +#define PSR_DEV_NAME "1c300000.decon_f/psr_info" +#endif #define VSYNC_DEV_NAME_EXT "19050000.decon_t/vsync" -#define PSR_DEV_NAME "19030000.decon_f/psr_info" #define DP_LINK_NAME "130b0000.displayport" #define DP_UEVENT_NAME "change@/devices/platform/%s/extcon/extcon0" #define DP_CABLE_STATE_NAME "/sys/devices/platform/%s/extcon/extcon0/cable.0/state" @@ -51,13 +64,14 @@ struct exynos_mpp_t { const dpp_channel_map_t IDMA_CHANNEL_MAP[] = { /* GF physical index is switched to change assign order */ - {MPP_DPP_GF, 1, IDMA_GF0, IDMA(0)}, - {MPP_DPP_VGRFS, 0, IDMA_VGRFS0,IDMA(1)}, - {MPP_DPP_GF, 0, IDMA_GF1, IDMA(2)}, - {MPP_DPP_VGF, 0, IDMA_VGF0, IDMA(3)}, - {MPP_DPP_VG, 0, IDMA_VG0, IDMA(4)}, - {MPP_DPP_VGS, 0, IDMA_VGS0, IDMA(5)}, - {MPP_P_TYPE_MAX, 0, ODMA_WB, IDMA(6)}, // not idma but.. + /* DECON_IDMA is not used */ + {MPP_DPP_GF, 0, IDMA(0), IDMA(0)}, + {MPP_DPP_VGRFS, 0, IDMA(1), IDMA(1)}, + {MPP_DPP_GF, 1, IDMA(2), IDMA(2)}, + {MPP_DPP_VGRFS, 1, IDMA(3), IDMA(3)}, + {MPP_DPP_GF, 2, IDMA(4), IDMA(4)}, + {MPP_DPP_VGRFS, 2, IDMA(5), IDMA(5)}, + {MPP_P_TYPE_MAX, 0, IDMA(6), IDMA(6)}, // not idma but.. {static_cast<mpp_phycal_type_t>(MAX_DECON_DMA_TYPE), 0, MAX_DECON_DMA_TYPE, IDMA(7)} }; @@ -89,22 +103,23 @@ enum { }; const exynos_mpp_t AVAILABLE_OTF_MPP_UNITS[] = { - {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF1", 0, 0, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}, - {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF0", 1, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT}, - {MPP_DPP_VG, MPP_LOGICAL_DPP_VG, "DPP_VG0", 0, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}, - {MPP_DPP_VGS, MPP_LOGICAL_DPP_VGS, "DPP_VGS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}, - {MPP_DPP_VGF, MPP_LOGICAL_DPP_VGF, "DPP_VGF0", 0, 0, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}, - {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT} + {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF0", 0, 0, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}, + {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF1", 1, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT}, + {MPP_DPP_GF, MPP_LOGICAL_DPP_GF, "DPP_GF2", 2, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}, + {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}, + {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}, + {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT} }; const exynos_mpp_t AVAILABLE_M2M_MPP_UNITS[] = { - {MPP_MSC, MPP_LOGICAL_MSC, "MSC0_PRI", 0, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT}, +#ifndef DISABLE_M2M_MPPS {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 0, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT}, {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_PRI", 0, 1, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT}, {MPP_G2D, MPP_LOGICAL_G2D_YUV, "G2D0-YUV_EXT", 0, 2, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}, {MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_PRI", 0, 3, HWC_DISPLAY_PRIMARY_BIT|EXTERNAL_MAIN_DISPLAY_PRIMARY_BIT}, {MPP_G2D, MPP_LOGICAL_G2D_RGB, "G2D0-RGB_EXT", 0, 4, HWC_DISPLAY_EXTERNAL_BIT|EXTERNAL_MAIN_DISPLAY_EXTERNAL_BIT}, {MPP_G2D, MPP_LOGICAL_G2D_COMBO, "G2D0-COMBO_VIR", 0, 5, HWC_DISPLAY_VIRTUAL_BIT|EXTERNAL_MAIN_DISPLAY_VIRTUAL_BIT} +#endif }; #endif |