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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-04 19:53:19 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-02-04 19:53:19 +0000 |
| commit | a435513a7c9513a43aef3cc902d7578682a4aff1 (patch) | |
| tree | 4984eb168eeb04ab1344bf8f06e4836519047543 /include/llvm/CodeGen | |
| parent | 9eeb421361b522418d63f410f3c3dcaf8caec18d (diff) | |
| download | llvm-a435513a7c9513a43aef3cc902d7578682a4aff1.tar.gz | |
GlobalISel: Allow constructing SrcOp/DstOp from MachineOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353080 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen')
| -rw-r--r-- | include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 44077a40975..1c5348b6cff 100644 --- a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -66,6 +66,7 @@ class DstOp { public: enum class DstType { Ty_LLT, Ty_Reg, Ty_RC }; DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} + DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {} DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {} DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} @@ -125,6 +126,7 @@ class SrcOp { public: enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate }; SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {} + SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} |