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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-02-11 22:00:39 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2019-02-11 22:00:39 +0000
commitf3f4691605009a5714f69892ef4237bf37f49b52 (patch)
treef07a3d9981a7c9f44ef7b2dab5670c69b2f1f701 /include
parent3038811553351be0868a4e29351d3e74c0b49899 (diff)
downloadllvm-f3f4691605009a5714f69892ef4237bf37f49b52.tar.gz
GlobalISel: Implement moreElementsVector for implicit_def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353754 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r--include/llvm/CodeGen/GlobalISel/LegalizerHelper.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
index 8f8a96bab02..c18631b759e 100644
--- a/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -86,7 +86,7 @@ public:
/// Legalize a vector instruction by increasing the number of vector elements
/// involved and ignoring the added elements later.
LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
- LLT WideTy);
+ LLT MoreTy);
/// Expose MIRBuilder so clients can set their own RecordInsertInstruction
/// functions
@@ -119,6 +119,11 @@ private:
// extending back with \p ExtOpcode.
void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx,
unsigned ExtOpcode);
+ /// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
+ /// Def by performing it with additional vector elements and extracting the
+ /// result elements, and replacing the vreg of the operand in place.
+ void moreElementsVectorDst(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
+
LegalizeResult
widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
LegalizeResult