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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-06 19:07:21 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-06 19:07:21 +0000 |
| commit | 195a164675af86f390f9816e53291013d1b551d7 (patch) | |
| tree | 22b17ee45b7096eedf7f261b91134bdac12d1a0d /test/CodeGen/Hexagon/idxload-with-zero-offset.ll | |
| parent | a05c22c9e81ed8b7b62ca4d1769a66bccd9d8530 (diff) | |
| download | llvm-195a164675af86f390f9816e53291013d1b551d7.tar.gz | |
[Hexagon] Remove {{ *}} from testcases
The spaces in the instructions are now consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326829 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon/idxload-with-zero-offset.ll')
| -rw-r--r-- | test/CodeGen/Hexagon/idxload-with-zero-offset.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/Hexagon/idxload-with-zero-offset.ll b/test/CodeGen/Hexagon/idxload-with-zero-offset.ll index f1a9d38f1b1..fc9fe8ac80f 100644 --- a/test/CodeGen/Hexagon/idxload-with-zero-offset.ll +++ b/test/CodeGen/Hexagon/idxload-with-zero-offset.ll @@ -4,7 +4,7 @@ ; load word define i32 @load_w(i32* nocapture %a, i32 %n, i32 %m) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2) +; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2) entry: %tmp = add i32 %n, %m %scevgep9 = getelementptr i32, i32* %a, i32 %tmp @@ -15,7 +15,7 @@ entry: ; load unsigned half word define i16 @load_uh(i16* nocapture %a, i32 %n, i32 %m) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1) +; CHECK: r{{[0-9]+}} = memuh(r{{[0-9]+}}+r{{[0-9]+}}<<#1) entry: %tmp = add i32 %n, %m %scevgep9 = getelementptr i16, i16* %a, i32 %tmp @@ -26,7 +26,7 @@ entry: ; load signed half word define i32 @load_h(i16* nocapture %a, i32 %n, i32 %m) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1) +; CHECK: r{{[0-9]+}} = memh(r{{[0-9]+}}+r{{[0-9]+}}<<#1) entry: %tmp = add i32 %n, %m %scevgep9 = getelementptr i16, i16* %a, i32 %tmp @@ -38,7 +38,7 @@ entry: ; load unsigned byte define i8 @load_ub(i8* nocapture %a, i32 %n, i32 %m) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#0) +; CHECK: r{{[0-9]+}} = memub(r{{[0-9]+}}+r{{[0-9]+}}<<#0) entry: %tmp = add i32 %n, %m %scevgep9 = getelementptr i8, i8* %a, i32 %tmp @@ -49,7 +49,7 @@ entry: ; load signed byte define i32 @foo_2(i8* nocapture %a, i32 %n, i32 %m) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#0) +; CHECK: r{{[0-9]+}} = memb(r{{[0-9]+}}+r{{[0-9]+}}<<#0) entry: %tmp = add i32 %n, %m %scevgep9 = getelementptr i8, i8* %a, i32 %tmp @@ -61,7 +61,7 @@ entry: ; load doubleword define i64 @load_d(i64* nocapture %a, i32 %n, i32 %m) nounwind { -; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#3) +; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+r{{[0-9]+}}<<#3) entry: %tmp = add i32 %n, %m %scevgep9 = getelementptr i64, i64* %a, i32 %tmp |