[Hexagon] Update MCTargetDesc

Changes include:
- Updates to the instruction descriptor flags.
- Improvements to the packet shuffler and checker.
- Updates to the handling of certain relocations.
- Better handling of duplex instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294226 91177308-0d34-0410-b5e6-96231b3b80d8

13 files changed, 164 insertions, 10 deletions

diff --git a/test/MC/Hexagon/common-redeclare.s b/test/MC/Hexagon/common-redeclare.s
new file mode 100644
index 00000000000..52b77992a87
--- /dev/null
+++ b/test/MC/Hexagon/common-redeclare.s
@@ -0,0 +1,6 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -t - | FileCheck %s
+
+# CHECK: 00000062 g       *COM*  00000008 quartet_table_isqrt
+
+.common quartet_table_isqrt, 98, 8
+.common quartet_table_isqrt, 98, 8
diff --git a/test/MC/Hexagon/dcfetch-symbol.s b/test/MC/Hexagon/dcfetch-symbol.s
new file mode 100644
index 00000000000..8309439a2aa
--- /dev/null
+++ b/test/MC/Hexagon/dcfetch-symbol.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=obj %s
+
+#CHECK: 9400c000 { dcfetch(r0 + #0) }
+
+junk:
+{
+  dcfetch(r0 + #junk)
+}
diff --git a/test/MC/Hexagon/dis-duplex-p0.s b/test/MC/Hexagon/dis-duplex-p0.s
index dc6a1260145..4ee518fa2a3 100644
--- a/test/MC/Hexagon/dis-duplex-p0.s
+++ b/test/MC/Hexagon/dis-duplex-p0.s
@@ -1,7 +1,10 @@
 // RUN: llvm-mc -arch=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
-// REQUIRES: asserts
-  .text
-// CHECK: { r7 = #-1; r7 = #-1 }
-  .long 0x3a373a27
-// CHECK: { if (!p0.new) r7 = #0; if (p0.new) r7 = #0 }
-  .long 0x3a573a47
+
+{ r7 = #-1
+  r6 = #-1 }
+// CHECK: { r7 = #-1; r6 = #-1 }
+
+{ p0 = r0
+  if (p0.new) r7 = #0
+  if (!p0.new) r7 = #0 }
+// CHECK: if (p0.new) r7 = #0; if (!p0.new) r7 = #0
diff --git a/test/MC/Hexagon/equ.s b/test/MC/Hexagon/equ.s
new file mode 100644
index 00000000000..fbf09edbbc1
--- /dev/null
+++ b/test/MC/Hexagon/equ.s
@@ -0,0 +1,9 @@
+# RUN: not llvm-mc -arch=hexagon %s 2> %t
+# RUN: FileCheck < %t %s
+
+.equ   a, 0
+.set   a, 1
+.equ   a, 2
+.equiv a, 3
+# CHECK: {{[Ee]}}rror: redefinition of 'a'
+
diff --git a/test/MC/Hexagon/extended_relocations.ll b/test/MC/Hexagon/extended_relocations.ll
new file mode 100644
index 00000000000..a16185c3994
--- /dev/null
+++ b/test/MC/Hexagon/extended_relocations.ll
@@ -0,0 +1,23 @@
+; RUN: llc -filetype=obj -march=hexagon %s -o - | llvm-objdump -r - | FileCheck %s
+
+; CHECK: RELOCATION RECORDS FOR [.rela.text]:
+; CHECK: 00000000 R_HEX_B22_PCREL printf
+; CHECK: 00000004 R_HEX_32_6_X .rodata.str1.1
+; CHECK: 00000008 R_HEX_6_X .rodata.str1.1
+
+target triple = "hexagon-unknown--elf"
+
+@.str = private unnamed_addr constant [10 x i8] c"cxfir.log\00", align 1
+
+declare i32 @printf(i8*, ...) #1
+
+; Function Attrs: nounwind
+define i32 @main() #0 {
+entry:
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i32 0, i32 0))
+  ret i32 0
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
diff --git a/test/MC/Hexagon/missing_label.s b/test/MC/Hexagon/missing_label.s
new file mode 100644
index 00000000000..80f69472029
--- /dev/null
+++ b/test/MC/Hexagon/missing_label.s
@@ -0,0 +1,8 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+#
+
+.I1:
+nop
+
+# CHECK: .I1:
+# CHECK:        nop
diff --git a/test/MC/Hexagon/non-relocatable.s b/test/MC/Hexagon/non-relocatable.s
new file mode 100644
index 00000000000..72a17901c62
--- /dev/null
+++ b/test/MC/Hexagon/non-relocatable.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=obj %s 2>%t; FileCheck %s <%t
+
+# Don't allow a symbolic operand for an insn that cannot take a
+# relocation.
+
+r7:6 = rol(r5:4,#r2)
+
+# This should produce an error
+#CHECK: error:
+
diff --git a/test/MC/Hexagon/not-over.s b/test/MC/Hexagon/not-over.s
new file mode 100644
index 00000000000..c31ce531230
--- /dev/null
+++ b/test/MC/Hexagon/not-over.s
@@ -0,0 +1,55 @@
+# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
+#
+
+# Check that proper packets are not wrongly flagged as invalid.
+
+1-3-4-f:
+	{
+	       r3 = memub(r2++#1)
+	       if (cmp.eq(r3.new,#0)) jump:nt .
+	       jumpr lr
+	       r4 = #4
+	}
+# CHECK-NOT: rror: invalid instruction packet
+
+1-3-f-f:
+        {
+                r3 = memub(r2++#1)
+                if (cmp.eq(r3.new,#0)) jump:nt .
+                r5 = #5
+                r4 = #4
+        }
+# CHECK-NOT: rror: invalid instruction packet
+
+# Special case of a fat packet that will slim when a compound is formed.
+3-3-8-c:
+   { LOOP0(3-3-8-c, R7)
+     P0 = CMP.GT(R7, #0)
+     IF (!P0.NEW) JUMP:NT .
+     R21:20 = MEMD(R0+#16)
+     R23:22 = MEMD(R0+#24)
+   }
+# CHECK-NOT: rror: invalid instruction packet
+
+1-f-f-f:
+        {
+                r3 = #3
+                if (cmp.eq(r3.new,#0)) jump:nt .
+                r5 = #5
+                r4 = #4
+        }
+# CHECK-NOT: rror: invalid instruction packet
+
+4:
+        jumpr lr
+# CHECK-NOT: rror: invalid instruction packet
+
+f-f-f-f:
+        {
+                r3 = #3
+                r2 = #2
+                r5 = #5
+                r4 = #4
+        }
+# CHECK-NOT: rror: invalid instruction packet
+
diff --git a/test/MC/Hexagon/not_found.s b/test/MC/Hexagon/not_found.s
new file mode 100644
index 00000000000..2403042792d
--- /dev/null
+++ b/test/MC/Hexagon/not_found.s
@@ -0,0 +1,4 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=asm junk123.s 2>%t ; FileCheck %s < %t
+#
+
+# CHECK: junk123.s: {{[N|n]}}o such file or directory
diff --git a/test/MC/Hexagon/offset.s b/test/MC/Hexagon/offset.s
new file mode 100644
index 00000000000..b079634814d
--- /dev/null
+++ b/test/MC/Hexagon/offset.s
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -t - | FileCheck %s
+#
+
+sym_a:
+.set sym_d, sym_a + 8
+# CHECK: 00000000         .text 00000000 sym_a
+# CHECK: 00000008         .text 00000000 sym_d
diff --git a/test/MC/Hexagon/operand-range.s b/test/MC/Hexagon/operand-range.s
new file mode 100644
index 00000000000..c38aab7060d
--- /dev/null
+++ b/test/MC/Hexagon/operand-range.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>&1 | FileCheck %s
+
+# Expect errors here, insn needs to be extended
+R1 = mpyi(R2, #-256)
+# CHECK: error:
+R3 = mpyi(R4, #256)
+# CHECK: error:
diff --git a/test/MC/Hexagon/reg_altnames.s b/test/MC/Hexagon/reg_altnames.s
new file mode 100644
index 00000000000..9c7f7e9b0bf
--- /dev/null
+++ b/test/MC/Hexagon/reg_altnames.s
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+
+# CHECK: 11 df 75 f1
+r17 = xor(r21, lr)
+
+# CHECK: 1d df 35 f3
+sp = sub(lr, r21)
+
+# CHECK: 15 c0 3e 71
+fp.l = #21
diff --git a/test/MC/Hexagon/relocations.s b/test/MC/Hexagon/relocations.s
index d52c37a66cc..4acc8084ae6 100644
--- a/test/MC/Hexagon/relocations.s
+++ b/test/MC/Hexagon/relocations.s
@@ -12,6 +12,14 @@ r_hex_b15_pcrel:
 r_hex_b7_pcrel:
 { loop1 (#undefined, #0) }
 
+# CHECK: R_HEX_LO16
+r_hex_lo16:
+{ r0.l = #lo(undefined) }
+
+# CHECK: R_HEX_HI16
+r_hex_hi16:
+{ r0.h = #hi(undefined) }
+
 # CHECK: R_HEX_32
 r_hex_32:
 .word undefined
@@ -68,10 +76,6 @@ r_hex_b22_pcrel_x:
 r_hex_b15_pcrel_x:
 { if (p0) jump ##undefined }
 
-# CHECK: R_HEX_B9_PCREL_X
-r_hex_b9_pcrel_x:
-{ r0 = #0 ; jump ##undefined }
-
 # CHECK: R_HEX_B7_PCREL_X
 r_hex_b7_pcrel_x:
 { loop1 (##undefined, #0) }