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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2017-09-18 14:17:57 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2017-09-18 14:17:57 +0000 |
| commit | 80ee0e02a2ad286f73559b380da660dbff86c6b4 (patch) | |
| tree | ca1c0f993348024e1eefae9aee8234eabf66ef50 /test/MC | |
| parent | 6ad4356f4dd70cae00ec397ad52f08f87cb6182b (diff) | |
| download | llvm-80ee0e02a2ad286f73559b380da660dbff86c6b4.tar.gz | |
[ARM] Fix for indexed dot product instruction descriptions
The indexed dot product instructions only accept the lower 16 D-registers as
the indexed register, but we were e.g. incorrectly accepting:
vudot.u8 d16,d16,d18[0]
Differential Revision: https://reviews.llvm.org/D37968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313531 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/ARM/armv8.2a-dotprod-error.s | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/test/MC/ARM/armv8.2a-dotprod-error.s b/test/MC/ARM/armv8.2a-dotprod-error.s index 424fa5a12c9..c8497c30a00 100644 --- a/test/MC/ARM/armv8.2a-dotprod-error.s +++ b/test/MC/ARM/armv8.2a-dotprod-error.s @@ -3,12 +3,34 @@ // RUN: not llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s +// Only indices 0 an 1 should be accepted: + vudot.u8 d0, d1, d2[2] vsdot.s8 d0, d1, d2[2] vudot.u8 q0, q1, d4[2] vsdot.s8 q0, q1, d4[2] // CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: vudot.u8 d0, d1, d2[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: vsdot.s8 d0, d1, d2[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: vudot.u8 q0, q1, d4[2] +// CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: vsdot.s8 q0, q1, d4[2] +// CHECK-ERROR: ^ + +// Only the lower 16 D-registers should be accepted: + +vudot.u8 q0, q1, d16[0] +vsdot.s8 q0, q1, d16[0] + // CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: vudot.u8 q0, q1, d16[0] +// CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: vsdot.s8 q0, q1, d16[0] +// CHECK-ERROR: ^ |