diff options
| -rw-r--r-- | lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 13 | ||||
| -rw-r--r-- | lib/Target/Hexagon/Hexagon.td | 1 | ||||
| -rw-r--r-- | lib/Target/Hexagon/HexagonAlias.td | 29 | ||||
| -rw-r--r-- | test/MC/Hexagon/v60-misc.s | 10 |
4 files changed, 53 insertions, 0 deletions
diff --git a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 3a80f487e8f..c54a6b26c69 100644 --- a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -1658,6 +1658,19 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, break; } + // Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)" + case Hexagon::HEXAGON_V6_vassignpair: { + MCOperand &MO = Inst.getOperand(1); + unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); + std::string R1 = v + llvm::utostr(RegPairNum + 1); + MO.setReg(MatchRegisterName(R1)); + // Add a new operand for the second register in the pair. + std::string R2 = v + llvm::utostr(RegPairNum); + Inst.addOperand(MCOperand::createReg(MatchRegisterName(R2))); + Inst.setOpcode(Hexagon::V6_vcombine); + break; + } + // Translate a "$Rx = CONST32(#imm)" to "$Rx = memw(gp+#LABEL) " case Hexagon::CONST32: case Hexagon::CONST32_Float_Real: diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index 602e27b932b..9e008566080 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -227,6 +227,7 @@ include "HexagonCallingConv.td" include "HexagonInstrInfo.td" include "HexagonIntrinsics.td" include "HexagonIntrinsicsDerived.td" +include "HexagonAlias.td" def HexagonInstrInfo : InstrInfo; diff --git a/lib/Target/Hexagon/HexagonAlias.td b/lib/Target/Hexagon/HexagonAlias.td new file mode 100644 index 00000000000..e14e5994cb4 --- /dev/null +++ b/lib/Target/Hexagon/HexagonAlias.td @@ -0,0 +1,29 @@ +//==- HexagonAlias.td - Hexagon Instruction Aliases ---------*- tablegen -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Hexagon Instruction Mappings +//===----------------------------------------------------------------------===// + +// V6_vassignp: Vector assign mapping. +let hasNewValue = 1, opNewValue = 0, isAsmParserOnly = 1 in +def HEXAGON_V6_vassignpair: CVI_VA_DV_Resource < + (outs VecDblRegs:$Vdd), + (ins VecDblRegs:$Vss), + "$Vdd = $Vss">; + +// maps Vd = #0 to Vd = vxor(Vd, Vd) +def : InstAlias<"$Vd = #0", + (V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>, + Requires<[HasV60T]>; + +// maps Vdd = #0 to Vdd = vsub(Vdd, Vdd) +def : InstAlias<"$Vdd = #0", + (V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>, + Requires<[HasV60T]>; diff --git a/test/MC/Hexagon/v60-misc.s b/test/MC/Hexagon/v60-misc.s new file mode 100644 index 00000000000..335f02983c0 --- /dev/null +++ b/test/MC/Hexagon/v60-misc.s @@ -0,0 +1,10 @@ +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -d - | FileCheck %s + +# CHECK: 1c2eceee { v14 = vxor(v14,{{ *}}v14) } +v14 = #0 + +# CHECK: 1c80c0a0 { v1:0.w = vsub(v1:0.w,v1:0.w) } +v1:0 = #0 + +# CHECK: 1f42c3e0 { v1:0 = vcombine(v3,v2) } +v1:0 = v3:2 |