diff options
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/inlineasm.ll | 9 |
2 files changed, 9 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 5b14ee873f8..ad865329ce3 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -12911,7 +12911,7 @@ RCPair ARMTargetLowering::getRegForInlineAsmConstraint( return RCPair(0U, &ARM::QPR_8RegClass); break; case 't': - if (VT == MVT::f32) + if (VT == MVT::f32 || VT == MVT::i32) return RCPair(0U, &ARM::SPRRegClass); break; } diff --git a/test/CodeGen/ARM/inlineasm.ll b/test/CodeGen/ARM/inlineasm.ll index 39962e08cdd..fdb8938884c 100644 --- a/test/CodeGen/ARM/inlineasm.ll +++ b/test/CodeGen/ARM/inlineasm.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null +; RUN: llc -mtriple=armv8-eabi -mattr=+neon %s -o - | FileCheck %s define i32 @test1(i32 %tmp54) { %tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 ) ; <i32> [#uses=1] @@ -9,3 +9,10 @@ define void @test2() { tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 ) ret void } + +define float @t-constraint-int(i32 %i) { + ; CHECK-LABEL: t-constraint-int + ; CHECK: vcvt.f32.s32 {{s[0-9]+}}, {{s[0-9]+}} + %ret = call float asm "vcvt.f32.s32 $0, $1\0A", "=t,t"(i32 %i) + ret float %ret +} |