diff options
Diffstat (limited to 'lib/Target/AArch64/AArch64FrameLowering.cpp')
-rw-r--r-- | lib/Target/AArch64/AArch64FrameLowering.cpp | 31 |
1 files changed, 25 insertions, 6 deletions
diff --git a/lib/Target/AArch64/AArch64FrameLowering.cpp b/lib/Target/AArch64/AArch64FrameLowering.cpp index 9c85001481d..422c91fa704 100644 --- a/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -585,10 +585,12 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec( const DebugLoc &DL, const TargetInstrInfo *TII, int CSStackSizeInc, bool NeedsWinCFI, bool InProlog = true) { // Ignore instructions that do not operate on SP, i.e. shadow call stack - // instructions. + // instructions and associated CFI instruction. while (MBBI->getOpcode() == AArch64::STRXpost || - MBBI->getOpcode() == AArch64::LDRXpre) { - assert(MBBI->getOperand(0).getReg() != AArch64::SP); + MBBI->getOpcode() == AArch64::LDRXpre || + MBBI->getOpcode() == AArch64::CFI_INSTRUCTION) { + if (MBBI->getOpcode() != AArch64::CFI_INSTRUCTION) + assert(MBBI->getOperand(0).getReg() != AArch64::SP); ++MBBI; } unsigned NewOpc; @@ -685,9 +687,11 @@ static void fixupCalleeSaveRestoreStackOffset(MachineInstr &MI, unsigned Opc = MI.getOpcode(); // Ignore instructions that do not operate on SP, i.e. shadow call stack - // instructions. - if (Opc == AArch64::STRXpost || Opc == AArch64::LDRXpre) { - assert(MI.getOperand(0).getReg() != AArch64::SP); + // instructions and associated CFI instruction. + if (Opc == AArch64::STRXpost || Opc == AArch64::LDRXpre || + Opc == AArch64::CFI_INSTRUCTION) { + if (Opc != AArch64::CFI_INSTRUCTION) + assert(MI.getOperand(0).getReg() != AArch64::SP); return; } @@ -1675,6 +1679,21 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( BuildMI(MBB, MI, DL, TII.get(AArch64::SEH_Nop)) .setMIFlag(MachineInstr::FrameSetup); + // Emit a CFI instruction that causes 8 to be subtracted from the value of + // x18 when unwinding past this frame. + static const char CFIInst[] = { + dwarf::DW_CFA_val_expression, + 18, // register + 2, // length + static_cast<char>(dwarf::DW_OP_breg18), + static_cast<char>(-8) & 0x7f, // addend (sleb128) + }; + unsigned CFIIndex = + MF.addFrameInst(MCCFIInstruction::createEscape(nullptr, CFIInst)); + BuildMI(MBB, MI, DL, TII.get(AArch64::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex) + .setMIFlag(MachineInstr::FrameSetup); + // This instruction also makes x18 live-in to the entry block. MBB.addLiveIn(AArch64::X18); } |