diff options
Diffstat (limited to 'utils')
| -rw-r--r-- | utils/TableGen/RegisterInfoEmitter.cpp | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 5b2659d64ef..b4a5fff5d19 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -868,8 +868,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, // Compute the corresponding sub-register indexes. SubRegIdxVec &SRIs = SubRegIdxLists[i]; - for (unsigned j = 0, je = SR.size(); j != je; ++j) - SRIs.push_back(Reg.getSubRegIndex(SR[j])); + for (const CodeGenRegister *S : SR) + SRIs.push_back(Reg.getSubRegIndex(S)); SubRegIdxSeqs.add(SRIs); // Super-registers are already computed. @@ -1007,8 +1007,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, OS << " // " << Name << " Register Class...\n" << " const MCPhysReg " << Name << "[] = {\n "; - for (unsigned i = 0, e = Order.size(); i != e; ++i) { - Record *Reg = Order[i]; + for (Record *Reg : Order) { OS << getQualifiedName(Reg) << ", "; } OS << "\n };\n\n"; @@ -1017,8 +1016,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, << " const uint8_t " << Name << "Bits[] = {\n "; BitVectorEmitter BVE; - for (unsigned i = 0, e = Order.size(); i != e; ++i) { - Record *Reg = Order[i]; + for (Record *Reg : Order) { BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); } BVE.print(OS); |