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2017-10-03[ARM] Use table-gen'd assembly operand diags in ARM asm parserOliver Stannard
This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314804 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-03[ARM, Asm] Use correct source location for register tokensOliver Stannard
tryParseRegister advances the lexer, so we need to take copies of the start and end locations of the register operand before calling it. Previously, the caret in the diagnostic pointer to the comma after the r0 operand in the test, rather than the start of the operand. Differential revision: https://reviews.llvm.org/D31537 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314799 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-03[WebAssembly] MC: Support for init_array and fini_arraySam Clegg
Differential Revision: https://reviews.llvm.org/D37757 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314783 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-03[ARM] Use new assembler diags for ARMOliver Stannard
This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314779 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-02[X86] Run dos2unix on two disassembler tests.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314727 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-02CodeView symbol dumper: use symbolic names for registersHans Wennborg
https://reviews.llvm.org/D38469 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314690 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-02[AsmParser] Support GAS's .print directiveCoby Tayree
Differential Revision: https://reviews.llvm.org/D38448 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314674 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-01[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMemCraig Topper
Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314639 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-29[WebAssembly] Allow each data segment to specify its own alignmentSam Clegg
Also, add a flags field as we will almost certainly be needing that soon too. Differential Revision: https://reviews.llvm.org/D38296 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314534 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-29AMDGPU: fix bad test exposed by r314522Nicolai Haehnle
The test attempts to use -1 as carry-in for v_addc_*. Before writing r314522, I did actually test this on real hardware, and found that it doesn't work. So r314522 is correct in restricting the carry-in operand: just remove those tests to make things pass again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314530 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-29[ARM] v8.3-a complex number supportSam Parker
New instructions are added to AArch32 and AArch64 to aid floating-point multiplication and addition of complex numbers, where the complex numbers are packed in a vector register as a pair of elements. The Imaginary part of the number is placed in the more significant element, and the Real part of the number is placed in the less significant element. This patch adds assembler for the ARM target. Differential Revision: https://reviews.llvm.org/D36789 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314511 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-29[mips] Add test cases for dext/dins family of instructionsAleksandar Beserminji
Add missing test cases for dext, dextm, dextu, dins, dinsm and dinsu instructions. Differential Revision: https://reviews.llvm.org/D37741 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314503 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-28[mips] Remove codegen support for branch likely instructions.Simon Dardis
This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314421 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-28[x86][AsmParser] Allow some more MS size directivesCoby Tayree
MS allows the following size directives: float/double and long as synonymous to dword/qword and dword, respectively. Differential Revision: https://reviews.llvm.org/D37190 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314410 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-28[RISCV] Add common fixups and relocationsAlex Bradbury
%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314389 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-28bpf: add new insns for bswap_to_le and negationYonghong Song
This patch adds new insn, "reg = be16/be32/be64 reg", for bswap to little endian for big-endian target (bpfeb). It also adds new insn for negation "reg = -reg". Currently, for source code, e.g., b = -a LLVM still prefers to generate: b = 0 - a But "reg = -reg" format can be used in assembly code. Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314376 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-27[X86][AsmParser] fix PR32035Coby Tayree
Differential Revision: https://reviews.llvm.org/D37473 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314295 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-26[WebAssembly] Model weakly defined symbols as wasm exportsSam Clegg
Previously these were being included as both imports and exports, with the import being satisfied by the export (or some strong symbol) at runtime. However proved unnecessary and actually complicated linking as it meant there was not a 1-to-1 mapping between a wasm function /global index and a linker symbol. Differential Revision: https://reviews.llvm.org/D38246 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314245 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-26[mips] Use llvm-dwarfdump to simplify the test. NFCSimon Atanasyan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314222 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-25[X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when ↵Konstantin Belochapka
x86-asm-syntax=intel (PR34617). Fix for incorrect code generation when x86-asm-syntax=intel. Differential Revision: https://reviews.llvm.org/D37945 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314140 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-22[X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038).Konstantin Belochapka
Fixed suboptimal encoding of instruction memory operand when assembler is used to select 32 bit fixup rather than 8 bit immediate for encoding memory offset value. Differential Revision: https://reviews.llvm.org/D38117 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314044 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-22[ARM] Fix assembly and disassembly for VMRS/VMSRAndre Vieira
Reviewed by: t.p.northover Differential Revision: https://reviews.llvm.org/D36306 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313979 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-22bpf: initial 32-bit ALU encoding support in assemblerYonghong Song
This patch adds instruction patterns for operations in BPF_ALU. After this, assembler could recognize some 32-bit ALU statement. For example, those listed int the unit test file. Separate MOV patterns are unnecessary as MOV is ALU operation that could reuse ALU encoding infrastructure, this patch removed those redundant patterns. Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313961 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-21[dwarfdump] Add verbose output for .debug-line sectionJonas Devlieghere
This patch adds dumping of line table instructions as well as the final state at each specified pc value in verbose mode. This is essentially the same as the default in Darwin's dwarfdump. Dumping the actual line table opcodes can be particularly useful for something like debugging a bad `.debug_line` section. Differential revision: https://reviews.llvm.org/D37971 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313910 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-21[mips] Implement generation of relocations "chains" used by N32 ABISimon Atanasyan
In case of using a "nested" relocation expressions like this `%hi(%neg(%gp_rel()))`, N32 ABI requires generation of three consecutive relocations. That differs from the N64 ABI case where all relocations are packed into the single relocation record. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313879 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-21[mips] Fix relocation record format and ELF header for N32 ABISimon Atanasyan
The N32 ABI uses RELA relocation format, do not use 3-in-1 relocation's encoding, and uses ELFCLASS32. This change passes the `IsN32` flag to the `MCAsmBackend` to distinguish usage of N32 ABI. We still do not handle some cases like providing the `-target-abi=o32` command line option with the `mips64` target triple. That's why elf_header.s contains some "FIXME" strings. This case will be fixed in a separate patch. Differential revision: https://reviews.llvm.org/D37960 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313873 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20[WebAssembly] Weak symbols should be defined in SF_GlobalSam Clegg
Summary: This manifested itself in lld since it meant that weak symbols were not appearing in archive symbol tables. Subscribers: jfb, dschuff, jgravelle-google, aheejin Differential Revision: https://reviews.llvm.org/D38111 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313838 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20[WebAssembly] Add support for local symbol bindingsSam Clegg
Differential Revision: https://reviews.llvm.org/D38096 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313817 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20[mips] Fix calculation of a branch instruction offset to escape left shift ↵Simon Atanasyan
of negative value git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313815 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20AMDGPU: Fix encoding of op_sel for mad_mix* opcodesMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313797 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20Reland "[WebAssembly] Add support for naming wasm data segments"Sam Clegg
Add adds support for naming data segments. This is useful useful linkers so that they can merge similar sections. Differential Revision: https://reviews.llvm.org/D37886 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313795 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20[mips] Add a valid test case to check the reason of the recent build-bot ↵Simon Atanasyan
failure. NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313761 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20'into' instruction should not be decoded as a valid instr in 64-bit modeAndrew V. Tischenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313735 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20Reverting due to Green Dragon bot failure.Mike Edwards
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/42594/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313706 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-19[WebAssembly] Add support for naming wasm data segmentsSam Clegg
Add adds support for naming data segments. This is useful useful linkers so that they can merge similar sections. Differential Revision: https://reviews.llvm.org/D37886 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313692 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-19[ARM] Relax 'cpsie'/'cpsid' flag parsing.Jonathan Roelofs
The ARM docs suggest in examples that the flags can have either case, and there are applications in the wild that (libopencm3, for example) that expect to be able to use the uppercase spelling. https://reviews.llvm.org/D37953 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313680 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-19Re-land "Fix Bug 30978 by emitting cv file checksums."Reid Kleckner
This reverts r313431 and brings back r313374 with a fix to write checksums as binary data and not ASCII hex strings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313657 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-19[Power9] Add missing Power9 instructions.Tony Jiang
The following 8 instructions are implemented in this patch. addpcis(subpcis, lnia), darn, maddhd, maddhdu, maddld, setb git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313636 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-18[AArch64] Add V8_2aOps feature to Cortex-A55 and 75Sam Parker
Add the missing hardware features the ProcA55 and ProcA75 feature. These are already enabled via the target parser, but I had missed them in the backend. Differential Revision: https://reviews.llvm.org/D37974 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313535 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-18[ARM] Fix for indexed dot product instruction descriptionsSjoerd Meijer
The indexed dot product instructions only accept the lower 16 D-registers as the indexed register, but we were e.g. incorrectly accepting: vudot.u8 d16,d16,d18[0] Differential Revision: https://reviews.llvm.org/D37968 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313531 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-18[dwarfdump] Make .eh_frame an alias for .debug_frameJonas Devlieghere
This patch makes the `.eh_frame` extension an alias for `.debug_frame`. Up till now it was only possible to dump the section using objdump, but not with dwarfdump. Since the two are essentially interchangeable, we dump whichever of the two is present. As a workaround, this patch also adds parsing for 3 currently unimplemented CFA instructions: `DW_CFA_def_cfa_expression`, `DW_CFA_expression`, and `DW_CFA_val_expression`. Because I lack the required knowledge, I just parse the fields without actually creating the instructions. Finally, this also fixes the typo in the `.debug_frame` section name which incorrectly contained a trailing `s`. Differential revision: https://reviews.llvm.org/D37852 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313530 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-17[RISCV] Add support for disassemblyAlex Bradbury
This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s has been updated appropriately. Differential Revision: https://reviews.llvm.org/D23567 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313486 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-17[RISCV] Add support for all RV32I instructionsAlex Bradbury
This patch supports all RV32I instructions as described in the RISC-V manual. A future patch will add support for pseudoinstructions and other instruction expansions (e.g. 0-arg fence -> fence iorw, iorw). Differential Revision: https://reviews.llvm.org/D23566 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313485 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-16Revert "Fix Bug 30978 by emitting cv file checksums."Eric Beckmann
This reverts commit 6389e7aa724ea7671d096f4770f016c3d86b0d54. There is a bug in this implementation where the string value of the checksum is outputted, instead of the actual hex bytes. Therefore the checksum is incorrect, and this prevent pdbs from being loaded by visual studio. Revert this until the checksum is emitted correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313431 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-15[WebAssembly] MC: Create wasm data segments based on MCSectionsSam Clegg
This means that we can honor -fdata-sections rather than always creating a segment for each symbol. It also allows for a followup change to add .init_array and friends. Differential Revision: https://reviews.llvm.org/D37876 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313395 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-15[WebAssembly] MC: Fix crash in getProvitionalValue on weak referencesSam Clegg
- Create helper function for resolving weak references. - Add test that preproduces the crash. Differential Revision: https://reviews.llvm.org/D37916 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313381 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-15Fix Bug 30978 by emitting cv file checksums.Eric Beckmann
Summary: The checksums had already been placed in the IR, this patch allows MCCodeView to actually write it out to an MCStreamer. Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37157 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313374 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-14[WebAssembly] Use a separate wasm data segment for each global symbolSam Clegg
This is stepping stone towards honoring -fdata-sections and letting the assembler decide how many wasm data segments to create. Differential Revision: https://reviews.llvm.org/D37834 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313313 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-14[bpf] Fix test to always use little endian.Simon Dardis
r313055 broke the big endian buildbots as the CHECK lines contained little endian data but -triple bpf uses the host endian. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313281 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-14[mips] Implement the 'dext' aliases and it's disassembly alias.Simon Dardis
The other members of the dext family of instructions (dextm, dextu) are traditionally handled by the assembler selecting the right variant of 'dext' depending on the values of the position and size operands. When these instructions are disassembled, rather than reporting the actual instruction, an equivalent aliased form of 'dext' is generated and is reported. This is to mimic the behaviour of binutils. Reviewers: slthakur, nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D34887 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313276 91177308-0d34-0410-b5e6-96231b3b80d8
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