diff options
| author | Andrei Homescu <ahomescu@google.com> | 2024-02-16 03:31:51 +0000 |
|---|---|---|
| committer | Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> | 2024-02-16 03:31:51 +0000 |
| commit | 0df18191b3912a43c379d35387502733d03ba919 (patch) | |
| tree | aeb35213dd29bc2636690ea96b703ac6b3b4ab42 | |
| parent | 14b21bb9ec9edc2a59846163dcb4bb0c93d5bcf7 (diff) | |
| parent | 425f3fc0068315ed13867b4afb402056d9f8af12 (diff) | |
| download | trusted-firmware-a-0df18191b3912a43c379d35387502733d03ba919.tar.gz | |
Merge Trusted Firmware-A v2.8 release am: 425f3fc006
Original change: https://android-review.googlesource.com/c/trusty/external/trusted-firmware-a/+/2628527
Change-Id: I4f1ba497032271b727c1b027d1af87d7f6014c47
Signed-off-by: Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>
870 files changed, 52953 insertions, 13355 deletions
diff --git a/.gitignore b/.gitignore index b005fab38..1f4efb65a 100644 --- a/.gitignore +++ b/.gitignore @@ -43,3 +43,9 @@ tags # Node.js node_modules/ + +# common python virtual environment directories +.env/ +env/ +.venv/ +venv/ @@ -0,0 +1 @@ +v16.17.1 @@ -8,7 +8,8 @@ # Trusted Firmware Version # VERSION_MAJOR := 2 -VERSION_MINOR := 7 +VERSION_MINOR := 8 +VERSION := ${VERSION_MAJOR}.${VERSION_MINOR} # Default goal is build all images .DEFAULT_GOAL := all @@ -58,6 +59,7 @@ LIB_DIRS_TO_CHECK := $(sort $(filter-out \ lib/compiler-rt \ lib/libfdt% \ lib/libc, \ + lib/zlib \ $(wildcard lib/*))) ROOT_DIRS_TO_CHECK := $(sort $(filter-out \ lib \ @@ -147,7 +149,10 @@ endif CTX_INCLUDE_EL2_REGS := 1 CTX_INCLUDE_AARCH32_REGS := 0 ARM_ARCH_MAJOR := 8 -ARM_ARCH_MINOR := 6 +ARM_ARCH_MINOR := 5 +ENABLE_FEAT_ECV = 1 +ENABLE_FEAT_FGT = 1 + endif # USE_SPINLOCK_CAS requires AArch64 build @@ -273,7 +278,7 @@ ifneq ($(findstring clang,$(notdir $(CC))),) TF_CFLAGS_aarch64 := -target aarch64-arm-none-eabi $(march64-directive) LD := $(LINKER) else - TF_CFLAGS_aarch32 := $(target32-directive) $(march32-directive) + TF_CFLAGS_aarch32 = $(target32-directive) $(march32-directive) TF_CFLAGS_aarch64 := -target aarch64-elf $(march64-directive) LD := $(shell $(CC) --print-prog-name ld.lld) @@ -322,7 +327,7 @@ endif ifeq (${BUILD_STRING},) BUILD_STRING := $(shell git describe --always --dirty --tags 2> /dev/null) endif -VERSION_STRING := v${VERSION_MAJOR}.${VERSION_MINOR}(${BUILD_TYPE}):${BUILD_STRING} +VERSION_STRING := v${VERSION}(${BUILD_TYPE}):${BUILD_STRING} ifeq (${AARCH32_INSTRUCTION_SET},A32) TF_CFLAGS_aarch32 += -marm @@ -399,6 +404,8 @@ TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ -ffreestanding -fno-builtin -fno-common \ -Os -std=gnu99 +$(eval $(call add_define,SVE_VECTOR_LEN)) + ifeq (${SANITIZE_UB},on) TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover endif @@ -600,6 +607,9 @@ endif PIE_FOUND := $(findstring --enable-default-pie,${GCC_V_OUTPUT}) ifneq ($(PIE_FOUND),) TF_CFLAGS += -fno-PIE +ifneq ($(findstring gcc,$(notdir $(LD))),) + TF_LDFLAGS += -no-pie +endif endif ifneq ($(findstring gcc,$(notdir $(LD))),) @@ -707,8 +717,8 @@ endif # For RAS_EXTENSION, require that EAs are handled in EL3 first ifeq ($(RAS_EXTENSION),1) - ifneq ($(HANDLE_EA_EL3_FIRST),1) - $(error For RAS_EXTENSION, HANDLE_EA_EL3_FIRST must also be 1) + ifneq ($(HANDLE_EA_EL3_FIRST_NS),1) + $(error For RAS_EXTENSION, HANDLE_EA_EL3_FIRST_NS must also be 1) endif endif @@ -726,7 +736,17 @@ ifeq ($(DYN_DISABLE_AUTH), 1) endif endif -ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT}),) +ifeq ($(MEASURED_BOOT)-$(TRUSTED_BOARD_BOOT),1-1) +# Support authentication verification and hash calculation + CRYPTO_SUPPORT := 3 +else ifeq ($(DRTM_SUPPORT)-$(TRUSTED_BOARD_BOOT),1-1) +# Support authentication verification and hash calculation + CRYPTO_SUPPORT := 3 +else ifneq ($(filter 1,${MEASURED_BOOT} ${DRTM_SUPPORT}),) +# Support hash calculation only + CRYPTO_SUPPORT := 2 +else ifeq (${TRUSTED_BOARD_BOOT},1) +# Support authentication verification only CRYPTO_SUPPORT := 1 else CRYPTO_SUPPORT := 0 @@ -790,11 +810,15 @@ ifeq (${ARCH},aarch32) $(error "ENABLE_SVE_FOR_NS cannot be used with ARCH=aarch32") endif - # BRBE is not supported in Aarch32 + # BRBE is not supported in AArch32 ifeq (${ENABLE_BRBE_FOR_NS},1) $(error "ENABLE_BRBE_FOR_NS cannot be used with ARCH=aarch32") endif + # FEAT_RNG_TRAP is not supported in AArch32 + ifeq (${ENABLE_FEAT_RNG_TRAP},1) + $(error "ENABLE_FEAT_RNG_TRAP cannot be used with ARCH=aarch32") + endif endif # Ensure ENABLE_RME is not used with SME @@ -834,6 +858,12 @@ ifeq ($(DRTM_SUPPORT),1) $(info DRTM_SUPPORT is an experimental feature) endif +ifeq (${ENABLE_RME},1) + ifneq (${SEPARATE_CODE_AND_RODATA},1) + $(error `ENABLE_RME=1` requires `SEPARATE_CODE_AND_RODATA=1`) + endif +endif + ################################################################################ # Process platform overrideable behaviour ################################################################################ @@ -1005,7 +1035,7 @@ $(eval $(call assert_booleans,\ FAULT_INJECTION_SUPPORT \ GENERATE_COT \ GICV2_G0_FOR_EL3 \ - HANDLE_EA_EL3_FIRST \ + HANDLE_EA_EL3_FIRST_NS \ HW_ASSISTED_COHERENCY \ INVERTED_MEMMAP \ MEASURED_BOOT \ @@ -1027,7 +1057,6 @@ $(eval $(call assert_booleans,\ SPMC_AT_EL3 \ SPMD_SPM_AT_SEL2 \ TRUSTED_BOARD_BOOT \ - CRYPTO_SUPPORT \ USE_COHERENT_MEM \ USE_DEBUGFS \ ARM_IO_IN_DTB \ @@ -1043,17 +1072,17 @@ $(eval $(call assert_booleans,\ ENCRYPT_BL31 \ ENCRYPT_BL32 \ ERRATA_SPECULATIVE_AT \ - RAS_TRAP_LOWER_EL_ERR_ACCESS \ + RAS_TRAP_NS_ERR_REC_ACCESS \ COT_DESC_IN_DTB \ USE_SP804_TIMER \ PSA_FWU_SUPPORT \ - ENABLE_BRBE_FOR_NS \ - ENABLE_TRBE_FOR_NS \ ENABLE_SYS_REG_TRACE_FOR_NS \ ENABLE_MPMM \ ENABLE_MPMM_FCONF \ SIMICS_BUILD \ FEATURE_DETECTION \ + TRNG_SUPPORT \ + CONDITIONAL_CMO \ ))) $(eval $(call assert_numerics,\ @@ -1064,6 +1093,9 @@ $(eval $(call assert_numerics,\ CTX_INCLUDE_PAUTH_REGS \ CTX_INCLUDE_MTE_REGS \ CTX_INCLUDE_NEVE_REGS \ + CRYPTO_SUPPORT \ + ENABLE_BRBE_FOR_NS \ + ENABLE_TRBE_FOR_NS \ ENABLE_BTI \ ENABLE_PAUTH \ ENABLE_FEAT_AMUv1 \ @@ -1075,6 +1107,7 @@ $(eval $(call assert_numerics,\ ENABLE_FEAT_HCX \ ENABLE_FEAT_PAN \ ENABLE_FEAT_RNG \ + ENABLE_FEAT_RNG_TRAP \ ENABLE_FEAT_SB \ ENABLE_FEAT_SEL2 \ ENABLE_FEAT_VHE \ @@ -1087,6 +1120,7 @@ $(eval $(call assert_numerics,\ RAS_EXTENSION \ TWED_DELAY \ ENABLE_FEAT_TWED \ + SVE_VECTOR_LEN \ ))) ifdef KEY_SIZE @@ -1142,7 +1176,7 @@ $(eval $(call add_defines,\ ERROR_DEPRECATED \ FAULT_INJECTION_SUPPORT \ GICV2_G0_FOR_EL3 \ - HANDLE_EA_EL3_FIRST \ + HANDLE_EA_EL3_FIRST_NS \ HW_ASSISTED_COHERENCY \ LOG_LEVEL \ MEASURED_BOOT \ @@ -1181,10 +1215,11 @@ $(eval $(call add_defines,\ BL2_INV_DCACHE \ USE_SPINLOCK_CAS \ ERRATA_SPECULATIVE_AT \ - RAS_TRAP_LOWER_EL_ERR_ACCESS \ + RAS_TRAP_NS_ERR_REC_ACCESS \ COT_DESC_IN_DTB \ USE_SP804_TIMER \ ENABLE_FEAT_RNG \ + ENABLE_FEAT_RNG_TRAP \ ENABLE_FEAT_SB \ ENABLE_FEAT_DIT \ NR_OF_FW_BANKS \ @@ -1209,6 +1244,7 @@ $(eval $(call add_defines,\ FEATURE_DETECTION \ TWED_DELAY \ ENABLE_FEAT_TWED \ + CONDITIONAL_CMO \ ))) ifeq (${SANITIZE_UB},trap) @@ -1436,7 +1472,7 @@ checkpatch: locate-checkpatch certtool: ${CRTTOOL} ${CRTTOOL}: FORCE - ${Q}${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} COT=${COT} OPENSSL_DIR=${OPENSSL_DIR} CRTTOOL=${CRTTOOL} --no-print-directory -C ${CRTTOOLPATH} + ${Q}${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} COT=${COT} OPENSSL_DIR=${OPENSSL_DIR} CRTTOOL=${CRTTOOL} DEBUG=${DEBUG} V=${V} --no-print-directory -C ${CRTTOOLPATH} all @${ECHO_BLANK_LINE} @echo "Built $@ successfully" @${ECHO_BLANK_LINE} @@ -1481,7 +1517,7 @@ fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME} ${FIPTOOL}: FORCE ifdef UNIX_MK - ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} --no-print-directory -C ${FIPTOOLPATH} + ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} V=${V} --no-print-directory -C ${FIPTOOLPATH} all else # Clear the MAKEFLAGS as we do not want # to pass the gnumake flags to nmake. @@ -1502,7 +1538,7 @@ doc: enctool: ${ENCTOOL} ${ENCTOOL}: FORCE - ${Q}${MAKE} PLAT=${PLAT} BUILD_INFO=0 OPENSSL_DIR=${OPENSSL_DIR} ENCTOOL=${ENCTOOL} --no-print-directory -C ${ENCTOOLPATH} + ${Q}${MAKE} PLAT=${PLAT} BUILD_INFO=0 OPENSSL_DIR=${OPENSSL_DIR} ENCTOOL=${ENCTOOL} DEBUG=${DEBUG} V=${V} --no-print-directory -C ${ENCTOOLPATH} all @${ECHO_BLANK_LINE} @echo "Built $@ successfully" @${ECHO_BLANK_LINE} diff --git a/bl1/aarch32/bl1_entrypoint.S b/bl1/aarch32/bl1_entrypoint.S index 94dfd3738..b22015eb9 100644 --- a/bl1/aarch32/bl1_entrypoint.S +++ b/bl1/aarch32/bl1_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,8 +23,8 @@ vector_base bl1_vector_table b bl1_entrypoint b report_exception /* Undef */ b bl1_aarch32_smc_handler /* SMC call */ - b report_exception /* Prefetch abort */ - b report_exception /* Data abort */ + b report_prefetch_abort /* Prefetch abort */ + b report_data_abort /* Data abort */ b report_exception /* Reserved */ b report_exception /* IRQ */ b report_exception /* FIQ */ diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index bc23828e4..c4ec5fe25 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -38,16 +38,16 @@ SECTIONS *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; - } >ROM + } >ROM - /* .ARM.extab and .ARM.exidx are only added because Clang need them */ - .ARM.extab . : { + /* .ARM.extab and .ARM.exidx are only added because Clang need them */ + .ARM.extab . : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } >ROM + } >ROM - .ARM.exidx . : { + .ARM.exidx . : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } >ROM + } >ROM .rodata . : { __RODATA_START__ = .; diff --git a/bl2/aarch32/bl2_el3_exceptions.S b/bl2/aarch32/bl2_el3_exceptions.S index 087b6656d..eaa258261 100644 --- a/bl2/aarch32/bl2_el3_exceptions.S +++ b/bl2/aarch32/bl2_el3_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,8 +14,8 @@ vector_base bl2_vector_table b bl2_entrypoint b report_exception /* Undef */ b report_exception /* SVC call */ - b report_exception /* Prefetch abort */ - b report_exception /* Data abort */ + b report_prefetch_abort /* Prefetch abort */ + b report_data_abort /* Data abort */ b report_exception /* Reserved */ b report_exception /* IRQ */ b report_exception /* FIQ */ diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S index 6e8e2c1e1..678d9c2f0 100644 --- a/bl2/aarch32/bl2_entrypoint.S +++ b/bl2/aarch32/bl2_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,8 +16,8 @@ vector_base bl2_vector_table b bl2_entrypoint b report_exception /* Undef */ b report_exception /* SVC call */ - b report_exception /* Prefetch abort */ - b report_exception /* Data abort */ + b report_prefetch_abort /* Prefetch abort */ + b report_data_abort /* Data abort */ b report_exception /* Reserved */ b report_exception /* IRQ */ b report_exception /* FIQ */ diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index d332ec069..80cf7db97 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -34,16 +34,16 @@ SECTIONS *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; - } >RAM + } >RAM - /* .ARM.extab and .ARM.exidx are only added because Clang need them */ - .ARM.extab . : { + /* .ARM.extab and .ARM.exidx are only added because Clang need them */ + .ARM.extab . : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } >RAM + } >RAM - .ARM.exidx . : { + .ARM.exidx . : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } >RAM + } >RAM .rodata . : { __RODATA_START__ = .; diff --git a/bl2u/aarch32/bl2u_entrypoint.S b/bl2u/aarch32/bl2u_entrypoint.S index e4dd03dec..106378915 100644 --- a/bl2u/aarch32/bl2u_entrypoint.S +++ b/bl2u/aarch32/bl2u_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,8 +16,8 @@ vector_base bl2u_vector_table b bl2u_entrypoint b report_exception /* Undef */ b report_exception /* SVC call */ - b report_exception /* Prefetch abort */ - b report_exception /* Data abort */ + b report_prefetch_abort /* Prefetch abort */ + b report_data_abort /* Data abort */ b report_exception /* Reserved */ b report_exception /* IRQ */ b report_exception /* FIQ */ diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S index fa6ede823..dbb32344d 100644 --- a/bl31/aarch64/ea_delegate.S +++ b/bl31/aarch64/ea_delegate.S @@ -1,5 +1,6 @@ /* * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -84,10 +85,6 @@ func enter_lower_el_sync_ea b 2f 1: - /* Test for EA bit in the instruction syndrome */ - mrs x30, esr_el3 - tbz x30, #ESR_ISS_EABORT_EA_BIT, 3f - /* * Save general purpose and ARMv8.3-PAuth registers (if enabled). * If Secure Cycle Counter is not disabled in MDCR_EL3 when @@ -114,7 +111,6 @@ func enter_lower_el_sync_ea ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] -3: /* Synchronous exceptions other than the above are assumed to be EA */ ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] no_ret report_unhandled_exception @@ -199,23 +195,30 @@ endfunc delegate_sync_ea */ func delegate_async_ea #if RAS_EXTENSION + /* Check Exception Class to ensure SError, as this function should + * only be invoked for SError. If that is not the case, which implies + * either an HW error or programming error, panic. + */ + ubfx x2, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x2, EC_SERROR + b.ne do_panic /* * Check for Implementation Defined Syndrome. If so, skip checking * Uncontainable error type from the syndrome as the format is unknown. */ tbnz x1, #SERROR_IDS_BIT, 1f + /* AET only valid when DFSC is 0x11 */ + ubfx x2, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH + cmp x2, #DFSC_SERROR + b.ne 1f + /* * Check for Uncontainable error type. If so, route to the platform * fatal error handler rather than the generic EA one. */ - ubfx x2, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH - cmp x2, #ERROR_STATUS_UET_UC - b.ne 1f - - /* Check DFSC for SError type */ - ubfx x3, x1, #EABORT_DFSC_SHIFT, #EABORT_DFSC_WIDTH - cmp x3, #DFSC_SERROR + ubfx x3, x1, #EABORT_AET_SHIFT, #EABORT_AET_WIDTH + cmp x3, #ERROR_STATUS_UET_UC b.ne 1f no_ret plat_handle_uncontainable_ea diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index bf5bd8d8d..028355396 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -512,7 +512,7 @@ smc_handler64: /* * Shift copied SCR_EL3.NSE bit by 5 to create space for - * SCR_EL3.NS bit. Bit 5 of the flag correspondes to + * SCR_EL3.NS bit. Bit 5 of the flag corresponds to * the SCR_EL3.NSE bit. */ lsl x7, x7, #5 @@ -521,6 +521,16 @@ smc_handler64: /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ bfi x7, x18, #0, #1 + /* + * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID + * passed through x0. Copy the SVE hint bit to flags and mask the + * bit in smc_fid passed to the standard service dispatcher. + * A service/dispatcher can retrieve the SVE hint bit state from + * flags using the appropriate helper. + */ + bfi x7, x0, #FUNCID_SVE_HINT_SHIFT, #FUNCID_SVE_HINT_MASK + bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) + mov sp, x12 /* Get the unique owning entity number */ diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 8a1573ab6..309e7526c 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -47,6 +47,10 @@ SECTIONS __RODATA_START__ = .; *(SORT_BY_ALIGNMENT(.rodata*)) +#if PLAT_EXTRA_RODATA_INCLUDES +#include <plat.ld.rodata.inc> +#endif + RODATA_COMMON /* Place pubsub sections for events */ @@ -186,10 +190,10 @@ SECTIONS __RW_END__ = .; __BL31_END__ = .; + ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") +#endif + /DISCARD/ : { *(.dynsym .dynstr .hash .gnu.hash) } - - ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") -#endif } diff --git a/bl31/bl31.mk b/bl31/bl31.mk index 3964469eb..4c93a55ad 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk @@ -147,6 +147,15 @@ ifeq ($(FEATURE_DETECTION),1) BL31_SOURCES += common/feat_detect.c endif +ifeq (${DRTM_SUPPORT},1) +BL31_SOURCES += services/std_svc/drtm/drtm_main.c \ + services/std_svc/drtm/drtm_dma_prot.c \ + services/std_svc/drtm/drtm_res_address_map.c \ + services/std_svc/drtm/drtm_measurements.c \ + services/std_svc/drtm/drtm_remediation.c \ + ${MBEDTLS_SOURCES} +endif + BL31_LINKERFILE := bl31/bl31.ld.S # Flag used to indicate if Crash reporting via console should be included diff --git a/bl31/ehf.c b/bl31/ehf.c index 745f165d4..b328380d1 100644 --- a/bl31/ehf.c +++ b/bl31/ehf.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -475,9 +475,16 @@ void __init ehf_init(void) assert((exception_data.pri_bits >= 1U) || (exception_data.pri_bits < 8U)); - /* Route EL3 interrupts when in Secure and Non-secure. */ + /* Route EL3 interrupts when in Non-secure. */ set_interrupt_rm_flag(flags, NON_SECURE); + + /* + * Route EL3 interrupts when in secure, only when SPMC is not present + * in S-EL2. + */ +#if !(defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1)) set_interrupt_rm_flag(flags, SECURE); +#endif /* !(defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1)) */ /* Register handler for EL3 interrupts */ ret = register_interrupt_type_handler(INTR_TYPE_EL3, diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index 39f1065f0..f10296724 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -51,8 +51,8 @@ vector_base sp_min_vector_table b sp_min_entrypoint b plat_panic_handler /* Undef */ b sp_min_handle_smc /* Syscall */ - b plat_panic_handler /* Prefetch abort */ - b plat_panic_handler /* Data abort */ + b report_prefetch_abort /* Prefetch abort */ + b report_data_abort /* Data abort */ b plat_panic_handler /* Reserved */ b plat_panic_handler /* IRQ */ b sp_min_handle_fiq /* FIQ */ diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 7d77f478b..e5ea88c4e 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,12 +10,16 @@ #include <asm_macros.S> #include <bl32/tsp/tsp.h> #include <lib/xlat_tables/xlat_tables_defs.h> +#include <smccc_helpers.h> #include "../tsp_private.h" .globl tsp_entrypoint .globl tsp_vector_table +#if SPMC_AT_EL3 + .globl tsp_cpu_on_entry +#endif @@ -25,10 +29,10 @@ * --------------------------------------------- */ .macro restore_args_call_smc - ldp x6, x7, [x0, #TSP_ARG6] - ldp x4, x5, [x0, #TSP_ARG4] - ldp x2, x3, [x0, #TSP_ARG2] - ldp x0, x1, [x0, #TSP_ARG0] + ldp x6, x7, [x0, #SMC_ARG6] + ldp x4, x5, [x0, #SMC_ARG4] + ldp x2, x3, [x0, #SMC_ARG2] + ldp x0, x1, [x0, #SMC_ARG0] smc #0 .endm diff --git a/bl32/tsp/ffa_helpers.c b/bl32/tsp/ffa_helpers.c new file mode 100644 index 000000000..3639c221c --- /dev/null +++ b/bl32/tsp/ffa_helpers.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include "ffa_helpers.h" +#include <services/ffa_svc.h> +#include "tsp_private.h" + +/******************************************************************************* + * Wrapper function to send a direct request. + ******************************************************************************/ +smc_args_t ffa_msg_send_direct_req(ffa_endpoint_id16_t sender, + ffa_endpoint_id16_t receiver, + uint32_t arg3, + uint32_t arg4, + uint32_t arg5, + uint32_t arg6, + uint32_t arg7) +{ + uint32_t src_dst_ids = (sender << FFA_DIRECT_MSG_SOURCE_SHIFT) | + (receiver << FFA_DIRECT_MSG_DESTINATION_SHIFT); + + + /* Send Direct Request. */ + return smc_helper(FFA_MSG_SEND_DIRECT_REQ_SMC64, src_dst_ids, + 0, arg3, arg4, arg5, arg6, arg7); +} + +/******************************************************************************* + * Wrapper function to send a direct response. + ******************************************************************************/ +smc_args_t *ffa_msg_send_direct_resp(ffa_endpoint_id16_t sender, + ffa_endpoint_id16_t receiver, + uint32_t arg3, + uint32_t arg4, + uint32_t arg5, + uint32_t arg6, + uint32_t arg7) +{ + uint32_t src_dst_ids = (sender << FFA_DIRECT_MSG_SOURCE_SHIFT) | + (receiver << FFA_DIRECT_MSG_DESTINATION_SHIFT); + + return set_smc_args(FFA_MSG_SEND_DIRECT_RESP_SMC64, src_dst_ids, + 0, arg3, arg4, arg5, arg6, arg7); +} + +/******************************************************************************* + * Memory Management Helpers. + ******************************************************************************/ + +/** + * Initialises the header of the given `ffa_mtd`, not including the + * composite memory region offset. + */ +static void ffa_memory_region_init_header( + struct ffa_mtd *memory_region, ffa_endpoint_id16_t sender, + ffa_mem_attr16_t attributes, ffa_mtd_flag32_t flags, + uint64_t handle, uint64_t tag, ffa_endpoint_id16_t *receivers, + uint32_t receiver_count, ffa_mem_perm8_t permissions) +{ + struct ffa_emad_v1_0 *emad; + + memory_region->emad_offset = sizeof(struct ffa_mtd); + memory_region->emad_size = sizeof(struct ffa_emad_v1_0); + emad = (struct ffa_emad_v1_0 *) + ((uint8_t *) memory_region + + memory_region->emad_offset); + memory_region->sender_id = sender; + memory_region->memory_region_attributes = attributes; + memory_region->reserved_36_39 = 0; + memory_region->flags = flags; + memory_region->handle = handle; + memory_region->tag = tag; + memory_region->reserved_40_47 = 0; + memory_region->emad_count = receiver_count; + for (uint32_t i = 0U; i < receiver_count; i++) { + emad[i].mapd.endpoint_id = receivers[i]; + emad[i].mapd.memory_access_permissions = permissions; + emad[i].mapd.flags = 0; + emad[i].comp_mrd_offset = 0; + emad[i].reserved_8_15 = 0; + } +} +/** + * Initialises the given `ffa_mtd` to be used for an + * `FFA_MEM_RETRIEVE_REQ` by the receiver of a memory transaction. + * TODO: Support differing attributes per receiver. + * + * Returns the size of the descriptor written. + */ +static uint32_t ffa_memory_retrieve_request_init( + struct ffa_mtd *memory_region, uint64_t handle, + ffa_endpoint_id16_t sender, ffa_endpoint_id16_t *receivers, uint32_t receiver_count, + uint64_t tag, ffa_mtd_flag32_t flags, + ffa_mem_perm8_t permissions, + ffa_mem_attr16_t attributes) +{ + ffa_memory_region_init_header(memory_region, sender, attributes, flags, + handle, tag, receivers, + receiver_count, permissions); + + return sizeof(struct ffa_mtd) + + memory_region->emad_count * sizeof(struct ffa_emad_v1_0); +} + +/* Relinquish access to memory region. */ +bool ffa_mem_relinquish(void) +{ + smc_args_t ret; + + ret = smc_helper(FFA_MEM_RELINQUISH, 0, 0, 0, 0, 0, 0, 0); + if (ffa_func_id(ret) != FFA_SUCCESS_SMC32) { + ERROR("%s failed to relinquish memory! error: (%x) %x\n", + __func__, ffa_func_id(ret), ffa_error_code(ret)); + return false; + } + return true; +} + +/* Retrieve memory shared by another partition. */ +smc_args_t ffa_mem_retrieve_req(uint32_t descriptor_length, + uint32_t fragment_length) +{ + return smc_helper(FFA_MEM_RETRIEVE_REQ_SMC32, + descriptor_length, + fragment_length, + 0, 0, 0, 0, 0); +} + +/* Retrieve the next memory descriptor fragment. */ +smc_args_t ffa_mem_frag_rx(uint64_t handle, uint32_t recv_length) +{ + return smc_helper(FFA_MEM_FRAG_RX, + FFA_MEM_HANDLE_LOW(handle), + FFA_MEM_HANDLE_HIGH(handle), + recv_length, + 0, 0, 0, 0); +} + +bool memory_retrieve(struct mailbox *mb, + struct ffa_mtd **retrieved, + uint64_t handle, ffa_endpoint_id16_t sender, + ffa_endpoint_id16_t *receivers, uint32_t receiver_count, + ffa_mtd_flag32_t flags, uint32_t *frag_length, + uint32_t *total_length) +{ + smc_args_t ret; + uint32_t descriptor_size; + struct ffa_mtd *memory_region = (struct ffa_mtd *)mb->tx_buffer; + + if (retrieved == NULL || mb == NULL) { + ERROR("Invalid parameters!\n"); + return false; + } + + /* Clear TX buffer. */ + memset(memory_region, 0, PAGE_SIZE); + + /* Clear local buffer. */ + memset(mem_region_buffer, 0, REGION_BUF_SIZE); + + descriptor_size = ffa_memory_retrieve_request_init( + memory_region, handle, sender, receivers, receiver_count, 0, flags, + FFA_MEM_PERM_RW | FFA_MEM_PERM_NX, + FFA_MEM_ATTR_NORMAL_MEMORY_CACHED_WB | + FFA_MEM_ATTR_INNER_SHAREABLE); + + ret = ffa_mem_retrieve_req(descriptor_size, descriptor_size); + + if (ffa_func_id(ret) == FFA_ERROR) { + ERROR("Couldn't retrieve the memory page. Error: %x\n", + ffa_error_code(ret)); + return false; + } + + /* + * Following total_size and fragment_size are useful to keep track + * of the state of transaction. When the sum of all fragment_size of all + * fragments is equal to total_size, the memory transaction has been + * completed. + */ + *total_length = ret._regs[1]; + *frag_length = ret._regs[2]; + + /* Validate frag_length is less than total_length and mailbox size. */ + if (*frag_length == 0U || *total_length == 0U || + *frag_length > *total_length || *frag_length > (mb->rxtx_page_count * PAGE_SIZE)) { + ERROR("Invalid parameters!\n"); + return false; + } + + /* Copy response to local buffer. */ + memcpy(mem_region_buffer, mb->rx_buffer, *frag_length); + + if (ffa_rx_release()) { + ERROR("Failed to release buffer!\n"); + return false; + } + + *retrieved = (struct ffa_mtd *) mem_region_buffer; + + if ((*retrieved)->emad_count > MAX_MEM_SHARE_RECIPIENTS) { + VERBOSE("SPMC memory sharing supports max of %u receivers!\n", + MAX_MEM_SHARE_RECIPIENTS); + return false; + } + + /* + * We are sharing memory from the normal world therefore validate the NS + * bit was set by the SPMC. + */ + if (((*retrieved)->memory_region_attributes & FFA_MEM_ATTR_NS_BIT) == 0U) { + ERROR("SPMC has not set the NS bit! 0x%x\n", + (*retrieved)->memory_region_attributes); + return false; + } + + VERBOSE("Memory Descriptor Retrieved!\n"); + + return true; +} + +/* Relinquish the memory region. */ +bool memory_relinquish(struct ffa_mem_relinquish_descriptor *m, uint64_t handle, + ffa_endpoint_id16_t id) +{ + ffa_mem_relinquish_init(m, handle, 0, id); + return ffa_mem_relinquish(); +} + +/* Query SPMC that the rx buffer of the partition can be released. */ +bool ffa_rx_release(void) +{ + smc_args_t ret; + + ret = smc_helper(FFA_RX_RELEASE, 0, 0, 0, 0, 0, 0, 0); + return ret._regs[SMC_ARG0] != FFA_SUCCESS_SMC32; +} + +/* Map the provided buffers with the SPMC. */ +bool ffa_rxtx_map(uintptr_t send, uintptr_t recv, uint32_t pages) +{ + smc_args_t ret; + + ret = smc_helper(FFA_RXTX_MAP_SMC64, send, recv, pages, 0, 0, 0, 0); + return ret._regs[0] != FFA_SUCCESS_SMC32; +} diff --git a/bl32/tsp/ffa_helpers.h b/bl32/tsp/ffa_helpers.h new file mode 100644 index 000000000..e650a070d --- /dev/null +++ b/bl32/tsp/ffa_helpers.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FFA_HELPERS_H +#define FFA_HELPERS_H + +#include <stdint.h> + +#include "../../services/std_svc/spm/el3_spmc/spmc.h" +#include "../../services/std_svc/spm/el3_spmc/spmc_shared_mem.h" +#include <services/el3_spmc_ffa_memory.h> +#include <services/ffa_svc.h> +#include "tsp_private.h" + +static inline uint32_t ffa_func_id(smc_args_t val) +{ + return (uint32_t) val._regs[0]; +} + +static inline int32_t ffa_error_code(smc_args_t val) +{ + return (uint32_t) val._regs[2]; +} + +extern uint8_t mem_region_buffer[4096 * 2] __aligned(PAGE_SIZE); +#define REGION_BUF_SIZE sizeof(mem_region_buffer) + +/** The maximum number of recipients a memory region may be sent to. */ +#define MAX_MEM_SHARE_RECIPIENTS 2U + +/* FFA Memory Management mode flags. */ +#define FFA_FLAG_SHARE_MEMORY (1U << 3) +#define FFA_FLAG_LEND_MEMORY (1U << 4) + +#define FFA_FLAG_MEMORY_MASK (3U << 3) + +#define FFA_MEM_HANDLE_LOW(x) (x & 0xFFFFFFFF) +#define FFA_MEM_HANDLE_HIGH(x) (x >> 32) + +#define FFA_MEM_PERM_DATA_OFFSET 0 +#define FFA_MEM_PERM_DATA_MASK 0x3 + +static inline uint32_t ffa_mem_relinquish_init( + struct ffa_mem_relinquish_descriptor *relinquish_request, + uint64_t handle, ffa_mtd_flag32_t flags, + ffa_endpoint_id16_t sender) +{ + relinquish_request->handle = handle; + relinquish_request->flags = flags; + relinquish_request->endpoint_count = 1; + relinquish_request->endpoint_array[0] = sender; + + return sizeof(struct ffa_mem_relinquish_descriptor) + sizeof(ffa_endpoint_id16_t); +} + +/** + * Gets the `ffa_comp_mrd` for the given receiver from an + * `ffa_mtd`, or NULL if it is not valid. + */ +static inline struct ffa_comp_mrd * +ffa_memory_region_get_composite(struct ffa_mtd *memory_region, + uint32_t receiver_index) +{ + struct ffa_emad_v1_0 *receivers; + uint32_t offset; + + receivers = (struct ffa_emad_v1_0 *) + ((uint8_t *) memory_region + + memory_region->emad_offset + + (memory_region->emad_size * receiver_index)); + offset = receivers->comp_mrd_offset; + + if (offset == 0U) { + return NULL; + } + + return (struct ffa_comp_mrd *) + ((uint8_t *) memory_region + offset); +} + +static inline uint32_t ffa_get_data_access_attr(ffa_mem_perm8_t perm) +{ + return ((perm >> FFA_MEM_PERM_DATA_OFFSET) & FFA_MEM_PERM_DATA_MASK); +} + +smc_args_t ffa_mem_frag_rx(uint64_t handle, uint32_t recv_length); +bool ffa_mem_relinquish(void); +bool ffa_rx_release(void); +bool memory_relinquish(struct ffa_mem_relinquish_descriptor *m, uint64_t handle, + ffa_endpoint_id16_t id); +bool ffa_rxtx_map(uintptr_t send, uintptr_t recv, uint32_t pages); +bool memory_retrieve(struct mailbox *mb, + struct ffa_mtd **retrieved, + uint64_t handle, ffa_endpoint_id16_t sender, + ffa_endpoint_id16_t *receivers, uint32_t receiver_count, + ffa_mtd_flag32_t flags, uint32_t *frag_length, + uint32_t *total_length); + +smc_args_t ffa_msg_send_direct_req(ffa_endpoint_id16_t sender, + ffa_endpoint_id16_t receiver, + uint32_t arg3, + uint32_t arg4, + uint32_t arg5, + uint32_t arg6, + uint32_t arg7); +smc_args_t *ffa_msg_send_direct_resp(ffa_endpoint_id16_t sender, + ffa_endpoint_id16_t receiver, + uint32_t arg3, + uint32_t arg4, + uint32_t arg5, + uint32_t arg6, + uint32_t arg7); +#endif /* FFA_HELPERS_H */ diff --git a/bl32/tsp/tsp.mk b/bl32/tsp/tsp.mk index 3fd6d9957..c31b9b543 100644 --- a/bl32/tsp/tsp.mk +++ b/bl32/tsp/tsp.mk @@ -1,17 +1,24 @@ # -# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # INCLUDES += -Iinclude/bl32/tsp -BL32_SOURCES += bl32/tsp/tsp_main.c \ - bl32/tsp/aarch64/tsp_entrypoint.S \ +ifeq (${SPMC_AT_EL3},1) + BL32_SOURCES += bl32/tsp/tsp_ffa_main.c \ + bl32/tsp/ffa_helpers.c +else + BL32_SOURCES += bl32/tsp/tsp_main.c +endif + +BL32_SOURCES += bl32/tsp/aarch64/tsp_entrypoint.S \ bl32/tsp/aarch64/tsp_exceptions.S \ bl32/tsp/aarch64/tsp_request.S \ bl32/tsp/tsp_interrupt.c \ bl32/tsp/tsp_timer.c \ + bl32/tsp/tsp_common.c \ common/aarch64/early_exceptions.S \ lib/locks/exclusive/aarch64/spinlock.S diff --git a/bl32/tsp/tsp_common.c b/bl32/tsp/tsp_common.c new file mode 100644 index 000000000..908b4ff09 --- /dev/null +++ b/bl32/tsp/tsp_common.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <inttypes.h> +#include <stdint.h> + +#include <arch_features.h> +#include <arch_helpers.h> +#include <bl32/tsp/tsp.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <lib/spinlock.h> +#include <plat/common/platform.h> +#include <platform_tsp.h> +#include "tsp_private.h" + +#include <platform_def.h> + +/******************************************************************************* + * Per cpu data structure to populate parameters for an SMC in C code and use + * a pointer to this structure in assembler code to populate x0-x7. + ******************************************************************************/ +static smc_args_t tsp_smc_args[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * Per cpu data structure to keep track of TSP activity + ******************************************************************************/ +work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; + +smc_args_t *set_smc_args(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id; + smc_args_t *pcpu_smc_args; + + /* + * Return to Secure Monitor by raising an SMC. The results of the + * service are passed as an arguments to the SMC. + */ + linear_id = plat_my_core_pos(); + pcpu_smc_args = &tsp_smc_args[linear_id]; + write_sp_arg(pcpu_smc_args, SMC_ARG0, arg0); + write_sp_arg(pcpu_smc_args, SMC_ARG1, arg1); + write_sp_arg(pcpu_smc_args, SMC_ARG2, arg2); + write_sp_arg(pcpu_smc_args, SMC_ARG3, arg3); + write_sp_arg(pcpu_smc_args, SMC_ARG4, arg4); + write_sp_arg(pcpu_smc_args, SMC_ARG5, arg5); + write_sp_arg(pcpu_smc_args, SMC_ARG6, arg6); + write_sp_arg(pcpu_smc_args, SMC_ARG7, arg7); + + return pcpu_smc_args; +} + +/******************************************************************************* + * Setup function for TSP. + ******************************************************************************/ +void tsp_setup(void) +{ + /* Perform early platform-specific setup. */ + tsp_early_platform_setup(); + + /* Perform late platform-specific setup. */ + tsp_plat_arch_setup(); + +#if ENABLE_PAUTH + /* + * Assert that the ARMv8.3-PAuth registers are present or an access + * fault will be triggered when they are being saved or restored. + */ + assert(is_armv8_3_pauth_present()); +#endif /* ENABLE_PAUTH */ +} + +/******************************************************************************* + * This function performs any remaining bookkeeping in the test secure payload + * before the system is switched off (in response to a psci SYSTEM_OFF request). + ******************************************************************************/ +smc_args_t *tsp_system_off_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Update this cpu's statistics. */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + + INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count); + + /* Indicate to the SPD that we have completed this request. */ + return set_smc_args(TSP_SYSTEM_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any remaining bookkeeping in the test secure payload + * before the system is reset (in response to a psci SYSTEM_RESET request). + ******************************************************************************/ +smc_args_t *tsp_system_reset_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Update this cpu's statistics. */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + + INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count); + + /* Indicate to the SPD that we have completed this request. */ + return set_smc_args(TSP_SYSTEM_RESET_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * TSP smc abort handler. This function is called when aborting a preempted + * yielding SMC request. It should cleanup all resources owned by the SMC + * handler such as locks or dynamically allocated memory so following SMC + * request are executed in a clean environment. + ******************************************************************************/ +smc_args_t *tsp_abort_smc_handler(uint64_t func, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + return set_smc_args(TSP_ABORT_DONE, 0, 0, 0, 0, 0, 0, 0); +} diff --git a/bl32/tsp/tsp_ffa_main.c b/bl32/tsp/tsp_ffa_main.c new file mode 100644 index 000000000..53dbd03d5 --- /dev/null +++ b/bl32/tsp/tsp_ffa_main.c @@ -0,0 +1,655 @@ +/* + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <inttypes.h> +#include <stdint.h> + +#include "../../services/std_svc/spm/el3_spmc/spmc.h" +#include "../../services/std_svc/spm/el3_spmc/spmc_shared_mem.h" +#include <arch_features.h> +#include <arch_helpers.h> +#include <bl32/tsp/tsp.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include "ffa_helpers.h" +#include <lib/psci/psci.h> +#include <lib/spinlock.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> +#include <platform_tsp.h> +#include <services/ffa_svc.h> +#include "tsp_private.h" + +#include <platform_def.h> + +static ffa_endpoint_id16_t tsp_id, spmc_id; +uint8_t mem_region_buffer[4096 * 2] __aligned(PAGE_SIZE); + +/* Partition Mailbox. */ +static uint8_t send_page[PAGE_SIZE] __aligned(PAGE_SIZE); +static uint8_t recv_page[PAGE_SIZE] __aligned(PAGE_SIZE); + +/* + * Declare a global mailbox for use within the TSP. + * This will be initialized appropriately when the buffers + * are mapped with the SPMC. + */ +static struct mailbox mailbox; + +/******************************************************************************* + * This enum is used to handle test cases driven from the FF-A Test Driver. + ******************************************************************************/ +/* Keep in Sync with FF-A Test Driver. */ +enum message_t { + /* Partition Only Messages. */ + FF_A_RELAY_MESSAGE = 0, + + /* Basic Functionality. */ + FF_A_ECHO_MESSAGE, + FF_A_RELAY_MESSAGE_EL3, + + /* Memory Sharing. */ + FF_A_MEMORY_SHARE, + FF_A_MEMORY_SHARE_FRAGMENTED, + FF_A_MEMORY_LEND, + FF_A_MEMORY_LEND_FRAGMENTED, + + FF_A_MEMORY_SHARE_MULTI_ENDPOINT, + FF_A_MEMORY_LEND_MULTI_ENDPOINT, + + LAST, + FF_A_RUN_ALL = 255, + FF_A_OP_MAX = 256 +}; + +#if SPMC_AT_EL3 +extern void tsp_cpu_on_entry(void); +#endif + +/******************************************************************************* + * Test Functions. + ******************************************************************************/ + +/******************************************************************************* + * Enable the TSP to forward the received message to another partition and ask + * it to echo the value back in order to validate direct messages functionality. + ******************************************************************************/ +static int ffa_test_relay(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + smc_args_t ffa_forward_result; + ffa_endpoint_id16_t receiver = arg5; + + ffa_forward_result = ffa_msg_send_direct_req(ffa_endpoint_source(arg1), + receiver, + FF_A_ECHO_MESSAGE, arg4, + 0, 0, 0); + return ffa_forward_result._regs[3]; +} + +/******************************************************************************* + * This function handles memory management tests, currently share and lend. + * This test supports the use of FRAG_RX to use memory descriptors that do not + * fit in a single 4KB buffer. + ******************************************************************************/ +static int test_memory_send(ffa_endpoint_id16_t sender, uint64_t handle, + ffa_mtd_flag32_t flags, bool multi_endpoint) +{ + struct ffa_mtd *m; + struct ffa_emad_v1_0 *receivers; + struct ffa_comp_mrd *composite; + int ret, status = 0; + unsigned int mem_attrs; + char *ptr; + ffa_endpoint_id16_t source = sender; + uint32_t total_length, recv_length = 0; + + /* + * In the case that we're testing multiple endpoints choose a partition + * ID that resides in the normal world so the SPMC won't detect it as + * invalid. + * TODO: Should get endpoint receiver id and flag as input from NWd. + */ + uint32_t receiver_count = multi_endpoint ? 2 : 1; + ffa_endpoint_id16_t test_receivers[2] = { tsp_id, 0x10 }; + + /* Ensure that the sender ID resides in the normal world. */ + if (ffa_is_secure_world_id(sender)) { + ERROR("Invalid sender ID 0x%x.\n", sender); + return FFA_ERROR_DENIED; + } + + if (!memory_retrieve(&mailbox, &m, handle, source, test_receivers, + receiver_count, flags, &recv_length, + &total_length)) { + return FFA_ERROR_INVALID_PARAMETER; + } + + receivers = (struct ffa_emad_v1_0 *) + ((uint8_t *) m + m->emad_offset); + while (total_length != recv_length) { + smc_args_t ffa_return; + uint32_t frag_length; + + ffa_return = ffa_mem_frag_rx(handle, recv_length); + + if (ffa_return._regs[0] == FFA_ERROR) { + WARN("TSP: failed to resume mem with handle %lx\n", + handle); + return ffa_return._regs[2]; + } + frag_length = ffa_return._regs[3]; + + /* Validate frag_length is less than total_length and mailbox size. */ + if (frag_length > total_length || + frag_length > (mailbox.rxtx_page_count * PAGE_SIZE)) { + ERROR("Invalid parameters!\n"); + return FFA_ERROR_INVALID_PARAMETER; + } + + /* Validate frag_length is less than remaining mem_region_buffer size. */ + if (frag_length + recv_length >= REGION_BUF_SIZE) { + ERROR("Out of memory!\n"); + return FFA_ERROR_INVALID_PARAMETER; + } + + memcpy(&mem_region_buffer[recv_length], mailbox.rx_buffer, + frag_length); + + if (ffa_rx_release()) { + ERROR("Failed to release buffer!\n"); + return FFA_ERROR_DENIED; + } + + recv_length += frag_length; + + assert(recv_length <= total_length); + } + + composite = ffa_memory_region_get_composite(m, 0); + if (composite == NULL) { + WARN("Failed to get composite descriptor!\n"); + return FFA_ERROR_INVALID_PARAMETER; + } + + VERBOSE("Address: %p; page_count: %x %lx\n", + (void *)composite->address_range_array[0].address, + composite->address_range_array[0].page_count, PAGE_SIZE); + + /* This test is only concerned with RW permissions. */ + if (ffa_get_data_access_attr( + receivers[0].mapd.memory_access_permissions) != FFA_MEM_PERM_RW) { + ERROR("Data permission in retrieve response %x does not match share/lend %x!\n", + ffa_get_data_access_attr(receivers[0].mapd.memory_access_permissions), + FFA_MEM_PERM_RW); + return FFA_ERROR_INVALID_PARAMETER; + } + + mem_attrs = MT_RW_DATA | MT_EXECUTE_NEVER; + + /* Only expecting to be sent memory from NWd so map accordingly. */ + mem_attrs |= MT_NS; + + for (uint32_t i = 0U; i < composite->address_range_count; i++) { + size_t size = composite->address_range_array[i].page_count * PAGE_SIZE; + + ptr = (char *) composite->address_range_array[i].address; + ret = mmap_add_dynamic_region( + (uint64_t)ptr, + (uint64_t)ptr, + size, mem_attrs); + + if (ret != 0) { + ERROR("Failed [%u] mmap_add_dynamic_region %u (%lx) (%lx) (%x)!\n", + i, ret, + (uint64_t)composite->address_range_array[i].address, + size, mem_attrs); + + /* Remove mappings created in this transaction. */ + for (i--; i >= 0U; i--) { + ret = mmap_remove_dynamic_region( + (uint64_t)ptr, + composite->address_range_array[i].page_count * PAGE_SIZE); + + if (ret != 0) { + ERROR("Failed [%d] mmap_remove_dynamic_region!\n", i); + panic(); + } + } + return FFA_ERROR_NO_MEMORY; + } + + /* Increment memory region for validation purposes. */ + ++(*ptr); + + /* + * Read initial magic number from memory region for + * validation purposes. + */ + if (!i) { + status = *ptr; + } + } + + for (uint32_t i = 0U; i < composite->address_range_count; i++) { + ret = mmap_remove_dynamic_region( + (uint64_t)composite->address_range_array[i].address, + composite->address_range_array[i].page_count * PAGE_SIZE); + + if (ret != 0) { + ERROR("Failed [%d] mmap_remove_dynamic_region!\n", i); + return FFA_ERROR_NO_MEMORY; + } + } + + if (!memory_relinquish((struct ffa_mem_relinquish_descriptor *)mailbox.tx_buffer, + m->handle, tsp_id)) { + ERROR("Failed to relinquish memory region!\n"); + return FFA_ERROR_INVALID_PARAMETER; + } + return status; +} + +static smc_args_t *send_ffa_pm_success(void) +{ + return set_smc_args(FFA_MSG_SEND_DIRECT_RESP_SMC32, + ((tsp_id & FFA_DIRECT_MSG_ENDPOINT_ID_MASK) + << FFA_DIRECT_MSG_SOURCE_SHIFT) | spmc_id, + FFA_FWK_MSG_BIT | + (FFA_PM_MSG_PM_RESP & FFA_FWK_MSG_MASK), + 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any remaining book keeping in the test secure payload + * before this cpu is turned off in response to a psci cpu_off request. + ******************************************************************************/ +smc_args_t *tsp_cpu_off_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* + * This cpu is being turned off, so disable the timer to prevent the + * secure timer interrupt from interfering with power down. A pending + * interrupt will be lost but we do not care as we are turning off. + */ + tsp_generic_timer_stop(); + + /* Update this cpu's statistics. */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_off_count++; + + INFO("TSP: cpu 0x%lx off request\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_off_count); + + return send_ffa_pm_success(); +} + +/******************************************************************************* + * This function performs any book keeping in the test secure payload before + * this cpu's architectural state is saved in response to an earlier psci + * cpu_suspend request. + ******************************************************************************/ +smc_args_t *tsp_cpu_suspend_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* + * Save the time context and disable it to prevent the secure timer + * interrupt from interfering with wakeup from the suspend state. + */ + tsp_generic_timer_save(); + tsp_generic_timer_stop(); + + /* Update this cpu's statistics. */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_suspend_count++; + + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_suspend_count); + + return send_ffa_pm_success(); +} + +/******************************************************************************* + * This function performs any bookkeeping in the test secure payload after this + * cpu's architectural state has been restored after wakeup from an earlier psci + * cpu_suspend request. + ******************************************************************************/ +smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Restore the generic timer context. */ + tsp_generic_timer_restore(); + + /* Update this cpu's statistics. */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_resume_count++; + + INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n", + read_mpidr(), max_off_pwrlvl); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_resume_count); + + return send_ffa_pm_success(); +} + +/******************************************************************************* + * This function handles framework messages. Currently only PM. + ******************************************************************************/ +static smc_args_t *handle_framework_message(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + /* Check if it is a power management message from the SPMC. */ + if (ffa_endpoint_source(arg1) != spmc_id) { + goto err; + } + + /* Check if it is a PM request message. */ + if ((arg2 & FFA_FWK_MSG_MASK) == FFA_FWK_MSG_PSCI) { + /* Check if it is a PSCI CPU_OFF request. */ + if (arg3 == PSCI_CPU_OFF) { + return tsp_cpu_off_main(arg0, arg1, arg2, arg3, + arg4, arg5, arg6, arg7); + } else if (arg3 == PSCI_CPU_SUSPEND_AARCH64) { + return tsp_cpu_suspend_main(arg0, arg1, arg2, arg3, + arg4, arg5, arg6, arg7); + } + } else if ((arg2 & FFA_FWK_MSG_MASK) == FFA_PM_MSG_WB_REQ) { + /* Check it is a PSCI Warm Boot request. */ + if (arg3 == FFA_WB_TYPE_NOTS2RAM) { + return tsp_cpu_resume_main(arg0, arg1, arg2, arg3, + arg4, arg5, arg6, arg7); + } + } + +err: + ERROR("%s: Unknown framework message!\n", __func__); + panic(); +} + +/******************************************************************************* + * Handles partition messages. Exercised from the FF-A Test Driver. + ******************************************************************************/ +static smc_args_t *handle_partition_message(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint16_t sender = ffa_endpoint_source(arg1); + uint16_t receiver = ffa_endpoint_destination(arg1); + int status = -1; + const bool multi_endpoint = true; + + switch (arg3) { + case FF_A_MEMORY_SHARE: + INFO("TSP Tests: Memory Share Request--\n"); + status = test_memory_send(sender, arg4, FFA_FLAG_SHARE_MEMORY, !multi_endpoint); + break; + + case FF_A_MEMORY_LEND: + INFO("TSP Tests: Memory Lend Request--\n"); + status = test_memory_send(sender, arg4, FFA_FLAG_LEND_MEMORY, !multi_endpoint); + break; + + case FF_A_MEMORY_SHARE_MULTI_ENDPOINT: + INFO("TSP Tests: Multi Endpoint Memory Share Request--\n"); + status = test_memory_send(sender, arg4, FFA_FLAG_SHARE_MEMORY, multi_endpoint); + break; + + case FF_A_MEMORY_LEND_MULTI_ENDPOINT: + INFO("TSP Tests: Multi Endpoint Memory Lend Request--\n"); + status = test_memory_send(sender, arg4, FFA_FLAG_LEND_MEMORY, multi_endpoint); + break; + case FF_A_RELAY_MESSAGE: + INFO("TSP Tests: Relaying message--\n"); + status = ffa_test_relay(arg0, arg1, arg2, arg3, arg4, + arg5, arg6, arg7); + break; + + case FF_A_ECHO_MESSAGE: + INFO("TSP Tests: echo message--\n"); + status = arg4; + break; + + default: + INFO("TSP Tests: Unknown request ID %d--\n", (int) arg3); + } + + /* Swap the sender and receiver in the response. */ + return ffa_msg_send_direct_resp(receiver, sender, status, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function implements the event loop for handling FF-A ABI invocations. + ******************************************************************************/ +static smc_args_t *tsp_event_loop(uint64_t smc_fid, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + /* Panic if the SPMC did not forward an FF-A call. */ + if (!is_ffa_fid(smc_fid)) { + ERROR("%s: Unknown SMC FID (0x%lx)\n", __func__, smc_fid); + panic(); + } + + switch (smc_fid) { + case FFA_INTERRUPT: + /* + * IRQs were enabled upon re-entry into the TSP. The interrupt + * must have been handled by now. Return to the SPMC indicating + * the same. + */ + return set_smc_args(FFA_MSG_WAIT, 0, 0, 0, 0, 0, 0, 0); + + case FFA_MSG_SEND_DIRECT_REQ_SMC64: + case FFA_MSG_SEND_DIRECT_REQ_SMC32: + /* Check if a framework message, handle accordingly. */ + if ((arg2 & FFA_FWK_MSG_BIT)) { + return handle_framework_message(smc_fid, arg1, arg2, arg3, + arg4, arg5, arg6, arg7); + } + return handle_partition_message(smc_fid, arg1, arg2, arg3, + arg4, arg5, arg6, arg7); + } + + ERROR("%s: Unsupported FF-A FID (0x%lx)\n", __func__, smc_fid); + panic(); +} + +static smc_args_t *tsp_loop(smc_args_t *args) +{ + smc_args_t ret; + + do { + /* -------------------------------------------- + * Mask FIQ interrupts to avoid preemption + * in case EL3 SPMC delegates an IRQ next or a + * managed exit. Lastly, unmask IRQs so that + * they can be handled immediately upon re-entry. + * --------------------------------------------- + */ + write_daifset(DAIF_FIQ_BIT); + write_daifclr(DAIF_IRQ_BIT); + ret = smc_helper(args->_regs[0], args->_regs[1], args->_regs[2], + args->_regs[3], args->_regs[4], args->_regs[5], + args->_regs[6], args->_regs[7]); + args = tsp_event_loop(ret._regs[0], ret._regs[1], ret._regs[2], + ret._regs[3], ret._regs[4], ret._regs[5], + ret._regs[6], ret._regs[7]); + } while (1); + + /* Not Reached. */ + return NULL; +} + +/******************************************************************************* + * TSP main entry point where it gets the opportunity to initialize its secure + * state/applications. Once the state is initialized, it must return to the + * SPD with a pointer to the 'tsp_vector_table' jump table. + ******************************************************************************/ +uint64_t tsp_main(void) +{ + smc_args_t smc_args = {0}; + + NOTICE("TSP: %s\n", version_string); + NOTICE("TSP: %s\n", build_message); + INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE); + INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE); + uint32_t linear_id = plat_my_core_pos(); + + /* Initialize the platform. */ + tsp_platform_setup(); + + /* Initialize secure/applications state here. */ + tsp_generic_timer_start(); + + /* Register secondary entrypoint with the SPMC. */ + smc_args = smc_helper(FFA_SECONDARY_EP_REGISTER_SMC64, + (uint64_t) tsp_cpu_on_entry, + 0, 0, 0, 0, 0, 0); + if (smc_args._regs[SMC_ARG0] != FFA_SUCCESS_SMC32) { + ERROR("TSP could not register secondary ep (0x%lx)\n", + smc_args._regs[2]); + panic(); + } + /* Get TSP's endpoint id. */ + smc_args = smc_helper(FFA_ID_GET, 0, 0, 0, 0, 0, 0, 0); + if (smc_args._regs[SMC_ARG0] != FFA_SUCCESS_SMC32) { + ERROR("TSP could not get own ID (0x%lx) on core%d\n", + smc_args._regs[2], linear_id); + panic(); + } + + tsp_id = smc_args._regs[2]; + INFO("TSP FF-A endpoint id = 0x%x\n", tsp_id); + + /* Get the SPMC ID. */ + smc_args = smc_helper(FFA_SPM_ID_GET, 0, 0, 0, 0, 0, 0, 0); + if (smc_args._regs[SMC_ARG0] != FFA_SUCCESS_SMC32) { + ERROR("TSP could not get SPMC ID (0x%lx) on core%d\n", + smc_args._regs[2], linear_id); + panic(); + } + + spmc_id = smc_args._regs[2]; + + /* Call RXTX_MAP to map a 4k RX and TX buffer. */ + if (ffa_rxtx_map((uintptr_t) send_page, + (uintptr_t) recv_page, 1)) { + ERROR("TSP could not map it's RX/TX Buffers\n"); + panic(); + } + + mailbox.tx_buffer = send_page; + mailbox.rx_buffer = recv_page; + mailbox.rxtx_page_count = 1; + + /* Update this cpu's statistics. */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_on_count++; + + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_on_count); + + /* Tell SPMD that we are done initialising. */ + tsp_loop(set_smc_args(FFA_MSG_WAIT, 0, 0, 0, 0, 0, 0, 0)); + + /* Not reached. */ + return 0; +} + +/******************************************************************************* + * This function performs any remaining book keeping in the test secure payload + * after this cpu's architectural state has been setup in response to an earlier + * psci cpu_on request. + ******************************************************************************/ +smc_args_t *tsp_cpu_on_main(void) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Initialize secure/applications state here. */ + tsp_generic_timer_start(); + + /* Update this cpu's statistics. */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_on_count++; + INFO("TSP: cpu 0x%lx turned on\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_on_count); + /* --------------------------------------------- + * Jump to the main event loop to return to EL3 + * and be ready for the next request on this cpu. + * --------------------------------------------- + */ + return tsp_loop(set_smc_args(FFA_MSG_WAIT, 0, 0, 0, 0, 0, 0, 0)); +} diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c index 430b5ddb8..a847b6c73 100644 --- a/bl32/tsp/tsp_interrupt.c +++ b/bl32/tsp/tsp_interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,8 +35,6 @@ void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN) tsp_stats[linear_id].sync_sel1_intr_ret_count++; -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - spin_lock(&console_lock); VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%" PRIx64 "\n", read_mpidr(), elr_el3); VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests," @@ -44,8 +42,6 @@ void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) read_mpidr(), tsp_stats[linear_id].sync_sel1_intr_count, tsp_stats[linear_id].sync_sel1_intr_ret_count); - spin_unlock(&console_lock); -#endif } /****************************************************************************** @@ -58,12 +54,8 @@ int32_t tsp_handle_preemption(void) uint32_t linear_id = plat_my_core_pos(); tsp_stats[linear_id].preempt_intr_count++; -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - spin_lock(&console_lock); VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n", read_mpidr(), tsp_stats[linear_id].preempt_intr_count); - spin_unlock(&console_lock); -#endif return TSP_PREEMPTED; } @@ -91,8 +83,18 @@ int32_t tsp_common_int_handler(void) id = plat_ic_get_pending_interrupt_id(); /* TSP can only handle the secure physical timer interrupt */ - if (id != TSP_IRQ_SEC_PHY_TIMER) + if (id != TSP_IRQ_SEC_PHY_TIMER) { +#if SPMC_AT_EL3 + /* + * With the EL3 FF-A SPMC we expect only Timer secure interrupt to fire in + * the TSP, so panic if any other interrupt does. + */ + ERROR("Unexpected interrupt id %u\n", id); + panic(); +#else return tsp_handle_preemption(); +#endif + } /* * Acknowledge and handle the secure timer interrupt. Also sanity check @@ -105,13 +107,9 @@ int32_t tsp_common_int_handler(void) /* Update the statistics and print some messages */ tsp_stats[linear_id].sel1_intr_count++; -#if LOG_LEVEL >= LOG_LEVEL_VERBOSE - spin_lock(&console_lock); VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n", read_mpidr(), id); VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n", read_mpidr(), tsp_stats[linear_id].sel1_intr_count); - spin_unlock(&console_lock); -#endif return 0; } diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index 522c1b403..df9903bb2 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c @@ -15,85 +15,10 @@ #include <common/debug.h> #include <lib/spinlock.h> #include <plat/common/platform.h> -#include <platform_def.h> #include <platform_tsp.h> - #include "tsp_private.h" - -/******************************************************************************* - * Lock to control access to the console - ******************************************************************************/ -spinlock_t console_lock; - -/******************************************************************************* - * Per cpu data structure to populate parameters for an SMC in C code and use - * a pointer to this structure in assembler code to populate x0-x7 - ******************************************************************************/ -static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT]; - -/******************************************************************************* - * Per cpu data structure to keep track of TSP activity - ******************************************************************************/ -work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; - -/******************************************************************************* - * The TSP memory footprint starts at address BL32_BASE and ends with the - * linker symbol __BL32_END__. Use these addresses to compute the TSP image - * size. - ******************************************************************************/ -#define BL32_TOTAL_LIMIT BL32_END -#define BL32_TOTAL_SIZE (BL32_TOTAL_LIMIT - (unsigned long) BL32_BASE) - -static tsp_args_t *set_smc_args(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7) -{ - uint32_t linear_id; - tsp_args_t *pcpu_smc_args; - - /* - * Return to Secure Monitor by raising an SMC. The results of the - * service are passed as an arguments to the SMC - */ - linear_id = plat_my_core_pos(); - pcpu_smc_args = &tsp_smc_args[linear_id]; - write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0); - write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1); - write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2); - write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3); - write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4); - write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5); - write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6); - write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7); - - return pcpu_smc_args; -} - -/******************************************************************************* - * Setup function for TSP. - ******************************************************************************/ -void tsp_setup(void) -{ - /* Perform early platform-specific setup */ - tsp_early_platform_setup(); - - /* Perform late platform-specific setup */ - tsp_plat_arch_setup(); - -#if ENABLE_PAUTH - /* - * Assert that the ARMv8.3-PAuth registers are present or an access - * fault will be triggered when they are being saved or restored. - */ - assert(is_armv8_3_pauth_present()); -#endif /* ENABLE_PAUTH */ -} +#include <platform_def.h> /******************************************************************************* * TSP main entry point where it gets the opportunity to initialize its secure @@ -120,15 +45,11 @@ uint64_t tsp_main(void) tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_on_count++; -#if LOG_LEVEL >= LOG_LEVEL_INFO - spin_lock(&console_lock); INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", read_mpidr(), tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_on_count); - spin_unlock(&console_lock); -#endif return (uint64_t) &tsp_vector_table; } @@ -137,7 +58,7 @@ uint64_t tsp_main(void) * after this cpu's architectural state has been setup in response to an earlier * psci cpu_on request. ******************************************************************************/ -tsp_args_t *tsp_cpu_on_main(void) +smc_args_t *tsp_cpu_on_main(void) { uint32_t linear_id = plat_my_core_pos(); @@ -149,16 +70,12 @@ tsp_args_t *tsp_cpu_on_main(void) tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_on_count++; -#if LOG_LEVEL >= LOG_LEVEL_INFO - spin_lock(&console_lock); INFO("TSP: cpu 0x%lx turned on\n", read_mpidr()); INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", read_mpidr(), tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_on_count); - spin_unlock(&console_lock); -#endif /* Indicate to the SPD that we have completed turned ourselves on */ return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0); } @@ -167,7 +84,7 @@ tsp_args_t *tsp_cpu_on_main(void) * This function performs any remaining book keeping in the test secure payload * before this cpu is turned off in response to a psci cpu_off request. ******************************************************************************/ -tsp_args_t *tsp_cpu_off_main(uint64_t arg0, +smc_args_t *tsp_cpu_off_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, @@ -190,16 +107,12 @@ tsp_args_t *tsp_cpu_off_main(uint64_t arg0, tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_off_count++; -#if LOG_LEVEL >= LOG_LEVEL_INFO - spin_lock(&console_lock); INFO("TSP: cpu 0x%lx off request\n", read_mpidr()); INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", read_mpidr(), tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_off_count); - spin_unlock(&console_lock); -#endif /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); @@ -210,7 +123,7 @@ tsp_args_t *tsp_cpu_off_main(uint64_t arg0, * this cpu's architectural state is saved in response to an earlier psci * cpu_suspend request. ******************************************************************************/ -tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, +smc_args_t *tsp_cpu_suspend_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, @@ -233,15 +146,11 @@ tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_suspend_count++; -#if LOG_LEVEL >= LOG_LEVEL_INFO - spin_lock(&console_lock); INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", read_mpidr(), tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_suspend_count); - spin_unlock(&console_lock); -#endif /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0); @@ -252,7 +161,7 @@ tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, * cpu's architectural state has been restored after wakeup from an earlier psci * cpu_suspend request. ******************************************************************************/ -tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, +smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, uint64_t arg1, uint64_t arg2, uint64_t arg3, @@ -271,8 +180,6 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_resume_count++; -#if LOG_LEVEL >= LOG_LEVEL_INFO - spin_lock(&console_lock); INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n", read_mpidr(), max_off_pwrlvl); INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n", @@ -280,83 +187,17 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_resume_count); - spin_unlock(&console_lock); -#endif /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* - * This function performs any remaining bookkeeping in the test secure payload - * before the system is switched off (in response to a psci SYSTEM_OFF request) - ******************************************************************************/ -tsp_args_t *tsp_system_off_main(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7) -{ - uint32_t linear_id = plat_my_core_pos(); - - /* Update this cpu's statistics */ - tsp_stats[linear_id].smc_count++; - tsp_stats[linear_id].eret_count++; - -#if LOG_LEVEL >= LOG_LEVEL_INFO - spin_lock(&console_lock); - INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr()); - INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(), - tsp_stats[linear_id].smc_count, - tsp_stats[linear_id].eret_count); - spin_unlock(&console_lock); -#endif - - /* Indicate to the SPD that we have completed this request */ - return set_smc_args(TSP_SYSTEM_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); -} - -/******************************************************************************* - * This function performs any remaining bookkeeping in the test secure payload - * before the system is reset (in response to a psci SYSTEM_RESET request) - ******************************************************************************/ -tsp_args_t *tsp_system_reset_main(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7) -{ - uint32_t linear_id = plat_my_core_pos(); - - /* Update this cpu's statistics */ - tsp_stats[linear_id].smc_count++; - tsp_stats[linear_id].eret_count++; - -#if LOG_LEVEL >= LOG_LEVEL_INFO - spin_lock(&console_lock); - INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr()); - INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(), - tsp_stats[linear_id].smc_count, - tsp_stats[linear_id].eret_count); - spin_unlock(&console_lock); -#endif - - /* Indicate to the SPD that we have completed this request */ - return set_smc_args(TSP_SYSTEM_RESET_DONE, 0, 0, 0, 0, 0, 0, 0); -} - -/******************************************************************************* * TSP fast smc handler. The secure monitor jumps to this function by * doing the ERET after populating X0-X7 registers. The arguments are received * in the function arguments in order. Once the service is rendered, this * function returns to Secure Monitor by raising SMC. ******************************************************************************/ -tsp_args_t *tsp_smc_handler(uint64_t func, +smc_args_t *tsp_smc_handler(uint64_t func, uint64_t arg1, uint64_t arg2, uint64_t arg3, @@ -376,16 +217,12 @@ tsp_args_t *tsp_smc_handler(uint64_t func, tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; -#if LOG_LEVEL >= LOG_LEVEL_INFO - spin_lock(&console_lock); INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(), ((func >> 31) & 1) == 1 ? "fast" : "yielding", func); INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(), tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count); - spin_unlock(&console_lock); -#endif /* Render secure services and obtain results here */ results[0] = arg1; @@ -427,11 +264,7 @@ tsp_args_t *tsp_smc_handler(uint64_t func, break; case TSP_CHECK_DIT: if (!is_armv8_4_dit_present()) { -#if LOG_LEVEL >= LOG_LEVEL_ERROR - spin_lock(&console_lock); ERROR("DIT not supported\n"); - spin_unlock(&console_lock); -#endif results[0] = 0; results[1] = 0xffff; break; @@ -451,21 +284,3 @@ tsp_args_t *tsp_smc_handler(uint64_t func, results[1], 0, 0, 0, 0); } - -/******************************************************************************* - * TSP smc abort handler. This function is called when aborting a preempted - * yielding SMC request. It should cleanup all resources owned by the SMC - * handler such as locks or dynamically allocated memory so following SMC - * request are executed in a clean environment. - ******************************************************************************/ -tsp_args_t *tsp_abort_smc_handler(uint64_t func, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7) -{ - return set_smc_args(TSP_ABORT_DONE, 0, 0, 0, 0, 0, 0, 0); -} diff --git a/bl32/tsp/tsp_private.h b/bl32/tsp/tsp_private.h index 38d9732f5..66873e276 100644 --- a/bl32/tsp/tsp_private.h +++ b/bl32/tsp/tsp_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,28 +7,22 @@ #ifndef TSP_PRIVATE_H #define TSP_PRIVATE_H -/* Definitions to help the assembler access the SMC/ERET args structure */ -#define TSP_ARGS_SIZE 0x40 -#define TSP_ARG0 0x0 -#define TSP_ARG1 0x8 -#define TSP_ARG2 0x10 -#define TSP_ARG3 0x18 -#define TSP_ARG4 0x20 -#define TSP_ARG5 0x28 -#define TSP_ARG6 0x30 -#define TSP_ARG7 0x38 -#define TSP_ARGS_END 0x40 - +/******************************************************************************* + * The TSP memory footprint starts at address BL32_BASE and ends with the + * linker symbol __BL32_END__. Use these addresses to compute the TSP image + * size. + ******************************************************************************/ +#define BL32_TOTAL_LIMIT BL32_END +#define BL32_TOTAL_SIZE (BL32_TOTAL_LIMIT - (unsigned long) BL32_BASE) #ifndef __ASSEMBLER__ #include <stdint.h> -#include <platform_def.h> /* For CACHE_WRITEBACK_GRANULE */ - #include <bl32/tsp/tsp.h> #include <lib/cassert.h> #include <lib/spinlock.h> +#include <smccc_helpers.h> typedef struct work_statistics { /* Number of s-el1 interrupts on this cpu */ @@ -47,23 +41,22 @@ typedef struct work_statistics { uint32_t cpu_resume_count; /* Number of cpu resume requests */ } __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t; -typedef struct tsp_args { - uint64_t _regs[TSP_ARGS_END >> 3]; -} __aligned(CACHE_WRITEBACK_GRANULE) tsp_args_t; - /* Macros to access members of the above structure using their offsets */ #define read_sp_arg(args, offset) ((args)->_regs[offset >> 3]) #define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3]) \ = val) -/* - * Ensure that the assembler's view of the size of the tsp_args is the - * same as the compilers - */ -CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch); uint128_t tsp_get_magic(void); -tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, +smc_args_t *set_smc_args(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, uint64_t arg1, uint64_t arg2, uint64_t arg3, @@ -71,7 +64,7 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, uint64_t arg5, uint64_t arg6, uint64_t arg7); -tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, +smc_args_t *tsp_cpu_suspend_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, @@ -79,8 +72,8 @@ tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, uint64_t arg5, uint64_t arg6, uint64_t arg7); -tsp_args_t *tsp_cpu_on_main(void); -tsp_args_t *tsp_cpu_off_main(uint64_t arg0, +smc_args_t *tsp_cpu_on_main(void); +smc_args_t *tsp_cpu_off_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, @@ -101,7 +94,6 @@ void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3); /* Data structure to keep track of TSP statistics */ -extern spinlock_t console_lock; extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; /* Vector table of jumps */ @@ -111,7 +103,7 @@ extern tsp_vectors_t tsp_vector_table; int32_t tsp_common_int_handler(void); int32_t tsp_handle_preemption(void); -tsp_args_t *tsp_abort_smc_handler(uint64_t func, +smc_args_t *tsp_abort_smc_handler(uint64_t func, uint64_t arg1, uint64_t arg2, uint64_t arg3, @@ -120,25 +112,25 @@ tsp_args_t *tsp_abort_smc_handler(uint64_t func, uint64_t arg6, uint64_t arg7); -tsp_args_t *tsp_smc_handler(uint64_t func, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); +smc_args_t *tsp_smc_handler(uint64_t func, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); -tsp_args_t *tsp_system_reset_main(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7); +smc_args_t *tsp_system_reset_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); -tsp_args_t *tsp_system_off_main(uint64_t arg0, +smc_args_t *tsp_system_off_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, diff --git a/changelog.yaml b/changelog.yaml index 1a11c9baf..cfb2bb5cc 100644 --- a/changelog.yaml +++ b/changelog.yaml @@ -31,7 +31,7 @@ sections: type: ci hidden: true - - title: Build System + - title: Documentation description: Documentation-only changes type: docs hidden: true @@ -89,15 +89,42 @@ subsections: - title: Activity Monitors Extension (FEAT_AMU) scope: amu + - title: Branch Record Buffer Extension (FEAT_BRBE) + scope: brbe + + - title: Branch Target Identification Extension + scope: bti + + - title: Confidential Compute Architecture (CCA) + scope: cca + + - title: Extended Cache Index (FEAT_CCIDX) + scope: ccidx + - title: Support for the `HCRX_EL2` register (FEAT_HCX) scope: hcx - title: Memory Partitioning and Monitoring (MPAM) Extension (FEAT_MPAM) scope: mpam + - title: Memory Tagging Extension + scope: mte + + - title: Pointer Authentication Extension + scope: pauth + + - title: Performance Monitors Extension (FEAT_PMUv3) + scope: pmu + + - title: Trapping support for RNDR/RNDRRS (FEAT_RNG_TRAP) + scope: rng-trap + - title: Scalable Matrix Extension (FEAT_SME) scope: sme + - title: Statistical profiling Extension (FEAT_SPE) + scope: spe + - title: Scalable Vector Extension (FEAT_SVE) scope: sve @@ -113,15 +140,6 @@ subsections: - title: Self-hosted Trace Extensions (FEAT_TRF) scope: trf - - title: Statistical profiling Extension (FEAT_SPE) - scope: spe - - - title: Branch Record Buffer Extension (FEAT_BRBE) - scope: brbe - - - title: Extended Cache Index (FEAT_CCIDX) - scope: ccidx - - title: Platforms subsections: @@ -138,6 +156,12 @@ subsections: - plat/arm subsections: + - title: CSS + scope: css + + deprecated: + - plat/arm/css + - title: FPGA scope: fpga @@ -151,6 +175,7 @@ subsections: deprecated: - plat/fvp + - fvp/tsp_manifest - title: FVP-R scope: fvp-r @@ -158,6 +183,9 @@ subsections: deprecated: - fvp_r + - title: FVP Versatile Express + scope: fvp_ve + - title: Juno scope: juno @@ -200,6 +228,16 @@ subsections: - title: Broadcom scope: brcm + - title: HiSilicon + scope: hisilicon + + subsections: + - title: HiKey + scope: hikey + + - title: HiKey960 + scope: hikey960 + - title: Intel scope: intel @@ -247,6 +285,16 @@ subsections: deprecated: - plat/mediatek/mt8183 + - title: MT8186 + scope: mt8186 + + deprecated: + - plat/mediatek/mt8186 + - mt8186-emi-mpu + + - title: MT8188 + scope: mt8188 + - title: MT8192 scope: mt8192 @@ -261,12 +309,6 @@ subsections: - plat/mediatek/mt8195 - plat/mdeiatek/mt8195 - - title: MT8186 - scope: mt8186 - - deprecated: - - plat/mediatek/mt8186 - - title: NVIDIA scope: nvidia @@ -417,6 +459,9 @@ subsections: - title: QTI scope: qti + deprecated: + - plat/qti + subsections: - title: SC1780 scope: sc7180 @@ -437,6 +482,9 @@ subsections: scope: rpi subsections: + - title: Raspberry Pi 3 + scope: rpi3 + - title: Raspberry Pi 4 scope: rpi4 @@ -485,12 +533,19 @@ subsections: - plat/st subsections: - - title: ST32MP1 + - title: STM32MP1 scope: stm32mp1 deprecated: - plat/st/stm32mp1 + subsections: + - title: STM32MP13 + scope: stm32mp13 + + - title: STM32MP15 + scope: stm32mp15 + - title: Texas Instruments scope: ti @@ -498,6 +553,9 @@ subsections: - title: K3 scope: k3 + deprecated: + - ti-k3 + - title: Xilinx scope: xilinx @@ -513,6 +571,13 @@ subsections: - plat/xilinx/versal - plat/versal + subsections: + - title: Versal NET + scope: versal-net + + deprecated: + - versal_net + - title: ZynqMP scope: zynqmp @@ -536,6 +601,13 @@ subsections: - title: BL31 scope: bl31 + - title: BL32 + scope: bl32 + + subsections: + - title: TSP + scope: tsp + - title: Services scope: services @@ -549,10 +621,16 @@ subsections: - title: RME scope: rme + deprecated: + - rme/fid + subsections: - title: TRP scope: trp + - title: RMMD + scope: rmmd + - title: SPM scope: spm @@ -560,12 +638,21 @@ subsections: - title: EL3 SPMC scope: el3-spmc + deprecated: + - spmc + - title: SPMD scope: spmd - title: SPM MM scope: spm-mm + - title: DRTM + scope: drtm + + - title: TRNG + scope: trng + - title: Libraries subsections: @@ -587,6 +674,9 @@ subsections: - title: Context Management scope: cm + - title: RAS + scope: ras + - title: FCONF scope: fconf @@ -623,6 +713,18 @@ subsections: - title: PSA scope: psa + deprecated: + - lib/psa + + - title: Context Management + scope: context-mgmt + + deprecated: + - context mgmt + + - title: Semihosting + scope: semihosting + - title: Drivers subsections: @@ -636,6 +738,12 @@ subsections: - title: CryptoCell-713 scope: cc-713 + - title: Crypto + scope: crypto + + - title: mbedTLS + scope: mbedtls + - title: Generic Clock scope: clk @@ -694,6 +802,7 @@ subsections: deprecated: - scmi_common - drivers/scmi-msg + - scmi-msg - title: UFS scope: ufs @@ -715,7 +824,13 @@ subsections: - title: GICv3 scope: gicv3 + deprecated: + - gicv3/multichip + subsections: + - title: GIC-600 + scope: gic600 + - title: GIC-600AE scope: gic600ae @@ -1035,6 +1150,13 @@ subsections: deprecated: - fdts stm32mp1 + subsections: + - title: STM32MP13 + scope: stm32mp13-fdts + + - title: STM32MP15 + scope: stm32mp15-fdts + - title: PIE scope: pie @@ -1123,6 +1245,9 @@ subsections: - title: Certificate Creation Tool scope: cert-create + deprecated: + - cert_create + - title: Dependencies scope: deps @@ -1133,8 +1258,15 @@ subsections: - title: commitlint scope: commitlint + - title: Compiler runtime libraries + scope: compiler-rt + - title: libfdt scope: libfdt - title: Node Package Manager (NPM) scope: npm + + - title: zlib + scope: zlib + diff --git a/common/aarch32/debug.S b/common/aarch32/debug.S index 9d410df07..ae0bb7ac7 100644 --- a/common/aarch32/debug.S +++ b/common/aarch32/debug.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,8 @@ .globl asm_assert .globl do_panic .globl report_exception + .globl report_prefetch_abort + .globl report_data_abort /* Since the max decimal input number is 65536 */ #define MAX_DEC_DIVISOR 10000 @@ -205,3 +207,33 @@ func report_exception bl plat_report_exception no_ret plat_panic_handler endfunc report_exception + + /*********************************************************** + * This function is called from the vector table for + * unhandled exceptions. The lr_abt is given as an + * argument to platform handler. + ***********************************************************/ +func report_prefetch_abort +#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) + b report_exception +#else + mrs r0, lr_abt + bl plat_report_prefetch_abort + no_ret plat_panic_handler +#endif +endfunc report_prefetch_abort + + /*********************************************************** + * This function is called from the vector table for + * unhandled exceptions. The lr_abt is given as an + * argument to platform handler. + ***********************************************************/ +func report_data_abort +#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) + b report_exception +#else + mrs r0, lr_abt + bl plat_report_data_abort + no_ret plat_panic_handler +#endif +endfunc report_data_abort diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S index d105d0871..742e022d5 100644 --- a/common/aarch64/debug.S +++ b/common/aarch64/debug.S @@ -168,7 +168,7 @@ func do_panic mrs x0, currentel ubfx x0, x0, #MODE_EL_SHIFT, #MODE_EL_WIDTH cmp x0, #MODE_EL3 -#if !HANDLE_EA_EL3_FIRST +#if !HANDLE_EA_EL3_FIRST_NS ldr x0, [sp], #0x10 b.eq el3_panic #else @@ -184,7 +184,7 @@ func do_panic to_panic_common: ldr x0, [sp], #0x10 -#endif /* HANDLE_EA_EL3_FIRST */ +#endif /* HANDLE_EA_EL3_FIRST_NS */ #endif /* CRASH_REPORTING */ panic_common: diff --git a/common/backtrace/backtrace.c b/common/backtrace/backtrace.c index 25e2c707b..f994ae5b6 100644 --- a/common/backtrace/backtrace.c +++ b/common/backtrace/backtrace.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,15 +37,21 @@ struct frame_record { uintptr_t return_addr; }; -const char *get_el_str(unsigned int el) +static inline uintptr_t extract_address(uintptr_t address) { - if (el == 3U) { - return "EL3"; - } else if (el == 2U) { - return "EL2"; - } else { - return "S-EL1"; - } + uintptr_t ret = address; + +#if ENABLE_PAUTH + /* + * When pointer authentication is enabled, the LR value saved on the + * stack contains a PAC. It must be stripped to retrieve the return + * address. + */ + + xpaci(ret); +#endif + + return ret; } /* @@ -53,18 +59,11 @@ const char *get_el_str(unsigned int el) * the current EL, false otherwise. */ #ifdef __aarch64__ -static bool is_address_readable(uintptr_t addr) +static bool is_address_readable(uintptr_t address) { unsigned int el = get_current_el(); + uintptr_t addr = extract_address(address); -#if ENABLE_PAUTH - /* - * When pointer authentication is enabled, the LR value saved on the - * stack contains a PAC. It must be stripped to retrieve the return - * address. - */ - xpaci(addr); -#endif if (el == 3U) { ats1e3r(addr); } else if (el == 2U) { @@ -185,7 +184,8 @@ static void unwind_stack(struct frame_record *fr, uintptr_t current_pc, return; } - if (fr->return_addr != link_register) { + call_site = extract_address(fr->return_addr); + if (call_site != link_register) { printf("ERROR: Corrupted stack (frame record address = %p)\n", fr); return; @@ -207,16 +207,9 @@ static void unwind_stack(struct frame_record *fr, uintptr_t current_pc, * call was made is the instruction before the return address, * which is always 4 bytes before it. */ - call_site = fr->return_addr - 4U; -#if ENABLE_PAUTH - /* - * When pointer authentication is enabled, the LR value saved on - * the stack contains a PAC. It must be stripped to retrieve the - * return address. - */ - xpaci(call_site); -#endif + call_site = extract_address(fr->return_addr) - 4U; + /* * If the address is invalid it means that the frame record is * probably corrupted. diff --git a/common/bl_common.c b/common/bl_common.c index 9bfaafd2b..8fce02fba 100644 --- a/common/bl_common.c +++ b/common/bl_common.c @@ -269,3 +269,12 @@ void print_entry_point_info(const entry_point_info_t *ep_info) #endif #undef PRINT_IMAGE_ARG } + +/* + * This function is for returning the TF-A version + */ +const char *get_version(void) +{ + extern const char version[]; + return version; +} diff --git a/common/fdt_fixup.c b/common/fdt_fixup.c index b1d628cc0..1bad74fe6 100644 --- a/common/fdt_fixup.c +++ b/common/fdt_fixup.c @@ -583,3 +583,44 @@ int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, (ac + sc + ac) * 4, val, sc * 4); } +/** + * fdt_set_mac_address () - store MAC address in device tree + * @dtb: pointer to the device tree blob in memory + * @eth_idx: number of Ethernet interface in /aliases node + * @mac_addr: pointer to 6 byte MAC address to store + * + * Use the generic local-mac-address property in a network device DT node + * to define the MAC address this device should be using. Many platform + * network devices lack device-specific non-volatile storage to hold this + * address, and leave it up to firmware to find and store a unique MAC + * address in the DT. + * The MAC address could be read from some board or firmware defined storage, + * or could be derived from some other unique property like a serial number. + * + * Return: 0 on success, a negative libfdt error value otherwise. + */ +int fdt_set_mac_address(void *dtb, unsigned int ethernet_idx, + const uint8_t *mac_addr) +{ + char eth_alias[12]; + const char *path; + int node; + + if (ethernet_idx > 9U) { + return -FDT_ERR_BADVALUE; + } + snprintf(eth_alias, sizeof(eth_alias), "ethernet%d", ethernet_idx); + + path = fdt_get_alias(dtb, eth_alias); + if (path == NULL) { + return -FDT_ERR_NOTFOUND; + } + + node = fdt_path_offset(dtb, path); + if (node < 0) { + ERROR("Path \"%s\" not found in DT: %d\n", path, node); + return node; + } + + return fdt_setprop(dtb, node, "local-mac-address", mac_addr, 6); +} diff --git a/common/feat_detect.c b/common/feat_detect.c index 8f98876ac..ee3458865 100644 --- a/common/feat_detect.c +++ b/common/feat_detect.c @@ -234,6 +234,36 @@ static void read_feat_rme(void) #endif } +/****************************************************** + * Feature : FEAT_BRBE (Branch Record Buffer Extension) + *****************************************************/ +static void read_feat_brbe(void) +{ +#if (ENABLE_BRBE_FOR_NS == FEAT_STATE_1) + feat_detect_panic(is_feat_brbe_present(), "BRBE"); +#endif +} + +/****************************************************** + * Feature : FEAT_TRBE (Trace Buffer Extension) + *****************************************************/ +static void read_feat_trbe(void) +{ +#if (ENABLE_TRBE_FOR_NS == FEAT_STATE_1) + feat_detect_panic(is_feat_trbe_present(), "TRBE"); +#endif +} + +/****************************************************************** + * Feature : FEAT_RNG_TRAP (Trapping support for RNDR/RNDRRS) + *****************************************************************/ +static void read_feat_rng_trap(void) +{ +#if (ENABLE_FEAT_RNG_TRAP == FEAT_STATE_1) + feat_detect_panic(is_feat_rng_trap_present(), "RNG_TRAP"); +#endif +} + /*********************************************************************************** * TF-A supports many Arm architectural features starting from arch version * (8.0 till 8.7+). These features are mostly enabled through build flags. This @@ -284,6 +314,7 @@ void detect_arch_features(void) read_feat_mte(); read_feat_rng(); read_feat_bti(); + read_feat_rng_trap(); /* v8.6 features */ read_feat_amuv1p1(); @@ -294,6 +325,10 @@ void detect_arch_features(void) /* v8.7 features */ read_feat_hcx(); + /* v9.0 features */ + read_feat_brbe(); + read_feat_trbe(); + /* v9.2 features */ read_feat_rme(); } diff --git a/docs/about/features.rst b/docs/about/features.rst index 4b7fbe56b..cb8b5527a 100644 --- a/docs/about/features.rst +++ b/docs/about/features.rst @@ -46,8 +46,8 @@ Current features - A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP interaction with PSCI. -- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_ - and `Trusty Secure OS`_. +- SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_, + `Trusty Secure OS`_ and `ProvenCore Secure OS`_. - A Trusted Board Boot implementation, conforming to all mandatory TBBR requirements. This includes image authentication, Firmware Update (or @@ -121,6 +121,7 @@ Still to come .. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os .. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary .. _Trusty Secure OS: https://source.android.com/security/trusty +.. _ProvenCore Secure OS: https://provenrun.com/products/provencore/ -------------- diff --git a/docs/about/index.rst b/docs/about/index.rst index 3a102668c..06973ef16 100644 --- a/docs/about/index.rst +++ b/docs/about/index.rst @@ -4,7 +4,6 @@ About .. toctree:: :maxdepth: 1 :caption: Contents - :numbered: features release-information diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst index 871afe3f3..9a2ae73e7 100644 --- a/docs/about/maintainers.rst +++ b/docs/about/maintainers.rst @@ -48,7 +48,20 @@ Maintainers :|G|: `madhukar-Arm`_ :|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com> :|G|: `raghuncstate`_ +:|M|: Manish Badarkhe <manish.badarkhe@arm.com> +:|G|: `ManishVB-Arm`_ + +LTS Maintainers +--------------- +:|M|: Bipin Ravi <bipin.ravi@arm.com> +:|G|: `bipinravi-arm`_ +:|M|: Joanna Farley <joanna.farley@arm.com> +:|G|: `joannafarley-arm`_ +:|M|: Okash Khawaja <okash@google.com> +:|G|: `bytefire`_ +:|M|: Varun Wadekar <vwadekar@nvidia.com> +:|G|: `vwadekar`_ .. _code owners: @@ -65,26 +78,26 @@ Armv7-A architecture port Build Definitions for CMake Build System ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com> -:|G|: `javieralso-arm`_ :|M|: Chris Kay <chris.kay@arm.com> :|G|: `CJKay`_ :|F|: / Software Delegated Exception Interface (SDEI) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Mark Dykes <mark.dykes@arm.com> -:|G|: `mardyk01`_ +:|M|: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> +:|G|: `jayanthchidanand-arm`_ +:|M|: Manish Pandey <manish.pandey2@arm.com> +:|G|: `manish-pandey-arm`_ :|F|: services/std_svc/sdei/ Trusted Boot ^^^^^^^^^^^^ :|M|: Sandrine Bailleux <sandrine.bailleux@arm.com> :|G|: `sandrine-bailleux-arm`_ -:|M|: Manish Pandey <manish.pandey2@arm.com> -:|G|: `manish-pandey-arm`_ :|M|: Manish Badarkhe <manish.badarkhe@arm.com> :|G|: `ManishVB-Arm`_ +:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com> +:|G|: `laurenw-arm`_ :|F|: drivers/auth/ Secure Partition Manager Core (EL3 FF-A SPMC) @@ -97,28 +110,34 @@ Secure Partition Manager Dispatcher (SPMD) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Olivier Deprez <olivier.deprez@arm.com> :|G|: `odeprez`_ -:|M|: Manish Pandey <manish.pandey2@arm.com> -:|G|: `manish-pandey-arm`_ -:|M|: Maksims Svecovs <maksims.svecovs@arm.com> -:|G|: `max-shvetsov`_ :|M|: Joao Alves <Joao.Alves@arm.com> :|G|: `J-Alves`_ :|F|: services/std_svc/spmd/\* Exception Handling Framework (EHF) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Manish Badarkhe <manish.badarkhe@arm.com> -:|G|: `ManishVB-Arm`_ +:|M|: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> +:|G|: `jayanthchidanand-arm`_ +:|M|: Manish Pandey <manish.pandey2@arm.com> +:|G|: `manish-pandey-arm`_ :|F|: bl31/ehf.c +Realm Management Monitor Dispatcher (RMMD) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Javier Almansa Sobrino <javier.almansasobrino@arm.com> +:|G|: `javieralso-arm`_ +:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com> +:|G|: `AlexeiFedorov`_ +:|F|: services/std_svc/rmmd/\* +:|F|: include/services/rmmd_svc.h +:|F|: include/services/rmm_core_manifest.h + Realm Management Extension (RME) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Bipin Ravi <bipin.ravi@arm.com> -:|G|: `bipinravi-arm`_ -:|M|: Mark Dykes <mark.dykes@arm.com> -:|G|: `mardyk01`_ -:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com> -:|G|: `zelalem-aweke`_ +:|M|: Javier Almansa Sobrino <javier.almansasobrino@arm.com> +:|G|: `javieralso-arm`_ +:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com> +:|G|: `AlexeiFedorov`_ Drivers, Libraries and Framework Code ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -152,25 +171,35 @@ eMMC/UFS drivers :|F|: include/drivers/ufs.h :|F|: include/drivers/synopsys/dw_mmc.h +Arm® Ethosâ„¢-N NPU driver +^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Joshua Slater <joshua.slater@arm.com> +:|G|: `jslater8`_ +:|M|: Mikael Olsson <mikael.olsson@arm.com> +:|G|: `mikaelolsson-arm`_ +:|F|: drivers/arm/ethosn/ +:|F|: include/drivers/arm/ethosn.h +:|F|: plat/arm/common/fconf/fconf_ethosn_getter.c +:|F|: include/plat/arm/common/fconf_ethosn_getter.h +:|F|: fdts/juno-ethosn.dtsi + JTAG DCC console driver ^^^^^^^^^^^^^^^^^^^^^^^ -:M: Michal Simek <michal.simek@xilinx.com> +:M: Michal Simek <michal.simek@amd.com> :G: `michalsimek`_ -:M: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> +:M: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> :G: `venkatesh`_ :F: drivers/arm/dcc/ :F: include/drivers/arm/dcc.h Power State Coordination Interface (PSCI) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com> -:|G|: `javieralso-arm`_ +:|M|: Manish Pandey <manish.pandey2@arm.com> +:|G|: `manish-pandey-arm`_ :|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com> :|G|: `madhukar-Arm`_ :|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com> :|G|: `laurenw-arm`_ -:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com> -:|G|: `zelalem-aweke`_ :|F|: lib/psci/ DebugFS @@ -195,18 +224,27 @@ Performance Measurement Framework (PMF) :|G|: `J-Alves`_ :|F|: lib/pmf/ +Errata Management +^^^^^^^^^^^^^^^^^ +:|M|: Bipin Ravi <bipin.ravi@arm.com> +:|G|: `bipinravi-arm`_ +:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com> +:|G|: `laurenw-arm`_ + Arm CPU libraries ^^^^^^^^^^^^^^^^^ +:|M|: Bipin Ravi <bipin.ravi@arm.com> +:|G|: `bipinravi-arm`_ :|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com> :|G|: `laurenw-arm`_ :|F|: lib/cpus/ Reliability Availability Serviceabilty (RAS) framework ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Olivier Deprez <olivier.deprez@arm.com> -:|G|: `odeprez`_ :|M|: Manish Pandey <manish.pandey2@arm.com> :|G|: `manish-pandey-arm`_ +:|M|: Olivier Deprez <olivier.deprez@arm.com> +:|G|: `odeprez`_ :|F|: lib/extensions/ras/ Activity Monitors Unit (AMU) extensions @@ -219,28 +257,28 @@ Activity Monitors Unit (AMU) extensions Memory Partitioning And Monitoring (MPAM) extensions ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com> -:|G|: `zelalem-aweke`_ +:|M|: Manish Pandey <manish.pandey2@arm.com> +:|G|: `manish-pandey-arm`_ :|F|: lib/extensions/mpam/ Pointer Authentication (PAuth) and Branch Target Identification (BTI) extensions ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Alexei Fedorov <Alexei.Fedorov@arm.com> :|G|: `AlexeiFedorov`_ -:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com> -:|G|: `zelalem-aweke`_ :|F|: lib/extensions/pauth/ Statistical Profiling Extension (SPE) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com> -:|G|: `zelalem-aweke`_ +:|M|: Manish Pandey <manish.pandey2@arm.com> +:|G|: `manish-pandey-arm`_ :|F|: lib/extensions/spe/ Standard C library ^^^^^^^^^^^^^^^^^^ -:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com> -:|G|: `AlexeiFedorov`_ +:|M|: Chris Kay <chris.kay@arm.com> +:|G|: `CJKay`_ +:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com> +:|G|: `madhukar-Arm`_ :|F|: lib/libc/ Library At ROM (ROMlib) @@ -251,8 +289,8 @@ Library At ROM (ROMlib) Translation tables (``xlat_tables``) library ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com> -:|G|: `javieralso-arm`_ +:|M|: Manish Badarkhe <manish.badarkhe@arm.com> +:|G|: `ManishVB-Arm`_ :|M|: Joao Alves <Joao.Alves@arm.com> :|G|: `J-Alves`_ :|F|: lib/xlat\_tables_\*/ @@ -309,17 +347,23 @@ Firmware Encryption Framework Measured Boot ^^^^^^^^^^^^^ -:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com> -:|G|: `AlexeiFedorov`_ -:|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com> -:|G|: `javieralso-arm`_ :|M|: Sandrine Bailleux <sandrine.bailleux@arm.com> :|G|: `sandrine-bailleux-arm`_ +:|M|: Manish Badarkhe <manish.badarkhe@arm.com> +:|G|: `ManishVB-Arm`_ :|F|: drivers/measured_boot :|F|: include/drivers/measured_boot :|F|: docs/components/measured_boot :|F|: plat/arm/board/fvp/fvp\*_measured_boot.c +DRTM +^^^^ +:|M|: Manish Badarkhe <manish.badarkhe@arm.com> +:|G|: `ManishVB-Arm`_ +:|M|: Manish Pandey <manish.pandey2@arm.com> +:|G|: `manish-pandey-arm`_ +:|F|: services/std_svc/drtm + PSA Firmware Update ^^^^^^^^^^^^^^^^^^^ :|M|: Manish Badarkhe <manish.badarkhe@arm.com> @@ -354,8 +398,10 @@ Max Power Mitigation Mechanism (MPMM) Granule Protection Tables Library (GPT-RME) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Mark Dykes <mark.dykes@arm.com> -:|G|: `mardyk01`_ +:|M|: Soby Mathew <soby.mathew@arm.com> +:|G|: `soby-mathew`_ +:|M|: Javier Almansa Sobrino <javier.almansasobrino@arm.com> +:|G|: `javieralso-arm`_ :|F|: lib/gpt_rme :|F|: include/lib/gpt_rme @@ -460,10 +506,8 @@ Arm Reference Design platform ports Arm Total Compute platform port ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> -:|G|: `arugan02`_ -:|M|: Usama Arif <usama.arif@arm.com> -:|G|: `uarif1`_ +:|M|: Anders Dellien <anders.dellien@arm.com> +:|G|: `andersdellien-arm`_ :|F|: plat/arm/board/tc HiSilicon HiKey and HiKey960 platform ports @@ -611,6 +655,8 @@ QTI platform port :|G|: `lachitp`_ :|M|: Sreevyshanavi Kare <skare@codeaurora.org> :|G|: `sreekare`_ +:|M|: Muhammad Arsath K F <quic_mkf@quicinc.com> +:|G|: `quic_mkf`_ :|M|: QTI TF Maintainers <qti.trustedfirmware.maintainers@codeaurora.org> :|F|: docs/plat/qti.rst :|F|: plat/qti/ @@ -717,11 +763,11 @@ UniPhier platform port Xilinx platform port ^^^^^^^^^^^^^^^^^^^^ -:|M|: Michal Simek <michal.simek@xilinx.com> +:|M|: Michal Simek <michal.simek@amd.com> :|G|: `michalsimek`_ -:|M|: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> +:|M|: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> :|G|: `venkatesh`_ -:|F|: docs/plat/xilinx-zynqmp.rst +:|F|: docs/plat/xilinx\* :|F|: plat/xilinx/ @@ -762,11 +808,20 @@ Test Secure Payload (TSP) :|F|: bl32/tsp/ :|F|: services/spd/tspd/ +ProvenCore Secure Payload Dispatcher +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Jérémie Corbier <jeremie.corbier@provenrun.com> +:|G|: `jcorbier`_ +:|F|: docs/components/spd/pnc-dispatcher.rst +:|F|: services/spd/pncd/ + Tools ~~~~~ Fiptool ^^^^^^^ +:|M|: Manish Badarkhe <manish.badarkhe@arm.com> +:|G|: `ManishVB-Arm`_ :|M|: Joao Alves <Joao.Alves@arm.com> :|G|: `J-Alves`_ :|F|: tools/fiptool/ @@ -775,6 +830,10 @@ Cert_create tool ^^^^^^^^^^^^^^^^ :|M|: Sandrine Bailleux <sandrine.bailleux@arm.com> :|G|: `sandrine-bailleux-arm`_ +:|M|: Manish Badarkhe <manish.badarkhe@arm.com> +:|G|: `ManishVB-Arm`_ +:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com> +:|G|: `laurenw-arm`_ :|F|: tools/cert_create/ Encrypt_fw tool @@ -793,6 +852,8 @@ Sptool Build system ^^^^^^^^^^^^ +:|M|: Chris Kay <chris.kay@arm.com> +:|G|: `CJKay`_ :|M|: Manish Pandey <manish.pandey2@arm.com> :|G|: `manish-pandey-arm`_ :|F|: Makefile @@ -800,8 +861,6 @@ Build system Threat Model ~~~~~~~~~~~~~ -:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com> -:|G|: `zelalem-aweke`_ :|M|: Sandrine Bailleux <sandrine.bailleux@arm.com> :|G|: `sandrine-bailleux-arm`_ :|M|: Joanna Farley <joanna.farley@arm.com> @@ -819,6 +878,7 @@ Conventional Changelog Extensions :|F|: tools/conventional-changelog-tf-a .. _AlexeiFedorov: https://github.com/AlexeiFedorov +.. _andersdellien-arm: https://github.com/andersdellien-arm .. _Andre-ARM: https://github.com/Andre-ARM .. _Anson-Huang: https://github.com/Anson-Huang .. _bijucdas: https://github.com/bijucdas @@ -832,7 +892,9 @@ Conventional Changelog Extensions .. _grandpaul: https://github.com/grandpaul .. _hzhuang1: https://github.com/hzhuang1 .. _JackyBai: https://github.com/JackyBai +.. _jcorbier: https://github.com/jcorbier .. _jenswi-linaro: https://github.com/jenswi-linaro +.. _jslater8: https://github.com/jslater8 .. _jwerner-chromium: https://github.com/jwerner-chromium .. _kostapr: https://github.com/kostapr .. _lachitp: https://github.com/lachitp @@ -840,6 +902,7 @@ Conventional Changelog Extensions .. _marex: https://github.com/marex .. _masahir0y: https://github.com/masahir0y .. _michalsimek: https://github.com/michalsimek +.. _mikaelolsson-arm: https://github.com/mikaelolsson-arm .. _mmind: https://github.com/mmind .. _MrVan: https://github.com/MrVan .. _mtk-rex-bc-chen: https://github.com/mtk-rex-bc-chen @@ -847,6 +910,7 @@ Conventional Changelog Extensions .. _niej: https://github.com/niej .. _npoushin: https://github.com/npoushin .. _prabhakarlad: https://github.com/prabhakarlad +.. _quic_mkf: https://github.com/quicmkf .. _remi-triplefault: https://github.com/repk .. _rockchip-linux: https://github.com/rockchip-linux .. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm @@ -873,7 +937,6 @@ Conventional Changelog Extensions .. _max-shvetsov: https://github.com/max-shvetsov .. _javieralso-arm: https://github.com/javieralso-arm .. _laurenw-arm: https://github.com/laurenw-arm -.. _zelalem-aweke: https://github.com/zelalem-aweke .. _J-Alves: https://github.com/J-Alves .. _madhukar-Arm: https://github.com/madhukar-Arm .. _raghuncstate: https://github.com/raghuncstate @@ -891,5 +954,7 @@ Conventional Changelog Extensions .. _arve-android: https://github.com/arve-android .. _marcone: https://github.com/marcone .. _marcbonnici: https://github.com/marcbonnici +.. _jayanthchidanand-arm: https://github.com/jayanthchidanand-arm +.. _bytefire: https://github.com/bytefire .. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/ diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst index e9eaa80eb..dead4f7bb 100644 --- a/docs/about/release-information.rst +++ b/docs/about/release-information.rst @@ -52,22 +52,27 @@ depending on project requirement and partner feedback. +-----------------+---------------------------+------------------------------+ | v2.8 | 5th week of Nov '22 | 3rd week of Nov '22 | +-----------------+---------------------------+------------------------------+ +| v2.9 | 1st week of May '23 | 3rd week of Apr '23 | ++-----------------+---------------------------+------------------------------+ Removal of Deprecated Interfaces -------------------------------- -As mentioned in the :ref:`Platform Compatibility Policy`, this is a live -document cataloging all the deprecated interfaces in TF-A project and the -Release version after which it will be removed. +As mentioned in the :ref:`Platform Ports Policy`, this is a live document +cataloging all the deprecated interfaces in TF-A project and the Release version +after which it will be removed. +--------------------------------+-------------+---------+---------------------------------------------------------+ | Interface | Deprecation | Removed | Comments | | | Date | after | | | | | Release | | +================================+=============+=========+=========================================================+ -| STM32MP_USE_STM32IMAGE macro | Dec '21 | 2.7 | FIP is the recommended boot method for STM32MP | +| plat_convert_pk() function | Nov'22 | Next | Platform conversion to manage specific PK hash | +| | | release | | +| | | after | | +| | | 2.8 | | +--------------------------------+-------------+---------+---------------------------------------------------------+ -------------- -*Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/change-log.md b/docs/change-log.md index 1a6570018..bb05afbad 100644 --- a/docs/change-log.md +++ b/docs/change-log.md @@ -3,7 +3,921 @@ This document contains a summary of the new features, changes, fixes and known issues in each release of Trusted Firmware-A. -## [2.7.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.6.0..refs/tags/v2.7.0) (2022-05-20) +## [2.8.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.7.0..refs/tags/v2.8.0) (2022-11-15) + +### âš BREAKING CHANGES + +- **Drivers** + + - **Arm** + + - **Ethos-N** + + - add support for SMMU streams + + **See:** add support for SMMU streams ([b139f1c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b139f1cf975f9968eb8bd1182a173b976ecf06f9)) + +### New Features + +- **Architecture** + + - pass SMCCCv1.3 SVE hint bit to dispatchers ([0fe7b9f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0fe7b9f2bcdf754c483399c841e5f0ec71e53ef3)) + + - **Branch Record Buffer Extension (FEAT_BRBE)** + + - add brbe under feature detection mechanism ([1298f2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1298f2f13d6d97dfcac120a2ee68d5eea3797068)) + + - **Confidential Compute Architecture (CCA)** + + - introduce new "cca" chain of trust ([56b741d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56b741d3e41cd6b2f6863a372a9489c819e2b0e9)) + + - **Pointer Authentication Extension** + + - add/modify helpers to support QARMA3 ([9ff5f75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ff5f754aea00d0e86ba5191839fc0faef949fe0)) + + - **Trapping support for RNDR/RNDRRS (FEAT_RNG_TRAP)** + + - add EL3 support for FEAT_RNG_TRAP ([ff86e0b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ff86e0b4e6c34d28b8642dd8eb9cbdd517bad195)) + + - **Scalable Matrix Extension (FEAT_SME)** + + - fall back to SVE if SME is not there ([26a3351](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26a3351edab1501d7e19ae96540c34b2700ac32f)) + + - **Scalable Vector Extension (FEAT_SVE)** + + - support full SVE vector length ([bebcf27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bebcf27f1c75f48cc129e8608cba113d0db32ef8)) + + - **Trace Buffer Extension (FEAT_TRBE)** + + - add trbe under feature detection mechanism ([47c681b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47c681b7d7f03e77f6cdd7b5d116ae64671ab8ca)) + +- **Platforms** + + - **Arm** + + - add support for cca CoT ([f242379](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f24237921e3fa61e64fa1ec845e14e2748d04a2b)) + - forbid running RME-enlightened BL31 from DRAM ([1164a59](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1164a59cb16a9bbc672fa6d07895bc6fa0361bcb)) + - provide some swd rotpk files ([98662a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/98662a73c903b06f53c9f9da6a9404187fc10352)) + - retrieve the right ROTPK for cca ([50b4497](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50b449776df11cac06347e8ef1af5dae701a0e3a)) + + - **CSS** + + - add interrupt handler for reboot request ([f1fe144](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1fe1440db197d514b5484e780cfb90f504c62b9)) + - add per-cpu power down support for warm reset ([158ed58](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/158ed580bdf5736abfa9f16f61be1ca1609e0e41)) + + - **FVP** + + - add example manifest for TSP ([3cf080e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3cf080ed61e90668f0c44ca7f577e51c081e5c7c)) + - add crypto support in BL31 ([c9bd1ba](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c9bd1bacffd9697ec4ebac77e45588cf6c261a3b)) + - add plat API to set and get the DRTM error ([586f60c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/586f60cc571f0f3b6d20eb5033717e9b0cc66af4)) + - add plat API to validate that passed region is non-secure ([d5f225d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d5f225d95d3dc7473340ffebfcb9068b54f91a17)) + - add platform hooks for DRTM DMA protection ([d72c486](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d72c486b52dc654e4216d41dcc1b0f87bdbdf3e9)) + - build delegated attestation in BL31 ([0271edd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0271eddb0c00b01033bf651f0eeaf659c0c2dd39)) + - dts: drop 32-bit .dts files ([b920330](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b92033075aa27031091e184b54f4dc278ecb27bc)) + - fdts: update rtsm_ve DT files from the Linux kernel ([2716bd3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2716bd33e318821c373b3d4dce88110a340a740d)) + - increase BL31's stack size for DRTM support ([44df105](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44df105ff867aeb2aa5d20faa3e8389866099956)) + - increase MAX_XLAT_TABLES entries for DRTM support ([8a8dace](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a8dace5a5cd3a51d67df3cea86628f29cc96013)) + - support building RSS comms driver ([29e6fc5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29e6fc5cc7d0c8bc4ba615fd97df4cb65d3c7ba3)) + + - **RD** + + - **RD-N2** + + - add a new 'isolated-cpu-list' property ([afa4157](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/afa41571b856509c25c66c331737b895144b681b)) + - add SPI ID ranges for RD-N2 multichip platform ([9f0835e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9f0835e9156f13b56336a47a4b51e90719a852ff)) + - enable extended SPI support ([108488f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/108488f9ac026f036c0de2b824b339a30f9a0cbb)) + + - **SGI** + + - increase memory reserved for bl31 image ([a62cc91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a62cc91aeedbdcfb3396983ed165eb35b8d4c3fa)) + - read isolated cpu mpid list from sds ([4243ef4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4243ef41d480fd8e870f74defe263156a6c02c8d)) + - add page table translation entry for secure uart ([2a7e080](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2a7e080cc50be5739afcfb3b7db59e4d610a7d53)) + - bump bl1 rw size ([94df8da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94df8da3ab520330b2e7d276603f33e284c27b3f)) + - configure SRAM and BL31 size for sgi platform ([8fd820f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8fd820ffb918ad8fdc1f2c72cc64dad5eaff77aa)) + - deviate from arm css common uart related definitions ([173674a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/173674ae428aa23e8f2a38d5542d0ea52eed7e80)) + - enable css implementation of warm reset ([18884c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18884c002e6c298f27d6e4792eab2c9f4d89bddb)) + - remove override for `ARM_BL31_IN_DRAM` build-option ([a371327](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a371327ba9fc2e1c5988ac1436b29c42aab8dfd8)) + - route TF-A logs via secure uart ([0601083](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0601083f0ce0045bd957c1343d2196be0887973b)) + + - **TC** + + - add MHU addresses for AP-RSS comms on TC2 ([6299c3a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6299c3a0f7c8220b0bf15723ec8995b72bf97677)) + - add RSS-AP message size macro ([445130b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/445130b127f411bdf4958fa10f292a930c9ae57d)) + - add RTC PL031 device tree node ([a816de5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a816de564f927ebb72ab7692b8b3f46073179310)) + - enable RSS backend based measured boot ([6cb5d32](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cb5d3268fa41d15480c4e070a51577b333767fe)) + - increase maximum BL1/BL2/BL31 sizes ([e6c1316](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6c131655fa168ffd1ae738a74ba25e5f850036c)) + - introduce TC2 platform ([eebd2c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eebd2c3f61c90942fb186fa43fbb4c4a543d8b55)) + - move start address for BL1 to 0x1000 ([9335c28](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9335c28a019ee2d9ab7a0f9276b91415f3c9f1bc)) + + - **HiSilicon** + + - **HiKey960** + + - add a FF-A logical partition ([25a357f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/25a357f1932cf2b0d125dd98b82eeacad14005ea)) + - add memory sharing hooks for SPMC_AT_EL3 ([5f905a2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f905a249839e9e20ebf44c22d95caaf3a2e5611)) + - add plat-defines for SPMC_AT_EL3 ([feebd4c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/feebd4c7a86b6f0fcc1eb5008ba5f7d44e75beaf)) + - add SP manifest for SPMC_AT_EL3 ([6971642](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6971642d23d0c5e33e507eb78b7c569045e2f85d)) + - define a datastore for SPMC_AT_EL3 ([e618c62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e618c621b3ece7a0262ff9245027132982e6207c)) + - increase secure workspace to 64MB ([e0eea33](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0eea337b32e37bbef9bad1310b96b9c0d86f7b9)) + - read serial number from UFS ([c371b83](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c371b83f0c5b503c21bd1b6092bc0230032329ce)) + - upgrade to xlat_tables_v2 ([6cfc807](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cfc8078d032d278e09523e236ab5b36f69f2ec0)) + + - **MediaTek** + + - add more flexibility of mtk_pm.c ([6ca2046](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ca2046ef15dcf19fbda5f12cbfe1004d340c969)) + - add more options for build helper ([5b95e43](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5b95e439c745dcf94899238b82826d8f1d32acbe)) + - add smcc call for MSDC ([4dbe24c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4dbe24cf7d2b04c552f394062f42c30fee7e26a6)) + - extend SiP vendor subscription events ([99d30b7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99d30b72c02502731ecf116acfda44ee3c2c9e5e)) + - implement generic platform port ([394b920](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/394b92084d53e2bf8960731be7a79c999871f127)) + - introduce mtk init framework ([52035de](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52035dee1ae7b0f2f0d5f16c734ca7a5cea127b7)) + - move dp drivers to common folder ([d150b62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d150b6296e6960f2548b265b8b23e6cdb502d3b7)) + - move lpm drivers back to common ([cd7890d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cd7890d79e9d508e82f3078f02e8277f8c8df181)) + - move mtk_cirq.c drivers to cirq folder ([cc76896](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc76896d9e416b15548b2d6bf068e5d3f9b4064a)) + - support coreboot BL31 loading ([ef988ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef988aed9e09a4108b87decb14dee5f2d23230a4)) + + - **MT8186** + + - add EMI MPU support for SCP and DSP ([3d4b6f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3d4b6f932444c7b0f70f8654b92193b294527056)) + + - **MT8188** + + - add armv8.2 support ([45711e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/45711e4e1614fbed75ea645777cc2bb11d4be96f)) + - add audio support ([c70f567](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c70f567ad75c30a990cb60c71b6c0b02538366fd)) + - add cpu_pm driver ([4fe7e6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fe7e6a8d9f09c40d087167432cb07621c175b3f)) + - add DCM driver ([bc9410e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc9410e2376e0b6355ea6440aa90ad968fc5f3b3)) + - add DFD control in SiP service ([7079a94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7079a942bd9705fd9e0cd220324f7dfd9c53dcad)) + - add display port control in SiP service ([a4e5023](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a4e502319d136d8854ef2ed4aaa6d5368541e551)) + - add EMI MPU basic drivers ([8454f0d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8454f0d65eeb85b72f454376faa0f7a15226e240)) + - add IOMMU enable control in SiP service ([be45724](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be457248c6b0a7f3c61bd95af58372938d13decd)) + - add LPM driver support ([f604e4e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f604e4ef6e306c6d87e17e77e50a68aad0510110)) + - add MCUSYS support ([4cc1ff7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4cc1ff7ef2c3544ef1aabeb2973a2d8f7800776b)) + - add pinctrl support ([ec4cfb9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ec4cfb91fc197a024d1edb9fae5e9ce100e5b200)) + - add pmic and pwrap support ([e9310c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e9310c34b018944a6c29a8f408f0a34b43a0df6d)) + - add reset and poweroff functions ([a72b9e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a72b9e7754a27e6ebccf79f0cc4fb7cc5a0a8a5e)) + - add RTC support ([af5d8e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af5d8e07955ddef9000c64de94deb2703e6ffcf0)) + - add support for PTP3 ([44a1051](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44a10511c9e5a66b3a33abba44856a7a5dc5e655)) + - apply ERRATA for CA-78 ([abb995a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/abb995abbe45874a397351cbb134ae32d4cc545b)) + - enable MTK_PUBEVENT_ENABLE ([0b1186a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0b1186a3e6fd6daffaef3f6cf59650bb9121191c)) + - initialize GIC ([cfb0516](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cfb0516f3cc36e3d0ec9b0bdabf1eb6ea2b275c1)) + - initialize platform for MediaTek MT8188 ([de310e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/de310e1e5f0b76b9de2b93759344540e0109c8eb)) + - initialize systimer ([215869c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/215869c693c136192505a004ec368f503f146505)) + + - **NXP** + + - **i.MX** + + - **i.MX 8M** + + - add dram retention flow for imx8m family ([c71793c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c71793c6476fa2828f866b8d7b272289f0d9a15c)) + - add support for high assurance boot ([720e7b6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/720e7b66f2353ef7ed32a8f85f8396fbc0766ffc)) + - add the anamix pll override setting ([66d399e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/66d399e454b160ce358346cfa9142a24d8493a41)) + - add the ddr frequency change support for imx8m family ([9c336f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c336f6118a94970f4045641a971fd1e24dba462)) + - add the PU power domain support on imx8mm/mn ([44dea54](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44dea5444b087acd758b1c8370999be635e17e43)) + - keep pu domains in default state during boot stage ([9d3249d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9d3249de8078e33b90193d8f91f4914acc36c6ec)) + - make psci common code pie compatible ([5d2d332](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d2d3328db88846accd179c96d71bab79a150937)) + + - **i.MX 8M Nano** + + - add BL31 PIE support ([62d37a4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62d37a4362456694bdae6d8921c2c7572a0d99a4)) + - add hab and map required memory blocks ([b5f06d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b5f06d3dfad8c27bdf528b083ef919ce4022c52d)) + - enable dram retention suuport on imx8mn ([2003fa9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2003fa94dc9b9eda575ebfd686308c6f87c366f0)) + + - **i.MX 8M Mini** + + - add BL31 PIE support ([a8e6a2c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a8e6a2c83ce511dad88eb68f98a3191fa93564d4)) + - add hab and map required memory blocks ([5941f37](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5941f37288a5ceac495cbdbd3e3d02f1a3c55e0a)) + - enable dram retention suuport on imx8mm ([b7abf48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b7abf485ee15c3e5b16522bb91dd6b0c24bfbfc0)) + + - **i.MX 8M Plus** + + - add BL31 PIE support ([7a443fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a443fefa4eaef65332a38c8189573b5b4b4a1e3)) + - add hab and map required memory blocks ([62a93aa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62a93aa7afcd022f06d322c36979f0aa02713beb)) + + - **i.MX 8Q** + + - add 100us delay after USB OTG SRC bit 0 clear ([66345b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/66345b8b13dc32bcd9f6af3c04f60532e7d82858)) + + - **Layerscape** + + - **LS1043A** + + - **LS1043ARDB** + + - update ddr configure for ls1043ardb-pd ([18af644](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18af644279b36e841068db0e1c857dedf1456b38)) + + - **QEMU** + + - increase size of bl31 ([0e6977e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e6977eee178a6436e4a7e1503ea854989316ff4)) + + - **QTI** + + - fix to support cpu errata ([6cc743c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cc743cf0fa9b216f2af8ff87c716dcc0bb6f6a0)) + - updated soc version for sc7180 and sc7280 ([39fdd3d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39fdd3d85d1165cd1b876288532000c5c6eb1ecb)) + + - **Socionext** + + - **Synquacer** + + - add BL2 support ([48ab390](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/48ab390444e1dabb669430ace9b8e5a80348eed0)) + - add FWU Multi Bank Update support ([a193825](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a19382521c583b3dde89df14678b011960097f6c)) + - add TBBR support ([19aaeea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/19aaeea00bc4fba94af7aca508af878136930f4a)) + + - **ST** + + - add trace for early console ([00606df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/00606df01201fcad509ea9ddff89d5f176bee793)) + - enable MMC_FLAG_SD_CMD6 for SD-cards ([53d5b8f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53d5b8ff50d322f764b1f5a8c882b9ee1ba952c9)) + - properly manage early console ([5223d88](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5223d88032dcecb880d620e63bfa70799dc6cc1a)) + - search pinctrl node by compatible ([b14d3e2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b14d3e22b4964ce589d107e7fd68601bf070f44c)) + + - **STM32MP1** + + - add a check on TRUSTED_BOARD_BOOT with secure chip ([54007c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/54007c37d560dd170efa52a79feb206aefb90ed4)) + - add a stm32mp crypto library ([ad3e46a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad3e46a35cb208e16adfe3d753214739583dca10)) + - add define for external scratch buffer for nand devices ([9ee2510](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ee2510b62ef9428d767523ddb9c5a39b7a2b954)) + - add early console in SP_min ([14a0704](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/14a070408d9231dc1c487dfe36058b93faf5915c)) + - add plat_report_*_abort functions ([0423868](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0423868373026a667f0c004e4d365fa12fd734ef)) + - add RNG initialization in BL2 for STM32MP13 ([2742374](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2742374414c5891ac37fd4d42ba62c3cff1474c6)) + - add the decryption support ([cd79116](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cd791164a9ad2f42d25d24012715bbe763b41e1c)) + - add the platform specific build for tools ([461d631](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/461d631acae9daec77c9668216280cbf66240249)) + - add the TRUSTED_BOARD_BOOT support ([beb625f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/beb625f90bfd1858b9d413cae67457e57c79a118)) + - allow to override MTD base offset ([e0bbc19](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0bbc190d500e53ee0566af85639d3cdbbe7177d)) + - configure the serial boot load address ([4b2f23e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b2f23e55f27b6baccf3e858234e69685d51fcf4)) + - extend STM32MP_EMMC_BOOT support to FIP format ([95e4908](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95e4908e17fbb44aed1f8612fefdd6d21fef8f49)) + - manage second NAND OTP on STM32MP13 ([d3434dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d3434dca0b3acb902fe3a6cf39065ba917f69b1c)) + - manage STM32MP13 rev.Y ([a3f97f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a3f97f66c36e987a6617f1f39c3b9e64b763212c)) + - optionally use paged OP-TEE ([c4dbcb8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4dbcb885201c89a44df203661af007945782993)) + - remove unused function from boot API ([f30034a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f30034a298a8d7260464cbcf2d2306bff533d6dd)) + - retrieve FIP partition by type UUID ([1dab28f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1dab28f99dfa03dc11538056a90f00f37bfb1085)) + - save boot auth status and partition info ([ab2b325](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab2b325c1ab895e626d4e11a9f26b9e7c968f8d8)) + - update ROM code API for header v2 management ([89c0774](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/89c07747d0396b92c83af8736ff49ef8c09bc176)) + + - **STM32MP13** + + - change BL33 memory mapping ([10f6dc7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10f6dc789350ed5915a474b2d411890261b741ae)) + + - **STM32MP15** + + - manage OP-TEE shared memory ([722ca35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/722ca35ecc1c5de8682ca8df315a6369d0c21946)) + + - **Texas Instruments** + + - **K3** + + - add support for J784S4 SoCs ([4a566b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4a566b26ae6135d4c13deab9d3f1c40c1cb8960a)) + + - **Xilinx** + + - **Versal** + + - add infrastructure to handle multiple interrupts ([e497421](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e497421d7f1e13d15313d1ca71a8e91f370cce1e)) + - get the handoff params using IPI ([205c7ad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/205c7ad4cd73e5c091b03f23a3a3be74da5c8aea)) + - resolve the misra 10.1 warnings ([b86e1aa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b86e1aade1c0953bd60ae0b35f1c3571ee8bae3f)) + - update macro name to generic and move to common place ([f99306d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f99306d49ba074279c5402a0a34e6bc9797d77de)) + + - **Versal NET** + + - add support for QEMU COSIM platform ([6a079ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a079efd909b459448f561618df24fa94038dbad)) + - add documentation for Versal NET SoC ([4efdc48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4efdc488961502033262613b6f20abcee68bbf84)) + - add SMP support for Versal NET ([8529c76](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8529c7694f8d614e76dcc80b394ec8a6751df44c)) + - add support for IPI ([0bf622d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0bf622de68cd353a8406f76647b6afd8791d675d)) + - add support for platform management ([0654ab7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0654ab7f75449307c79789e12be7aab2338edcc3)) + - add support for Xilinx Versal NET platform ([1d333e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d333e69091f0c71854a224e8cfec08695b7d1f3)) + + - **ZynqMP** + + - optimization on pinctrl_functions ([314f9f7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/314f9f7957fbab12dc8d073cf054b99520372e0e)) + - add support for ProvenCore ([358aa6b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/358aa6b21118ae4eedf816f663aa950b58f7fd4e)) + - add support for xck24 silicon ([86869f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/86869f99d0c144ed18fb947866554a4a56b67741)) + - protect eFuses from non-secure access ([d0b7286](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0b7286e48f0a34e7e9a8db3948caf1809193430)) + - resolve the misra 10.1 warnings ([bfd7c88](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bfd7c881905702082e3c2a56d5228ccf5fe98f11)) + +- **Bootloader Images** + + - add interface to query TF-A semantic ver ([dddf428](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dddf4283b043ad0a81d27bd5bb2f0c647c511e11)) + + - **BL32** + + - **TSP** + + - add FF-A support to the TSP ([4a8bfdb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4a8bfdb90956ecec02ba5e189fe5452817a65179)) + - add ffa_helpers to enable more FF-A functionality ([e9b1f30](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e9b1f300a974a7e82190b95899c3128b73088488)) + - enable test cases for EL3 SPMC ([15ca1ee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15ca1ee342a4dcd8a73a4ae158d245cd4266c832)) + - increase stack size for tsp ([5b7bd2a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5b7bd2af0b2972dfffeaa674947c0082d6b5126b)) + +- **Services** + + - add a SPD for ProvenCore ([b0980e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0980e584398fc5adc908cd68f1a6deefa943d29)) + + - **RME** + + - **RMMD** + + - add support for RMM Boot interface ([8c980a4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8c980a4a468aeabb9e49875fec395c625a0c2b2b)) + - add support to create a boot manifest ([1d0ca40](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d0ca40e9084903d21e570bb312646626aaf574b)) + + - **SPM** + + - add tpm event log node to spmc manifest ([054f0fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/054f0fe1361ba0cb339fb0902470988a82a24cf7)) + + - **SPMD** + + - avoid spoofing in FF-A direct request ([5519f07](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5519f07cd46a4139615a3e8f5e57d1834b23a6f8)) + + - **DRTM** + + - add a few DRTM DMA protection APIs ([2b13a98](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b13a985994213f766ada197427f96e064f1b59b)) + - add DRTM parameters structure version check ([c503ded](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c503ded2c5d9ceec9fba4cc0901805307a14af3d)) + - add Event Log driver support for DRTM ([4081426](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40814266d53b7154daf5d212de481b397db43823)) + - add PCR entries for DRTM ([ff1e42e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ff1e42e20aa247ba11cf81742abff07ece376ba8)) + - add platform functions for DRTM ([2a1cdee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2a1cdee4f5e6fe0b90399e442075880acad1869e)) + - add remediation driver support in DRTM ([1436e37](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1436e37dcb894a539a22da48a34ef01566ae728b)) + - add standard DRTM service ([e62748e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e62748e3f1f16934f0ef2d5742f3ca0b125eaea2)) + - check drtm arguments during dynamic launch ([40e1fad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40e1fad69b9f28ab5e57cea33261bf629b05519c)) + - ensure that no SDEI event registered during dynamic launch ([b1392f4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b1392f429cdd368ea2b8e183a1ac0fb31deaf694)) + - ensure that passed region lies within Non-Secure region of DRAM ([764aa95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/764aa951b2ca451694c74791964a712d423d8206)) + - flush dcache before DLME launch ([67471e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/67471e75b3cf48c361e71894a666bce4395bbb35)) + - introduce drtm dynamic launch function ([bd6cc0b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd6cc0b2388c52f2b232427be61ff52c042d724a)) + - invalidate icache before DLME launch ([2c26597](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2c265975a76977c6373636f5f28e114d1b73e10e)) + - prepare DLME data for DLME launch ([d42119c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d42119cc294fbca2afc263fe5e44538a0ca5e7b8)) + - prepare EL state during dynamic launch ([d1747e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1747e1b8e617ad024456791ce0ab8950bb282ca)) + - retrieve DRTM features ([e9467af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e9467afb2d483ccec8f816902624d848e8f21d86)) + - take DRTM components measurements before DLME launch ([2090e55](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2090e55283c4bf85c7a61735ca0e872745c55896)) + - update drtm setup function ([d54792b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d54792bd93f76b943bf0559c8373b898e0e3b93c)) + +- **Libraries** + + - **CPU Support** + + - add library support for Hunter ELP ([8c87bec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8c87becbc64f2e233ac905aa006d5e15a63a9a8b)) + - add a64fx cpu to tf-a ([74ec90e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/74ec90e69bbd0e932a61f5461eedc4abd1b99d44)) + - make cache ops conditional ([04c7303](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04c7303b9c3d2215eebc3d59431519990abe03d0)) + - remove plat_can_cmo check for aarch32 ([92f8be8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/92f8be8fd1e77be67e9c9711afa8705204758304)) + - update doc and check for plat_can_cmo ([a2e0123](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a2e0123484e62df8ed9f2943dbd158471bf31221)) + + - **OP-TEE** + + - check paged_image_info ([c0a11cd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0a11cd8698394e1d3d3d7c9cedb19846ba59223)) + + - **PSCI** + + - add a helper function to ensure that non-boot PEs are offline ([ce14a12](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ce14a12f8b8f02b7221f37c7c4b46f909c1a4346)) + + - **C Standard Library** + + - introduce __maybe_unused ([351f9cd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/351f9cd8897fd3ea52db2421721a152494b16328)) + + - **PSA** + + - add delegated attestation partition API ([4b09ffe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b09ffef49663ebc8c8f5c3da19636208fe2fa06)) + - remove initial attestation partition API ([420deb5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/420deb5a0dbbd35962e5449f82434c703e7a1179)) + +- **Drivers** + + - **Authentication** + + - allow to verify PublicKey with platform format PK ([40f9f64](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40f9f644e8af34e745dbaec73d7128c0a4902e54)) + - enable MBEDTLS_CHECK_RETURN_WARNING ([a4e485d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a4e485d7bf1c428d64e90e9821e4b1a109d10626)) + + - **Crypto** + + - update crypto module for DRTM support ([e43caf3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e43caf3890817e91b3d35b5ae1149a208f1a4016)) + + - **mbedTLS** + + - update mbedTLS driver for DRTM support ([8b65390](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b653909b7e2371c6dcddbeac112b9671c886f34)) + + - **I/O** + + - **MTD** + + - add platform function to allow using external buffer ([f29c070](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f29c0702d2e7a67327b67766f91793d8ae6d0f73)) + + - **MMC** + + - get boot partition size ([f462c12](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f462c1249ac41f43423011bb12ace38cbeb0af4c)) + - manage SD Switch Function for high speed mode ([e5b267b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5b267bba14c55e7906d120c52d4e8e8bbb68df6)) + + - **MTD** + + - add platform function to allow using external buffer ([f29c070](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f29c0702d2e7a67327b67766f91793d8ae6d0f73)) + + - **GUID Partition Tables Support** + + - allow to find partition by type UUID ([564f5d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/564f5d477663bc007916a11c48bdd8b9be4ad369)) + + - **SCMI** + + - send powerdown request to online secondary cpus ([14a2892](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/14a289230918b23b0985e215d38614dc7480bd02)) + - set warm reboot entry point ([5cf9cc1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cf9cc130a90fd8c4503c57ec4af235b469fd473)) + + - **Arm** + + - **Ethos-N** + + - add support for SMMU streams ([b139f1c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b139f1cf975f9968eb8bd1182a173b976ecf06f9)) + + - **GIC** + + - add APIs to raise NS and S-EL1 SGIs ([dcb31ff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dcb31ff79096fc88b45df8068e5de83b93f833ed)) + + - **GICv3** + + - validate multichip data for GIC-700 ([a78b3b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a78b3b382b07675a89a66ddffe926ed225eeb245)) + + - **RSS** + + - add new comms protocols ([3125901](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31259019235aebf7aa533d5c893940f597fb1a8b)) + + - **ST** + + - **Crypto** + + - add AES decrypt/auth by SAES IP ([4bb4e83](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4bb4e836498b0131feefbba3f857a0bf3b89e543)) + - add ECDSA signature check with PKA ([b0fbc02](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0fbc02aea76d31e749444da63b084e6b2bd089b)) + - add STM32 RNG driver ([af8dee2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af8dee20d5fee29f34ccd9b9556e0c23655ff549)) + - remove BL32 HASH driver usage ([6b5fc19](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b5fc19227ff8935b1352c0e4c0d716ebee60aa2)) + - update HASH for new hardware version used in STM32MP13 ([68039f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68039f2d14626adce09512871d6cde20ff45e1d9)) + + - **SDMMC2** + + - define FIFO size ([b46f74d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b46f74d4e68ee08b6e912cd7f855a16cc5e79a6a)) + - make reset property optional ([8324b16](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8324b16cd5e0b1ae2f85264a74f879e8fb1bca2a)) + - manage CMD6 ([3deebd4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3deebd4ccf39904d7fe777f53e9dbaa86691d653)) + + - **UART** + + - add initialization with the device tree ([d99998f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d99998f76ed2e8676be25e31e9479a90c16c7098)) + - manage STM32MP_RECONFIGURE_CONSOLE ([ea69dcd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ea69dcdc737d8b48fec769042922914e988153ef)) + +- **Miscellaneous** + + - **Debug** + + - add AARCH32 CP15 fault registers ([bb22891](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb2289142cbf0f3546c1034e0500b5dc32aef740)) + - add helpers for aborts on AARCH32 ([6dc5979](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6dc5979a6cb2121e4c16e7bd62e24030e0f42755)) + + - **FDTs** + + - **STM32MP1** + + - add CoT and fuse references for authentication ([928fa66](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/928fa66272a0985c900c996912b54904c64d0520)) + - change pin-controller to pinctrl ([44fea93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44fea93bf729f631f6ae47e06ac7b6012a795791)) + + - **STM32MP13** + + - use STM32MP_DDR_S_SIZE in fw-config ([936f29f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/936f29f6b51b3c7f37fd34e30a7f1f7c3944b361)) + + - **STM32MP15** + + - add Avenger96 board with STM32MP157A DHCOR SoM ([51e2230](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/51e223058fe70b311542178f1865514745fa7874)) + - add support for STM32MP157C based DHCOM SoM on PDK2 board ([eef485a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eef485abb13b6df9a94137edd82904aab0ecf02d)) + + - **SDEI** + + - add a function to return total number of events registered ([e6381f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6381f9cf8c0c62c32d5a4765aaf166f50786914)) + + - **TBBR** + + - increase PK_DER_LEN size ([1ef303f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ef303f9f79020330bbd8e48ac652e8f2121a41b)) + +- **Tools** + + - **Firmware Image Package Tool** + + - add cca, core_swd, plat cert in FIP ([147f52f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/147f52f3e81f7ccf1dae90bc5687ec137feeb46c)) + + - **Certificate Creation Tool** + + - define the cca chain of trust ([0a6bf81](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0a6bf811d7f873a180ef4b9f96f5596b26d270c6)) + - update for ECDSA brainpoolP256r/t1 support ([e78ba69](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e78ba69e3525c968118eb91f443b1e9db9eee5f5)) + +- **Dependencies** + + - **Compiler runtime libraries** + + - update compiler-rt source files ([8a6a956](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a6a9560b5dcccfb68064c0c8c9b4b47981c6ac7)) + + - **libfdt** + + - add function to set MAC addresses ([1aa7e30](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1aa7e302a84bbf46a97bcfbb54b6b6d57de76cee)) + - upgrade libfdt source files ([94b2f94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94b2f94bd63258c300b53ad421488c3c4455712b)) + + - **zlib** + + - update zlib source files ([a194255](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a194255d75ed9e2ef56bd6e14349a3e7d86af934)) + +### Resolved Issues + +- **Architecture** + + - **Performance Monitors Extension (FEAT_PMUv3)** + + - add sensible default for MDCR_EL2 ([7f85619](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f8561985778cbe5cdc7d57984c818119e87adaf)) + + - **Scalable Matrix Extension (FEAT_SME)** + + - add missing ISBs ([46e92f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/46e92f2862326cbe57acecb2d0f3c2ffbcc176d2)) + +- **Platforms** + + - **Arm** + + - **FVP** + + - fdts: Fix idle-states entry method ([0e3d880](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e3d88070f69c6aa7cc51a2847cbba3535992397)) + - fdts: fix memtimer subframe addressing ([3fd12bb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3fd12bb8c622917d8491082b1472c39efb89c0cf)) + - fdts: unify and fix PSCI nodes ([6b2721c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b2721c01691743a65475e82944e2f8868bf0159)) + + - **FVP Versatile Express** + + - fdts: Fix vexpress,config-bus subnode names ([60da130](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/60da130a8c5ac29bc35870180c35ca04db506e0f)) + + - **Morello** + + - dts: add model names ([30df890](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/30df8904d0f6973bbce1ecb51f14c1e4725ddf0b)) + - dts: fix DP SMMU IRQ ordering ([fba729b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fba729b0ca22be379792ce677296cda075036753)) + - dts: fix DT node naming ([41c310b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/41c310b4f691c1eefcd0234619bc751966389297)) + - dts: fix GICv3 compatible string ([982f258](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/982f2585bb27b58c017af70d852a433f36711db1)) + - dts: fix SCMI shmem/mboxes grouping ([8aeb1fc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8aeb1fcf832d4e06157a1bed1d18ba244c1fe9ee)) + - dts: fix SMMU IRQ ordering ([5016ee4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5016ee44a740127f7865dc26ed0efbbff1481c7e)) + - dts: fix stdout-path target ([67a8a5c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/67a8a5c92e7c65108b3cdf6f4f9dd2de7e22f3cd)) + - dts: remove #a-c and #s-c from memory node ([f33e113](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f33e113c7a7dffd8ed219f25191907fd64bcf19f)) + - dts: use documented DPU compatible string ([3169572](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3169572ed1bf0de17bb813583cab7ea295a8ec8d)) + - move BL31 to run from DRAM space ([05330a4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/05330a49cd91c346a8b9dc3aff35d0032db4d413)) + + - **N1SDP** + + - add numa node id for pcie controllers ([2974d2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2974d2f2d03e842ed5e01e2e04dd3de6c1d07277)) + - mapping Run-time UART to IOFPGA UART0 ([4a81e91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4a81e91f2752a817364e1fccedb08bb453ad5a56)) + - replace non-inclusive terms from dts file ([e6ffafb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6ffafbeeae8c78abac37475f19899f0c98523ca)) + + - **TC** + + - resolve the static-checks errors ([066450a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/066450abf326f1a68a21cdddf29f62eff95041a9)) + - tc2 bl1 start address shifted by one page ([8597a8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8597a8cbc23f0f03a15d013dd44a4ed59c991872)) + + - **Intel** + + - fix asynchronous read response by copying data to input buffer ([dd7adcf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd7adcf3a89a75973a88118eeb867d1c212c4ad0)) + - fix Mac verify update and finalize for return response data ([fbf7aef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbf7aef408a9f67fabc712bbfd52438290364879)) + + - **MediaTek** + + - remove unused cold_boot.[c|h] ([8cd3b69](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8cd3b693d6d5d3db2433a96c5f2905d92a387cc4)) + - switch console to runtime state before leaving BL31 ([fcf4dd9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcf4dd9f794b28bbfff3ee7d66bac8d5e260f46a)) + - use uppercase for definition ([810d568](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/810d568141050db7d500c5f5ad91efaff93d2036)) + - wrap cold_boot.h with MTK_SIP_KERNEL_BOOT_ENABLE ([24476b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24476b2e6128dae2ca2ac46344e18f6f02eae7bf)) + + - **MT8186** + + - fix SCP permission ([8a998b5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a998b5aca3ca895a7722e7496a7fd18cd838f94)) + - fix EMI_MPU domain setting for DSP ([28a8b73](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/28a8b738feaade74f23af0e889005e687fde38b5)) + - fix the DRAM voltage after the system resumes ([600f168](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/600f168172a9281a0061f84e4da5318e08762aa1)) + - move SSPM base register definition to platform_def.h ([2a2b51d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2a2b51d8f76e2acdabb431e928beb90e0a30c87c)) + + - **MT8188** + + - add mmap entry for CPU idle SRAM ([32071c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32071c0263899e0e7a4b7f2c754e6363547f33b1)) + - refine c-state power domain for extensibility ([e35f4cb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e35f4cbf80ba671c42644c1ac7f8f6541042c6e5)) + - refine gic init flow after system resume ([210ebbb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/210ebbb0a6a0520cb3a5930c4fefa94baee33462)) + + - **NXP** + + - **i.MX** + + - **i.MX 8M** + + - correct serial output for HAB JR0 ([6e24d79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e24d795094e7fac1edc13336ce0bfd39d98e66f)) + - fix dram retention fsp_table access ([6c8f523](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6c8f523138cd94bc0608708e821a09b02c8c2f5a)) + - move caam init after serial init ([901d74b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/901d74b2d46cbd8b1d27477fa16388520fdabab1)) + - update poweroff related SNVS_LPCR bits only ([ad6eb19](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad6eb1951b986f30635025bbdf29e257b6b1e362)) + + - **i.MX 8Q** + + - correct architected counter frequency ([21189b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/21189b8e21062b71c9056ac1cf60d25bb018007c)) + + - **QEMU** + + - enable SVE and SME ([337ff4f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/337ff4f1dd6604738d79fd3fa275ae74d74256b2)) + + - **QTI** + + - adding secure rm flag ([b5959ab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b5959ab029fb0a8a271967b0bd7ef438d59061bd)) + + - **Raspberry Pi** + + - **Raspberry Pi 3** + + - tighten platform pwr_domain_pwr_down_wfi behaviour ([028c4e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/028c4e42d8f632d40081b88f66d0d05c7d7c9b23)) + + - **Renesas** + + - **R-Car** + + - **R-Car 3** + + - fix RPC-IF device node name ([08ae247](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/08ae2471b1417f1d8083a79771338aa2a00b6711)) + + - **Rockchip** + + - align fdt buffer on 8 bytes ([621acbd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/621acbd055d712ab8bf79054911155598fdb74d0)) + + - **RK3399** + + - explicitly define the sys_sleep_flag_sram type ([7a5e90a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a5e90a89d91d6662d3e468893e07c91b3a165ee)) + + - **Socionext** + + - **Synquacer** + + - increase size of BL33 ([a12a66d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a12a66d0d6d4732d41a27b1ecbc8874731c78101)) + + - **ST** + + - add max size for FIP in eMMC boot part ([e7cb4a8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e7cb4a86b884d2922984d3cd4651fb905650cfd6)) + - add missing string.h include ([0d33d38](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0d33d38334cae909a66c74187a36b5833afb8093)) + + - **STM32MP1** + + - enable crash console in FIQ handler ([484e846](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/484e846a03a1af5f88e2e28835b6349cc5977935)) + - fdts: stm32mp1: align DDR regulators with new driver ([9eed71b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9eed71b7221c5fc7ed887f1087e42c9f1a62f581)) + - update the FIP load address for serial boot ([32f2ca0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32f2ca04bfd2d93329f2f17d9c9d134f339710f9)) + + - **STM32MP13** + + - correct USART addresses ([de1ab9f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/de1ab9fe052deba06a0904b10a6e0312ca49658e)) + + - **Xilinx** + + - include missing header ([28ba140](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/28ba1400216d7c7195929d1bd53f059a440a89a2)) + - miscellaneous fixes for xilinx platforms ([bfc514f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bfc514f10393fb7f4641ad5e75049f3acc246dd2)) + - remove unnecessary header include ([0ee2dc1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ee2dc118c34ceacc921fee196a4ba9102bdfbea)) + - update define for ZynqMP specific functions ([24b5b53](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24b5b53a5922de40e53f0a7ecf65d3d0acc30a0d)) + + - **Versal** + + - add SGI register call version check ([5897e13](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5897e135445e2bf3345297fbe9971a113506d714)) + - enable a72 erratum 859971 and 1319367 ([769446a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/769446a6899d840df8aa5746ec32bf7530fc9826)) + - fix code indentation issues ([72583f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72583f92e6cc1d691b709e05c3ae280dce016fef)) + - fix macro coding style issues ([80806aa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/80806aa1234606bb55af40ae0667cdf4d44423be)) + - fix Misra-C violations in bl31_setup and pm_svc_main ([68ffcd1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68ffcd1bb22f2c2eac6c3329a1974b3e8ec6f515)) + - remove clock related macros ([47f8145](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47f8145324181b86b6f460fb0c92144ef43e4e14)) + - resolve misra 10.1 warnings ([19f92c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/19f92c4cfe014c5495f3073917119385b0014eda)) + - resolve misra 15.6 warnings ([1117a16](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1117a16e0379986ea68581c02fb2fee40937452b)) + - resolve misra 8.13 warnings ([3d2ebe7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3d2ebe756a50c27a00a03ae7f0109ed04681ac96)) + - resolve the misra 4.6 warnings ([f7c48d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f7c48d9e30e9444f1fdb808ae5d06ed675e335fa)) + - resolve the misra 4.6 warnings ([912b7a6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/912b7a6fe46619e5df55dbd0b95d306f7bb2695c)) + - route GIC IPI interrupts during setup ([04cc91b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04cc91b43c1d10fcba563e18f06336987e6e3a24)) + - use only one space for indentation ([dee5885](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dee588591328b96d9b9ef908869c8b42bd2632f2)) + + - **Versal NET** + + - Enable a78 errata workarounds ([bcc6e4a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bcc6e4a02a88056b9c45ff28f405e09444433528)) + - add default values for silicon ([faa22d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/faa22d48d9929d57975b84ab76cb595afdcf57f4)) + - use api_id directly without FUNCID_MASK ([b0eb6d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0eb6d124b1764264778d17b1519bfe62b7b9337)) + + - **ZynqMP** + + - fix coverity scan warnings ([1ac6af1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ac6af1199e2d14492a9d75aaba69bc775e55bd8)) + - ensure memory write finish with dsb() ([ac6c135](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac6c135c83fe4efa4d6e9b9c06e899b57ce5647a)) + - fix for incorrect afi write mask value ([4264bd3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4264bd33e718023c62a2776e3ca40db88fce8b08)) + - move bl31 with DEBUG=1 back to OCM ([389594d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/389594dfa7e60a720d60f0d55296f91ba1610de5)) + - move debug bl31 based address back to OCM ([0ba3d7a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ba3d7a4ca04486f45d062fab54238d9a554a682)) + - remove additional 0x in %p print ([05a6107](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/05a6107ff18b03f4ca33496268398133abf04aaa)) + - resolve misra 4.6 warnings ([cdb6211](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cdb62114cfcdaeb85e64bcde459342a0a95f58e3)) + - resolve misra 8.13 warnings ([8695ffc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8695ffcfcb3801ea287fae7652ba1c350636831f)) + - resolve MISRA-C:2012 R.10.1 warnings ([c889088](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c889088386432af69e3ca853825c4219884c1cc1)) + - resolve the misra 4.6 warnings ([15dc3e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15dc3e4f8d9730ce58cc599fb9970d486c8b9202)) + - resolve the misra 4.6 warnings ([ffa9103](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ffa910312c371080f4d0d50eb1354ad05b7be7a8)) + - resolve the misra 8.6 warnings ([7b1a6a0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b1a6a08ccc7522687f66e6e989bbc597d08ab06)) + +- **Bootloader Images** + + - **BL31** + + - allow use of EHF with S-EL2 SPMC ([7c2fe62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c2fe62f1347bb94d82e9fdd3bc5eaebedaf0bc7)) + - harden check in delegate_async_ea ([d435238](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d435238dc364f0c9f0e41661365f83d83899829d)) + - pass the EA bit to 'delegate_sync_ea' ([df56e9d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/df56e9d199939c571b3fd8f539d213fc36e14494)) + +- **Services** + + - **RME** + + - refactor RME fid macros ([fb00dc4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb00dc4a7b208cf416d082bb4367b54286bc8e3b)) + - relax RME compiler requirements ([7670ddb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7670ddb1fb5d4fa5e2e234375f7a4c0763f1c57a)) + - update FVP platform token ([364b4cd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/364b4cddbab859a56e63813aab4e983433187191)) + - use RMM shared buffer for attest SMCs ([dc65ae4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dc65ae46439f4d1be06e3a016fe76319d7a62954)) + - xlat table setup fails for bl2 ([e516ba6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e516ba6de5e248e93156b5261cedbff811226e0e)) + + - **RMMD** + + - return X4 output value ([8e51ccc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e51cccaefc1e0e79ac2f0667ffec1cc46cf7665)) + + - **SPM** + + - **EL3 SPMC** + + - check descriptor size for overflow ([eed15e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eed15e4310a7bcd90bf6d66b00037e05186329bb)) + - compute full FF-A V1.1 desc size ([be075c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be075c3edf634a2df1065597266c3e41d284287b)) + - deadlock when relinquishing memory ([ac568b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac568b2bccb9da71f2bd7f1c7204189d1ff678d9)) + - error handling in allocation ([cee8bb3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cee8bb3b38ea266a5008719548965352ec695cae)) + - fix detection of overlapping memory regions ([0dc3518](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0dc35186669ddaedb3a932e103c3976bc3bf75d6)) + - fix incomplete reclaim validation ([c4adbe6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4adbe6e67617bb2d4f0ffb1c1daa3395f7ac227)) + - fix location of fragment length check ([21ed9ea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/21ed9ea32325fc556fa7e907e4995888bd3a3b45)) + - fix relinquish validation check ([b4c3621](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b4c3621e0dc8e7ec6d3229253e0326f12c8fe5a9)) + +- **Libraries** + + - **CPU Support** + + - fix cpu version check for Neoverse N2, V1 ([03ebf40](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03ebf409c711e9f2006cedded7dc415dfe566975)) + - workaround for Cortex-A510 erratum 2666669 ([afb5d06](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/afb5d069a6fa049f18e90fa50e714b8a4acc55f4)) + - workaround for Cortex-A710 2216384 ([b781fcf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b781fcf139c3a609f1adffb8097a23eadbed53a9)) + - workaround for Cortex-A710 erratum 2291219 ([888eafa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/888eafa00b99aa06b4ff688407336811a7ff439a)) + - workaround for Cortex-A76 erratum 2743102 ([4927309](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49273098a5ccd87a2084a85f9e47d74fa3ecfc90)) + - workaround for Cortex-A77 erratum 2743100 ([4fdeaff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fdeaffe860a998e8503b847ecceec60dcddcdc5)) + - workaround for Cortex-A78C erratum 2376749 ([5d3c1f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d3c1f58905d3b7350e02c4687dceaf0971700b3)) + - workaround for Cortex-X3 erratum 2313909 ([7954412](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/79544126943a90d31d81177655be11f75330ffed)) + - workaround for Neoverse N1 erratum 2743102 ([8ce4050](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8ce40503ad00fe0dd35de6e51551da2b4f08a848)) + - workaround for Neoverse-N2 erratum 2326639 ([43438ad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/43438ad1ad6651964e9ae75d35f40aed8d86d088)) + - workaround for Neoverse-N2 erratum 2388450 ([884d515](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/884d515625aa09b22245c32db2fcc9222c7f34fd)) + - workaround for Cortex A78C erratum 2242638 ([6979f47](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6979f47fecfd34ac1405117c23f2e36ecb552a20)) + - workaround for Cortex-A510 erratum 2347730 ([11d448c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/11d448c93463180d03b46e9ba204124ff7ad5116)) + - workaround for Cortex-A510 erratum 2371937 ([a67c1b1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a67c1b1b2b521c888790c68e4201ecce0836a0e9)) + - workaround for Cortex-A710 erratum 2147715 ([3280e5e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3280e5e655ad64b6e299e18624d9c586e6b37cb1)) + - workaround for Cortex-A710 erratum 2371105 ([3220f05](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3220f05ef900addccb6e444d6746e4ed28c9804f)) + - workaround for Cortex-A77 erratum 2356587 ([7bf1a7a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7bf1a7aaaa41034587e43d5805b42da83090b85b)) + - workaround for Cortex-A78C 2132064 ([8008bab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8008babd58f60c91a88ad79df3d32f63596b433a)) + - workaround for Cortex-A78C erratum 2395411 ([4b6f002](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b6f0026ea2622b3f46cdef5b468853ddd281b39)) + - workaround for Cortex-X2 erratum 2371105 ([bc0f84d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc0f84de40d4f1efddfb50071fff09d32f0ea9b2)) + - workaround for Neoverse-N2 erratum 2376738 ([e6602d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6602d4b153b81b49b39c22e70f052f9018687b7)) + - workaround for Neoverse-V1 erratum 1618635 ([14a6fed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/14a6fed5ac14035f578a75a9758f9df7ba4d7496)) + - workaround for Neoverse-V1 erratum 2294912 ([39eb5dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39eb5ddbbf98bdb6c012a9d852f489f2f8e15c05)) + - workaround for Neoverse-V1 erratum 2372203 ([57b73d5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57b73d553305d89da7098f9b53b0a2356ca7ff8b)) + + - **EL3 Runtime** + + - **RAS** + + - restrict RAS support for NS world ([46cc41d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/46cc41d5592a16f702f7f0c0c41f8948a3e11cda)) + - trap "RAS error record" accesses only for NS ([00e8f79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/00e8f79c15d36f65f6c7f127177105e02177cbc0)) + + - **FCONF** + + - fix type error displaying disable_auth ([381f465](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/381f465ca92f7c9759e85c1bfb4c95ceda26581e)) + + - **PSCI** + + - fix MISRA failure - Memory - illegal accesses ([0551aac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0551aac5637a638d4b9d8865a2c20ec5153de3bf)) + + - **GPT** + + - correct the GPC enable sequence ([14cddd7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/14cddd7a58799c8a9d349a4adc0136c1ab5d0b6c)) + + - **C Standard Library** + + - pri*ptr macros for aarch64 ([d307229](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d307229d754ae4d833ed50be50420aaf070065bf)) + + - **PSA** + + - fix Null pointer dereference error ([c32ab75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c32ab75c41adfe28a60f1ff159012a7d78e72fdc)) + - update measured boot handle ([4d879e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d879e1e5a40cefae5b5e13086a16741bf3f6d67)) + - add missing semicolon ([d219ead](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d219ead1db5ca02ec7c7905ac01d7b268c5026ae)) + - align with original API in tf-m-extras ([471c989](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/471c9895a630560561717067113e4c4d7127bb9f)) + - extend measured boot logging ([901b0a3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/901b0a3015a652d9eb66c063b0984fade9adf08f)) + + - **Context Management** + + - remove explicit ICC_SRE_EL2 register read ([2b28727](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b28727e6dafdaa08a517b5a97bda5de26cc8919)) + + - **Semihosting** + + - fix seek call failure check ([7c49438](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c4943887477754024f0f736461d9543d502efcc)) + +- **Drivers** + + - **Authentication** + + - correct sign-compare warning ([ed38366](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ed38366f1dfeb0b0789fd69b400728598ae3c64e)) + + - **Measured Boot** + + - add SP entries to event_log_metadata ([e637a5e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e637a5e19da72599229fd2c70e793c123aaf14ca)) + - clear the entire digest array of Startup Locality event ([70b1c02](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70b1c025003452602f68feb13402c705e44145aa)) + - fix verbosity level of RSS digests traces ([2abd317](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2abd317d27a26bbfa3da7fe3fe709da3fa0f09af)) + + - **MMC** + + - remove broken, unsecure, unused eMMC RPMB handling ([86b015e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/86b015eb1be57439c2a01cb35d800c7f1b5c8467)) + - resolve the build error ([ccf8392](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ccf8392ccb105638fe710901d3c7ed6594d9450e)) + + - **SCMI** + + - base: fix protocol list querying ([cad90b5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cad90b569db7c547470cca922bd93207adcadfad)) + - base: fix protocol list response size ([d323f0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d323f0cf000f1d999bf78d89c0037af76b6bf8d8)) + + - **UFS** + + - add retries to ufs_read_capacity ([28645eb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/28645ebd706fe6ac9f34db9f7be5657fe4cffc1a)) + - fix slot base address computation ([7d9648d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7d9648dd6cf3b1dcd90b6917d9d0b545b1c4c975)) + - init utrlba/utrlbau with desc_base ([9d6d1a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9d6d1a94c99c3a0e89792c5cc118a1d8c8a9dbb7)) + - point utrlbau to header instead of upiu ([9d3f6c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9d3f6c4b6068b3a4747f5d1dc650607876eff583)) + - removes dp and run-stop polling loops ([660c208](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/660c208d9bd2770f295005fc26a9b6f788567f41)) + - retry commands on unit attention ([3d30955](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3d309556c75bcdb59fd4e4178fa2b79aa472dc90)) + + - **Arm** + + - **GIC** + + - **GICv3** + + - fix overflow caused by left shift ([6aea762](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6aea7624a01cc39c19d4237c4b108659270a61c5)) + - update the affinity mask to 8 bit ([e689048](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e689048e20af70983e0d384301c408fc725cb5eb)) + + - **GIC-600** + + - implement workaround to forward highest priority interrupt ([e1b15b0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e1b15b09a530f2a0b0edc4384e977452d6b389eb)) + + - **RSS** + + - clear the message buffer ([e3a6fb8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e3a6fb84f523e68d2f1398348d1ae2635f3e57bc)) + - determine the size of sw_type in RSS mboot metadata ([2c8f2a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2c8f2a9ad45023354516d419dc9fda2a4f02812b)) + - fix build issues with comms protocol ([ab545ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab545efddcdbf5d08ad3b1e8f4ea15a0faf168a7)) + - reduce input validation for measured boot ([13a129e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/13a129e8dcea358033f3c83b2d81b25129e02d43)) + - remove dependency on attestation header ([6aa7154](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6aa71542f35047ea0b537e3a6016de6c579c9d6b)) + - rename AP-RSS message size macro ([70247dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70247ddbbd0a55a1ddf1d02f2a35b5cad3949dd1)) + + - **NXP** + + - **DDR** + + - fix firmware buffer re-mapping issue ([742c23a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/742c23aab79a21803472c5b4314b43057f1d3e84)) + + - **ST** + + - **Clock** + + - correct MISRA C2012 15.6 ([56f895e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56f895ede3a2a4a97c0e4f8270050aff20a167bc)) + - correctly check ready bit ([3b06a53](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b06a53044e754979cb0608fd93a137a5879a6a0)) + +- **Miscellaneous** + + - **AArch64** + + - make AArch64 FGT feature detection more robust ([c687776](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c6877763cd3a286983df160c8207368174c1b820)) + + - **Debug** + + - backtrace stack unwind misses lr adjustment ([a149eb4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a149eb4d87453f58418ad32c570090739a3e0dd6)) + - decouple "get_el_str()" from backtrace ([0ae4a3a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ae4a3a3f0cd841b83f2944dde9837ea67f08813)) + + - **FDTs** + + - **STM32MP1** + + - **STM32MP13** + + - align sdmmc pins with kernel ([c7ac7d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c7ac7d65a7d1ee1b656bf1260ede6b8e2226bbac)) + - cleanup DT files ([4c07deb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4c07deb53e0e7daafc93bc67fdcbb3de7b73d730)) + - correct PLL nodes name ([93ed4f0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93ed4f0801f5b3571abdd7e039d09d508c987063)) + - remove secure status ([8ef8e0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8ef8e0e30e301e6b2595d571f004ae86b1a1ce06)) + - update SDMMC max frequency ([c9a4cb5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c9a4cb552cdd168fcab2c0383b8fbe30dc99092f)) + + - **Security** + + - optimisations for CVE-2022-23960 ([e74d658](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e74d658181e5e69b6b5e16b40adc1ffef4c1efb9)) + +- **Documentation** + + - document missing RMM-EL3 runtime services ([e50fedb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e50fedbc869341d044d4cb3479a0ab3d4edaf225)) + - add LTS maintainers ([ab0d4d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab0d4d9d44fe54535a0ae647092a3cfff368f126)) + - update maintainers list ([f23ce63](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f23ce639050481cda939b9e4738ed01d46481ee3)) + + - **Changelog** + + - fix the broken link to commitlintrc.js ([c1284a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c1284a7f93309c88fd781d2b4720f742e147284e)) + +- **Build System** + + - disable default PIE when linking ([7b59241](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b5924184566bcdcc01966905ffdcabcd6ea4b32)) + - discard sections also with SEPARATE_NOBITS_REGION ([64207f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/64207f858f5cbf44aa6528be19a863acc4444568)) + - ensure that the correct rule is called for tools ([598b166](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/598b166bbc2f09fc219d44ecff0c870854bfa093)) + - fix arch32 build issue for clang ([94eb127](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94eb127719881f39c7f235c887fb2c0b82341696)) + - make TF-A use provided OpenSSL binary ([e95abc4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e95abc4c01822ef43e9e874d63d6596dc0b57279)) + +- **Tools** + + - **Secure Partition Tool** + + - fix concurrency issue for SP packages ([0aaa382](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0aaa382fe2395c82c9491b199b6b82819afd368f)) + - operators "is/is not" in sp_mk_gen.py ([1a28f29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a28f290b8224eb1d78a2476faaedc5154f82208)) + - 'sp_mk_generator.py' reference to undef var ([0be2475](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0be2475f6990a37d2d54b7ed06bac9cb46f4660d)) + +- **Dependencies** + + - add missing aeabi_memcpy.S ([93cec69](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93cec697deb654303379cae8f25a31dc8b90cd31)) + +## [2.7.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.6..refs/tags/v2.7.0) (2022-05-20) ### New Features diff --git a/docs/components/el3-spmc.rst b/docs/components/el3-spmc.rst new file mode 100644 index 000000000..1a2d4273b --- /dev/null +++ b/docs/components/el3-spmc.rst @@ -0,0 +1,597 @@ +EL3 Secure Partition Manager +**************************** + +.. contents:: + +Foreword +======== + +This document describes the design of the EL3 SPMC based on the FF-A specification. +EL3 SPMC provides reference FF-A compliant implementation without S-EL2 virtualization support, +to help adopt and migrate to FF-A early. +EL3 SPMC implementation in TF-A: + +- Manages a single S-EL1 Secure Partition +- Provides a standard protocol for communication and memory sharing between FF-A endpoints. +- Provides support for EL3 Logical Partitions to support easy migration from EL3 to S-EL1. + +Sample reference stack +====================== + +The following diagram illustrates a possible configuration when the +FEAT_SEL2 architecture extension is not implemented, showing the SPMD +and SPMC at EL3, one S-EL1 secure partition, with an optional +Hypervisor: + +.. image:: ../resources/diagrams/ff-a-spm-at-el3.png + +TF-A build options +================== + +This section explains the TF-A build options involved in building +an FF-A based SPM where the SPMD and SPMC are located at EL3: + +- **SPD=spmd**: this option selects the SPMD component to relay the FF-A + protocol from NWd to SWd back and forth. It is not possible to + enable another Secure Payload Dispatcher when this option is chosen. +- **SPMC_AT_EL3**: this option adjusts the SPMC exception level to being + at EL3. +- **ARM_SPMC_MANIFEST_DTS**: this option specifies a manifest file + providing SP description. It is required when + ``SPMC_AT_EL3`` is enabled, the secure partitions are loaded + by BL2 on behalf of the SPMC. + +Notes: + +- BL32 option is re-purposed to specify the S-EL1 TEE or SP image. + BL32 option can be omitted if using TF-A Test Secure Payload as SP. +- BL33 option can specify the TFTF binary or a normal world loader + such as U-Boot or the UEFI framework payload. + +Sample TF-A build command line when the SPMC is located at EL3: + +.. code:: shell + + make \ + CROSS_COMPILE=aarch64-none-elf- \ + SPD=spmd \ + SPMD_SPM_AT_SEL2=0 \ + SPMC_AT_EL3=1 \ + BL32=<path-to-tee-binary> (opt for TSP) \ + BL33=<path-to-bl33-binary> \ + PLAT=fvp \ + all fip + +FVP model invocation +==================== + +Sample FVP command line invocation: + +.. code:: shell + + <path-to-fvp-model>/FVP_Base_RevC-2xAEMvA -C pctl.startup=0.0.0.0 \ + -C cluster0.NUM_CORES=4 -C cluster1.NUM_CORES=4 -C bp.secure_memory=1 \ + -C bp.secureflashloader.fname=trusted-firmware-a/build/fvp/debug/bl1.bin \ + -C bp.flashloader0.fname=trusted-firmware-a/build/fvp/debug/fip.bin \ + -C bp.pl011_uart0.out_file=fvp-uart0.log -C bp.pl011_uart1.out_file=fvp-uart1.log \ + -C bp.pl011_uart2.out_file=fvp-uart2.log -C bp.vis.disable_visualisation=1 + + +Platform Guide +============== + +- Platform Hooks See - `[4]`_ + + - plat_spmc_shmem_begin + - plat_spmc_shmem_reclaim + +SPMC provides platform hooks related to memory management interfaces. +These hooks can be used for platform specific implementations like +for managing access control, programming TZ Controller or MPUs. +These hooks are called by SPMC before the initial share request completes, +and after the final reclaim has been completed. + +- Datastore + + - plat_spmc_shmem_datastore_get + + EL3 SPMC uses datastore for tracking memory transaction descriptors. + On FVP platform datastore is allocated from TZC DRAM section. + Other platforms need to allocate a similar secure memory region + to be used as shared memory datastore. + + The accessor function is used during SPMC initialization to obtain + address and size of the datastore. + SPMC will also zero out the provided memory region. + +- Platform Defines See - `[5]`_ + + - SECURE_PARTITION_COUNT + Number of Secure Partitions supported: must be 1. + + - NS_PARTITION_COUNT + Number of NWd Partitions supported. + + - MAX_EL3_LP_DESCS_COUNT + Number of Logical Partitions supported. + +Logical Secure Partition (LSP) +============================== + +- The SPMC provides support for statically allocated EL3 Logical Secure Partitions + as per FF-A v1.1 specification. +- The DECLARE_LOGICAL_PARTITION macro can be used to add a LSP. +- For reference implementation See - `[2]`_ + +.. image:: ../resources/diagrams/ff-a-lsp-at-el3.png + +SPMC boot +========= + +The SPMD and SPMC are built into the BL31 image along with TF-A's runtime components. +BL2 loads the BL31 image as a part of (secure) boot process. + +The SPMC manifest is loaded by BL2 as the ``TOS_FW_CONFIG`` image `[9]`_. + +BL2 passes the SPMC manifest address to BL31 through a register. + +At boot time, the SPMD in BL31 runs from the primary core, initializes the core +contexts and launches the SPMC passing the following information through +registers: + +- X0 holds the SPMC manifest blob address. +- X4 holds the currently running core linear id. + +Parsing SP partition manifests +------------------------------ + +SPMC consumes the SP manifest, as defined in `[7]`_. +SP manifest fields align with Hafnium SP manifest for easy porting. + +.. code:: shell + + compatible = "arm,ffa-manifest-1.0"; + + ffa-version = <0x00010001>; /* 31:16 - Major, 15:0 - Minor */ + id = <0x8001>; + uuid = <0x6b43b460 0x74a24b78 0xade24502 0x40682886>; + messaging-method = <0x3>; /* Direct Messaging Only */ + exception-level = <0x2>; /* S-EL1 */ + execution-state = <0>; + execution-ctx-count = <8>; + gp-register-num = <0>; + power-management-messages = <0x7>; + + +Passing boot data to the SP +--------------------------- + +In `[1]`_ , the section "Boot information protocol" defines a method for passing +data to the SPs at boot time. It specifies the format for the boot information +descriptor and boot information header structures, which describe the data to be +exchanged between SPMC and SP. +The specification also defines the types of data that can be passed. +The aggregate of both the boot info structures and the data itself is designated +the boot information blob, and is passed to a Partition as a contiguous memory +region. + +Currently, the SPM implementation supports the FDT type which is used to pass the +partition's DTB manifest. + +The region for the boot information blob is statically allocated (4K) by SPMC. +BLOB contains Boot Info Header, followed by SP Manifest contents. + +The configuration of the boot protocol is done in the SP manifest. As defined by +the specification, the manifest field 'gp-register-num' configures the GP register +which shall be used to pass the address to the partitions boot information blob when +booting the partition. + +Supported interfaces +==================== + +The following interfaces are exposed to SPs only: + +- ``FFA_MSG_WAIT`` +- ``FFA_MEM_RETRIEVE_REQ`` +- ``FFA_MEM_RETRIEVE_RESP`` +- ``FFA_MEM_RELINQUISH`` +- ``FFA_SECONDARY_EP_REGISTER`` + +The following interfaces are exposed to both NS Client and SPs: + +- ``FFA_VERSION`` +- ``FFA_FEATURES`` +- ``FFA_RX_RELEASE`` +- ``FFA_RXTX_MAP`` +- ``FFA_RXTX_UNMAP`` +- ``FFA_PARTITION_INFO_GET`` +- ``FFA_ID_GET`` +- ``FFA_MSG_SEND_DIRECT_REQ`` +- ``FFA_MSG_SEND_DIRECT_RESP`` +- ``FFA_MEM_FRAG_TX`` +- ``FFA_SPM_ID_GET`` + +The following additional interfaces are forwarded from SPMD to support NS Client: + +- ``FFA_RUN`` +- ``FFA_MEM_LEND`` +- ``FFA_MEM_SHARE`` +- ``FFA_MEM_FRAG_RX`` +- ``FFA_MEM_RECLAIM`` + + +FFA_VERSION +----------- + +``FFA_VERSION`` requires a *requested_version* parameter from the caller. +SPMD forwards call to SPMC, the SPMC returns its own implemented version. +SPMC asserts SP and SPMC are at same FF-A Version. + +FFA_FEATURES +------------ + +FF-A features supported by the SPMC may be discovered by secure partitions at +boot (that is prior to NWd is booted) or run-time. + +The SPMC calling FFA_FEATURES at secure physical FF-A instance always get +FFA_SUCCESS from the SPMD. + +The request made by an Hypervisor or OS kernel is forwarded to the SPMC and +the response relayed back to the NWd. + + +FFA_RXTX_MAP +------------ + +FFA_RXTX_UNMAP +-------------- + +When invoked from a secure partition FFA_RXTX_MAP maps the provided send and +receive buffers described by their PAs to the EL3 translation regime +as secure buffers in the MMU descriptors. + +When invoked from the Hypervisor or OS kernel, the buffers are mapped into the +SPMC EL3 translation regime and marked as NS buffers in the MMU +descriptors. + +The FFA_RXTX_UNMAP unmaps the RX/TX pair from the translation regime of the +caller, either it being the Hypervisor or OS kernel, as well as a secure +partition. + +FFA_PARTITION_INFO_GET +---------------------- + +Partition info get call can originate: + +- from SP to SPMC +- from Hypervisor or OS kernel to SPMC. The request is relayed by the SPMD. + +The format (v1.0 or v1.1) of the populated data structure returned is based upon the +FFA version of the calling entity. + +EL3 SPMC also supports returning only the count of partitions deployed. + +All LSPs and SP are discoverable from FFA_PARTITION_INFO_GET call made by +either SP or NWd entities. + +FFA_ID_GET +---------- + +The FF-A ID space is split into a non-secure space and secure space: + +- FF-A ID with bit 15 clear relates to VMs. +- FF-A ID with bit 15 set related to SPs or LSPs. +- FF-A IDs 0, 0xffff, 0x8000 are assigned respectively to the Hypervisor + (or OS Kernel if Hyp is absent), SPMD and SPMC. + +This convention helps the SPM to determine the origin and destination worlds in +an FF-A ABI invocation. In particular the SPM shall filter unauthorized +transactions in its world switch routine. It must not be permitted for a VM to +use a secure FF-A ID as origin world by spoofing: + +- A VM-to-SP direct request/response shall set the origin world to be non-secure + (FF-A ID bit 15 clear) and destination world to be secure (FF-A ID bit 15 + set). +- Similarly, an SP-to-LSP direct request/response shall set the FF-A ID bit 15 + for both origin and destination IDs. + +An incoming direct message request arriving at SPMD from NWd is forwarded to +SPMC without a specific check. The SPMC is resumed through eret and "knows" the +message is coming from normal world in this specific code path. Thus the origin +endpoint ID must be checked by SPMC for being a normal world ID. + +An SP sending a direct message request must have bit 15 set in its origin +endpoint ID and this can be checked by the SPMC when the SP invokes the ABI. + +The SPMC shall reject the direct message if the claimed world in origin endpoint +ID is not consistent: + +- It is either forwarded by SPMD and thus origin endpoint ID must be a "normal + world ID", +- or initiated by an SP and thus origin endpoint ID must be a "secure world ID". + + +FFA_MSG_SEND_DIRECT_REQ +----------------------- + +FFA_MSG_SEND_DIRECT_RESP +------------------------ + +This is a mandatory interface for secure partitions participating in direct request +and responses with the following rules: + +- An SP can send a direct request to LSP. +- An LSP can send a direct response to SP. +- An SP cannot send a direct request to an Hypervisor or OS kernel. +- An Hypervisor or OS kernel can send a direct request to an SP or LSP. +- An SP and LSP can send a direct response to an Hypervisor or OS kernel. +- SPMD can send direct request to SPMC. + +FFA_SPM_ID_GET +-------------- + +Returns the FF-A ID allocated to an SPM component which can be one of SPMD +or SPMC. + +At initialization, the SPMC queries the SPMD for the SPMC ID, using the +FFA_ID_GET interface, and records it. The SPMC can also query the SPMD ID using +the FFA_SPM_ID_GET interface at the secure physical FF-A instance. + +Secure partitions call this interface at the virtual FF-A instance, to which +the SPMC returns the SPMC ID. + +The Hypervisor or OS kernel can issue the FFA_SPM_ID_GET call handled by the +SPMD, which returns the SPMC ID. + +FFA_ID_GET +---------- + +Returns the FF-A ID of the calling endpoint. + +FFA_MEM_SHARE +------------- + +FFA_MEM_LEND +------------ + +- If SP is borrower in the memory transaction, these calls are forwarded to SPMC. + SPMC performs Relayer responsibilities, caches the memory descriptors in the datastore, + and allocates FF-A memory handle. +- If format of descriptor was v1.0, SPMC converts the descriptor to v1.1 before caching. + In case of fragmented sharing, conversion of memory descriptors happens after last + fragment has been received. +- Multiple borrowers (including NWd endpoint) and fragmented memory sharing are supported. + +FFA_MEM_RETRIEVE_REQ +-------------------- + +FFA_MEM_RETRIEVE_RESP +--------------------- + +- Memory retrieve is supported only from SP. +- SPMC fetches the cached memory descriptor from the datastore, +- Performs Relayer responsiilities and sends FFA_MEM_RETRIEVE_RESP back to SP. +- If descriptor size is more than RX buffer size, SPMC will send the descriptor in fragments. +- SPMC will set NS Bit to 1 in memory descriptor response. + +FFA_MEM_FRAG_RX +--------------- + +FFA_MEM_FRAG_TX +--------------- + +FFA_MEM_FRAG_RX is to be used by: + +- SP if FFA_MEM_RETRIEVE_RESP returned descriptor with fragment length less than total length. +- or by SPMC if FFA_MEM_SHARE/FFA_MEM_LEND is called with fragment length less than total length. + +SPMC validates handle and Endpoint ID and returns response with FFA_MEM_FRAG_TX. + +FFA_SECONDARY_EP_REGISTER +------------------------- + +When the SPMC boots, secure partition is initialized on its primary +Execution Context. + +The FFA_SECONDARY_EP_REGISTER interface is to be used by a secure partition +from its first execution context, to provide the entry point address for +secondary execution contexts. + +A secondary EC is first resumed either upon invocation of PSCI_CPU_ON from +the NWd or by invocation of FFA_RUN. + +Power management +================ + +In platforms with or without secure virtualization: + +- The NWd owns the platform PM policy. +- The Hypervisor or OS kernel is the component initiating PSCI service calls. +- The EL3 PSCI library is in charge of the PM coordination and control + (eventually writing to platform registers). +- While coordinating PM events, the PSCI library calls backs into the Secure + Payload Dispatcher for events the latter has statically registered to. + +When using the SPMD as a Secure Payload Dispatcher: + +- A power management event is relayed through the SPD hook to the SPMC. +- In the current implementation CPU_ON (svc_on_finish), CPU_OFF + (svc_off), CPU_SUSPEND (svc_suspend) and CPU_SUSPEND_RESUME (svc_suspend_finish) + hooks are registered. + +Secure partitions scheduling +============================ + +The FF-A specification `[1]`_ provides two ways to relinquinsh CPU time to +secure partitions. For this a VM (Hypervisor or OS kernel), or SP invokes one of: + +- the FFA_MSG_SEND_DIRECT_REQ interface. +- the FFA_RUN interface. + +Additionally a secure interrupt can pre-empt the normal world execution and give +CPU cycles by transitioning to EL3. + +Partition Runtime State and Model +================================= + +EL3 SPMC implements Partition runtime states are described in v1.1 FF-A specification `[1]`_ + +An SP can be in one of the following state: + +- RT_STATE_WAITING +- RT_STATE_RUNNING +- RT_STATE_PREEMPTED +- RT_STATE_BLOCKED + +An SP will transition to one of the following runtime model when not in waiting state: + +- RT_MODEL_DIR_REQ +- RT_MODEL_RUN +- RT_MODEL_INIT +- RT_MODEL_INTR + +Platform topology +================= + +SPMC only supports a single Pinned MP S-EL1 SP. The *execution-ctx-count* +SP manifest field should match the number of physical PE. + +Interrupt handling +================== + +Secure Interrupt handling +------------------------- + +- SPMC is capable of forwarding Secure interrupt to S-EL1 SP + which has preempted the normal world. +- Interrupt is forwarded to SP using FFA_INTERRUPT interface. +- Interrupt Number is not passed, S-EL1 SP can access the GIC registers directly. +- Upon completion of Interrupt handling SP is expected to return to + SPMC using FFA_MSG_WAIT interface. +- SPMC returns to normal world after interrupt handling is completed. + +In the scenario when secure interrupt occurs while the secure partition is running, +the SPMC is not involved and the handling is implementation defined in the TOS. + +Non-Secure Interrupt handling +----------------------------- + +The 'managed exit' scenario is the responsibility of the TOS and the SPMC is not involved. + +Test Secure Payload (TSP) +========================= + +- TSP provides reference implementation of FF-A programming model. +- TSP has the following support: + + - SP initialization on all CPUs. + - Consuming Power Messages including CPU_ON, CPU_OFF, CPU_SUSPEND, CPU_SUSPEND_RESUME. + - Event Loop to receive Direct Requests. + - Sending Direct Response. + - Memory Sharing helper library. + - Ability to handle secure interrupt (timer). + +TSP Tests in CI +--------------- + +- TSP Tests are exercised in the TF-A CI using prebuilt FF-A Linux Test driver in NWd. +- Expected output: + +.. code:: shell + + #ioctl 255 + Test: Echo Message to SP. + Status: Completed Test Case: 1 + Test Executed Successfully + + Test: Message Relay vis SP to EL3 LSP. + Status: Completed Test Case: 2 + Test Executed Successfully + + Test: Memory Send. + Verified 1 constituents successfully + Status: Completed Test Case: 3 + Test Executed Successfully + + Test: Memory Send in Fragments. + Verified 256 constituents successfully + Status: Completed Test Case: 4 + Test Executed Successfully + + Test: Memory Lend. + Verified 1 constituents successfully + Status: Completed Test Case: 5 + Test Executed Successfully + + Test: Memory Lend in Fragments. + Verified 256 constituents successfully + Status: Completed Test Case: 6 + Test Executed Successfully + + Test: Memory Send with Multiple Endpoints. + random: fast init done + Verified 256 constituents successfully + Status: Completed Test Case: 7 + Test Executed Successfully + + Test: Memory Lend with Multiple Endpoints. + Verified 256 constituents successfully + Status: Completed Test Case: 8 + Test Executed Successfully + + Test: Ensure Duplicate Memory Send Requests are Rejected. + Status: Completed Test Case: 9 + Test Executed Successfully + + Test: Ensure Duplicate Memory Lend Requests are Rejected. + Status: Completed Test Case: 10 + Test Executed Successfully + + 0 Tests Failed + + Exiting Test Application - Total Failures: 0 + + +References +========== + +.. _[1]: + +[1] `Arm Firmware Framework for Arm A-profile <https://developer.arm.com/docs/den0077/latest>`__ + +.. _[2]: + +[2] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fvp_el3_spmc_logical_sp.c + +.. _[3]: + +[3] `Trusted Boot Board Requirements +Client <https://developer.arm.com/documentation/den0006/d/>`__ + +.. _[4]: + +[4] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fvp_el3_spmc.c + +.. _[5]: + +[5] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/include/platform_def.h + +.. _[6]: + +[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html + +.. _[7]: + +[7] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts + +.. _[8]: + +[8] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/CFQFGU6H2D5GZYMUYGTGUSXIU3OYZP6U/ + +.. _[9]: + +[9] https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#dynamic-configuration-during-cold-boot + +-------------- + +*Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/components/ffa-manifest-binding.rst b/docs/components/ffa-manifest-binding.rst index 6d2f905a5..7483c9002 100644 --- a/docs/components/ffa-manifest-binding.rst +++ b/docs/components/ffa-manifest-binding.rst @@ -114,6 +114,19 @@ Partition Properties - managed-exit - value type: <empty> - Specifies if managed exit is supported. + - This field is deprecated in favor of ns-interrupts-action field in the FF-A + v1.1 EAC0 spec. + +- ns-interrupts-action [mandatory] + - value type: <u32> + - Specifies the action that the SPMC must take in response to a Non-secure + physical interrupt. + + - 0x0: Non-secure interrupt is queued + - 0x1: Non-secure interrupt is signaled after a managed exit + - 0x2: Non-secure interrupt is signaled + + - This field supersedes the managed-exit field in the FF-A v1.0 spec. - has-primary-scheduler - value type: <empty> diff --git a/docs/components/firmware-update.rst b/docs/components/firmware-update.rst index a59156568..1ba1e1c6e 100644 --- a/docs/components/firmware-update.rst +++ b/docs/components/firmware-update.rst @@ -1,22 +1,118 @@ Firmware Update (FWU) ===================== +This document describes the design of the various Firmware Update (FWU) +mechanisms available in TF-A. + +1. PSA Firmware Update (PSA FWU) +2. TBBR Firmware Update (TBBR FWU) + +PSA Firmware Update implements the specification of the same name (Arm document +IHI 0093), which defines a standard firmware interface for installing firmware +updates. +On the other hand, TBBR Firmware Update only covers firmware recovery. Arguably, +its name is somewhat misleading but the TBBR specification and terminology +predates PSA FWU. Both mechanisms are complementary in the sense that PSA FWU +assumes that the device has a backup or recovery capability in the event of a +failed update, which can be fulfilled with TBBR FWU implementation. + +.. _PSA Firmware Update: + +PSA Firmware Update (PSA FWU) +----------------------------- + Introduction ------------- +~~~~~~~~~~~~ +The `PSA FW update specification`_ defines the concepts of ``Firmware Update +Client`` and ``Firmware Update Agent``. +The new firmware images are provided by the ``Client`` to the ``Update Agent`` +to flash them in non-volatile storage. -This document describes the design of the Firmware Update (FWU) feature, which -enables authenticated firmware to update firmware images from external -interfaces such as USB, UART, SD-eMMC, NAND, NOR or Ethernet to SoC Non-Volatile -memories such as NAND Flash, LPDDR2-NVM or any memory determined by the -platform. This feature functions even when the current firmware in the system -is corrupt or missing; it therefore may be used as a recovery mode. It may also -be complemented by other, higher level firmware update software. +A common system design will place the ``Update Agent`` in the Secure-world +while the ``Client`` executes in the Normal-world. +The `PSA FW update specification`_ provides ABIs meant for a Normal-world +entity aka ``Client`` to transmit the firmware images to the ``Update Agent``. + +Scope +~~~~~ +The design of the ``Client`` and ``Update Agent`` is out of scope of this +document. +This document mainly covers ``Platform Boot`` details i.e. the role of +the second stage Bootloader after FWU has been done by ``Client`` and +``Update Agent``. + +Overview +~~~~~~~~ + +There are active and update banks in the non-volatile storage identified +by the ``active_index`` and the ``update_index`` respectively. +An active bank stores running firmware, whereas an update bank contains +firmware updates. + +Once Firmwares are updated in the update bank of the non-volatile +storage, then ``Update Agent`` marks the update bank as the active bank, +and write updated FWU metadata in non-volatile storage. +On subsequent reboot, the second stage Bootloader (BL2) performs the +following actions: + +- Read FWU metadata in memory +- Retrieve the image specification (offset and length) of updated images + present in non-volatile storage with the help of FWU metadata +- Set these image specification in the corresponding I/O policies of the + updated images using the FWU platform functions + ``plat_fwu_set_images_source()`` and ``plat_fwu_set_metadata_image_source()``, + please refer :ref:`Porting Guide` +- Use these I/O policies to read the images from this address into the memory + +By default, the platform uses the active bank of non-volatile storage to boot +the images in ``trial state``. If images pass through the authentication check +and also if the system successfully booted the Normal-world image then +``Update Agent`` marks this update as accepted after further sanitisation +checking at Normal-world. + +The second stage Bootloader (BL2) avoids upgrading the platform NV-counter until +it's been confirmed that given update is accepted. + +The following sequence diagram shows platform-boot flow: + +.. image:: ../resources/diagrams/PSA-FWU.png + +If the platform fails to boot from active bank due to any reasons such +as authentication failure or non-fuctionality of Normal-world software then the +watchdog will reset to give a chance to the platform to fix the issue. This +boot failure & reset sequence might be repeated up to ``trial state`` times. +After that, the platform can decide to boot from the ``previous_active_index`` +bank. + +If the images still does not boot successfully from the ``previous_active_index`` +bank (e.g. due to ageing effect of non-volatile storage) then the platform can +choose firmware recovery mechanism :ref:`TBBR Firmware Update` to bring system +back to life. + +.. _TBBR Firmware Update: + +TBBR Firmware Update (TBBR FWU) +------------------------------- + +Introduction +~~~~~~~~~~~~ + +This technique enables authenticated firmware to update firmware images from +external interfaces such as USB, UART, SD-eMMC, NAND, NOR or Ethernet to SoC +Non-Volatile memories such as NAND Flash, LPDDR2-NVM or any memory determined +by the platform. +This feature functions even when the current firmware in the system is corrupt +or missing; it therefore may be used as a recovery mode. It may also be +complemented by other, higher level firmware update software. FWU implements a specific part of the Trusted Board Boot Requirements (TBBR) specification, Arm DEN0006C-1. It should be used in conjunction with the :ref:`Trusted Board Boot` design document, which describes the image authentication parts of the Trusted Firmware-A (TF-A) TBBR implementation. +It can be used as a last resort when all firmware updates that are carried out +as part of the :ref:`PSA Firmware Update` procedure have failed to function. + Scope ~~~~~ @@ -25,8 +121,8 @@ describe how normal world FWU images should operate. To implement normal world FWU images, please refer to the "Non-Trusted Firmware Updater" requirements in the TBBR. -FWU Overview ------------- +Overview +~~~~~~~~ The FWU boot flow is primarily mediated by BL1. Since BL1 executes in ROM, and it is usually desirable to minimize the amount of ROM code, the design allows @@ -66,7 +162,7 @@ use all defined FWU images. Other platforms may use a subset of these. |Flow Diagram| Image Identification --------------------- +~~~~~~~~~~~~~~~~~~~~ Each FWU image and certificate is identified by a unique ID, defined by the platform, which BL1 uses to fetch an image descriptor (``image_desc_t``) via a @@ -93,7 +189,7 @@ BL1 uses the FWU image descriptors to: - Initialize the execution state of the next FWU image. FWU State Machine ------------------ +~~~~~~~~~~~~~~~~~ BL1 maintains state for each FWU image during FWU execution. FWU images at lower Exception Levels raise SMCs to invoke FWU functionality in BL1, which causes @@ -126,10 +222,10 @@ The following is a brief description of the supported states: requested BL1 to resume normal world execution. BL1 SMC Interface ------------------ +~~~~~~~~~~~~~~~~~ BL1_SMC_CALL_COUNT -~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^ :: @@ -142,7 +238,7 @@ BL1_SMC_CALL_COUNT This SMC returns the number of SMCs supported by BL1. BL1_SMC_UID -~~~~~~~~~~~ +^^^^^^^^^^^ :: @@ -156,7 +252,7 @@ This SMC returns the 128-bit `Universally Unique Identifier`_ for the BL1 SMC service. BL1_SMC_VERSION -~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^ :: @@ -170,7 +266,7 @@ BL1_SMC_VERSION This SMC returns the current version of the BL1 SMC service. BL1_SMC_RUN_IMAGE -~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^ :: @@ -190,7 +286,7 @@ This SMC passes execution control to an EL3 image described by the provided this SMC for BL1 to pass execution control to BL31. FWU_SMC_IMAGE_COPY -~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^ :: @@ -239,7 +335,7 @@ contiguous memory. Once the SMC is handled, BL1 returns from exception to the normal world caller. FWU_SMC_IMAGE_AUTH -~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^ :: @@ -279,7 +375,7 @@ sets the image state to AUTHENTICATED. If authentication fails then BL1 returns the -EAUTH error and sets the image state back to RESET. FWU_SMC_IMAGE_EXECUTE -~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^ :: @@ -307,7 +403,7 @@ BL1 saves the normal world caller's context, sets the secure image state to EXECUTED, and returns from exception to the secure image. FWU_SMC_IMAGE_RESUME -~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^ :: @@ -334,7 +430,7 @@ the resuming world. If the call is successful then the caller provided returned to the caller. FWU_SMC_SEC_IMAGE_DONE -~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^ :: @@ -355,7 +451,7 @@ restores the normal world context and returns from exception into the normal world. FWU_SMC_UPDATE_DONE -~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^ :: @@ -371,7 +467,7 @@ function ``bl1_plat_fwu_done``, passing the optional argument ``client_cookie`` a ``void *``. The SMC does not return. FWU_SMC_IMAGE_RESET -~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^ :: @@ -393,8 +489,9 @@ This is only allowed if the image is not being executed. -------------- -*Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.* .. _Universally Unique Identifier: https://tools.ietf.org/rfc/rfc4122.txt .. |Flow Diagram| image:: ../resources/diagrams/fwu_flow.png .. |FWU state machine| image:: ../resources/diagrams/fwu_states.png +.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ diff --git a/docs/components/index.rst b/docs/components/index.rst index 2f81f23f2..30d80fcdd 100644 --- a/docs/components/index.rst +++ b/docs/components/index.rst @@ -4,7 +4,6 @@ Components .. toctree:: :maxdepth: 1 :caption: Contents - :numbered: spd/index activity-monitors @@ -20,8 +19,10 @@ Components romlib-design sdei secure-partition-manager + el3-spmc secure-partition-manager-mm xlat-tables-lib-v2-design cot-binding realm-management-extension + rmm-el3-comms-spec granule-protection-tables-design diff --git a/docs/components/ras.rst b/docs/components/ras.rst index 02207d8b7..871be2d76 100644 --- a/docs/components/ras.rst +++ b/docs/components/ras.rst @@ -6,10 +6,11 @@ Serviceability (RAS) extensions. RAS is a mandatory extension for Armv8.2 and later CPUs, and also an optional extension to the base Armv8.0 architecture. In conjunction with the |EHF|, support for RAS extension enables firmware-first -paradigm for handling platform errors: exceptions resulting from errors are -routed to and handled in EL3. Said errors are Synchronous External Abort (SEA), -Asynchronous External Abort (signalled as SErrors), Fault Handling and Error -Recovery interrupts. The |EHF| document mentions various :ref:`error handling +paradigm for handling platform errors: exceptions resulting from errors in +Non-secure world are routed to and handled in EL3. +Said errors are Synchronous External Abort (SEA), Asynchronous External Abort +(signalled as SErrors), Fault Handling and Error Recovery interrupts. +The |EHF| document mentions various :ref:`error handling use-cases <delegation-use-cases>` . For the description of Arm RAS extensions, Standard Error Records, and the @@ -29,9 +30,9 @@ introduced by the RAS extensions. .. __: `Standard Error Record helpers`_ The build option ``RAS_EXTENSION`` when set to ``1`` includes the RAS in run -time firmware; ``EL3_EXCEPTION_HANDLING`` and ``HANDLE_EA_EL3_FIRST`` must also -be set ``1``. ``RAS_TRAP_LOWER_EL_ERR_ACCESS`` controls the access to the RAS -error record registers from lower ELs. +time firmware; ``EL3_EXCEPTION_HANDLING`` and ``HANDLE_EA_EL3_FIRST_NS`` must also +be set ``1``. ``RAS_TRAP_NS_ERR_REC_ACCESS`` controls the access to the RAS +error record registers from Non-secure. .. _ras-figure: @@ -198,8 +199,8 @@ related, build options: - ``EL3_EXCEPTION_HANDLING=1`` enables handling of exceptions at EL3. See `Interaction with Exception Handling Framework`_; -- ``HANDLE_EA_EL3_FIRST=1`` enables routing of External Aborts and SErrors to - EL3. +- ``HANDLE_EA_EL3_FIRST_NS=1`` enables routing of External Aborts and SErrors, + resulting from errors in NS world, to EL3. The RAS support in |TF-A| introduces a default implementation of ``plat_ea_handler``, the External Abort handler in EL3. When ``RAS_EXTENSION`` diff --git a/docs/components/realm-management-extension.rst b/docs/components/realm-management-extension.rst index 5fa51400d..6fc0c2e25 100644 --- a/docs/components/realm-management-extension.rst +++ b/docs/components/realm-management-extension.rst @@ -73,6 +73,14 @@ RMMD is a new standard runtime service that handles the switch to the Realm world. It initializes the RMM and handles Realm Management Interface (RMI) SMC calls from Non-secure and Realm worlds. +There is a contract between RMM and RMMD that defines the arguments that the +former needs to take in order to initialize and also the possible return values. +This contract is defined in the RMM Boot Interface, which can be found at +:ref:`rmm_el3_boot_interface`. + +There is also a specification of the runtime services provided by TF-A +to RMM. This can be found at :ref:`runtime_services_and_interface`. + Test Realm Payload (TRP) ************************* TRP is a small test payload that runs at R-EL2 and implements a subset of @@ -87,66 +95,218 @@ Building and running TF-A with RME This section describes how you can build and run TF-A with RME enabled. We assume you have all the :ref:`Prerequisites` to build TF-A. -To enable RME, you need to set the ENABLE_RME build flag when building -TF-A. Currently, this feature is only supported for the FVP platform. - The following instructions show you how to build and run TF-A with RME -for two scenarios: TF-A with TF-A Tests, and four-world execution with -Hafnium and TF-A Tests. The instructions assume you have already obtained -TF-A. You can use the following command to clone TF-A. +for two scenarios: -.. code:: shell +- Three-world execution: TF-A with TF-A Tests or Linux. - git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + - NS (TF-A Test or Linux), + - Root (TF-A) + - Realm (RMM or TRP) + +- Four-world execution: TF-A, Hafnium and TF-A Tests or Linux. + + - NS (TF-A Test or Linux), + - Root (TF-A) + - Realm (RMM or TRP) + - SPM (Hafnium) To run the tests, you need an FVP model. Please use the :ref:`latest version <Arm Fixed Virtual Platforms (FVP)>` of *FVP_Base_RevC-2xAEMvA* model. -.. note:: +Three World Testing with TF-A Tests +************************************* - ENABLE_RME build option is currently experimental. +**1. Obtain and build TF-A Tests with Realm Payload** + +The full set of instructions to setup build host and build options for +TF-A-Tests can be found in the `TFTF Getting Started`_. -Building TF-A with TF-A Tests -******************************************** Use the following instructions to build TF-A with `TF-A Tests`_ as the non-secure payload (BL33). -**1. Obtain and build TF-A Tests** - .. code:: shell git clone https://git.trustedfirmware.org/TF-A/tf-a-tests.git cd tf-a-tests - make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 + make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 all pack_realm -This produces a TF-A Tests binary (*tftf.bin*) in the *build/fvp/debug* directory. +This produces a TF-A Tests binary (**tftf.bin**) with Realm payload packaged +and **sp_layout.json** in the **build/fvp/debug** directory. -**2. Build TF-A** +**2. Obtain and build RMM Image** + +Please refer to the `RMM Getting Started`_ on how to setup +Host Environment and build RMM. + +The below command shows how to build RMM using the default build options for FVP. + +.. code:: shell + + git clone --recursive https://git.trustedfirmware.org/TF-RMM/tf-rmm.git + cd tf-rmm + cmake -DRMM_CONFIG=fvp_defcfg -S . -B build + cmake --build build + +This will generate **rmm.img** in **build** folder. + +**3. Build TF-A** + +The `TF-A Getting Started`_ has the necessary instructions to setup Host +machine and build TF-A. + +To build for RME, set ``ENABLE_RME`` build option to 1 and provide the path to +the RMM binary using the ``RMM`` build option. +Currently, this feature is only supported for the FVP platform. + +.. note:: + + ENABLE_RME build option is currently experimental. + +If the ``RMM`` option is not used, then the Test Realm Payload (TRP) in TF-A +will be built and used as the RMM. .. code:: shell + git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git cd trusted-firmware-a make CROSS_COMPILE=aarch64-none-elf- \ PLAT=fvp \ ENABLE_RME=1 \ + RMM=<path/to/rmm.img> \ FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts \ DEBUG=1 \ BL33=<path/to/tftf.bin> \ all fip -This produces *bl1.bin* and *fip.bin* binaries in the *build/fvp/debug* directory. -The above command also builds TRP. The TRP binary is packaged in *fip.bin*. +This produces **bl1.bin** and **fip.bin** binaries in the **build/fvp/debug** directory. + +Running the tests for a 3 world FVP setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Use the following command to run the tests on FVP. TF-A Tests should boot +and run the default tests including Realm world tests. + +.. code:: shell + + FVP_Base_RevC-2xAEMvA \ + -C bp.refcounter.non_arch_start_at_default=1 \ + -C bp.secureflashloader.fname=<path/to/bl1.bin> \ + -C bp.flashloader0.fname=<path/to/fip.bin> \ + -C bp.refcounter.use_real_time=0 \ + -C bp.ve_sysregs.exit_on_shutdown=1 \ + -C cache_state_modelled=1 \ + -C bp.dram_size=2 \ + -C bp.secure_memory=1 \ + -C pci.pci_smmuv3.mmu.SMMU_ROOT_IDR0=3 \ + -C pci.pci_smmuv3.mmu.SMMU_ROOT_IIDR=0x43B \ + -C pci.pci_smmuv3.mmu.root_register_page_offset=0x20000 \ + -C cluster0.NUM_CORES=4 \ + -C cluster0.PA_SIZE=48 \ + -C cluster0.ecv_support_level=2 \ + -C cluster0.gicv3.cpuintf-mmap-access-level=2 \ + -C cluster0.gicv3.without-DS-support=1 \ + -C cluster0.gicv4.mask-virtual-interrupt=1 \ + -C cluster0.has_arm_v8-6=1 \ + -C cluster0.has_amu=1 \ + -C cluster0.has_branch_target_exception=1 \ + -C cluster0.rme_support_level=2 \ + -C cluster0.has_rndr=1 \ + -C cluster0.has_v8_7_pmu_extension=2 \ + -C cluster0.max_32bit_el=-1 \ + -C cluster0.stage12_tlb_size=1024 \ + -C cluster0.check_memory_attributes=0 \ + -C cluster0.ish_is_osh=1 \ + -C cluster0.restriction_on_speculative_execution=2 \ + -C cluster0.restriction_on_speculative_execution_aarch32=2 \ + -C cluster1.NUM_CORES=4 \ + -C cluster1.PA_SIZE=48 \ + -C cluster1.ecv_support_level=2 \ + -C cluster1.gicv3.cpuintf-mmap-access-level=2 \ + -C cluster1.gicv3.without-DS-support=1 \ + -C cluster1.gicv4.mask-virtual-interrupt=1 \ + -C cluster1.has_arm_v8-6=1 \ + -C cluster1.has_amu=1 \ + -C cluster1.has_branch_target_exception=1 \ + -C cluster1.rme_support_level=2 \ + -C cluster1.has_rndr=1 \ + -C cluster1.has_v8_7_pmu_extension=2 \ + -C cluster1.max_32bit_el=-1 \ + -C cluster1.stage12_tlb_size=1024 \ + -C cluster1.check_memory_attributes=0 \ + -C cluster1.ish_is_osh=1 \ + -C cluster1.restriction_on_speculative_execution=2 \ + -C cluster1.restriction_on_speculative_execution_aarch32=2 \ + -C pctl.startup=0.0.0.0 \ + -C bp.smsc_91c111.enabled=1 \ + -C bp.hostbridge.userNetworking=1 + +The bottom of the output from *uart0* should look something like the following. + +.. code-block:: shell + + ... + + > Test suite 'FF-A Interrupt' + Passed + > Test suite 'SMMUv3 tests' + Passed + > Test suite 'PMU Leakage' + Passed + > Test suite 'DebugFS' + Passed + > Test suite 'RMI and SPM tests' + Passed + > Test suite 'Realm payload at EL1' + Passed + > Test suite 'Invalid memory access' + Passed + ... + +Building TF-A with RME enabled Linux Kernel +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +If an RME enabled Linux kernel and filesystem is available for testing, +and a suitable NS boot loader is not available, then this option can be used to +launch kernel directly after BL31: + +.. code-block:: shell + + cd trusted-firmware-a + make CROSS_COMPILE=aarch64-none-elf- \ + PLAT=fvp \ + ENABLE_RME=1 \ + RMM=<path/to/rmm.img> \ + FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts \ + DEBUG=1 \ + ARM_LINUX_KERNEL_AS_BL33=1 \ + PRELOADED_BL33_BASE=0x84000000 \ + all fip + +Boot and run the RME enabled Linux Kernel +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Use the following additional arguments to boot the kernel on FVP. + +.. code-block:: shell + + --data cluster0.cpu0=<path_to_kernel_Image>@0x84000000 \ + -C bp.virtioblockdevice.image_path=<path_to_rootfs.ext4> + +.. tip:: + + Set the FVP option `cache_state_modelled=0` to run Linux based tests much faster. Four-world execution with Hafnium and TF-A Tests -**************************************************** -Four-world execution involves software components at each security state: root, +************************************************* + +Four-world execution involves software components in each security state: root, secure, realm and non-secure. This section describes how to build TF-A -with four-world support. We use TF-A as the root firmware, `Hafnium`_ as the -secure component, TRP as the realm-world firmware and TF-A Tests as the -non-secure payload. +with four-world support. -Before building TF-A, you first need to build the other software components. -You can find instructions on how to get and build TF-A Tests above. +We use TF-A as the root firmware, `Hafnium SPM`_ is the reference Secure world component +and the software components for the other 2 worlds (Realm and Non-Secure) +are as described in the previous section. **1. Obtain and build Hafnium** @@ -156,6 +316,27 @@ You can find instructions on how to get and build TF-A Tests above. cd hafnium # Use the default prebuilt LLVM/clang toolchain PATH=$PWD/prebuilts/linux-x64/clang/bin:$PWD/prebuilts/linux-x64/dtc:$PATH + +Feature MTE needs to be disabled in Hafnium build, apply following patch to +project/reference submodule + +.. code:: diff + + diff --git a/BUILD.gn b/BUILD.gn + index cc6a78f..234b20a 100644 + --- a/BUILD.gn + +++ b/BUILD.gn + @@ -83,7 +83,6 @@ aarch64_toolchains("secure_aem_v8a_fvp") { + pl011_base_address = "0x1c090000" + smmu_base_address = "0x2b400000" + smmu_memory_size = "0x100000" + - enable_mte = "1" + plat_log_level = "LOG_LEVEL_INFO" + } + } + +.. code:: shell + make PROJECT=reference The Hafnium binary should be located at @@ -165,6 +346,8 @@ The Hafnium binary should be located at Build TF-A with RME as well as SPM enabled. +Use sp_layout.json previously generated in tf-a-test build. + .. code:: shell make CROSS_COMPILE=aarch64-none-elf- \ @@ -176,92 +359,33 @@ Build TF-A with RME as well as SPM enabled. BRANCH_PROTECTION=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ DEBUG=1 \ - SP_LAYOUT_FILE=<path/to/tf-a-tests>/build/fvp/debug/sp_layout.json> \ + SP_LAYOUT_FILE=<path/to/sp_layout.json> \ BL32=<path/to/hafnium.bin> \ BL33=<path/to/tftf.bin> \ + RMM=<path/to/rmm.img> \ all fip -Running the tests -********************* -Use the following command to run the tests on FVP. TF-A Tests should boot -and run the default tests including RME tests. +Running the tests for a 4 world FVP setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. code:: shell - - FVP_Base_RevC-2xAEMvA \ - -C bp.flashloader0.fname=<path/to/fip.bin> \ - -C bp.secureflashloader.fname=<path/to/bl1.bin> \ - -C bp.refcounter.non_arch_start_at_default=1 \ - -C bp.refcounter.use_real_time=0 \ - -C bp.ve_sysregs.exit_on_shutdown=1 \ - -C cache_state_modelled=1 \ - -C cluster0.NUM_CORES=4 \ - -C cluster0.PA_SIZE=48 \ - -C cluster0.ecv_support_level=2 \ - -C cluster0.gicv3.cpuintf-mmap-access-level=2 \ - -C cluster0.gicv3.without-DS-support=1 \ - -C cluster0.gicv4.mask-virtual-interrupt=1 \ - -C cluster0.has_arm_v8-6=1 \ - -C cluster0.has_branch_target_exception=1 \ - -C cluster0.has_rme=1 \ - -C cluster0.has_rndr=1 \ - -C cluster0.has_amu=1 \ - -C cluster0.has_v8_7_pmu_extension=2 \ - -C cluster0.max_32bit_el=-1 \ - -C cluster0.restriction_on_speculative_execution=2 \ - -C cluster0.restriction_on_speculative_execution_aarch32=2 \ - -C cluster1.NUM_CORES=4 \ - -C cluster1.PA_SIZE=48 \ - -C cluster1.ecv_support_level=2 \ - -C cluster1.gicv3.cpuintf-mmap-access-level=2 \ - -C cluster1.gicv3.without-DS-support=1 \ - -C cluster1.gicv4.mask-virtual-interrupt=1 \ - -C cluster1.has_arm_v8-6=1 \ - -C cluster1.has_branch_target_exception=1 \ - -C cluster1.has_rme=1 \ - -C cluster1.has_rndr=1 \ - -C cluster1.has_amu=1 \ - -C cluster1.has_v8_7_pmu_extension=2 \ - -C cluster1.max_32bit_el=-1 \ - -C cluster1.restriction_on_speculative_execution=2 \ - -C cluster1.restriction_on_speculative_execution_aarch32=2 \ - -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 \ - -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B \ - -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 \ - -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 \ - -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0475 \ - -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 \ - -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 \ - -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 \ - -C bp.pl011_uart0.out_file=uart0.log \ - -C bp.pl011_uart1.out_file=uart1.log \ - -C bp.pl011_uart2.out_file=uart2.log \ - -C pctl.startup=0.0.0.0 \ - -Q 1000 \ - "$@" +Use the following arguments in addition to +`Running the tests for a 3 world FVP setup`_ to run tests for 4 world setup. -The bottom of the output from *uart0* should look something like the following. - -.. code-block:: shell - - ... - - > Test suite 'FF-A Interrupt' - Passed - > Test suite 'SMMUv3 tests' - Passed - > Test suite 'PMU Leakage' - Passed - > Test suite 'DebugFS' - Passed - > Test suite 'Realm payload tests' - Passed - > Test suite 'Invalid memory access' - Passed - ... +.. code:: shell + -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 \ + -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B \ + -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 \ + -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 \ + -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0475 \ + -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 \ + -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 \ + -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 .. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture .. _Arm Architecture Models website: https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models +.. _TF-A Getting Started: https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/index.html .. _TF-A Tests: https://trustedfirmware-a-tests.readthedocs.io/en/latest -.. _Hafnium: https://www.trustedfirmware.org/projects/hafnium +.. _TFTF Getting Started: https://trustedfirmware-a-tests.readthedocs.io/en/latest/getting_started/index.html +.. _Hafnium SPM: https://www.trustedfirmware.org/projects/hafnium +.. _RMM Getting Started: https://git.trustedfirmware.org/TF-RMM/tf-rmm.git/tree/docs/getting_started/index.rst diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst new file mode 100644 index 000000000..8070ff446 --- /dev/null +++ b/docs/components/rmm-el3-comms-spec.rst @@ -0,0 +1,543 @@ +RMM-EL3 Communication interface +******************************* + +This document defines the communication interface between RMM and EL3. +There are two parts in this interface: the boot interface and the runtime +interface. + +The Boot Interface defines the ABI between EL3 and RMM when the CPU enters +R-EL2 for the first time after boot. The cold boot interface defines the ABI +for the cold boot path and the warm boot interface defines the same for the +warm path. + +The RMM-EL3 runtime interface defines the ABI for EL3 services which can be +invoked by RMM as well as the register save-restore convention when handling an +SMC call from NS. + +The below sections discuss these interfaces more in detail. + +.. _rmm_el3_ifc_versioning: + +RMM-EL3 Interface versioning +____________________________ + +The RMM Boot and Runtime Interface uses a version number to check +compatibility with the register arguments passed as part of Boot Interface and +RMM-EL3 runtime interface. + +The Boot Manifest, discussed later in section :ref:`rmm_el3_boot_manifest`, +uses a separate version number but with the same scheme. + +The version number is a 32-bit type with the following fields: + +.. csv-table:: + :header: "Bits", "Value" + + [0:15],``VERSION_MINOR`` + [16:30],``VERSION_MAJOR`` + [31],RES0 + +The version numbers are sequentially increased and the rules for updating them +are explained below: + + - ``VERSION_MAJOR``: This value is increased when changes break + compatibility with previous versions. If the changes + on the ABI are compatible with the previous one, ``VERSION_MAJOR`` + remains unchanged. + + - ``VERSION_MINOR``: This value is increased on any change that is backwards + compatible with the previous version. When ``VERSION_MAJOR`` is increased, + ``VERSION_MINOR`` must be set to 0. + + - ``RES0``: Bit 31 of the version number is reserved 0 as to maintain + consistency with the versioning schemes used in other parts of RMM. + +This document specifies the 0.1 version of Boot Interface ABI and RMM-EL3 +services specification and the 0.1 version of the Boot Manifest. + +.. _rmm_el3_boot_interface: + +RMM Boot Interface +__________________ + +This section deals with the Boot Interface part of the specification. + +One of the goals of the Boot Interface is to allow EL3 firmware to pass +down into RMM certain platform specific information dynamically. This allows +RMM to be less platform dependent and be more generic across platform +variations. It also allows RMM to be decoupled from the other boot loader +images in the boot sequence and remain agnostic of any particular format used +for configuration files. + +The Boot Interface ABI defines a set of register conventions and +also a memory based manifest file to pass information from EL3 to RMM. The +boot manifest and the associated platform data in it can be dynamically created +by EL3 and there is no restriction on how the data can be obtained (e.g by DTB, +hoblist or other). + +The register convention and the manifest are versioned separately to manage +future enhancements and compatibility. + +RMM completes the boot by issuing the ``RMM_BOOT_COMPLETE`` SMC (0xC40001CF) +back to EL3. After the RMM has finished the boot process, it can only be +entered from EL3 as part of RMI handling. + +If RMM returns an error during boot (in any CPU), then RMM must not be entered +from any CPU. + +.. _rmm_cold_boot_interface: + +Cold Boot Interface +~~~~~~~~~~~~~~~~~~~ + +During cold boot RMM expects the following register values: + +.. csv-table:: + :header: "Register", "Value" + :widths: 1, 5 + + x0,Linear index of this PE. This index starts from 0 and must be less than the maximum number of CPUs to be supported at runtime (see x2). + x1,Version for this Boot Interface as defined in :ref:`rmm_el3_ifc_versioning`. + x2,Maximum number of CPUs to be supported at runtime. RMM should ensure that it can support this maximum number. + x3,Base address for the shared buffer used for communication between EL3 firmware and RMM. This buffer must be of 4KB size (1 page). The boot manifest must be present at the base of this shared buffer during cold boot. + +During cold boot, EL3 firmware needs to allocate a 4K page that will be +passed to RMM in x3. This memory will be used as shared buffer for communication +between EL3 and RMM. It must be assigned to Realm world and must be mapped with +Normal memory attributes (IWB-OWB-ISH) at EL3. At boot, this memory will be +used to populate the Boot Manifest. Since the Boot Manifest can be accessed by +RMM prior to enabling its MMU, EL3 must ensure that proper cache maintenance +operations are performed after the Boot Manifest is populated. + +EL3 should also ensure that this shared buffer is always available for use by RMM +during the lifetime of the system and that it can be used for runtime +communication between RMM and EL3. For example, when RMM invokes attestation +service commands in EL3, this buffer can be used to exchange data between RMM +and EL3. It is also allowed for RMM to invoke runtime services provided by EL3 +utilizing this buffer during the boot phase, prior to return back to EL3 via +RMM_BOOT_COMPLETE SMC. + +RMM should map this memory page into its Stage 1 page-tables using Normal +memory attributes. + +During runtime, it is the RMM which initiates any communication with EL3. If that +communication requires the use of the shared area, it is expected that RMM needs +to do the necessary concurrency protection to prevent the use of the same buffer +by other PEs. + +The following sequence diagram shows how a generic EL3 Firmware would boot RMM. + +.. image:: ../resources/diagrams/rmm_cold_boot_generic.png + +Warm Boot Interface +~~~~~~~~~~~~~~~~~~~ + +At warm boot, RMM is already initialized and only some per-CPU initialization +is still pending. The only argument that is required by RMM at this stage is +the CPU Id, which will be passed through register x0 whilst x1 to x3 are RES0. +This is summarized in the following table: + +.. csv-table:: + :header: "Register", "Value" + :widths: 1, 5 + + x0,Linear index of this PE. This index starts from 0 and must be less than the maximum number of CPUs to be supported at runtime (see x2). + x1 - x3,RES0 + +Boot error handling and return values +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +After boot up and initialization, RMM returns control back to EL3 through a +``RMM_BOOT_COMPLETE`` SMC call. The only argument of this SMC call will +be returned in x1 and it will encode a signed integer with the error reason +as per the following table: + +.. csv-table:: + :header: "Error code", "Description", "ID" + :widths: 2 4 1 + + ``E_RMM_BOOT_SUCCESS``,Boot successful,0 + ``E_RMM_BOOT_ERR_UNKNOWN``,Unknown error,-1 + ``E_RMM_BOOT_VERSION_NOT_VALID``,Boot Interface version reported by EL3 is not supported by RMM,-2 + ``E_RMM_BOOT_CPUS_OUT_OF_RAGE``,Number of CPUs reported by EL3 larger than maximum supported by RMM,-3 + ``E_RMM_BOOT_CPU_ID_OUT_OF_RAGE``,Current CPU Id is higher or equal than the number of CPUs supported by RMM,-4 + ``E_RMM_BOOT_INVALID_SHARED_BUFFER``,Invalid pointer to shared memory area,-5 + ``E_RMM_BOOT_MANIFEST_VERSION_NOT_SUPPORTED``,Version reported by the boot manifest not supported by RMM,-6 + ``E_RMM_BOOT_MANIFEST_DATA_ERROR``,Error parsing core boot manifest,-7 + +For any error detected in RMM during cold or warm boot, RMM will return back to +EL3 using ``RMM_BOOT_COMPLETE`` SMC with an appropriate error code. It is +expected that EL3 will take necessary action to disable Realm world for further +entry from NS Host on receiving an error. This will be done across all the PEs +in the system so as to present a symmetric view to the NS Host. Any further +warm boot by any PE should not enter RMM using the warm boot interface. + +.. _rmm_el3_boot_manifest: + +Boot Manifest +~~~~~~~~~~~~~ + +During cold boot, EL3 Firmware passes a memory boot manifest to RMM containing +platform information. + +This boot manifest is versioned independently of the boot interface, to help +evolve the boot manifest independent of the rest of Boot Manifest. +The current version for the boot manifest is ``v0.1`` and the rules explained +in :ref:`rmm_el3_ifc_versioning` apply on this version as well. + +The boot manifest is divided into two different components: + + - Core Manifest: This is the generic parameters passed to RMM by EL3 common to all platforms. + - Platform data: This is defined by the platform owner and contains information specific to that platform. + +For the current version of the manifest, the core manifest contains a pointer +to the platform data. EL3 must ensure that the whole boot manifest, +including the platform data, if available, fits inside the RMM EL3 shared +buffer. + +For the type specification of the RMM Boot Manifest v0.1, refer to +:ref:`rmm_el3_manifest_struct` + +.. _runtime_services_and_interface: + +RMM-EL3 Runtime Interface +__________________________ + +This section defines the RMM-EL3 runtime interface which specifies the ABI for +EL3 services expected by RMM at runtime as well as the register save and +restore convention between EL3 and RMM as part of RMI call handling. It is +important to note that RMM is allowed to invoke EL3-RMM runtime interface +services during the boot phase as well. The EL3 runtime service handling must +not result in a world switch to another world unless specified. Both the RMM +and EL3 are allowed to make suitable optimizations based on this assumption. + +If the interface requires the use of memory, then the memory references should +be within the shared buffer communicated as part of the boot interface. See +:ref:`rmm_cold_boot_interface` for properties of this shared buffer which both +EL3 and RMM must adhere to. + +RMM-EL3 runtime service return codes +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The return codes from EL3 to RMM is a 32 bit signed integer which encapsulates +error condition as described in the following table: + +.. csv-table:: + :header: "Error code", "Description", "ID" + :widths: 2 4 1 + + ``E_RMM_OK``,No errors detected,0 + ``E_RMM_UNK``,Unknown/Generic error,-1 + ``E_RMM_BAD_ADDR``,The value of an address used as argument was invalid,-2 + ``E_RMM_BAD_PAS``,Incorrect PAS,-3 + ``E_RMM_NOMEM``,Not enough memory to perform an operation,-4 + ``E_RMM_INVAL``,The value of an argument was invalid,-5 + +If multiple failure conditions are detected in an RMM to EL3 command, then EL3 +is allowed to return an error code corresponding to any of the failure +conditions. + +RMM-EL3 runtime services +~~~~~~~~~~~~~~~~~~~~~~~~ + +The following table summarizes the RMM runtime services that need to be +implemented by EL3 Firmware. + +.. csv-table:: + :header: "FID", "Command" + :widths: 2 5 + + 0xC400018F,``RMM_RMI_REQ_COMPLETE`` + 0xC40001B0,``RMM_GTSI_DELEGATE`` + 0xC40001B1,``RMM_GTSI_UNDELEGATE`` + 0xC40001B2,``RMM_ATTEST_GET_REALM_KEY`` + 0xC40001B3,``RMM_ATTEST_GET_PLAT_TOKEN`` + +RMM_RMI_REQ_COMPLETE command +============================ + +Notifies the completion of an RMI call to the Non-Secure world. + +This call is the only function currently in RMM-EL3 runtime interface which +results in a world switch to NS. This call is the reply to the original RMI +call and it is forwarded by EL3 to the NS world. + +FID +--- + +``0xC400018F`` + +Input values +------------ + +.. csv-table:: + :header: "Name", "Register", "Field", "Type", "Description" + :widths: 1 1 1 1 5 + + fid,x0,[63:0],UInt64,Command FID + err_code,x1,[63:0],RmiCommandReturnCode,Error code returned by the RMI service invoked by NS World. See Realm Management Monitor specification for more info + +Output values +------------- + +This call does not return. + +Failure conditions +------------------ + +Since this call does not return to RMM, there is no failure condition which +can be notified back to RMM. + +RMM_GTSI_DELEGATE command +========================= + +Delegate a memory granule by changing its PAS from Non-Secure to Realm. + +FID +--- + +``0xC40001B0`` + +Input values +------------ + +.. csv-table:: + :header: "Name", "Register", "Field", "Type", "Description" + :widths: 1 1 1 1 5 + + fid,x0,[63:0],UInt64,Command FID + base_pa,x1,[63:0],Address,PA of the start of the granule to be delegated + +Output values +------------- + +.. csv-table:: + :header: "Name", "Register", "Field", "Type", "Description" + :widths: 1 1 1 2 4 + + Result,x0,[63:0],Error Code,Command return status + +Failure conditions +------------------ + +The table below shows all the possible error codes returned in ``Result`` upon +a failure. The errors are ordered by condition check. + +.. csv-table:: + :header: "ID", "Condition" + :widths: 1 5 + + ``E_RMM_BAD_ADDR``,``PA`` does not correspond to a valid granule address + ``E_RMM_BAD_PAS``,The granule pointed by ``PA`` does not belong to Non-Secure PAS + ``E_RMM_OK``,No errors detected + +RMM_GTSI_UNDELEGATE command +=========================== + +Undelegate a memory granule by changing its PAS from Realm to Non-Secure. + +FID +--- + +``0xC40001B1`` + +Input values +------------ + +.. csv-table:: + :header: "Name", "Register", "Field", "Type", "Description" + :widths: 1 1 1 1 5 + + fid,x0,[63:0],UInt64,Command FID + base_pa,x1,[63:0],Address,PA of the start of the granule to be undelegated + +Output values +------------- + +.. csv-table:: + :header: "Name", "Register", "Field", "Type", "Description" + :widths: 1 1 1 2 4 + + Result,x0,[63:0],Error Code,Command return status + +Failure conditions +------------------ + +The table below shows all the possible error codes returned in ``Result`` upon +a failure. The errors are ordered by condition check. + +.. csv-table:: + :header: "ID", "Condition" + :widths: 1 5 + + ``E_RMM_BAD_ADDR``,``PA`` does not correspond to a valid granule address + ``E_RMM_BAD_PAS``,The granule pointed by ``PA`` does not belong to Realm PAS + ``E_RMM_OK``,No errors detected + +RMM_ATTEST_GET_REALM_KEY command +================================ + +Retrieve the Realm Attestation Token Signing key from EL3. + +FID +--- + +``0xC40001B2`` + +Input values +------------ + +.. csv-table:: + :header: "Name", "Register", "Field", "Type", "Description" + :widths: 1 1 1 1 5 + + fid,x0,[63:0],UInt64,Command FID + buf_pa,x1,[63:0],Address,PA where the Realm Attestation Key must be stored by EL3. The PA must belong to the shared buffer + buf_size,x2,[63:0],Size,Size in bytes of the Realm Attestation Key buffer. ``bufPa + bufSize`` must lie within the shared buffer + ecc_curve,x3,[63:0],Enum,Type of the elliptic curve to which the requested attestation key belongs to. See :ref:`ecc_curves` + +Output values +------------- + +.. csv-table:: + :header: "Name", "Register", "Field", "Type", "Description" + :widths: 1 1 1 1 5 + + Result,x0,[63:0],Error Code,Command return status + keySize,x1,[63:0],Size,Size of the Realm Attestation Key + +Failure conditions +------------------ + +The table below shows all the possible error codes returned in ``Result`` upon +a failure. The errors are ordered by condition check. + +.. csv-table:: + :header: "ID", "Condition" + :widths: 1 5 + + ``E_RMM_BAD_ADDR``,``PA`` is outside the shared buffer + ``E_RMM_INVAL``,``PA + BSize`` is outside the shared buffer + ``E_RMM_INVAL``,``Curve`` is not one of the listed in :ref:`ecc_curves` + ``E_RMM_UNK``,An unknown error occurred whilst processing the command + ``E_RMM_OK``,No errors detected + +.. _ecc_curves: + +Supported ECC Curves +-------------------- + +.. csv-table:: + :header: "ID", "Curve" + :widths: 1 5 + + 0,ECC SECP384R1 + +RMM_ATTEST_GET_PLAT_TOKEN command +================================= + +Retrieve the Platform Token from EL3. + +FID +--- + +``0xC40001B3`` + +Input values +------------ + +.. csv-table:: + :header: "Name", "Register", "Field", "Type", "Description" + :widths: 1 1 1 1 5 + + fid,x0,[63:0],UInt64,Command FID + buf_pa,x1,[63:0],Address,PA of the platform attestation token. The challenge object is passed in this buffer. The PA must belong to the shared buffer + buf_size,x2,[63:0],Size,Size in bytes of the platform attestation token buffer. ``bufPa + bufSize`` must lie within the shared buffer + c_size,x3,[63:0],Size,Size in bytes of the challenge object. It corresponds to the size of one of the defined SHA algorithms + +Output values +------------- + +.. csv-table:: + :header: "Name", "Register", "Field", "Type", "Description" + :widths: 1 1 1 1 5 + + Result,x0,[63:0],Error Code,Command return status + tokenSize,x1,[63:0],Size,Size of the platform token + +Failure conditions +------------------ + +The table below shows all the possible error codes returned in ``Result`` upon +a failure. The errors are ordered by condition check. + +.. csv-table:: + :header: "ID", "Condition" + :widths: 1 5 + + ``E_RMM_BAD_ADDR``,``PA`` is outside the shared buffer + ``E_RMM_INVAL``,``PA + BSize`` is outside the shared buffer + ``E_RMM_INVAL``,``CSize`` does not represent the size of a supported SHA algorithm + ``E_RMM_UNK``,An unknown error occurred whilst processing the command + ``E_RMM_OK``,No errors detected + +RMM-EL3 world switch register save restore convention +_____________________________________________________ + +As part of NS world switch, EL3 is expected to maintain a register context +specific to each world and will save and restore the registers +appropriately. This section captures the contract between EL3 and RMM on the +register set to be saved and restored. + +EL3 must maintain a separate register context for the following: + + #. General purpose registers (x0-x30) and ``sp_el0``, ``sp_el2`` stack pointers + #. EL2 system register context for all enabled features by EL3. These include system registers with the ``_EL2`` prefix. The EL2 physical and virtual timer registers must not be included in this. + +As part of SMC forwarding between the NS world and Realm world, EL3 allows x0-x7 to be passed +as arguments to Realm and x0-x4 to be used for return arguments back to Non Secure. +As per SMCCCv1.2, x4 must be preserved if not being used as return argument by the SMC function +and it is the responsibility of RMM to preserve this or use this as a return argument. +EL3 will always copy x0-x4 from Realm context to NS Context. + +EL3 will not save some registers as mentioned in the below list. It is the +responsibility of RMM to ensure that these are appropriately saved if the +Realm World makes use of them: + + #. FP/SIMD registers + #. SVE registers + #. SME registers + #. EL1/0 registers + +It is the responsibility of EL3 that any other registers other than the ones mentioned above +will not be leaked to the NS Host and to maintain the confidentiality of the Realm World. + +SMCCC v1.3 allows NS world to specify whether SVE context is in use. In this +case, RMM could choose to not save the incoming SVE context but must ensure +to clear SVE registers if they have been used in Realm World. The same applies +to SME registers. + +Types +_____ + +.. _rmm_el3_manifest_struct: + +RMM-EL3 Boot Manifest Version +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The RMM-EL3 Boot Manifest structure contains platform boot information passed +from EL3 to RMM. The width of the Boot Manifest is 128 bits + +.. image:: ../resources/diagrams/rmm_el3_manifest_struct.png + +The members of the RMM-EL3 Boot Manifest structure are shown in the following +table: + +.. csv-table:: + :header: "Name", "Range", "Type", Description + :widths: 2 1 1 4 + + ``Version Minor``,15:0,uint16_t,Version Minor part of the Boot Manifest Version. + ``Version Major``,30:16,uint16_t,Version Major part of the Boot Manifest Version. + ``RES0``,31,bit,Reserved. Set to 0. + ``Platform Data``,127:64,Address,Pointer to the Platform Data section of the Boot Manifest. diff --git a/docs/components/secure-partition-manager.rst b/docs/components/secure-partition-manager.rst index 18d870bdc..cd439ad6f 100644 --- a/docs/components/secure-partition-manager.rst +++ b/docs/components/secure-partition-manager.rst @@ -794,6 +794,8 @@ As part of the FF-A v1.1 support, the following interfaces were added: - ``FFA_SECONDARY_EP_REGISTER`` - ``FFA_MEM_PERM_GET`` - ``FFA_MEM_PERM_SET`` + - ``FFA_MSG_SEND2`` + - ``FFA_RX_ACQUIRE`` FFA_VERSION ~~~~~~~~~~~ @@ -827,7 +829,11 @@ regime as secure buffers in the MMU descriptors. When invoked from the Hypervisor or OS kernel, the buffers are mapped into the SPMC EL2 Stage-1 translation regime and marked as NS buffers in the MMU -descriptors. +descriptors. The provided addresses may be owned by a VM in the normal world, +which is expected to receive messages from the secure world. The SPMC will in +this case allocate internal state structures to facilitate RX buffer access +synchronization (through FFA_RX_ACQUIRE interface), and to permit SPs to send +messages. The FFA_RXTX_UNMAP unmaps the RX/TX pair from the translation regime of the caller, either it being the Hypervisor or OS kernel, as well as a secure @@ -969,6 +975,53 @@ secondary execution contexts. A secondary EC is first resumed either upon invocation of PSCI_CPU_ON from the NWd or by invocation of FFA_RUN. +FFA_RX_ACQUIRE/FFA_RX_RELEASE +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The RX buffers can be used to pass information to an FF-A endpoint in the +following scenarios: + + - When it was targetted by a FFA_MSG_SEND2 invokation from another endpoint. + - Return the result of calling ``FFA_PARTITION_INFO_GET``. + - In a memory share operation, as part of the ``FFA_MEM_RETRIEVE_RESP``, + with the memory descriptor of the shared memory. + +If a normal world VM is expected to exchange messages with secure world, +its RX/TX buffer addresses are forwarded to the SPMC via FFA_RXTX_MAP ABI, +and are from this moment owned by the SPMC. +The hypervisor must call the FFA_RX_ACQUIRE interface before attempting +to use the RX buffer, in any of the aforementioned scenarios. A successful +call to FFA_RX_ACQUIRE transfers ownership of RX buffer to hypervisor, such +that it can be safely used. + +The FFA_RX_RELEASE interface is used after the FF-A endpoint is done with +processing the data received in its RX buffer. If the RX buffer has been +acquired by the hypervisor, the FFA_RX_RELEASE call must be forwarded to +the SPMC to reestablish SPMC's RX ownership. + +An attempt from an SP to send a message to a normal world VM whose RX buffer +was acquired by the hypervisor fails with error code FFA_BUSY, to preserve +the RX buffer integrity. +The operation could then be conducted after FFA_RX_RELEASE. + +FFA_MSG_SEND2 +~~~~~~~~~~~~~ + +Hafnium copies a message from the sender TX buffer into receiver's RX buffer. +For messages from SPs to VMs, operation is only possible if the SPMC owns +the receiver's RX buffer. + +Both receiver and sender need to enable support for indirect messaging, +in their respective partition manifest. The discovery of support +of such feature can be done via FFA_PARTITION_INFO_GET. + +On a successful message send, Hafnium pends an RX buffer full framework +notification for the receiver, to inform it about a message in the RX buffer. + +The handling of framework notifications is similar to that of +global notifications. Binding of these is not necessary, as these are +reserved to be used by the hypervisor or SPMC. + SPMC-SPMD direct requests/responses ----------------------------------- @@ -1009,6 +1062,40 @@ configuration is made part of a vCPU context. For S-EL0 partitions with VHE enabled, a single secure EL2&0 Stage-1 translation regime is used for both Hafnium and the partition. +Schedule modes and SP Call chains +--------------------------------- + +An SP execution context is said to be in SPMC scheduled mode if CPU cycles are +allocated to it by SPMC. Correspondingly, an SP execution context is said to be +in Normal world scheduled mode if CPU cycles are allocated by the normal world. + +A call chain represents all SPs in a sequence of invocations of a direct message +request. When execution on a PE is in the secure state, only a single call chain +that runs in the Normal World scheduled mode can exist. FF-A v1.1 spec allows +any number of call chains to run in the SPMC scheduled mode but the Hafnium +SPMC restricts the number of call chains in SPMC scheduled mode to only one for +keeping the implementation simple. + +Partition runtime models +------------------------ + +The runtime model of an endpoint describes the transitions permitted for an +execution context between various states. These are the four partition runtime +models supported (refer to `[1]`_ section 7): + + - RTM_FFA_RUN: runtime model presented to an execution context that is + allocated CPU cycles through FFA_RUN interface. + - RTM_FFA_DIR_REQ: runtime model presented to an execution context that is + allocated CPU cycles through FFA_MSG_SEND_DIRECT_REQ interface. + - RTM_SEC_INTERRUPT: runtime model presented to an execution context that is + allocated CPU cycles by SPMC to handle a secure interrupt. + - RTM_SP_INIT: runtime model presented to an execution context that is + allocated CPU cycles by SPMC to initialize its state. + +If an endpoint execution context attempts to make an invalid transition or a +valid transition that could lead to a loop in the call chain, SPMC denies the +transition with the help of above runtime models. + Interrupt management -------------------- @@ -1020,44 +1107,58 @@ trapped at S-EL2. The SPMC manages interrupt resources and allocates interrupt IDs based on SP manifests. The SPMC acknowledges physical interrupts and injects virtual interrupts by setting the use of vIRQ/vFIQ bits before resuming a SP. -Non-secure interrupt handling -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Abbreviations: -The following illustrate the scenarios of non secure physical interrupts trapped -by the SPMC: + - NS-Int: A non-secure physical interrupt. It requires a switch to the normal + world to be handled if it triggers while execution is in secure world. + - Other S-Int: A secure physical interrupt targeted to an SP different from + the one that is currently running. + - Self S-Int: A secure physical interrupt targeted to the SP that is currently + running. -- The SP handles a managed exit operation: +Non-secure interrupt handling +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. image:: ../resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png +This section documents the actions supported in SPMC in response to a non-secure +interrupt as per the guidance provided by FF-A v1.1 EAC0 specification. +An SP specifies one of the following actions in its partition manifest: -- The SP is pre-empted without managed exit: + - Non-secure interrupt is signaled. + - Non-secure interrupt is signaled after a managed exit. + - Non-secure interrupt is queued. -.. image:: ../resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png +An SP execution context in a call chain could specify a less permissive action +than subsequent SP execution contexts in the same call chain. The less +permissive action takes precedence over the more permissive actions specified +by the subsequent execution contexts. Please refer to FF-A v1.1 EAC0 section +8.3.1 for further explanation. Secure interrupt handling -------------------------- +~~~~~~~~~~~~~~~~~~~~~~~~~ This section documents the support implemented for secure interrupt handling in -SPMC as per the guidance provided by FF-A v1.1 Beta0 specification. +SPMC as per the guidance provided by FF-A v1.1 EAC0 specification. The following assumptions are made about the system configuration: - In the current implementation, S-EL1 SPs are expected to use the para - virtualized ABIs for interrupt management rather than accessing virtual GIC - interface. + virtualized ABIs for interrupt management rather than accessing the virtual + GIC interface. - Unless explicitly stated otherwise, this support is applicable only for S-EL1 SPs managed by SPMC. - Secure interrupts are configured as G1S or G0 interrupts. - All physical interrupts are routed to SPMC when running a secure partition execution context. - -A physical secure interrupt could preempt normal world execution. Moreover, when -the execution is in secure world, it is highly likely that the target of a -secure interrupt is not the currently running execution context of an SP. It -could be targeted to another FF-A component. Consequently, secure interrupt -management depends on the state of the target execution context of the SP that -is responsible for handling the interrupt. Hence, the spec provides guidance on -how to signal start and completion of secure interrupt handling as discussed in -further sections. + - All endpoints with multiple execution contexts have their contexts pinned + to corresponding CPUs. Hence, a secure virtual interrupt cannot be signaled + to a target vCPU that is currently running or blocked on a different + physical CPU. + +A physical secure interrupt could trigger while CPU is executing in normal world +or secure world. +The action of SPMC for a secure interrupt depends on: the state of the target +execution context of the SP that is responsible for handling the interrupt; +whether the interrupt triggered while execution was in normal world or secure +world. Secure interrupt signaling mechanisms ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1100,47 +1201,46 @@ following mechanisms: - ``FFA_MSG_WAIT`` ABI if it was in WAITING state. - ``FFA_RUN`` ABI if its was in BLOCKED state. -In the current implementation, S-EL1 SPs use para-virtualized HVC interface -implemented by SPMC to perform priority drop and interrupt deactivation (we -assume EOImode = 0, i.e. priority drop and deactivation are done together). - -If normal world execution was preempted by secure interrupt, SPMC uses +This is a remnant of SPMC implementation based on the FF-A v1.0 specification. +In the current implementation, S-EL1 SPs use the para-virtualized HVC interface +implemented by SPMC to perform priority drop and interrupt deactivation (SPMC +configures EOImode = 0, i.e. priority drop and deactivation are done together). +The SPMC performs checks to deny the state transition upon invocation of +either FFA_MSG_WAIT or FFA_RUN interface if the SP didn't perform the +deactivation of the secure virtual interrupt. + +If the current SP execution context was preempted by a secure interrupt to be +handled by execution context of target SP, SPMC resumes current SP after signal +completion by target SP execution context. + +Actions for a secure interrupt triggered while execution is in normal world +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ++-------------------+----------+-----------------------------------------------+ +| State of target | Action | Description | +| execution context | | | ++-------------------+----------+-----------------------------------------------+ +| WAITING | Signaled | This starts a new call chain in SPMC scheduled| +| | | mode. | ++-------------------+----------+-----------------------------------------------+ +| PREEMPTED | Queued | The target execution must have been preempted | +| | | by a non-secure interrupt. SPMC queues the | +| | | secure virtual interrupt now. It is signaled | +| | | when the target execution context next enters | +| | | the RUNNING state. | ++-------------------+----------+-----------------------------------------------+ +| BLOCKED, RUNNING | NA | The target execution context is blocked or | +| | | running on a different CPU. This is not | +| | | supported by current SPMC implementation and | +| | | execution hits panic. | ++-------------------+----------+-----------------------------------------------+ + +If normal world execution was preempted by a secure interrupt, SPMC uses FFA_NORMAL_WORLD_RESUME ABI to indicate completion of secure interrupt handling -and further return execution to normal world. If the current SP execution -context was preempted by a secure interrupt to be handled by execution context -of target SP, SPMC resumes current SP after signal completion by target SP -execution context. - -An action is broadly a set of steps taken by the SPMC in response to a physical -interrupt. In order to simplify the design, the current version of secure -interrupt management support in SPMC (Hafnium) does not fully implement the -Scheduling models and Partition runtime models. However, the current -implementation loosely maps to the following actions that are legally allowed -by the specification. Please refer to the Table 8.4 in the spec for further -description of actions. The action specified for a type of interrupt when the -SP is in the message processing running state cannot be less permissive than the -action specified for the same type of interrupt when the SP is in the interrupt -handling running state. - -+--------------------+--------------------+------------+-------------+ -| Runtime Model | NS-Int | Self S-Int | Other S-Int | -+--------------------+--------------------+------------+-------------+ -| Message Processing | Signalable with ME | Signalable | Signalable | -+--------------------+--------------------+------------+-------------+ -| Interrupt Handling | Queued | Queued | Queued | -+--------------------+--------------------+------------+-------------+ +and further returns execution to normal world. -Abbreviations: - - - NS-Int: A Non-secure physical interrupt. It requires a switch to the Normal - world to be handled. - - Other S-Int: A secure physical interrupt targeted to an SP different from - the one that is currently running. - - Self S-Int: A secure physical interrupt targeted to the SP that is currently - running. - -The following figure describes interrupt handling flow when secure interrupt -triggers while in normal world: +The following figure describes interrupt handling flow when a secure interrupt +triggers while execution is in normal world: .. image:: ../resources/diagrams/ffa-secure-interrupt-handling-nwd.png @@ -1151,40 +1251,78 @@ A brief description of the events: - 3) SPMD signals secure interrupt to SPMC at S-EL2 using FFA_INTERRUPT ABI. - 4) SPMC identifies target vCPU of SP and injects virtual interrupt (pends vIRQ). - - 5) Since SP1 vCPU is in WAITING state, SPMC signals using FFA_INTERRUPT with - interrupt id as argument and resume it using ERET. - - 6) Execution traps to vIRQ handler in SP1 provided that interrupt is not - masked i.e., PSTATE.I = 0 - - 7) SP1 services the interrupt and invokes the de-activation HVC call. - - 8) SPMC does internal state management and further de-activates the physical - interrupt and resumes SP vCPU. - - 9) SP performs secure interrupt completion through FFA_MSG_WAIT ABI. + - 5) Assuming SP1 vCPU is in WAITING state, SPMC signals virtual interrupt + using FFA_INTERRUPT with interrupt id as an argument and resumes the SP1 + vCPU using ERET in SPMC scheduled mode. + - 6) Execution traps to vIRQ handler in SP1 provided that the virtual + interrupt is not masked i.e., PSTATE.I = 0 + - 7) SP1 queries for the pending virtual interrupt id using a paravirtualized + HVC call. SPMC clears the pending virtual interrupt state management + and returns the pending virtual interrupt id. + - 8) SP1 services the virtual interrupt and invokes the paravirtualized + de-activation HVC call. SPMC de-activates the physical interrupt, + clears the fields tracking the secure interrupt and resumes SP1 vCPU. + - 9) SP1 performs secure interrupt completion through FFA_MSG_WAIT ABI. - 10) SPMC returns control to EL3 using FFA_NORMAL_WORLD_RESUME. - 11) EL3 resumes normal world execution. -The following figure describes interrupt handling flow when secure interrupt -triggers while in secure world: +Actions for a secure interrupt triggered while execution is in secure world +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ++-------------------+----------+------------------------------------------------+ +| State of target | Action | Description | +| execution context | | | ++-------------------+----------+------------------------------------------------+ +| WAITING | Signaled | This starts a new call chain in SPMC scheduled | +| | | mode. | ++-------------------+----------+------------------------------------------------+ +| PREEMPTED by Self | Signaled | The target execution context reenters the | +| S-Int | | RUNNING state to handle the secure virtual | +| | | interrupt. | ++-------------------+----------+------------------------------------------------+ +| PREEMPTED by | Queued | SPMC queues the secure virtual interrupt now. | +| NS-Int | | It is signaled when the target execution | +| | | context next enters the RUNNING state. | ++-------------------+----------+------------------------------------------------+ +| BLOCKED | Signaled | Both preempted and target execution contexts | +| | | must have been part of the Normal world | +| | | scheduled call chain. Refer scenario 1 of | +| | | Table 8.4 in the FF-A v1.1 EAC0 spec. | ++-------------------+----------+------------------------------------------------+ +| RUNNING | NA | The target execution context is running on a | +| | | different CPU. This scenario is not supported | +| | | by current SPMC implementation and execution | +| | | hits panic. | ++-------------------+----------+------------------------------------------------+ + +The following figure describes interrupt handling flow when a secure interrupt +triggers while execution is in secure world. We assume OS kernel sends a direct +request message to SP1. Further, SP1 sends a direct request message to SP2. SP1 +enters BLOCKED state and SPMC resumes SP2. .. image:: ../resources/diagrams/ffa-secure-interrupt-handling-swd.png A brief description of the events: - - 1) Secure interrupt triggers while SP2 is running and SP1 is blocked. - - 2) Gets trapped to SPMC as IRQ. + - 1) Secure interrupt triggers while SP2 is running. + - 2) SP2 gets preempted and execution traps to SPMC as IRQ. - 3) SPMC finds the target vCPU of secure partition responsible for handling this secure interrupt. In this scenario, it is SP1. - 4) SPMC pends vIRQ for SP1 and signals through FFA_INTERRUPT interface. - SPMC further resumes SP1 through ERET conduit. - - 5) Execution traps to vIRQ handler in SP1 provided that interrupt is not - masked i.e., PSTATE.I = 0 - - 6) SP1 services the secure interrupt and invokes the de-activation HVC call. - - 7) SPMC does internal state management, de-activates the physical interrupt - and resumes SP1 vCPU. - - 8) Assuming SP1 is in BLOCKED state, SP1 performs secure interrupt completion - through FFA_RUN ABI. + SPMC further resumes SP1 through ERET conduit. Note that SP1 remains in + Normal world schedule mode. + - 6) Execution traps to vIRQ handler in SP1 provided that the virtual + interrupt is not masked i.e., PSTATE.I = 0 + - 7) SP1 queries for the pending virtual interrupt id using a paravirtualized + HVC call. SPMC clears the pending virtual interrupt state management + and returns the pending virtual interrupt id. + - 8) SP1 services the virtual interrupt and invokes the paravirtualized + de-activation HVC call. SPMC de-activates the physical interrupt and + clears the fields tracking the secure interrupt and resumes SP1 vCPU. + - 9) Since SP1 direct request completed with FFA_INTERRUPT, it resumes the + direct request to SP2 by invoking FFA_RUN. - 9) SPMC resumes the pre-empted vCPU of SP2. - Power management ---------------- @@ -1374,13 +1512,13 @@ S-EL0 partitions are required by the FF-A specification to be UP endpoints, capable of migrating, and the SPMC enforces this requirement. The SPMC allows a S-EL0 partition to accept a direct message from secure world and normal world, and generate direct responses to them. +All S-EL0 partitions must use AArch64. AArch32 S-EL0 partitions are not supported. -Memory sharing between and with S-EL0 partitions is supported. -Indirect messaging, Interrupt handling and Notifications are not supported with -S-EL0 partitions and is work in progress, planned for future releases. -All S-EL0 partitions must use AArch64. AArch32 S-EL0 partitions are not -supported. +Memory sharing, indirect messaging, and notifications functionality with S-EL0 +partitions is supported. +Interrupt handling is not supported with S-EL0 partitions and is work in +progress. References ========== diff --git a/docs/components/spd/index.rst b/docs/components/spd/index.rst index 25d0124b1..6857806c2 100644 --- a/docs/components/spd/index.rst +++ b/docs/components/spd/index.rst @@ -8,3 +8,4 @@ Secure Payload Dispatcher (SPD) optee-dispatcher tlk-dispatcher trusty-dispatcher + pnc-dispatcher diff --git a/docs/components/spd/pnc-dispatcher.rst b/docs/components/spd/pnc-dispatcher.rst new file mode 100644 index 000000000..5be2fc7dc --- /dev/null +++ b/docs/components/spd/pnc-dispatcher.rst @@ -0,0 +1,10 @@ +ProvenCore Dispatcher +===================== + +ProvenCore dispatcher (PnC-D) adds support for ProvenRun's ProvenCore micro-kernel +to work with Trusted Firmware-A (TF-A). + +ProvenCore is a secure OS developed by ProvenRun S.A.S. using deductive formal methods. + +Once a BL32 is ready, PnC-D can be included in the image by adding "SPD=pncd" +to the build command. diff --git a/docs/conf.py b/docs/conf.py index ef77f6bfe..371632a56 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -36,12 +36,13 @@ master_doc = 'index' # # This is also used if you do content translation via gettext catalogs. # Usually you set "language" from the command line for these cases. -language = None +language = "en" # List of patterns, relative to source directory, that match files and # directories to ignore when looking for source files. # This pattern also affects html_static_path and html_extra_path . -exclude_patterns = [] +# Don't try to build the venv in case it's placed with the sources +exclude_patterns = [".env", "env", ".venv", "venv"] # The name of the Pygments (syntax highlighting) style to use. pygments_style = 'sphinx' diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index fbd2cbca4..55e265c9a 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -256,6 +256,10 @@ For Cortex-A76, the following errata build flags are defined : - ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. +- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 + CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is + still open. + For Cortex-A77, the following errata build flags are defined : - ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 @@ -270,6 +274,15 @@ For Cortex-A77, the following errata build flags are defined : - ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. +- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 + CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. + + - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 + CPU. This needs to be enabled for revisions <= r1p1 of the CPU. + + - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 + CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. + For Cortex-A78, the following errata build flags are defined : - ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 @@ -322,6 +335,24 @@ For Cortex-A78 AE, the following errata build flags are defined : Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. +For Cortex-A78C, the following errata build flags are defined : + +- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to + Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and + it is still open. + +- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to + Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and + it is still open. + +- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to + Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This + erratum is still open. + +- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to + Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This + erratum is still open. + For Cortex-X1 CPU, the following errata build flags are defined: - ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 @@ -375,8 +406,16 @@ For Neoverse N1, the following errata build flags are defined : CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for revisions r0p0, r1p0, and r2p0 there is no workaround. +- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 + CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is + still open. + For Neoverse V1, the following errata build flags are defined : +- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 + CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in + r1p0. + - ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed in r1p1. @@ -414,6 +453,13 @@ For Neoverse V1, the following errata build flags are defined : issue is present in r0p0 as well but there is no workaround for that revision. It is still open. +- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 + CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. + +- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 + CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. + It is still open. + For Cortex-A710, the following errata build flags are defined : - ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to @@ -448,14 +494,30 @@ For Cortex-A710, the following errata build flags are defined : Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. +- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to + Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU + and is fixed in r2p1. + +- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to + Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 + of the CPU and is fixed in r2p1. + - ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. +- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to + Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 + of the CPU and is fixed in r2p1. + - ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is fixed in r2p1. +- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to + Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 + of the CPU and is fixed in r2p1. + For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 @@ -488,6 +550,18 @@ For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. +- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in + r0p1. + +- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in + r0p1. + +- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in + r0p1. + For Cortex-X2, the following errata build flags are defined : - ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 @@ -517,6 +591,16 @@ For Cortex-X2, the following errata build flags are defined : Cortex-X2 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed in r2p1. +- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to + Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 + of the CPU and is fixed in r2p1. + +For Cortex-X3, the following errata build flags are defined : + +- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to + Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 + of the CPU, it is fixed in r1p1. + For Cortex-A510, the following errata build flags are defined : - ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to @@ -549,6 +633,18 @@ For Cortex-A510, the following errata build flags are defined : Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and r1p0, it is fixed in r1p1. +- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to + Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, + r0p3, r1p0 and r1p1. It is fixed in r1p2. + +- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to + Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, + r0p3, r1p0, r1p1, and is fixed in r1p2. + +- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to + Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, + r0p3, r1p0, r1p1. It is fixed in r1p2. + DSU Errata Workarounds ---------------------- @@ -624,9 +720,17 @@ architecture that can be enabled by the platform as desired. This is used to control how the LL_CACHE* PMU events count. Default value is 0 (Disabled). +GIC Errata Workarounds +---------------------- +- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 + workaround for the affected GIC600 and GIC600-AE implementations. It applies + to implementations of GIC600 and GIC600-AE with revisions less than or equal + to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, + then this flag is enabled; otherwise, it is 0 (Disabled). + -------------- -*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.* .. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 .. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index 71fdfcb23..84bba18e6 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -990,9 +990,10 @@ The service's ``handle()`` callback is provided with five of the SMC parameters directly, the others are saved into memory for retrieval (if needed) by the handler. The handler is also provided with an opaque ``handle`` for use with the supporting library for parameter retrieval, setting return values and context -manipulation; and with ``flags`` indicating the security state of the caller. The -framework finally sets up the execution stack for the handler, and invokes the -services ``handle()`` function. +manipulation. The ``flags`` parameter indicates the security state of the caller +and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets +up the execution stack for the handler, and invokes the services ``handle()`` +function. On return from the handler the result registers are populated in X0-X7 as needed before restoring the stack and CPU state and returning from the original SMC. diff --git a/docs/design/index.rst b/docs/design/index.rst index e3b8f7429..17ef75611 100644 --- a/docs/design/index.rst +++ b/docs/design/index.rst @@ -4,7 +4,6 @@ System Design .. toctree:: :maxdepth: 1 :caption: Contents - :numbered: alt-boot-flows auth-framework diff --git a/docs/design/trusted-board-boot-build.rst b/docs/design/trusted-board-boot-build.rst index dd61b61f5..c3f3a2f53 100644 --- a/docs/design/trusted-board-boot-build.rst +++ b/docs/design/trusted-board-boot-build.rst @@ -35,6 +35,13 @@ images with support for these features: By default, this will use the Chain of Trust described in the TBBR-client document. To select a different one, use the ``COT`` build option. + If using a custom build of OpenSSL, set the ``OPENSSL_DIR`` variable + accordingly so it points at the OpenSSL installation path, as explained in + :ref:`Build Options`. In addition, set the ``LD_LIBRARY_PATH`` variable + when running to point at the custom OpenSSL path, so the OpenSSL libraries + are loaded from that path instead of the default OS path. Export this + variable if necessary. + In the case of Arm platforms, the location of the ROTPK hash must also be specified at build time. The following locations are currently supported (see ``ARM_ROTPK_LOCATION`` build option): @@ -63,7 +70,7 @@ images with support for these features: make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ - BL33=<path-to>/<bl33_image> \ + BL33=<path-to>/<bl33_image> OPENSSL_DIR=<path-to>/<openssl> \ all fip The result of this build will be the bl1.bin and the fip.bin binaries. This @@ -87,7 +94,7 @@ images with support for these features: make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ - BL33=<path-to>/<bl33_image> \ + BL33=<path-to>/<bl33_image> OPENSSL_DIR=<path-to>/<openssl> \ SCP_BL2=<path-to>/<scp_bl2_image> \ SCP_BL2U=<path-to>/<scp_bl2u_image> \ NS_BL2U=<path-to>/<ns_bl2u_image> \ @@ -109,7 +116,7 @@ images with support for these features: -------------- -*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* .. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git .. _mbed TLS Security Center: https://tls.mbed.org/security diff --git a/docs/design_documents/drtm_poc.rst b/docs/design_documents/drtm_poc.rst new file mode 100644 index 000000000..79e11429d --- /dev/null +++ b/docs/design_documents/drtm_poc.rst @@ -0,0 +1,132 @@ +DRTM Proof of Concept +===================== + +Dynamic Root of Trust for Measurement (DRTM) begins a new trust environment +by measuring and executing a protected payload. + +Static Root of Trust for Measurement (SRTM)/Measured Boot implementation, +currently used by TF-A covers all firmwares, from the boot ROM to the normal +world bootloader. As a whole, they make up the system's TCB. These boot +measurements allow attesting to what software is running on the system and +enable enforcing security policies. + +As the boot chain grows or firmware becomes dynamically extensible, +establishing an attestable TCB becomes more challenging. DRTM provides a +solution to this problem by allowing measurement chains to be started at +any time. As these measurements are stored separately from the boot-time +measurements, they reduce the size of the TCB, which helps reduce the attack +surface and the risk of untrusted code executing, which could compromise +the security of the system. + +Components +~~~~~~~~~~ + + - **DCE-Preamble**: The DCE Preamble prepares the platform for DRTM by + doing any needed configuration, loading the target payload image(DLME), + and preparing input parameters needed by DRTM. Finally, it invokes the + DL Event to start the dynamic launch. + + - **D-CRTM**: The D-CRTM is the trust anchor (or root of trust) for the + DRTM boot sequence and is where the dynamic launch starts. The D-CRTM + must be implemented as a trusted agent in the system. The D-CRTM + initializes the TPM for DRTM and prepares the environment for the next + stage of DRTM, the DCE. The D-CRTM measures the DCE, verifies its + signature, and transfers control to it. + + - **DCE**: The DCE executes on an application core. The DCE verifies the + system’s state, measures security-critical attributes of the system, + prepares the memory region for the target payload, measures the payload, + and finally transfers control to the payload. + + - **DLME**: The protected payload is referred to as the Dynamically Launched + Measured Environment, or DLME. The DLME begins execution in a safe state, + with a single thread of execution, DMA protections, and interrupts + disabled. The DCE provides data to the DLME that it can use to verify the + configuration of the system. + +In this proof of concept, DCE and D-CRTM are implemented in BL31 and +DCE-Preamble and DLME are implemented in UEFI application. A DL Event is +triggered as a SMC by DCE-Preamble and handled by D-CRTM, which launches the +DLME via DCE. + +This manual provides instructions to build TF-A code with pre-buit EDK2 +and DRTM UEFI application. + +Building the PoC for the Arm FVP platform +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +(1) Use the below command to clone TF-A source code - + +.. code:: shell + + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + +(2) There are prebuilt binaries required to execute the DRTM implementation + in the `prebuilts-drtm-bins`_. + Download EDK2 *FVP_AARCH64_EFI.fd* and UEFI DRTM application *test-disk.img* + binary from `prebuilts-drtm-bins`_. + +(3) Build the TF-A code using below command + +.. code:: shell + + $ make CROSS_COMPILE=aarch64-none-elf- ARM_ROTPK_LOCATION=devel_rsa + DEBUG=1 V=1 BL33=</path/to/FVP_AARCH64_EFI.fd> DRTM_SUPPORT=1 + MBEDTLS_DIR=</path/to/mbedTLS-source> USE_ROMLIB=1 all fip + +Running DRTM UEFI application on the Armv8-A AEM FVP +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +To run the DRTM test application along with DRTM implementation in BL31, +you need an FVP model. Please use the version of FVP_Base_RevC-2xAEMvA model +advertised in the TF-A documentation. + +.. code:: shell + + FVP_Base_RevC-2xAEMvA \ + --data cluster0.cpu0=</path/to/romlib.bin>@0x03ff2000 \ + --stat \ + -C bp.flashloader0.fname=<path/to/fip.bin> \ + -C bp.secureflashloader.fname=<path/to/bl1.bin> \ + -C bp.ve_sysregs.exit_on_shutdown=1 \ + -C bp.virtioblockdevice.image_path=<path/to/test-disk.img> \ + -C cache_state_modelled=1 \ + -C cluster0.check_memory_attributes=0 \ + -C cluster0.cpu0.etm-present=0 \ + -C cluster0.cpu1.etm-present=0 \ + -C cluster0.cpu2.etm-present=0 \ + -C cluster0.cpu3.etm-present=0 \ + -C cluster0.stage12_tlb_size=1024 \ + -C cluster1.check_memory_attributes=0 \ + -C cluster1.cpu0.etm-present=0 \ + -C cluster1.cpu1.etm-present=0 \ + -C cluster1.cpu2.etm-present=0 \ + -C cluster1.cpu3.etm-present=0 \ + -C cluster1.stage12_tlb_size=1024 \ + -C pctl.startup=0.0.0.0 \ + -Q 1000 \ + "$@" + +The bottom of the output from *uart1* should look something like the +following to indicate that the last SMC to unprotect memory has been fired +successfully. + +.. code-block:: shell + + ... + + INFO: DRTM service handler: version + INFO: ++ DRTM service handler: TPM features + INFO: ++ DRTM service handler: Min. mem. requirement features + INFO: ++ DRTM service handler: DMA protection features + INFO: ++ DRTM service handler: Boot PE ID features + INFO: ++ DRTM service handler: TCB-hashes features + INFO: DRTM service handler: dynamic launch + WARNING: DRTM service handler: close locality is not supported + INFO: DRTM service handler: unprotect mem + +-------------- + +*Copyright (c) 2022, Arm Limited. All rights reserved.* + +.. _prebuilts-drtm-bins: https://downloads.trustedfirmware.org/tf-a/drtm +.. _DRTM-specification: https://developer.arm.com/documentation/den0113/a diff --git a/docs/design_documents/index.rst b/docs/design_documents/index.rst index 257a510d0..3e20c07ca 100644 --- a/docs/design_documents/index.rst +++ b/docs/design_documents/index.rst @@ -4,12 +4,12 @@ Design Documents .. toctree:: :maxdepth: 1 :caption: Contents - :numbered: cmake_framework context_mgmt_rework measured_boot_poc + drtm_poc -------------- -*Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index cfd7201c3..402de1361 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -313,7 +313,13 @@ Common build options - ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` - mechanism. Default is ``0``. + mechanism. Default value is ``0``. + +- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` + extension. This feature is only supported in AArch64 state. This flag can + take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. + Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from + Armv8.5 onwards. - ``ENABLE_FEAT_SB``: Numeric value to enable the ``FEAT_SB`` (Speculation Barrier) extension allowing access to ``sb`` instruction. ``FEAT_SB`` is an @@ -461,8 +467,11 @@ Common build options - ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions targeted at EL3. When set ``0`` (default), no exceptions are expected or - handled at EL3, and a panic will result. This is supported only for AArch64 - builds. + handled at EL3, and a panic will result. The exception to this rule is when + ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions + occuring during normal world execution, are trapped to EL3. Any exception + trapped during secure world execution are trapped to the SPMC. This is + supported only for AArch64 builds. - ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. @@ -560,10 +569,11 @@ Common build options EL1 for handling. The default value of this option is ``0``, which means the Group 0 interrupts are assumed to be handled by Secure EL1. -- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError - Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to - ``0`` (default), these exceptions will be trapped in the current exception - level (or in EL1 if the current exception level is EL0). +- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError + Interrupts, resulting from errors in NS world, will be always trapped in + EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions + will be trapped in the current exception level (or in EL1 if the current + exception level is EL0). - ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific software operations are required for CPUs to enter and exit coherency. @@ -600,22 +610,28 @@ Common build options - ``KEY_ALG``: This build flag enables the user to select the algorithm to be used for generating the PKCS keys and subsequent signing of the certificate. - It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option - ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR - compliant and is retained only for compatibility. The default value of this - flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. + It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` + and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 + RSA 1.5 algorithm which is not TBBR compliant and is retained only for + compatibility. The default value of this flag is ``rsa`` which is the TBBR + compliant PKCS#1 RSA 2.1 scheme. - ``KEY_SIZE``: This build flag enables the user to select the key size for the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` depend on the chosen algorithm and the cryptographic module. - +-----------+------------------------------------+ - | KEY_ALG | Possible key sizes | - +===========+====================================+ - | rsa | 1024 , 2048 (default), 3072, 4096* | - +-----------+------------------------------------+ - | ecdsa | unavailable | - +-----------+------------------------------------+ + +---------------------------+------------------------------------+ + | KEY_ALG | Possible key sizes | + +===========================+====================================+ + | rsa | 1024 , 2048 (default), 3072, 4096* | + +---------------------------+------------------------------------+ + | ecdsa | unavailable | + +---------------------------+------------------------------------+ + | ecdsa-brainpool-regular | unavailable | + +---------------------------+------------------------------------+ + | ecdsa-brainpool-twisted | unavailable | + +---------------------------+------------------------------------+ + * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. Only 3072 bits size is available with CryptoCell 712 SBROM release 2. @@ -716,7 +732,7 @@ Common build options or later CPUs. This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. - When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be + When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST_NS`` must also be set to ``1``. This option is disabled by default. @@ -834,6 +850,17 @@ Common build options to mask these events. Platforms that enable FIQ handling in SP_MIN shall implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. +- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. + Platforms can configure this if they need to lower the hardware + limit, for example due to asymmetric configuration or limitations of + software run at lower ELs. The default is the architectural maximum + of 2048 which should be suitable for most configurations, the + hardware will limit the effective VL to the maximum physically supported + VL. + +- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True + Random Number Generator Interface to BL31 image. This defaults to ``0``. + - ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board Boot feature. When set to '1', BL1 and BL2 images include support to load and verify the certificates and images in a FIP, and BL1 includes support @@ -970,28 +997,31 @@ Common build options implement this workaround due to the behaviour of the errata mentioned in new SDEN document which will get published soon. -- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR +- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. This flag is disabled by default. -- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory - path on the host machine which is used to build certificate generation and - firmware encryption tool. +- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the + host machine where a custom installation of OpenSSL is located, which is used + to build the certificate generation, firmware encryption and FIP tools. If + this option is not set, the default OS installation will be used. - ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for functions that wait for an arbitrary time length (udelay and mdelay). The default value is 0. -- ``ENABLE_BRBE_FOR_NS``: This flag enables access to the branch record buffer - registers from NS ELs when FEAT_BRBE is implemented. BRBE is an optional - architectural feature for AArch64. The default is 0 and it is automatically - disabled when the target architecture is AArch32. +- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record + buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an + optional architectural feature for AArch64. This flag can take the values + 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 + and it is automatically disabled when the target architecture is AArch32. -- ``ENABLE_TRBE_FOR_NS``: This flag is used to enable access of trace buffer +- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural - feature for AArch64. The default is 0 and it is automatically disabled when - the target architecture is AArch32. + feature for AArch64. This flag can take the values 0 to 2, to align with the + ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically + disabled when the target architecture is AArch32. - ``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented @@ -1008,6 +1038,12 @@ Common build options functionalities). When enabled (``1``), a mocked version of the APIs are used. The default value is 0. +- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine + ``plat_can_cmo`` which will return zero if cache management operations should + be skipped and non-zero otherwise. By default, this option is disabled which + means platform hook won't be checked and CMOs will always be performed when + related functions are called. + GICv3 driver options -------------------- diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst index 87c677fcd..4a480590b 100644 --- a/docs/getting_started/docs-build.rst +++ b/docs/getting_started/docs-build.rst @@ -17,22 +17,28 @@ check that you have the required software packages, as described in the Prerequisites ------------- -For building a local copy of the |TF-A| documentation you will need, at minimum: +For building a local copy of the |TF-A| documentation you will need: - Python 3 (3.5 or later) - PlantUML (1.2017.15 or later) +- Python modules specified in ``docs/requirements.txt`` -Optionally, the `Dia`_ application can be installed if you need to edit -existing ``.dia`` diagram files, or create new ones. + You can install these with ``pip3`` (the Python Package Installer) by + passing it the requirements file above (with ``-r``). An optional ``--user`` + argument will install them locally, but you have to add their location to + $PATH (pip will emit a warning). Alternatively, they can be installed + globally (but will probably require root privileges). -You must also install the Python modules that are specified in the -``requirements.txt`` file in the root of the ``docs`` directory. These modules -can be installed using ``pip3`` (the Python Package Installer). Passing this -requirements file as an argument to ``pip3`` automatically installs the specific -module versions required by |TF-A|. + .. note:: + Although not necessary, it is recommended you use a virtual environment. + More advanced usage instructions for *pip* are beyond the scope of this + document but you can refer to the `pip homepage`_ for detailed guides. -An example set of installation commands for Ubuntu 18.04 LTS follows, assuming -that the working directory is ``docs``: +- Optionally, the `Dia`_ application can be installed if you need to edit + existing ``.dia`` diagram files, or create new ones. + +An example set of installation commands for Ubuntu follows, assuming that the +working directory is ``docs``: .. code:: shell @@ -44,15 +50,6 @@ that the working directory is ``docs``: the list to ensure that there will be no conflicts with other modules already installed in your environment. -Passing the optional ``--user`` argument to ``pip3`` will install the Python -packages only for the current user. Omitting this argument will attempt to -install the packages globally and this will likely require the command to be run -as root or using ``sudo``. - -.. note:: - More advanced usage instructions for *pip* are beyond the scope of this - document but you can refer to the `pip homepage`_ for detailed guides. - Building rendered documentation ------------------------------- diff --git a/docs/getting_started/image-terminology.rst b/docs/getting_started/image-terminology.rst index a90ec0b3f..66f47e8ac 100644 --- a/docs/getting_started/image-terminology.rst +++ b/docs/getting_started/image-terminology.rst @@ -4,8 +4,8 @@ Image Terminology This page contains the current name, abbreviated name and purpose of the various images referred to in the Trusted Firmware project. -General Notes -------------- +Common Image Features +--------------------- - Some of the names and abbreviated names have changed to accommodate new requirements. The changed names are as backward compatible as possible to @@ -40,6 +40,15 @@ General Notes Trusted Firmware Images ----------------------- +Firmware Image Package: ``FIP`` +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This is a packaging format used by TF-A to package firmware images in a single +binary. The number and type of images that should be packed in a FIP is +platform-specific and may include TF-A images and other firmware images +required by the platform. For example, most platforms require a BL33 image +which corresponds to the normal world bootloader (e.g. UEFI or U-Boot). + AP Boot ROM: ``AP_BL1`` ~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/getting_started/index.rst b/docs/getting_started/index.rst index 817beaf8e..3fbf48dca 100644 --- a/docs/getting_started/index.rst +++ b/docs/getting_started/index.rst @@ -4,12 +4,11 @@ Getting Started .. toctree:: :maxdepth: 1 :caption: Contents - :numbered: prerequisites docs-build - tools-build initial-build + tools-build build-options image-terminology porting-guide diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst index 62f1941b1..4f41be413 100644 --- a/docs/getting_started/initial-build.rst +++ b/docs/getting_started/initial-build.rst @@ -2,7 +2,7 @@ Performing an Initial Build =========================== - Before building TF-A, the environment variable ``CROSS_COMPILE`` must point - to the Linaro cross compiler. + to your cross compiler. For AArch64: diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index 2c6a0059e..aa57e1db6 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -23,8 +23,8 @@ Some modifications are common to all Boot Loader (BL) stages. Section 2 discusses these in detail. The subsequent sections discuss the remaining modifications for each BL stage in detail. -Please refer to the :ref:`Platform Compatibility Policy` for the policy -regarding compatibility and deprecation of these porting interfaces. +Please refer to the :ref:`Platform Ports Policy` for the policy regarding +compatibility and deprecation of these porting interfaces. Only Arm development platforms (such as FVP and Juno) may use the functions/definitions in ``include/plat/arm/common/`` and the corresponding @@ -89,6 +89,8 @@ and caches disabled. Examples are given below. The following variables, functions and constants must be defined by the platform for the firmware to work correctly. +.. _platform_def_mandatory: + File : platform_def.h [mandatory] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -118,7 +120,7 @@ likely to be suitable for all platform ports. - **#define : CACHE_WRITEBACK_GRANULE** - Defines the size in bits of the largest cache line across all the cache + Defines the size in bytes of the largest cache line across all the cache levels in the platform. - **#define : FIRMWARE_WELCOME_STR** @@ -240,6 +242,11 @@ likely to be suitable for all platform ports. Defines the maximum address in secure RAM that the BL31 image can occupy. +- **#define : PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE** + + Defines the maximum message size between AP and RSS. Need to define if + platform supports RSS. + For every image, the platform must define individual identifiers that will be used by BL1 or BL2 to load the corresponding image into memory from non-volatile storage. For the sake of performance, integer numbers will be used as @@ -562,6 +569,21 @@ behaviour of the ``assert()`` function (for example, to save memory). doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't defined, it defaults to ``LOG_LEVEL``. +If the platform port uses the DRTM feature, the following constants must be +defined: + +- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE** + + Maximum Event Log size used by the platform. Platform can decide the maximum + size of the Event Log buffer, depending upon the highest hash algorithm + chosen and the number of components selected to measure during the DRTM + execution flow. + +- **#define : PLAT_DRTM_MMAP_ENTRIES** + + Number of the MMAP entries used by the DRTM implementation to calculate the + size of address map region of the platform. + File : plat_macros.S [mandatory] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -787,6 +809,214 @@ The function returns 0 on success. Any other value means the counter value either could not be updated or the authentication image descriptor indicates that it is not allowed to be updated. +Function: plat_convert_pk() +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void *, unsigned int, void **, unsigned int * + Return : int + +This function is optional when Trusted Board Boot is enabled, and only +used if the platform saves a hash of the ROTPK. +First argument is the Distinguished Encoding Rules (DER) ROTPK. +Second argument is its size. +Third argument is used to return a pointer to a buffer, which hash should +be the one saved in OTP. +Fourth argument is a pointer to return its size. + +Most platforms save the hash of the ROTPK, but some may save slightly different +information - e.g the hash of the ROTPK plus some related information. +Defining this function allows to transform the ROTPK used to verify +the signature to the buffer (a platform specific public key) which +hash is saved in OTP. + +The default implementation copies the input key and length to the output without +modification. + +The function returns 0 on success. Any other value means the expected +public key buffer cannot be extracted. + +Dynamic Root of Trust for Measurement support (in BL31) +------------------------------------------------------- + +The functions mentioned in this section are mandatory, when platform enables +DRTM_SUPPORT build flag. + +Function : plat_get_addr_mmap() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : const mmap_region_t * + +This function is used to return the address of the platform *address-map* table, +which describes the regions of normal memory, memory mapped I/O +and non-volatile memory. + +Function : plat_has_non_host_platforms() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : bool + +This function returns *true* if the platform has any trusted devices capable of +DMA, otherwise returns *false*. + +Function : plat_has_unmanaged_dma_peripherals() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : bool + +This function returns *true* if platform uses peripherals whose DMA is not +managed by an SMMU, otherwise returns *false*. + +Note - +If the platform has peripherals that are not managed by the SMMU, then the +platform should investigate such peripherals to determine whether they can +be trusted, and such peripherals should be moved under "Non-host platforms" +if they can be trusted. + +Function : plat_get_total_num_smmus() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : unsigned int + +This function returns the total number of SMMUs in the platform. + +Function : plat_enumerate_smmus() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +:: + + + Argument : void + Return : const uintptr_t *, size_t + +This function returns an array of SMMU addresses and the actual number of SMMUs +reported by the platform. + +Function : plat_drtm_get_dma_prot_features() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : const plat_drtm_dma_prot_features_t* + +This function returns the address of plat_drtm_dma_prot_features_t structure +containing the maximum number of protected regions and bitmap with the types +of DMA protection supported by the platform. +For more details see section 3.3 Table 6 of `DRTM`_ specification. + +Function : plat_drtm_dma_prot_get_max_table_bytes() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : uint64_t + +This function returns the maximum size of DMA protected regions table in +bytes. + +Function : plat_drtm_get_tpm_features() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : const plat_drtm_tpm_features_t* + +This function returns the address of *plat_drtm_tpm_features_t* structure +containing PCR usage schema, TPM-based hash, and firmware hash algorithm +supported by the platform. + +Function : plat_drtm_get_min_size_normal_world_dce() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : uint64_t + +This function returns the size normal-world DCE of the platform. + +Function : plat_drtm_get_imp_def_dlme_region_size() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : uint64_t + +This function returns the size of implementation defined DLME region +of the platform. + +Function : plat_drtm_get_tcb_hash_table_size() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : uint64_t + +This function returns the size of TCB hash table of the platform. + +Function : plat_drtm_get_tcb_hash_features() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : uint64_t + +This function returns the Maximum number of TCB hashes recorded by the +platform. +For more details see section 3.3 Table 6 of `DRTM`_ specification. + +Function : plat_drtm_validate_ns_region() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : uintptr_t, uintptr_t + Return : int + +This function validates that given region is within the Non-Secure region +of DRAM. This function takes a region start address and size an input +arguments, and returns 0 on success and -1 on failure. + +Function : plat_set_drtm_error() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : uint64_t + Return : int + +This function writes a 64 bit error code received as input into +non-volatile storage and returns 0 on success and -1 on failure. + +Function : plat_get_drtm_error() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : uint64_t* + Return : int + +This function reads a 64 bit error code from the non-volatile storage +into the received address, and returns 0 on success and -1 on failure. + Common mandatory function modifications --------------------------------------- @@ -1095,6 +1325,20 @@ environment is initialized. The address from where it was called is stored in x30 (Link Register). The default implementation simply spins. +Function : plat_system_reset() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : void + +This function is used by the platform to resets the system. It can be used +in any specific use-case where system needs to be resetted. For example, +in case of DRTM implementation this function reset the system after +writing the DRTM error code in the non-volatile storage. This function +never returns. Failure in reset results in panic. + Function : plat_get_bl_image_load_info() ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1245,6 +1489,22 @@ When the MEASURED_BOOT flag is enabled: When the MEASURED_BOOT flag is disabled, this function doesn't do anything. +Function : plat_can_cmo() +~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : uint64_t + +When CONDITIONAL_CMO flag is enabled: + +- This function indicates whether cache management operations should be + performed. It returns 0 if CMOs should be skipped and non-zero + otherwise. +- The function must not clobber x1, x2 and x3. It's also not safe to rely on + stack. Otherwise obey AAPCS. + Modifications specific to a Boot Loader stage --------------------------------------------- @@ -1663,6 +1923,42 @@ element in the boot sequence. If there are no more boot sources then it must return 0, otherwise it must return 1. The default implementation of this always returns 0. +Function : bl2_plat_mboot_init() [optional] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : void + +When the MEASURED_BOOT flag is enabled: + +- This function is used to initialize the backend driver(s) of measured boot. +- On the Arm FVP port, this function is used to initialize the Event Log + backend driver with the Event Log buffer information (base address and + size) received from BL1. It results in panic on error. + +When the MEASURED_BOOT flag is disabled, this function doesn't do anything. + +Function : bl2_plat_mboot_finish() [optional] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : void + +When the MEASURED_BOOT flag is enabled: + +- This function is used to finalize the measured boot backend driver(s), + and also, set the information for the next bootloader component to extend + the measurement if needed. +- On the Arm FVP port, this function is used to pass the Event Log buffer + information (base address and size) to non-secure(BL33) and trusted OS(BL32) + via nt_fw and tos_fw config respectively. It results in panic on error. + +When the MEASURED_BOOT flag is disabled, this function doesn't do anything. + Boot Loader Stage 2 (BL2) at EL3 -------------------------------- @@ -1820,42 +2116,6 @@ Application Processor (AP) for BL2U execution to continue. This function returns 0 on success, a negative error code otherwise. This function is included if SCP_BL2U_BASE is defined. -Function : bl2_plat_mboot_init() [optional] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -:: - - Argument : void - Return : void - -When the MEASURED_BOOT flag is enabled: - -- This function is used to initialize the backend driver(s) of measured boot. -- On the Arm FVP port, this function is used to initialize the Event Log - backend driver with the Event Log buffer information (base address and - size) received from BL1. It results in panic on error. - -When the MEASURED_BOOT flag is disabled, this function doesn't do anything. - -Function : bl2_plat_mboot_finish() [optional] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -:: - - Argument : void - Return : void - -When the MEASURED_BOOT flag is enabled: - -- This function is used to finalize the measured boot backend driver(s), - and also, set the information for the next bootloader component to extend - the measurement if needed. -- On the Arm FVP port, this function is used to pass the Event Log buffer - information (base address and size) to non-secure(BL33) and trusted OS(BL32) - via nt_fw and tos_fw config respectively. It results in panic on error. - -When the MEASURED_BOOT flag is disabled, this function doesn't do anything. - Boot Loader Stage 3-1 (BL31) ---------------------------- @@ -2017,7 +2277,7 @@ state. This function must return a pointer to the ``entry_point_info`` structure (that was copied during ``bl31_early_platform_setup()``) if the image exists. It should return NULL otherwise. -Function : plat_get_cca_attest_token() [mandatory when ENABLE_RME == 1] +Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: @@ -2043,8 +2303,8 @@ The parameters of the function are: The function returns 0 on success, -EINVAL on failure. -Function : plat_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: @@ -2069,6 +2329,31 @@ The parameters of the function are: The function returns 0 on success, -EINVAL on failure. +Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : uintptr_t * + Return : size_t + +This function returns the size of the shared area between EL3 and RMM (or 0 on +failure). A pointer to the shared area (or a NULL pointer on failure) is stored +in the pointer passed as argument. + +Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Arguments : rmm_manifest_t *manifest + Return : int + +When ENABLE_RME is enabled, this function populates a boot manifest for the +RMM image and stores it in the area specified by manifest. + +When ENABLE_RME is disabled, this function is not used. + Function : bl31_plat_enable_mmu [optional] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -2227,7 +2512,7 @@ value: uuid_t plat_trng_uuid [mandatory] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This value must be defined to the UUID of the TRNG backend that is specific to -the hardware after ``plat_trng_setup`` function is called. This value must +the hardware after ``plat_entropy_setup`` function is called. This value must conform to the SMCCC calling convention; The most significant 32 bits of the UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in w0 indicates failure to get a TRNG source. @@ -2528,7 +2813,8 @@ must ensure that races between multiple CPUs cannot occur. The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` operation and it encodes the platform coordinated target local power states for the CPU power domain and its parent power domain levels. This function must -not return back to the caller. +not return back to the caller (by calling wfi in an infinite loop to ensure +some CPUs power down mitigations work properly). If this function is not implemented by the platform, PSCI generic implementation invokes ``psci_power_down_wfi()`` for power down. @@ -2914,6 +3200,34 @@ Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* (``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. +Common helper functions +----------------------- + +Function : do_panic() +~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : void + +This API is called from assembly files when encountering a critical failure that +cannot be recovered from. It also invokes elx_panic() which allows to report a +crash from lower exception level. This function assumes that it is invoked from +a C runtime environment i.e. valid stack exists. This call **must not** return. + +Function : panic() +~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : void + +This API called from C files when encountering a critical failure that cannot +be recovered from. This function in turn prints backtrace (if enabled) and calls +do_panic(). This call **must not** return. + Crash Reporting mechanism (in BL31) ----------------------------------- @@ -3198,3 +3512,4 @@ amount of open resources per driver. .. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html .. _FreeBSD: https://www.freebsd.org .. _SCC: http://www.simple-cc.org/ +.. _DRTM: https://developer.arm.com/documentation/den0113/a diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst index 0b8a71cbc..37232942b 100644 --- a/docs/getting_started/prerequisites.rst +++ b/docs/getting_started/prerequisites.rst @@ -7,13 +7,14 @@ AArch32 and AArch64 target platforms. It may possible to build |TF-A| with combinations of software packages that are different from those listed below, however only the software described in this document can be officially supported. + Build Host ---------- |TF-A| can be built using either a Linux or a Windows machine as the build host. A relatively recent Linux distribution is recommended for building |TF-A|. We -have performed tests using Ubuntu 16.04 LTS (64-bit) but other distributions +have performed tests using Ubuntu 20.04 LTS (64-bit) but other distributions should also work fine as a base, provided that the necessary tools and libraries can be installed. @@ -25,7 +26,11 @@ Toolchain |TF-A| can be built with any of the following *cross-compiler* toolchains that target the Armv7-A or Armv8-A architectures: -- GCC >= 11.2-2022.02 (from the `Arm Developer website`_) +- GCC >= 11.3.Rel1 (from the `Arm Developer website`_) + + You will need the targets ``arm-none-eabi`` and ``aarch64-none-elf`` for + AArch32 and AArch64 builds respectively. + - Clang >= 14.0.0 - Arm Compiler >= 6.18 @@ -53,14 +58,20 @@ The following tools are required to obtain and build |TF-A|: The following libraries must be available to build one or more components or supporting tools: -- OpenSSL >= 3.0 +- OpenSSL >= 1.1.1 (v3.0.0 to v3.0.6 highly discouraged due to security issues) + + Required to build the cert_create, encrypt_fw, and fiptool tools. + + .. note:: - Required to build the cert_create tool. + If using OpenSSL 3, older Linux versions may require it to be built from + source code, as it may not be available in the default package repositories. + Please refer to the OpenSSL project documentation for more information. The following libraries are required for Trusted Board Boot and Measured Boot support: -- mbed TLS == 2.28.0 (tag: ``mbedtls-2.28.0``) +- mbed TLS == 2.28.1 (tag: ``mbedtls-2.28.1``) These tools are optional: @@ -89,7 +100,7 @@ required packages with the following command: .. code:: shell - sudo apt install build-essential git libssl-dev + sudo apt install build-essential git The optional packages can be installed using: @@ -97,14 +108,15 @@ The optional packages can be installed using: sudo apt install device-tree-compiler -Additionally, to install an up-to-date version of Node.js, you can use the `Node -Version Manager`_ to install a version of your choosing (we recommend 16, but -later LTS versions might offer a more stable experience): +Additionally, to install a version of Node.js compatible with TF-A's repository +scripts, you can use the `Node Version Manager`_. To install both NVM and an +appropriate version of Node.js, run the following **from the root directory of +the repository**: .. code:: shell - curl -o- https://raw.githubusercontent.com/nvm-sh/nvm/v0.39.0/install.sh | "$SHELL" - exec "$SHELL" -ic "nvm install 16; exec $SHELL" + curl -o- https://raw.githubusercontent.com/nvm-sh/nvm/v0.39.1/install.sh | bash + exec "$SHELL" -ic "nvm install; exec $SHELL" .. _Node Version Manager: https://github.com/nvm-sh/nvm#install--update-script diff --git a/docs/getting_started/psci-lib-integration-guide.rst b/docs/getting_started/psci-lib-integration-guide.rst index 37352659d..4d690a978 100644 --- a/docs/getting_started/psci-lib-integration-guide.rst +++ b/docs/getting_started/psci-lib-integration-guide.rst @@ -337,16 +337,6 @@ at address ``addr`` (first argument) address and of size ``size`` (second argume This function invalidates (flushes) the data cache for memory at address ``addr`` (first argument) address and of size ``size`` (second argument). -**Function : do_panic()** - -:: - - Argument : void - Return : void - -This function will be called by the PSCI library on encountering a critical -failure that cannot be recovered from. This function **must not** return. - CPU Context management API ~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/getting_started/tools-build.rst b/docs/getting_started/tools-build.rst index c050f5851..166b527d4 100644 --- a/docs/getting_started/tools-build.rst +++ b/docs/getting_started/tools-build.rst @@ -1,15 +1,24 @@ Building Supporting Tools ========================= +.. note:: + + OpenSSL 3.0 is needed in order to build the tools. A custom installation + can be used if not updating the OpenSSL version on the OS. In order to do + this, use the ``OPENSSL_DIR`` variable after the ``make`` command to + indicate the location of the custom OpenSSL build. Then, to run the tools, + use the ``LD_LIBRARY_PATH`` to indicate the location of the built + libraries. More info about ``OPENSSL_DIR`` can be found at + :ref:`Build Options`. + Building and using the FIP tool ------------------------------- -Firmware Image Package (FIP) is a packaging format used by TF-A to package -firmware images in a single binary. The number and type of images that should -be packed in a FIP is platform specific and may include TF-A images and other -firmware images required by the platform. For example, most platforms require -a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or -U-Boot). +The following snippets build a :ref:`FIP<Image Terminology>` for the FVP +platform. While it is not an intrinsic part of the FIP format, a BL33 image is +required for these examples. For the purposes of experimentation, `Trusted +Firmware-A Tests`_ (`tftf.bin``) may be used. Refer to to the `TFTF +documentation`_ for instructions on building a TFTF binary. The TF-A build system provides the make target ``fip`` to create a FIP file for the specified platform using the FIP creation tool included in the TF-A @@ -164,4 +173,7 @@ via using ``cat <filename>`` instead of a hex string. -------------- -*Copyright (c) 2019, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* + +.. _Trusted Firmware-A Tests: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/ +.. _TFTF documentation: https://trustedfirmware-a-tests.readthedocs.io/en/latest/ diff --git a/docs/glossary.rst b/docs/glossary.rst index aeeb133cb..e6b023960 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -40,6 +40,18 @@ You can find additional definitions in the `Arm Glossary`_. Common Vulnerabilities and Exposures. A CVE document is commonly used to describe a publicly-known security vulnerability. + DCE + DRTM Configuration Environment + + D-CRTM + Dynamic Code Root of Trust for Measurement + + DLME + Dynamically Launched Measured Environment + + DRTM + Dynamic Root of Trust for Measurement + DS-5 Arm Development Studio 5 @@ -86,6 +98,9 @@ You can find additional definitions in the `Arm Glossary`_. A collaborative engineering organization consolidating and optimizing open source software and tools for the Arm architecture. + LSP + A logical secure partition managed by SPM + MMU Memory Management Unit @@ -186,6 +201,9 @@ You can find additional definitions in the `Arm Glossary`_. TBBR Trusted Board Boot Requirements + TCB + Trusted Compute Base + TEE Trusted Execution Environment diff --git a/docs/index.rst b/docs/index.rst index edc2535a4..386019943 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -3,7 +3,7 @@ Trusted Firmware-A Documentation .. toctree:: :maxdepth: 1 - :hidden: + :numbered: Home<self> about/index diff --git a/docs/perf/index.rst b/docs/perf/index.rst index 1482b80f6..bccad006c 100644 --- a/docs/perf/index.rst +++ b/docs/perf/index.rst @@ -4,7 +4,6 @@ Performance & Testing .. toctree:: :maxdepth: 1 :caption: Contents - :numbered: psci-performance-juno tsp diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst index 339ebbe33..407c04bbb 100644 --- a/docs/plat/arm/arm-build-options.rst +++ b/docs/plat/arm/arm-build-options.rst @@ -92,7 +92,7 @@ Arm Platform Build Options SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag. - ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can - configure an Arm Ethos-N NPU. To use this service the target platform's + configure an Arm® Ethosâ„¢-N NPU. To use this service the target platform's ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. @@ -152,6 +152,11 @@ Arm CSS Platform-Specific Build Options to select the appropriate platform variant for the build. The range of valid values is platform specific. +- ``CSS_SYSTEM_GRACEFUL_RESET``: Build option to enable graceful powerdown of + CPU core on reset. This build option can be used on CSS platforms that + require all the CPUs to execute the CPU specific power down sequence to + complete a warm reboot sequence in which only the CPUs are power cycled. + -------------- .. |FIP in a GPT image| image:: ../../resources/diagrams/FIP_in_a_GPT_image.png diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 3d10e459f..42c0eda25 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -12,61 +12,59 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only). .. note:: - The FVP models used are Version 11.17 Build 21, unless otherwise stated. + The FVP models used are Version 11.19 Build 14, unless otherwise stated. - ``Foundation_Platform`` -- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` -- ``FVP_Base_AEMv8A-AEMv8A`` (For certain configurations also uses 11.14/21) -- ``FVP_Base_AEMv8A-GIC600AE`` -- ``FVP_Base_AEMvA`` (For certain configurations also uses 0.0/6684) -- ``FVP_Base_Cortex-A32x4`` (Version 11.12/38) +- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21) +- ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21) +- ``FVP_Base_AEMvA`` +- ``FVP_Base_AEMvA-AEMvA`` +- ``FVP_Base_Cortex-A32x4`` (Version 11.12/38) - ``FVP_Base_Cortex-A35x4`` - ``FVP_Base_Cortex-A53x4`` -- ``FVP_Base_Cortex-A55x4`` +- ``FVP_Base_Cortex-A55`` - ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` +- ``FVP_Base_Cortex-A55x4+Cortex-A76x2`` - ``FVP_Base_Cortex-A57x1-A53x1`` - ``FVP_Base_Cortex-A57x2-A53x4`` -- ``FVP_Base_Cortex-A57x4-A53x4`` - ``FVP_Base_Cortex-A57x4`` -- ``FVP_Base_Cortex-A65AEx8`` -- ``FVP_Base_Cortex-A65x4`` -- ``FVP_Base_Cortex-A710x4`` -- ``FVP_Base_Cortex-A72x4-A53x4`` +- ``FVP_Base_Cortex-A57x4-A53x4`` +- ``FVP_Base_Cortex-A65`` +- ``FVP_Base_Cortex-A65AE`` +- ``FVP_Base_Cortex-A710x4`` (Version 11.17/21) - ``FVP_Base_Cortex-A72x4`` -- ``FVP_Base_Cortex-A73x4-A53x4`` +- ``FVP_Base_Cortex-A72x4-A53x4`` - ``FVP_Base_Cortex-A73x4`` -- ``FVP_Base_Cortex-A75x4`` -- ``FVP_Base_Cortex-A76AEx4`` -- ``FVP_Base_Cortex-A76AEx8`` -- ``FVP_Base_Cortex-A76x4`` -- ``FVP_Base_Cortex-A77x4`` -- ``FVP_Base_Cortex-A78x4`` -- ``FVP_Base_Neoverse-E1x1`` -- ``FVP_Base_Neoverse-E1x2`` -- ``FVP_Base_Neoverse-E1x4`` -- ``FVP_Base_Neoverse-N1x4`` -- ``FVP_Base_Neoverse-N2x4`` (Version 11.12 build 38) -- ``FVP_Base_Neoverse-V1x4`` -- ``FVP_Base_RevC-2xAEMvA`` (For certain configurations also uses 0.0/6557) -- ``FVP_CSS_SGI-575`` (Version 11.17/33) +- ``FVP_Base_Cortex-A73x4-A53x4`` +- ``FVP_Base_Cortex-A75`` +- ``FVP_Base_Cortex-A76`` +- ``FVP_Base_Cortex-A76AE`` +- ``FVP_Base_Cortex-A77`` +- ``FVP_Base_Cortex-A78`` +- ``FVP_Base_Cortex-A78C`` +- ``FVP_Base_Cortex-X2x4`` (Version 11.17/21) +- ``FVP_Base_Neoverse-E1`` +- ``FVP_Base_Neoverse-N1`` +- ``FVP_Base_Neoverse-N2x4`` (Version 11.16/16) +- ``FVP_Base_Neoverse-V1`` +- ``FVP_Base_RevC-2xAEMvA`` - ``FVP_Morello`` (Version 0.11/33) -- ``FVP_RD_E1_edge`` (Version 11.17/33) -- ``FVP_RD_N1_edge_dual`` (Version 11.17/33) -- ``FVP_RD_N1_edge`` (Version 11.17/33) -- ``FVP_RD_V1`` (Version 11.17/33) -- ``FVP_TC0`` -- ``FVP_TC1`` +- ``FVP_RD_E1_edge`` (Version 11.17/29) +- ``FVP_RD_V1`` (Version 11.17/29) +- ``FVP_TC0`` (Version 11.17/18) +- ``FVP_TC1`` (Version 11.17/33) +- ``FVP_TC2`` (Version 11.18/28) The latest version of the AArch32 build of TF-A has been tested on the following Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only). - ``FVP_Base_AEMvA`` -- ``FVP_Base_AEMv8A-AEMv8A`` +- ``FVP_Base_AEMvA-AEMvA`` - ``FVP_Base_Cortex-A32x4`` .. note:: - The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which + The ``FVP_Base_RevC-2xAEMvA`` FVP only supports shifted affinities, which is not compatible with legacy GIC configurations. Therefore this FVP does not support these legacy GIC configurations. @@ -327,19 +325,14 @@ or ``FVP_HW_CONFIG_DTS`` build options (refer to - ``fvp-base-gicv2-psci.dts`` - For use with models such as the Cortex-A57-A53 Base FVPs without shifted - affinities and with Base memory map configuration. - -- ``fvp-base-gicv2-psci-aarch32.dts`` - - For use with models such as the Cortex-A32 Base FVPs without shifted - affinities and running Linux in AArch32 state with Base memory map - configuration. + For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs + without shifted affinities and with Base memory map configuration. - ``fvp-base-gicv3-psci.dts`` - For use with models such as the Cortex-A57-A53 Base FVPs without shifted - affinities and with Base memory map configuration and Linux GICv3 support. + For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs + without shifted affinities and with Base memory map configuration and + Linux GICv3 support. - ``fvp-base-gicv3-psci-1t.dts`` @@ -352,12 +345,6 @@ or ``FVP_HW_CONFIG_DTS`` build options (refer to single cluster, single threaded CPUs, Base memory map configuration and Linux GICv3 support. -- ``fvp-base-gicv3-psci-aarch32.dts`` - - For use with models such as the Cortex-A32 Base FVPs without shifted - affinities and running Linux in AArch32 state with Base memory map - configuration and Linux GICv3 support. - - ``fvp-foundation-gicv2-psci.dts`` For use with Foundation FVP with Base memory map configuration. diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst index 8b9d45311..91e681f6d 100644 --- a/docs/plat/arm/juno/index.rst +++ b/docs/plat/arm/juno/index.rst @@ -241,13 +241,13 @@ configure it. -------------- -*Copyright (c) 2019-2021, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* .. _Linaro release software stack: http://releases.linaro.org/members/arm/platforms/ .. _Juno platform software user guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/juno/user-guide.rst .. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.8.0/juno/ .. _build the binaries from source: https://github.com/ARM-software/SCP-firmware/blob/master/user_guide.md#scp-firmware-user-guide .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/ -.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf +.. _Juno Getting Started Guide: https://developer.arm.com/documentation/den0928/f/?lang=en .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf .. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php diff --git a/docs/plat/arm/tc/index.rst b/docs/plat/arm/tc/index.rst index 20d3e562e..df1847d61 100644 --- a/docs/plat/arm/tc/index.rst +++ b/docs/plat/arm/tc/index.rst @@ -13,10 +13,13 @@ Some of the features of TC platform referenced in TF-A include: - SCMI - MHUv2 -Currently, the main difference between TC0 (TARGET_PLATFORM=0) and TC1 -(TARGET_PLATFORM=1) platforms w.r.t to TF-A is the CPUs supported. TC0 has -support for Cortex A510, Cortex A710 and Cortex X2, while TC1 has support for -Cortex A510, Cortex Makalu and Cortex Makalu ELP Arm CPUs. +Currently, the main difference between TC0 (TARGET_PLATFORM=0), TC1 +(TARGET_PLATFORM=1), TC2 (TARGET_PLATFORM=2) platforms w.r.t to TF-A +is the CPUs supported as below: + +- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. +- TC1 has support for Cortex A510, Cortex Makalu and Cortex X3. +- TC2 has support for Hayes and Hunter Arm CPUs. Boot Sequence @@ -33,15 +36,15 @@ Non-secure world (u-boot). Build Procedure (TF-A only) ~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Obtain arm `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_. - Set the CROSS_COMPILE environment variable to point to the toolchain folder. +- Obtain `Arm toolchain`_ and set the CROSS_COMPILE environment variable to + point to the toolchain folder. - Build TF-A: .. code:: shell make PLAT=tc BL33=<path_to_uboot.bin> \ - SCP_BL2=<path_to_scp_ramfw.bin> TARGET_PLATFORM={0,1} all fip + SCP_BL2=<path_to_scp_ramfw.bin> TARGET_PLATFORM={0,1,2} all fip Enable TBBR by adding the following options to the make command: @@ -53,4 +56,8 @@ Build Procedure (TF-A only) ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem -*Copyright (c) 2020-2021, Arm Limited. All rights reserved.* +-------------- + +*Copyright (c) 2020-2022, Arm Limited. All rights reserved.* + +.. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads diff --git a/docs/plat/deprecated.rst b/docs/plat/deprecated.rst deleted file mode 100644 index 7cc425814..000000000 --- a/docs/plat/deprecated.rst +++ /dev/null @@ -1,20 +0,0 @@ -Deprecated platforms -==================== - -Process of deprecating a platform ---------------------------------- - -Platform can be deprecated and its source can be kept in repository for a cooling -off period before deleting it or it can be deleted straight away. For later types -Deprecated/Deleted version would be same. - -List of deprecated platforms ----------------------------- - -+----------------+----------------+--------------------+--------------------+ -| Platform | Vendor | Deprecated version | Deleted version | -+================+================+====================+====================+ -| sgm775 | Arm | 2.5 | 2.7 | -+----------------+----------------+--------------------+--------------------+ -| mt6795 | MTK | 2.5 | 2.7 | -+----------------+----------------+--------------------+--------------------+ diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst index 101d52bef..f8071f71d 100644 --- a/docs/plat/imx8m.rst +++ b/docs/plat/imx8m.rst @@ -68,3 +68,46 @@ When setting MEASURED_BOOT=1 on imx8mm we can let TF-A generate event logs with a DTB overlay. The overlay will be put at PLAT_IMX8M_DTO_BASE with maximum size PLAT_IMX8M_DTO_MAX_SIZE. Then in U-boot we can apply the DTB overlay and let U-boot to parse the event log and update the PCRs. + +High Assurance Boot (HABv4) +--------------------------- + +All actively maintained platforms have a support for High Assurance +Boot (HABv4), which is implemented via ROM Vector Table (RVT) API to +extend the Root-of-Trust beyond the SPL. Those calls are done via SMC +and are executed in EL3, with results returned back to original caller. + +Note on DRAM Memory Mapping +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +There is a special case of mapping the DRAM: entire DRAM available on the +platform is mapped into the EL3 with MT_RW attributes. + +Mapping the entire DRAM allows the usage of 2MB block mapping in Level-2 +Translation Table entries, which use less Page Table Entries (PTEs). If +Level-3 PTE mapping is used instead then additional PTEs would be required, +which leads to the increase of translation table size. + +Due to the fact that the size of SRAM is limited on some platforms in the +family it should rather be avoided creating additional Level-3 mapping and +introduce more PTEs, hence the implementation uses Level-2 mapping which +maps entire DRAM space. + +The reason for the MT_RW attribute mapping scheme is the fact that the SMC +API to get the status and events is called from NS world passing destination +pointers which are located in DRAM. Mapping DRAM without MT_RW permissions +causes those locations not to be filled, which in turn causing EL1&0 software +not to receive replies. + +Therefore, DRAM mapping is done with MT_RW attributes, as it is required for +data exchange between EL3 and EL1&0 software. + +Reference Documentation +~~~~~~~~~~~~~~~~~~~~~~~ + +Details on HABv4 usage and implementation could be found in following documents: + +- AN4581: "i.MX Secure Boot on HABv4 Supported Devices", Rev. 4 - June 2020 +- AN12263: "HABv4 RVT Guidelines and Recommendations", Rev. 1 - 06/2020 +- "HABv4 API Reference Manual". This document in the part of NXP Code Signing Tool (CST) distribution. + diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 0cef16a34..a4e206780 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst @@ -4,12 +4,10 @@ Platform Ports .. toctree:: :maxdepth: 1 :caption: Contents - :numbered: :hidden: allwinner arm/index - deprecated meson-axg meson-gxbb meson-gxl @@ -21,6 +19,7 @@ Platform Ports marvell/index mt8183 mt8186 + mt8188 mt8192 mt8195 nvidia-tegra @@ -42,6 +41,7 @@ Platform Ports synquacer stm32mp1 ti-k3 + xilinx-versal-net xilinx-versal xilinx-zynqmp brcm-stingray @@ -57,10 +57,26 @@ documentation associated with them. - Arm Neoverse N1 System Development Platform (N1SDP) - Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP - Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP - - Arm SGI-575 and SGM-775 - - MediaTek MT6795 and MT8173 SoCs - - Arm Morello Platform + - Arm SGI-575 + - MediaTek MT8173 SoCs + +Deprecated platforms +-------------------- + ++----------------+----------------+--------------------+--------------------+ +| Platform | Vendor | Deprecated version | Deleted version | ++================+================+====================+====================+ +| sgm775 | Arm | 2.5 | 2.7 | ++----------------+----------------+--------------------+--------------------+ +| mt6795 | MTK | 2.5 | 2.7 | ++----------------+----------------+--------------------+--------------------+ +| sgi575 | Arm | 2.8 | 3.0 | ++----------------+----------------+--------------------+--------------------+ +| rdn1edge | Arm | 2.8 | 3.0 | ++----------------+----------------+--------------------+--------------------+ +| tc0 | Arm | 2.8 | 3.0 | ++----------------+----------------+--------------------+--------------------+ -------------- -*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst index adb960312..8cb3fdf2f 100644 --- a/docs/plat/marvell/armada/build.rst +++ b/docs/plat/marvell/armada/build.rst @@ -26,7 +26,7 @@ BL33 should be ``~/project/u-boot/u-boot.bin`` *u-boot.bin* should be used and not *u-boot-spl.bin* -Set MSS/SCP image path (mandatory only for A7K/8K/CN913x when MSS_SUPPORT=1) +Set MSS/SCP image path (mandatory only for A7K/A8K/CN913x when MSS_SUPPORT=1) .. code:: shell @@ -109,7 +109,7 @@ There are several build options: - MV_DDR_PATH This parameter is required for ``mrvl_flash`` and ``mrvl_uart`` targets. - For A7K/8K/CN913x it is used for BLE build and for Armada37x0 it used + For A7K/A8K/CN913x it is used for BLE build and for Armada37x0 it used for ddr_tool build. Specify path to the full checkout of Marvell mv-ddr-marvell git @@ -131,7 +131,7 @@ CN913x specific build options: values with CP_NUM are in a range of 1 to 3. -A7K/8K/CN913x specific build options: +A7K/A8K/CN913x specific build options: - BLE_PATH @@ -165,14 +165,14 @@ Globalscale MOCHAbin specific build options: Armada37x0 specific build options: -- HANDLE_EA_EL3_FIRST +- HANDLE_EA_EL3_FIRST_NS - When ``HANDLE_EA_EL3_FIRST=1``, External Aborts and SError Interrupts will be always trapped - in TF-A. TF-A in this case enables dirty hack / workaround for a bug found in U-Boot and - Linux kernel PCIe controller driver pci-aardvark.c, traps and then masks SError interrupt - caused by AXI SLVERR on external access (syndrome 0xbf000002). + When ``HANDLE_EA_EL3_FIRST_NS=1``, External Aborts and SError Interrupts, resulting from errors + in NS world, will be always trapped in TF-A. TF-A in this case enables dirty hack / workaround for + a bug found in U-Boot and Linux kernel PCIe controller driver pci-aardvark.c, traps and then masks + SError interrupt caused by AXI SLVERR on external access (syndrome 0xbf000002). - Otherwise when ``HANDLE_EA_EL3_FIRST=0``, these exceptions will be trapped in the current + Otherwise when ``HANDLE_EA_EL3_FIRST_NS=0``, these exceptions will be trapped in the current exception level (or in EL1 if the current exception level is EL0). So exceptions caused by U-Boot will be trapped in U-Boot, exceptions caused by Linux kernel (or user applications) will be trapped in Linux kernel. @@ -185,8 +185,8 @@ Armada37x0 specific build options: recommended to not enable this workaround as it disallows propagating of all External Aborts to running Linux kernel and makes correctable errors as fatal aborts. - This option is now disabled by default. In past this option was enabled by default in - TF-A versions v2.2, v2.3, v2.4 and v2.5. + This option is now disabled by default. In past this option has different name "HANDLE_EA_EL3_FIRST" and + was enabled by default in TF-A versions v2.2, v2.3, v2.4 and v2.5. - CM3_SYSTEM_RESET @@ -387,7 +387,7 @@ Special Build Flags - PLAT_RECOVERY_IMAGE_ENABLE When set this option to enable secondary recovery function when build atf. In order to build UART recovery image this operation should be disabled for - A7K/8K/CN913x because of hardware limitation (boot from secondary image + A7K/A8K/CN913x because of hardware limitation (boot from secondary image can interrupt UART recovery process). This MACRO definition is set in ``plat/marvell/armada/a8k/common/include/platform_def.h`` file. diff --git a/docs/plat/marvell/armada/uart-booting.rst b/docs/plat/marvell/armada/uart-booting.rst new file mode 100644 index 000000000..04ce46485 --- /dev/null +++ b/docs/plat/marvell/armada/uart-booting.rst @@ -0,0 +1,103 @@ +TF-A UART Booting Instructions for Marvell Platforms +==================================================== + +This section describes how to temporary boot the Trusted Firmware-A (TF-A) project over UART +without flashing it to non-volatile storage for Marvell's platforms. + +See :ref:`TF-A Build Instructions for Marvell Platforms` how to build ``mrvl_uart`` and +``mrvl_flash`` targets used in this section. + +Armada37x0 UART image downloading +--------------------------------- + +There are two options how to download UART image into any Armada37x0 board. + +Marvell Wtpdownloader +~~~~~~~~~~~~~~~~~~~~~ + +Marvell Wtpdownloader works only with UART images stored in separate files and supports only upload +speed with 115200 bauds. Target ``mrvl_uart`` produces GZIPed TAR archive ``uart-images.tgz.bin`` +with either three files ``TIM_ATF.bin``, ``wtmi_h.bin`` and ``boot-image_h.bin`` for non-secure +boot or with four files ``TIM_ATF_TRUSTED.bin``, ``TIMN_ATF_TRUSTED.bin``, ``wtmi_h.bin`` and +``boot-image_h.bin`` when secure boot is enabled. + +Compilation: + +.. code:: shell + + > git clone https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git + > make -C A3700-utils-marvell/wtptp/src/Wtpdownloader_Linux -f makefile.mk + +It produces executable binary ``A3700-utils-marvell/wtptp/src/Wtpdownloader_Linux/WtpDownload_linux`` + +To download images from ``uart-images.tgz.bin`` archive unpack it and for non-secure boot variant run: + +.. code:: shell + + > stty -F /dev/ttyUSB<port#> clocal + > WtpDownload_linux -P UART -C <port#> -E -B TIM_ATF.bin -I wtmi_h.bin -I boot-image_h.bin + +After that immediately start terminal on ``/dev/ttyUSB<port#>`` to see boot output. + +CZ.NIC mox-imager +~~~~~~~~~~~~~~~~~ + +CZ.NIC mox-imager supports all Armada37x0 boards (not only Turris MOX as name suggests). It works +with either with separate files from ``uart-images.tgz.bin`` archive (like Marvell Wtpdownloader) +produced by ``mrvl_uart`` target or also with ``flash-image.bin`` file produced by ``mrvl_flash`` +target, which is the exactly same file as used for flashing. So when using CZ.NIC mox-imager there +is no need to build separate files for UART flashing like in case with Marvell Wtpdownloader. + +CZ.NIC mox-imager moreover supports higher upload speeds up to the 6000000 bauds (which seems to +be limit of Armada37x0 SoC) which is much higher and faster than Marvell Wtpdownloader. + +Compilation: + +.. code:: shell + + > git clone https://gitlab.nic.cz/turris/mox-imager.git + > make -C mox-imager + +It produces executable binary ``mox-imager/mox-imager`` + +To download single file image built by ``mrvl_flash`` target at the highest speed, run: + +.. code:: shell + + > mox-imager -D /dev/ttyUSB<port#> -E -b 6000000 -t flash-image.bin + +To download images from ``uart-images.tgz.bin`` archive built by ``mrvl_uart`` target for +non-secure boot variant (like Wtpdownloader) but at the highest speed, first unpack +``uart-images.tgz.bin`` archive and then run: + +.. code:: shell + + > mox-imager -D /dev/ttyUSB<port#> -E -b 6000000 -t TIM_ATF.bin wtmi_h.bin boot-image_h.bin + +CZ.NIC mox-imager after successful download will start its own mini terminal (option ``-t``) to +not loose any boot output. It also prints boot output which is sent either by image files or by +bootrom during transferring of image files. This mini terminal can be quit by CTRL-\\ + C keypress. + + +A7K/A8K/CN913x UART image downloading +------------------------------------- + +A7K/A8K/CN913x uses same image ``flash-image.bin`` for both flashing and booting over UART. +For downloading image over UART it is possible to use mvebu64boot tool. + +Compilation: + +.. code:: shell + + > git clone https://github.com/pali/mvebu64boot.git + > make -C mvebu64boot + +It produces executable binary ``mvebu64boot/mvebu64boot`` + +To download ``flash-image.bin`` image run: + +.. code:: shell + + > mvebu64boot -t -b flash-image.bin /dev/ttyUSB0 + +After successful download it will start own mini terminal (option ``-t``) like CZ.NIC mox-imager. diff --git a/docs/plat/marvell/index.rst b/docs/plat/marvell/index.rst index 0d33432ba..2d5cdeb3f 100644 --- a/docs/plat/marvell/index.rst +++ b/docs/plat/marvell/index.rst @@ -6,6 +6,7 @@ Marvell :caption: Contents armada/build + armada/uart-booting armada/porting armada/misc/mvebu-a8k-addr-map armada/misc/mvebu-amb diff --git a/docs/plat/mt8188.rst b/docs/plat/mt8188.rst new file mode 100644 index 000000000..93abaa5cd --- /dev/null +++ b/docs/plat/mt8188.rst @@ -0,0 +1,21 @@ +MediaTek 8188 +============= + +MediaTek 8188 (MT8188) is a 64-bit ARM SoC introduced by MediaTek in 2022. +The chip incorporates eight cores - six Cortex-A55 little cores and two Cortex-A78. +Cortex-A78 can operate at up to 2.6 GHz. +Cortex-A55 can operate at up to 2.0 GHz. + +Boot Sequence +------------- + +:: + + Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel + + How to Build + ------------ + + .. code:: shell + + make CROSS_COMPILE=aarch64-linux-gnu- LD=aarch64-linux-gnu-gcc PLAT=mt8188 DEBUG=1 COREBOOT=1 diff --git a/docs/plat/qemu.rst b/docs/plat/qemu.rst index 66b82473c..698632697 100644 --- a/docs/plat/qemu.rst +++ b/docs/plat/qemu.rst @@ -136,3 +136,37 @@ To start (QEMU v5.0.0): -append 'console=ttyAMA0,38400 keep_bootcon' \ -initrd rootfs.cpio.gz -smp 2 -m 1024 -bios flash.bin \ -d unimp + +Running QEMU in OpenCI +----------------------- + +Linaro's continuous integration platform OpenCI supports running emulated tests +on QEMU. The tests are kicked off on Jenkins and deployed through the Linaro +Automation and Validation Architecture `LAVA`_. + +There are a set of Linux boot tests provided in OpenCI. They rely on prebuilt +`binaries`_ for UEFI, the kernel, root file system, as well as, any other TF-A +dependencies, and are run as part of the OpenCI TF-A `daily job`_. To run them +manually, a `builder`_ job may be triggered with the test configuration +``qemu-boot-tests``. + + +You may see the following warning repeated several times in the boot logs: + +.. code:: shell + + pflash_write: Write to buffer emulation is flawed + +Please ignore this as it is an unresolved `issue in QEMU`_, it is an internal +QEMU warning that logs flawed use of "write to buffer". + +.. note:: + For more information on how to trigger jobs in OpenCI, please refer to + Linaro's CI documentation, which explains how to trigger a `manual job`_. + +.. _binaries: https://downloads.trustedfirmware.org/tf-a/linux_boot/ +.. _daily job: https://ci.trustedfirmware.org/view/TF-A/job/tf-a-main/ +.. _builder: https://ci.trustedfirmware.org/view/TF-A/job/tf-a-builder/ +.. _LAVA: https://tf.validation.linaro.org/ +.. _manual job: https://tf-ci-users-guide.readthedocs.io/en/latest/#manual-job-trigger +.. _issue in QEMU: https://git.qemu.org/?p=qemu.git;a=blob;f=hw/block/pflash_cfi01.c;h=0cbc2fb4cbf62c9a033b8dd89012374ff74ed610;hb=refs/heads/master#l500 diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst index 7ae98b1d2..23ea25aec 100644 --- a/docs/plat/stm32mp1.rst +++ b/docs/plat/stm32mp1.rst @@ -63,15 +63,6 @@ Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are inside the FIP binary: BL32 (SP_min or OP-TEE), U-Boot and their respective device tree blobs. -STM32IMAGE bootchain -~~~~~~~~~~~~~~~~~~~~ -Although still supported, this way of booting is not recommended. -Pease use FIP instead. -At compilation step, BL2, BL32 and DTB file are linked together in a single -binary. The stm32image tool is also generated and the header is added to TF-A -binary. This binary file with header is named tf-a-stm32mp157c-ev1.stm32. -It can then be copied in the first partition of the boot device. - Memory mapping ~~~~~~~~~~~~~~ @@ -144,8 +135,12 @@ Other configuration flags: - | ``DTB_FILE_NAME``: to precise board device-tree blob to be used. | Default: stm32mp157c-ev1.dtb +- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP, + | default location (end of the first 128MB) is used when absent - | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup. | Default: 0 (disabled) +- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2). + | Default: 0 (disabled) - | ``STM32MP_UART_BAUDRATE``: to select UART baud rate. | Default: 115200 - | ``STM32_TF_VERSION``: to manage BL2 monotonic counter. @@ -231,44 +226,40 @@ With OP-TEE: BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin fip +Trusted Boot Board +__________________ -STM32IMAGE bootchain -~~~~~~~~~~~~~~~~~~~~ -You need to add the following flag to the make command: -``STM32MP_USE_STM32IMAGE=1`` - -To build with SP_min and support for SD-card boot: - -.. code:: bash - - make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ - AARCH32_SP=sp_min STM32MP_SDMMC=1 DTB_FILE_NAME=stm32mp157c-ev1.dtb \ - STM32MP_USE_STM32IMAGE=1 - - cd <u-boot_directory> - make stm32mp15_trusted_defconfig - make DEVICE_TREE=stm32mp157c-ev1 all - -To build TF-A with OP-TEE support for SD-card boot: - -.. code:: bash - - make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ - AARCH32_SP=optee STM32MP_SDMMC=1 DTB_FILE_NAME=stm32mp157c-ev1.dtb \ - STM32MP_USE_STM32IMAGE=1 - - cd <optee_directory> - make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \ - CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts - - cd <u-boot_directory> - make stm32mp15_trusted_defconfig - make DEVICE_TREE=stm32mp157c-ev1 all - - -The following build options are supported: +.. code:: shell + + tools/cert_create/cert_create -n --rot-key "build/stm32mp1/debug/rot_key.pem" \ + --tfw-nvctr 0 \ + --ntfw-nvctr 0 \ + --key-alg ecdsa --hash-alg sha256 \ + --trusted-key-cert build/stm32mp1/cert_images/trusted-key-cert.key-crt \ + --tos-fw <optee_directory>/tee-header_v2.bin \ + --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \ + --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \ + --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \ + --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \ + --nt-fw <u-boot_directory>/u-boot-nodtb.bin \ + --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \ + --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \ + --hw-config <u-boot_directory>/u-boot.dtb \ + --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \ + --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt + + tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \ + --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \ + --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \ + --nt-fw <u-boot_directory>/u-boot-nodtb.bin \ + --hw-config <u-boot_directory>/u-boot.dtb \ + --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \ + --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \ + --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \ + --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \ + --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \ + --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt stm32mp1.fip -- ``ENABLE_STACK_PROTECTOR``: To enable the stack protection. Populate SD-card @@ -284,22 +275,6 @@ It should contain at least those partitions: Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl. -STM32IMAGE bootchain -~~~~~~~~~~~~~~~~~~~~ -The SD-card has to be formatted with GPT. -It should contain at least those partitions: - -- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary -- ssbl: to copy the u-boot.stm32 binary - -Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl. - -OP-TEE artifacts go into separate partitions as follows: - -- teeh: tee-header_v2.stm32 -- teed: tee-pageable_v2.stm32 -- teex: tee-pager_v2.stm32 - .. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html .. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification diff --git a/docs/plat/xilinx-versal-net.rst b/docs/plat/xilinx-versal-net.rst new file mode 100644 index 000000000..5d2e663e5 --- /dev/null +++ b/docs/plat/xilinx-versal-net.rst @@ -0,0 +1,31 @@ +Xilinx Versal NET +================= + +Trusted Firmware-A implements the EL3 firmware layer for Xilinx Versal NET. +The platform only uses the runtime part of TF-A as Xilinx Versal NET already +has a BootROM (BL1) and PMC FW (BL2). + +BL31 is TF-A. +BL32 is an optional Secure Payload. +BL33 is the non-secure world software (U-Boot, Linux etc). + +To build: +```bash +make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net bl31 +``` + +Xilinx Versal NET platform specific build options +------------------------------------------------- + +* `VERSAL_NET_ATF_MEM_BASE`: Specifies the base address of the bl31 binary. +* `VERSAL_NET_ATF_MEM_SIZE`: Specifies the size of the memory region of the bl31 binary. +* `VERSAL_NET_BL32_MEM_BASE`: Specifies the base address of the bl32 binary. +* `VERSAL_NET_BL32_MEM_SIZE`: Specifies the size of the memory region of the bl32 binary. + +* `VERSAL_NET_CONSOLE`: Select the console driver. Options: + - `pl011`, `pl011_0`: ARM pl011 UART 0 + - `pl011_1` : ARM pl011 UART 1 + +* `TFA_NO_PM` : Platform Management support. + - 0 : Enable Platform Management (Default) + - 1 : Disable Platform Management diff --git a/docs/process/coding-guidelines.rst b/docs/process/coding-guidelines.rst index ef319e441..26c272d86 100644 --- a/docs/process/coding-guidelines.rst +++ b/docs/process/coding-guidelines.rst @@ -463,11 +463,11 @@ There are, however, legitimate uses of assembly language. These include: -------------- -*Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2020, 2022, Arm Limited and Contributors. All rights reserved.* .. _`Linux master tree`: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/ -.. _`Procedure Call Standard for the Arm Architecture`: https://developer.arm.com/docs/ihi0042/latest/ -.. _`Procedure Call Standard for the Arm 64-bit Architecture`: https://developer.arm.com/docs/ihi0055/latest/ +.. _`Procedure Call Standard for the Arm Architecture`: https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst +.. _`Procedure Call Standard for the Arm 64-bit Architecture`: https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst .. _`EditorConfig`: http://editorconfig.org/ .. _`Why the “volatile†type class should not be used`: https://www.kernel.org/doc/html/latest/process/volatile-considered-harmful.html .. _`MISRA C:2012 Guidelines`: https://www.misra.org.uk/Activities/MISRAC/tabid/160/Default.aspx diff --git a/docs/process/commit-style.rst b/docs/process/commit-style.rst index de899ab1f..d7e937bec 100644 --- a/docs/process/commit-style.rst +++ b/docs/process/commit-style.rst @@ -96,36 +96,25 @@ locally, as commitlint reports a live list of the acceptable scopes. Adding Scopes ------------- -Scopes that are either a) unblessed in the configuration file, or b) do not -exist in the configuration file at all are considered to be deprecated. If you -are adding a new component that does not yet have a designated scope, please -feel free to add one. +Scopes that are not present in the changelog configuration file are considered +to be deprecated, and should be avoided. If you are adding a new component that +does not yet have a designated scope, please add one. For example, if you are adding or making modifications to `Foo`'s latest and -greatest new platform `Bar`, you would add it to the `Platforms` changelog -section, and the hierarchy should look something like this: - -.. code:: json - - { - "sections": [ - { - "title": "Platforms", - "sections": [ - { - "title": "Foo", - "scopes": ["foo"], - "sections": [ - { - "title": "Bar", - "scopes": ["bar"] - } - ] - } - ] - } - ] - } +greatest new platform `Bar` then you would add it to the `Platforms` changelog +sub-section, and the hierarchy should look something like this: + +.. code:: yaml + + - title: Platforms + + subsections: + - title: Foo + scope: foo + + subsections: + - title: Bar + scope: bar When creating new scopes, try to keep them short and succinct, and use kebab case (``this-is-kebab-case``). Components with a product name (i.e. most @@ -138,7 +127,9 @@ Mandated Trailers Commits are expected to be signed off with the ``Signed-off-by:`` trailer using your real name and email address. You can do this automatically by committing -with Git's ``-s`` flag. +with Git's ``-s`` flag. By adding this line the contributor certifies the +contribution is made under the terms of the :download:`Developer Certificate of +Origin <../../dco.txt>`. There may be multiple ``Signed-off-by:`` lines depending on the history of the patch, but one **must** be the committer. More details may be found in the diff --git a/docs/process/index.rst b/docs/process/index.rst index bba2b40eb..7914a4e27 100644 --- a/docs/process/index.rst +++ b/docs/process/index.rst @@ -4,10 +4,9 @@ Processes & Policies .. toctree:: :maxdepth: 1 :caption: Contents - :numbered: security - platform-compatibility-policy + platform-ports-policy commit-style coding-style coding-guidelines diff --git a/docs/process/platform-compatibility-policy.rst b/docs/process/platform-ports-policy.rst index a10236c8c..798374944 100644 --- a/docs/process/platform-compatibility-policy.rst +++ b/docs/process/platform-ports-policy.rst @@ -1,11 +1,8 @@ -Platform Compatibility Policy -============================= +Platform Ports Policy +===================== -Introduction ------------- - -This document clarifies the project's policy around compatibility for upstream -platforms. +This document clarifies a couple of policy points around platform ports +management. Platform compatibility policy ----------------------------- @@ -29,6 +26,24 @@ public mailing list`_ to notify platforms that they should migrate away from the deprecated interfaces. Platforms are expected to migrate before the removal of the deprecated interface. +Platform deprecation policy +--------------------------- + +If a platform is no longer maintained, it is best to deprecate it to keep the +projects' source tree clean and healthy. Deprecation can be a 1-stage or 2-stage +process (up to the platform maintainers). + + - *2-stage*: The platform's source code can be kept in the repository for a + cooling off period before deleting it (typically 2 release cycles). In this + case, we keep track ot the *Deprecated* version separately from the *Deleted* + version. + + - *1-stage*: The platform's source code can be deleted straight away. In this + case, both versions are the same. + +The :ref:`Platform Ports` page provides a list of all deprecated/deleted +platform ports (or soon to be) to this day. + -------------- *Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/resources/diagrams/Makefile b/docs/resources/diagrams/Makefile index 7f583b524..c951754cf 100644 --- a/docs/resources/diagrams/Makefile +++ b/docs/resources/diagrams/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -61,7 +61,25 @@ XLAT_PNG = xlat_align.png xlat_align_layers = "bg,translations" xlat_align_opts = -all:$(RESET_PNGS) $(INT_PNGS) $(XLAT_PNG) +RMM_DIA = rmm_cold_boot_generic.dia +RMM_PNG = rmm_cold_boot_generic.png + +rmm_cold_boot_generic_layers = "background" +rmm_cold_boot_generic_opts = + +RMM_EL3_MANIFEST_DIA = rmm_el3_manifest_struct.dia +RMM_EL3_MANIFEST_PNG = rmm_el3_manifest_struct.png + +rmm_el3_manifest_struct_layers = "Background" +rmm_el3_manifest_struct_opts = + +PSA_FWU_DIA = PSA-FWU.dia +PSA_FWU_PNG = PSA-FWU.png + +FWU-update_struct_layers = "background" +FWU-update_struct_opts = + +all:$(RESET_PNGS) $(INT_PNGS) $(XLAT_PNG) $(RMM_PNG) $(RMM_EL3_MANIFEST_PNG) $(PSA_FWU_PNG) $(RESET_PNGS):$(RESET_DIA) $(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<) @@ -72,3 +90,12 @@ $(INT_PNGS):$(INT_DIA) $(XLAT_PNG):$(XLAT_DIA) $(call generate_image,$($(patsubst %.png,%_layers,$@)),$(patsubst %.png,%.svg,$@),svg,$($(patsubst %.png,%_opts,$@)),$<) inkscape -z $(patsubst %.png,%.svg,$@) -e $@ -d 45 + +$(RMM_PNG):$(RMM_DIA) + $(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<) + +$(RMM_EL3_MANIFEST_PNG):$(RMM_EL3_MANIFEST_DIA) + $(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<) + +$(PSA_FWU_PNG):$(PSA_FWU_DIA) + $(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<) diff --git a/docs/resources/diagrams/PSA-FWU.dia b/docs/resources/diagrams/PSA-FWU.dia Binary files differnew file mode 100644 index 000000000..aac527697 --- /dev/null +++ b/docs/resources/diagrams/PSA-FWU.dia diff --git a/docs/resources/diagrams/PSA-FWU.png b/docs/resources/diagrams/PSA-FWU.png Binary files differnew file mode 100644 index 000000000..d58ba8697 --- /dev/null +++ b/docs/resources/diagrams/PSA-FWU.png diff --git a/docs/resources/diagrams/ff-a-lsp-at-el3.png b/docs/resources/diagrams/ff-a-lsp-at-el3.png Binary files differnew file mode 100644 index 000000000..7cff34f29 --- /dev/null +++ b/docs/resources/diagrams/ff-a-lsp-at-el3.png diff --git a/docs/resources/diagrams/ff-a-spm-at-el3.png b/docs/resources/diagrams/ff-a-spm-at-el3.png Binary files differnew file mode 100644 index 000000000..3b263b052 --- /dev/null +++ b/docs/resources/diagrams/ff-a-spm-at-el3.png diff --git a/docs/resources/diagrams/plantuml/el3_spm_dfd.puml b/docs/resources/diagrams/plantuml/el3_spm_dfd.puml new file mode 100644 index 000000000..c716180b6 --- /dev/null +++ b/docs/resources/diagrams/plantuml/el3_spm_dfd.puml @@ -0,0 +1,78 @@ +/' + ' Copyright (c) 2022, Arm Limited. All rights reserved. + ' + ' SPDX-License-Identifier: BSD-3-Clause + '/ + +/' +TF-A EL3 SPMC Data Flow Diagram +'/ + +@startuml +digraph tfa_el3_dfd { + + # Allow arrows to end on cluster boundaries + compound=true + concentrate=false + newrank=true + + # Default settings for edges and nodes + edge [minlen=2 color="#8c1b07"] + node [fillcolor="#ffb866" style=filled shape=box fixedsize=true width=1.6 height=0.7] + + # Nodes outside of the trust boundary + nsec [label="NS Client"] + ddr [label="External memory (DDR)"] + + {rank="same" smmu, spmd} + # Trust boundary cluster + subgraph cluster_trusted { + graph [style=dashed color="#f22430"] + concentrate=false + + # HW IPs cluster + subgraph cluster_ip { + label ="Hardware IPs"; + graph [style=filled color="#000000" fillcolor="#ffd29e"] + + rank="same" + gic [label="GIC" width=1.2 height=0.5] + smmu [label="SMMU" width=1.2 height=0.5] + uart [label="UART" width=1.2 height=0.5] + pe [label="PE" width=1.2 height=0.5] + } + + # TF-A cluster + subgraph cluster_tfa { + label ="EL3 monitor"; + graph [style=filled color="#000000" fillcolor="#faf9cd"] + {rank="same" spmc, bl31} + {rank="same" spmd, lsp} + spmc [label="SPMC" fillcolor="#ddffb3"] + bl31 [label="BL31" fillcolor="#ddffb3"]; + spmd [label="SPMD" fillcolor="#ddffb3"] + lsp[label="LSP1" fillcolor="#ddffb3"] + } + bl2 [label="BL2" width=1.2 height=0.5] + } + + # Secure Partitions cluster + subgraph cluster_sp { + label ="Secure Partitions"; + graph [style=filled color="#000000" fillcolor="#faf9cd"] + + sp1 [label="SP1" fillcolor="#ddffb3"] + } + + sp1 -> spmc [dir="both" label="DF1"] + lsp -> spmc [dir="both" label="DF4"] + spmc -> spmd [dir="both" label="DF2"] + spmd -> nsec [dir="both" label="DF3"] + spmc -> smmu [lhead=cluster_spmc label="DF5"] + bl2 -> spmc [lhead=cluster_spmc label="DF6"] + bl2 -> sp1 [lhead=cluster_spmc label="DF6"] + sp1 -> ddr [dir="both" label="DF7"] + spmc -> ddr [dir="both" label="DF7"] +} + +@enduml diff --git a/docs/resources/diagrams/rmm_cold_boot_generic.dia b/docs/resources/diagrams/rmm_cold_boot_generic.dia Binary files differnew file mode 100644 index 000000000..739a1dfb4 --- /dev/null +++ b/docs/resources/diagrams/rmm_cold_boot_generic.dia diff --git a/docs/resources/diagrams/rmm_cold_boot_generic.png b/docs/resources/diagrams/rmm_cold_boot_generic.png Binary files differnew file mode 100644 index 000000000..df4c1ba83 --- /dev/null +++ b/docs/resources/diagrams/rmm_cold_boot_generic.png diff --git a/docs/resources/diagrams/rmm_el3_manifest_struct.dia b/docs/resources/diagrams/rmm_el3_manifest_struct.dia Binary files differnew file mode 100644 index 000000000..7b7a9c2ba --- /dev/null +++ b/docs/resources/diagrams/rmm_el3_manifest_struct.dia diff --git a/docs/resources/diagrams/rmm_el3_manifest_struct.png b/docs/resources/diagrams/rmm_el3_manifest_struct.png Binary files differnew file mode 100644 index 000000000..8b5776c07 --- /dev/null +++ b/docs/resources/diagrams/rmm_el3_manifest_struct.png diff --git a/docs/security_advisories/index.rst b/docs/security_advisories/index.rst index 887b06a55..b80ba34d3 100644 --- a/docs/security_advisories/index.rst +++ b/docs/security_advisories/index.rst @@ -4,7 +4,6 @@ Security Advisories .. toctree:: :maxdepth: 1 :caption: Contents - :numbered: security-advisory-tfv-1.rst security-advisory-tfv-2.rst diff --git a/docs/security_advisories/security-advisory-tfv-9.rst b/docs/security_advisories/security-advisory-tfv-9.rst index 74b85dcd9..d73e74b6b 100644 --- a/docs/security_advisories/security-advisory-tfv-9.rst +++ b/docs/security_advisories/security-advisory-tfv-9.rst @@ -57,20 +57,38 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2). +----------------------+ | Cortex-A76 | +----------------------+ +| Cortex-A76AE | ++----------------------+ | Cortex-A77 | +----------------------+ | Cortex-A78 | +----------------------+ +| Cortex-A78AE | ++----------------------+ +| Cortex-A78C | ++----------------------+ +| Cortex-X1 | ++----------------------+ | Cortex-X2 | +----------------------+ +| Cortex-X3 | ++----------------------+ | Cortex-A710 | +----------------------+ +| Cortex-A715 | ++----------------------+ +| Cortex-Hunter | ++----------------------+ | Neoverse-N1 | +----------------------+ | Neoverse-N2 | +----------------------+ | Neoverse-V1 | +----------------------+ +| Neoverse-V2 | ++----------------------+ +| Neoverse-Poseidon | ++----------------------+ For all other cores impacted by Spectre-BHB, some of which that do not implement FEAT_CSV2 and some that do e.g. Cortex-A73, the recommended mitigation is to @@ -81,7 +99,9 @@ In case local workaround is not feasible, the Rich OS can invoke the SMC Convention specification`_ for more details. `Gerrit topic #spectre_bhb`_ This patchset implements the Spectre-BHB loop -workaround for CPUs mentioned in the above table. It also mitigates against +workaround for CPUs mentioned in the above table. For CPUs supporting +speculative barrier instruction, the loop workaround is optimised by using SB +in place of the common DSB and ISB sequence. It also mitigates against this vulnerability for Cortex-A72 CPU versions that support the CSV2 feature (from r1p0). The patch stack also includes an implementation for a specified `CVE-2022-23960`_ workaround SMC(``SMCCC_ARCH_WORKAROUND_3``) for use by normal @@ -90,7 +110,7 @@ in the `SMCCC Calling Convention specification`_. The specification and implementation also enables the normal world to discover the presence of this firmware service. This patch also implements ``SMCCC_ARCH_WORKAROUND_3`` for Cortex-A57, Coxtex-A72, Cortex-A73 and Cortex-A75 using the existing workaround. -for CVE-2017-5715. +for CVE-2017-5715. Cortex-A15 patch extends Spectre V2 mitigation to Spectre-BHB. The above workaround is enabled by default (on vulnerable CPUs only). Platforms can choose to disable them at compile time if they do not require them. diff --git a/docs/threat_model/index.rst b/docs/threat_model/index.rst index 335937e97..ad8b82ac0 100644 --- a/docs/threat_model/index.rst +++ b/docs/threat_model/index.rst @@ -11,10 +11,10 @@ based on the data flow diagram and potential threat mitigations. .. toctree:: :maxdepth: 1 :caption: Contents - :numbered: threat_model threat_model_spm + threat_model_el3_spm threat_model_fvp_r -------------- diff --git a/docs/threat_model/threat_model_el3_spm.rst b/docs/threat_model/threat_model_el3_spm.rst new file mode 100644 index 000000000..c3af7a2d8 --- /dev/null +++ b/docs/threat_model/threat_model_el3_spm.rst @@ -0,0 +1,650 @@ +EL3 SPMC Threat Model +********************* + +************ +Introduction +************ +This document provides a threat model for the TF-A `EL3 Secure Partition Manager`_ +(EL3 SPM) implementation. The EL3 SPM implementation is based on the +`Arm Firmware Framework for Arm A-profile`_ specification. + +******************** +Target of Evaluation +******************** +In this threat model, the target of evaluation is the ``Secure Partition Manager Core`` +component (SPMC) within the EL3 firmware. +The monitor and SPMD at EL3 are covered by the `Generic TF-A threat model`_. + +The scope for this threat model is: + +- The TF-A implementation for the EL3 SPMC +- The implementation complies with the FF-A v1.1 specification. +- Secure partition is statically provisioned at boot time. +- Focus on the run-time part of the life-cycle (no specific emphasis on boot + time, factory firmware provisioning, firmware udpate etc.) +- Not covering advanced or invasive physical attacks such as decapsulation, + FIB etc. + +Data Flow Diagram +================= +Figure 1 shows a high-level data flow diagram for the SPM split into an SPMD +and SPMC component at EL3. The SPMD mostly acts as a relayer/pass-through between +the normal world and the secure world. It is assumed to expose small attack surface. + +A description of each diagram element is given in Table 1. In the diagram, the +red broken lines indicate trust boundaries. + +Components outside of the broken lines are considered untrusted. + +.. uml:: ../resources/diagrams/plantuml/el3_spm_dfd.puml + :caption: Figure 1: EL3 SPMC Data Flow Diagram + +.. table:: Table 1: EL3 SPMC Data Flow Diagram Description + + +---------------------+--------------------------------------------------------+ + | Diagram Element | Description | + +=====================+========================================================+ + | DF1 | SP to SPMC communication. FF-A function invocation or | + | | implementation-defined Hypervisor call. | + | | | + | | Note:- To communicate with LSP, SP1 performs a direct | + | | message request to SPMC targeting LSP as destination. | + +---------------------+--------------------------------------------------------+ + | DF2 | SPMC to SPMD communication. | + +---------------------+--------------------------------------------------------+ + | DF3 | SPMD to NS forwarding. | + +---------------------+--------------------------------------------------------+ + | DF4 | SPMC to LSP communication. | + | | NWd to LSP communication happens through SPMC. | + | | LSP can send direct response SP1 or NWd through SPMC. | + +---------------------+--------------------------------------------------------+ + | DF5 | HW control. | + +---------------------+--------------------------------------------------------+ + | DF6 | Bootloader image loading. | + +---------------------+--------------------------------------------------------+ + | DF7 | External memory access. | + +---------------------+--------------------------------------------------------+ + + +*************** +Threat Analysis +*************** + +This threat model follows a similar methodology to the `Generic TF-A threat model`_. +The following sections define: + +- Trust boundaries +- Assets +- Theat agents +- Threat types + +Trust boundaries +================ + +- Normal world is untrusted. +- Secure world and normal world are separate trust boundaries. +- EL3 monitor, SPMD and SPMC are trusted. +- Bootloaders (in particular BL1/BL2 if using TF-A) and run-time BL31 are + implicitely trusted by the usage of trusted boot. +- EL3 monitor, SPMD, SPMC do not trust SPs. + +Assets +====== + +The following assets are identified: + +- SPMC state. +- SP state. +- Information exchange between endpoints (partition messages). +- SPMC secrets (e.g. pointer authentication key when enabled) +- SP secrets (e.g. application keys). +- Scheduling cycles. +- Shared memory. + +Threat Agents +============= + +The following threat agents are identified: + +- Non-secure endpoint (referred NS-Endpoint later): normal world client at + NS-EL2 (Hypervisor) or NS-EL1 (VM or OS kernel). +- Secure endpoint (referred as S-Endpoint later): typically a secure partition. +- Hardware attacks (non-invasive) requiring a physical access to the device, + such as bus probing or DRAM stress. + +Threat types +============ + +The following threat categories as exposed in the `Generic TF-A threat model`_ +are re-used: + +- Spoofing +- Tampering +- Repudiation +- Information disclosure +- Denial of service +- Elevation of privileges + +Similarly this threat model re-uses the same threat risk ratings. The risk +analysis is evaluated based on the environment being ``Server`` or ``Mobile``. +IOT is not evaluated as the EL3 SPMC is primarily meant for use in Client. + +Threat Assessment +================= + +The following threats are identified by applying STRIDE analysis on each diagram +element of the data flow diagram. + ++------------------------+----------------------------------------------------+ +| ID | 01 | ++========================+====================================================+ +| Threat | **An endpoint impersonates the sender | +| | FF-A ID in a direct request/response invocation.** | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF2, DF3, DF4 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMD, SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | SP state | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Spoofing | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------++------------------------+ +| Impact | Critical(5) | Critical(5) | ++------------------------+--------------------------++------------------------+ +| Likelihood | Critical(5) | Critical(5) | ++------------------------+--------------------------++------------------------+ +| Total Risk Rating | Critical(25) | Critical(25) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | SPMC must be able to correctly identify an | +| | endpoint and enforce checks to disallow spoofing. | ++------------------------+----------------------------------------------------+ +| Mitigations | Yes. | +| implemented? | The SPMC enforces checks in the direct message | +| | request/response interfaces such an endpoint cannot| +| | spoof the origin and destination worlds (e.g. a NWd| +| | originated message directed to the SWd cannot use a| +| | SWd ID as the sender ID). | +| | Also enforces check for direct response being sent | +| | only to originator of request. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 02 | ++========================+====================================================+ +| Threat | **An endpoint impersonates the receiver | +| | FF-A ID in a direct request/response invocation.** | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF2, DF3, DF4 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMD, SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | SP state | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Spoofing, Denial of Service | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------++------------------------+ +| Impact | Critical(5) | Critical(5) | ++------------------------+--------------------------++------------------------+ +| Likelihood | Critical(5) | Critical(5) | ++------------------------+--------------------------++------------------------+ +| Total Risk Rating | Critical(25) | Critical(25) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | Validate if endpoind has permission to send | +| | request to other endpoint by implementation | +| | defined means. | ++------------------------+----------------------------------------------------+ +| Mitigations | Platform specific. | +| implemented? | | +| | The guidance below is left for a system integrator | +| | to implement as necessary. | +| | | +| | Additionally a software component residing in the | +| | SPMC can be added for the purpose of direct | +| | request/response filtering. | +| | | +| | It can be configured with the list of known IDs | +| | and about which interaction can occur between one | +| | and another endpoint (e.g. which NWd endpoint ID | +| | sends a direct request to which SWd endpoint ID). | +| | | +| | This component checks the sender/receiver fields | +| | for a legitimate communication between endpoints. | +| | | +| | A similar component can exist in the OS kernel | +| | driver, or Hypervisor although it remains untrusted| +| | by the SPMD/SPMC. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 03 | ++========================+====================================================+ +| Threat | **Tampering with memory shared between an endpoint | +| | and the SPMC.** | +| | | +| | A malicious endpoint may attempt tampering with its| +| | RX/TX buffer contents while the SPMC is processing | +| | it (TOCTOU). | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF3, DF7 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | Shared memory, Information exchange | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Tampering | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------+-------------------------+ +| Impact | High (4) | High (4) | ++------------------------+--------------------------+-------------------------+ +| Likelihood | High (4) | High (4) | ++------------------------+--------------------------+-------------------------+ +| Total Risk Rating | High (16) | High (16) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | Validate all inputs, copy before use. | ++------------------------+----------------------------------------------------+ +| Mitigations | Yes. In context of FF-A v1.1 this is the case of | +| implemented? | sharing the RX/TX buffer pair and usage in the | +| | PARTITION_INFO_GET or memory sharing primitives. | +| | | +| | The SPMC copies the contents of the TX buffer | +| | to an internal temporary buffer before processing | +| | its contents. The SPMC implements hardened input | +| | validation on data transmitted through the TX | +| | buffer by an untrusted endpoint. | +| | | +| | The TF-A SPMC enforces | +| | checks on data transmitted through RX/TX buffers. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 04 | ++========================+====================================================+ +| Threat | **An endpoint may tamper with its own state or the | +| | state of another endpoint.** | +| | | +| | A malicious endpoint may attempt violating: | +| | | +| | - its own or another SP state by using an unusual | +| | combination (or out-of-order) FF-A function | +| | invocations. | +| | This can also be an endpoint emitting FF-A | +| | function invocations to another endpoint while | +| | the latter in not in a state to receive it (e.g. | +| | SP sends a direct request to the normal world | +| | early while the normal world is not booted yet). | +| | - the SPMC state itself by employing unexpected | +| | transitions in FF-A memory sharing, direct | +| | requests and responses, or handling of interrupts| +| | This can be led by random stimuli injection or | +| | fuzzing. | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMD, SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | SP state, SPMC state | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Tampering | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------+-------------------------+ +| Impact | High (4) | High (4) | ++------------------------+--------------------------+-------------------------+ +| Likelihood | Medium (3) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Total Risk Rating | High (12) | High (12) | ++------------------------+------------------+-----------------+---------------+ +| Mitigations | Follow guidelines in FF-A v1.1 specification on | +| | state transitions (run-time model). | ++------------------------+----------------------------------------------------+ +| Mitigations | Yes. The TF-A SPMC is hardened to follow this | +| implemented? | guidance. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 05 | ++========================+====================================================+ +| Threat | **Replay fragments of past communication between | +| | endpoints.** | +| | | +| | A malicious endpoint may replay a message exchange | +| | that occurred between two legitimate endpoints as | +| | a matter of triggering a malfunction or extracting | +| | secrets from the receiving endpoint. In particular | +| | the memory sharing operation with fragmented | +| | messages between an endpoint and the SPMC may be | +| | replayed by a malicious agent as a matter of | +| | getting access or gaining permissions to a memory | +| | region which does not belong to this agent. | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF2, DF3 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | Information exchange | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Repudiation | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------+-------------------------+ +| Impact | Medium (3) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Likelihood | High (4) | High (4) | ++------------------------+--------------------------+-------------------------+ +| Total Risk Rating | High (12) | High (12) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | Strict input validation and state tracking. | ++------------------------+----------------------------------------------------+ +| Mitigations | Platform specific. | +| implemented? | | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 06 | ++========================+====================================================+ +| Threat | **A malicious endpoint may attempt to extract data | +| | or state information by the use of invalid or | +| | incorrect input arguments.** | +| | | +| | Lack of input parameter validation or side effects | +| | of maliciously forged input parameters might affect| +| | the SPMC. | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMD, SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | SP secrets, SPMC secrets, SP state, SPMC state | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Information discolure | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------+-------------------------+ +| Impact | High (4) | High (4) | ++------------------------+--------------------------+-------------------------+ +| Likelihood | Medium (3) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Total Risk Rating | High (12) | High (12) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | SPMC must be prepared to receive incorrect input | +| | data from secure partitions and reject them | +| | appropriately. | +| | The use of software (canaries) or hardware | +| | hardening techniques (XN, WXN, pointer | +| | authentication) helps detecting and stopping | +| | an exploitation early. | ++------------------------+----------------------------------------------------+ +| Mitigations | Yes. The TF-A SPMC mitigates this threat by | +| implemented? | implementing stack protector, pointer | +| | authentication, XN, WXN, security hardening | +| | techniques. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 07 | ++========================+====================================================+ +| Threat | **A malicious endpoint may forge a direct message | +| | request such that it reveals the internal state of | +| | another endpoint through the direct message | +| | response.** | +| | | +| | The secure partition or SPMC replies to a partition| +| | message by a direct message response with | +| | information which may reveal its internal state | +| | (e.g. partition message response outside of | +| | allowed bounds). | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | SPMC or SP state | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Information discolure | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------+-------------------------+ +| Impact | Medium (3) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Likelihood | Low (2) | Low (2) | ++------------------------+--------------------------+-------------------------+ +| Total Risk Rating | Medium (6) | Medium (6) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | Follow FF-A specification about state transitions, | +| | run time model, do input validation. | ++------------------------+----------------------------------------------------+ +| Mitigations | Yes. For the specific case of direct requests | +| implemented? | targeting the SPMC, the latter is hardened to | +| | prevent its internal state or the state of an SP | +| | to be revealed through a direct message response. | +| | Further FF-A v1.1 guidance about run time models | +| | and partition states is followed. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 08 | ++========================+====================================================+ +| Threat | **Probing the FF-A communication between | +| | endpoints.** | +| | | +| | SPMC and SPs are typically loaded to external | +| | memory (protected by a TrustZone memory | +| | controller). A malicious agent may use non invasive| +| | methods to probe the external memory bus and | +| | extract the traffic between an SP and the SPMC or | +| | among SPs when shared buffers are held in external | +| | memory. | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF7 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | SP/SPMC state, SP/SPMC secrets | ++------------------------+----------------------------------------------------+ +| Threat Agent | Hardware attack | ++------------------------+----------------------------------------------------+ +| Threat Type | Information disclosure | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------+-------------------------+ +| Impact | Medium (3) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Likelihood | Low (2) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Total Risk Rating | Medium (6) | Medium (9) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | Implement DRAM protection techniques using | +| | hardware countermeasures at platform or chip level.| ++------------------------+--------------------------+-------------------------+ +| Mitigations | Platform specific. | +| implemented? | | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 09 | ++========================+====================================================+ +| Threat | **A malicious agent may attempt revealing the SPMC | +| | state or secrets by the use of software-based cache| +| | side-channel attack techniques.** | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF7 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | SP or SPMC state | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Information disclosure | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------+-------------------------+ +| Impact | Medium (3) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Likelihood | Low (2) | Low (2) | ++------------------------+--------------------------+-------------------------+ +| Total Risk Rating | Medium (6) | Medium (6) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | The SPMC may be hardened further with SW | +| | mitigations (e.g. speculation barriers) for the | +| | cases not covered in HW. Usage of hardened | +| | compilers and appropriate options, code inspection | +| | are recommended ways to mitigate Spectre types of | +| | attacks. | ++------------------------+----------------------------------------------------+ +| Mitigations | No. | +| implemented? | | ++------------------------+----------------------------------------------------+ + + ++------------------------+----------------------------------------------------+ +| ID | 10 | ++========================+====================================================+ +| Threat | **A malicious endpoint may attempt flooding the | +| | SPMC with requests targeting a service within an | +| | endpoint such that it denies another endpoint to | +| | access this service.** | +| | | +| | Similarly, the malicious endpoint may target a | +| | a service within an endpoint such that the latter | +| | is unable to request services from another | +| | endpoint. | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | SPMC state, Scheduling cycles | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Denial of service | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------+-------------------------+ +| Impact | Medium (3) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Likelihood | Medium (3) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Total Risk Rating | Medium (9) | Medium (9) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | Bounding the time for operations to complete can | +| | be achieved by the usage of a trusted watchdog. | +| | Other quality of service monitoring can be achieved| +| | in the SPMC such as counting a number of operations| +| | in a limited timeframe. | ++------------------------+----------------------------------------------------+ +| Mitigations | Platform specific. | +| implemented? | | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 11 | ++========================+====================================================+ +| Threat | **Denying a lender endpoint to make progress if | +| | borrower endpoint encountered a fatal exception. | +| | Denying a new sender endpoint to make progress | +| | if receiver encountered a fatal exception.** | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | Shared resources, Scheduling cycles. | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Denial of service | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------+-------------------------+ +| Impact | Medium (3) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Likelihood | Medium (3) | Medium (3) | ++------------------------+--------------------------+-------------------------+ +| Total Risk Rating | Medium (9) | Medium (9) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | SPMC must be able to detect fatal error in SP and | +| | take ownership of shared resources. It should | +| | be able to relinquish the access to shared memory | +| | regions to allow lender to proceed. | +| | SPMC must return ABORTED if new direct requests are| +| | targeted to SP which has had a fatal error. | ++------------------------+----------------------------------------------------+ +| Mitigations | Platform specific. | +| implemented? | | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 12 | ++========================+====================================================+ +| Threat | **A malicious endpoint may attempt to donate, | +| | share, lend, relinquish or reclaim unauthorized | +| | memory region.** | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | SPMC | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | SP secrets, SPMC secrets, SP state, SPMC state | ++------------------------+----------------------------------------------------+ +| Threat Agent | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| Threat Type | Elevation of Privilege | ++------------------------+--------------------------+-------------------------+ +| Application | Server | Mobile | ++------------------------+--------------------------+-------------------------+ +| Impact | High (4) | High (4) | ++------------------------+--------------------------+-------------------------+ +| Likelihood | High (4) | High (4) | ++------------------------+--------------------------+-------------------------+ +| Total Risk Rating | High (16) | High (16) | ++------------------------+--------------------------+-------------------------+ +| Mitigations | Follow FF-A specification guidelines | +| | on Memory management transactions. | ++------------------------+----------------------------------------------------+ +| Mitigations | Yes. The SPMC tracks ownership and access state | +| implemented? | for memory transactions appropriately, and | +| | validating the same for all operations. | +| | SPMC follows FF-A v1.1 | +| | guidance for memory transaction lifecycle. | ++------------------------+----------------------------------------------------+ + +--------------- + +*Copyright (c) 2022, Arm Limited. All rights reserved.* + +.. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest +.. _EL3 Secure Partition Manager: ../components/el3-spmc.html +.. _Generic TF-A threat model: ./threat_model.html#threat-analysis +.. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases diff --git a/docs/threat_model/threat_model_spm.rst b/docs/threat_model/threat_model_spm.rst index a7bc2a920..98dbf768d 100644 --- a/docs/threat_model/threat_model_spm.rst +++ b/docs/threat_model/threat_model_spm.rst @@ -258,7 +258,7 @@ element of the data flow diagram. | | invocations. | | | This can also be an endpoint emitting | | | FF-A function invocations to another endpoint while| -| | the latter in not in a state to receive it (e.g. a | +| | the latter is not in a state to receive it (e.g. a | | | SP sends a direct request to the normal world early| | | while the normal world is not booted yet). | | | - the SPMC state itself by employing unexpected | @@ -286,14 +286,12 @@ element of the data flow diagram. +------------------------+------------------+-----------------+---------------+ | ``Total Risk Rating`` | High (12) | High (12) | | +------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The SPMC may be vulnerable to invalid state | -| | transitions for itself or while handling an SP | -| | state. The FF-A v1.1 specification provides a | -| | guidance on those state transitions (run-time | -| | model). The TF-A SPMC will be hardened in future | -| | releases to follow this guidance. | -| | Additionally The TF-A SPMC mitigates the threat by | -| | runs of the Arm `FF-A ACS`_ compliance test suite. | +| ``Mitigations`` | The TF-A SPMC provides mitigation against such | +| | threat by following the guidance for partition | +| | runtime models as described in FF-A v1.1 EAC0 spec.| +| | The SPMC performs numerous checks in runtime to | +| | prevent illegal state transitions by adhering to | +| | the partition runtime model. | +------------------------+----------------------------------------------------+ +------------------------+----------------------------------------------------+ @@ -482,9 +480,11 @@ element of the data flow diagram. | | the SPMC, the latter is hardened to prevent | | | its internal state or the state of an SP to be | | | revealed through a direct message response. | -| | Further FF-A v1.1 guidance about run time models | -| | and partition states will be implemented in future | -| | TF-A SPMC releases. | +| | Further, SPMC performs numerous checks in runtime | +| | on the basis of the rules established by partition | +| | runtime models to stop any malicious attempts by | +| | an endpoint to extract internal state of another | +| | endpoint. | +------------------------+----------------------------------------------------+ +------------------------+----------------------------------------------------+ @@ -882,9 +882,278 @@ element of the data flow diagram. | | execution context. | +------------------------+----------------------------------------------------+ ---------------- ++------------------------+----------------------------------------------------+ +| ID | 19 | ++========================+====================================================+ +| ``Threat`` | **A malicious endpoint may abuse FFA_RUN call to | +| | resume or turn on other endpoint execution | +| | contexts, attempting to alter the internal state of| +| | SPMC and SPs, potentially leading to illegal state | +| | transitions and deadlocks.** | +| | An endpoint can call into another endpoint | +| | execution context using FFA_MSG_SEND_DIRECT_REQ | +| | ABI to create a call chain. A malicious endpoint | +| | could abuse this to form loops in a call chain that| +| | could lead to potential deadlocks. | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF4 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC, SPMD | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state, SP state, Scheduling cycles | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Tampering, Denial of Service | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Medium (9) | Medium (9) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC provides mitigation against such | +| | threats by following the guidance for partition | +| | runtime models as described in FF-A v1.1 EAC0 spec.| +| | The SPMC performs numerous checks in runtime to | +| | prevent illegal state transitions by adhering to | +| | the partition runtime model. Further, if the | +| | receiver endpoint is a predecessor of current | +| | endpoint in the present call chain, the SPMC denies| +| | any attempts to form loops by returning FFA_DENIED | +| | error code. Only the primary scheduler is allowed | +| | to turn on execution contexts of other partitions | +| | though SPMC does not have the ability to | +| | scrutinize its identity. Secure partitions have | +| | limited ability to resume execution contexts of | +| | other partitions based on the runtime model. Such | +| | attempts cannot compromise the integrity of the | +| | SPMC. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 20 | ++========================+====================================================+ +| ``Threat`` | **A malicious endpoint can perform a | +| | denial-of-service attack by using FFA_INTERRUPT | +| | call that could attempt to cause the system to | +| | crash or enter into an unknown state as no physical| +| | interrupt could be pending for it to be handled in | +| | the SPMC.** | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF5 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC, SPMD | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state, SP state, Scheduling cycles | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Tampering, Denial of Service | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Medium (9) | Medium (9) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC provides mitigation against such | +| | attack by detecting invocations from partitions | +| | and simply returning FFA_ERROR status interface. | +| | SPMC only allows SPMD to use FFA_INTERRUPT ABI to | +| | communicate a pending secure interrupt triggered | +| | while execution was in normal world. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 21 | ++========================+====================================================+ +| ``Threat`` | **A malicious secure endpoint might deactivate a | +| | (virtual) secure interrupt that was not originally | +| | signaled by SPMC, thereby attempting to alter the | +| | state of the SPMC and potentially lead to system | +| | crash.** | +| | SPMC maps the virtual interrupt ids to the physical| +| | interrupt ids to keep the implementation of virtual| +| | interrupt driver simple. | +| | Similarly, a malicious secure endpoint might invoke| +| | the deactivation ABI more than once for a secure | +| | interrupt. Moreover, a malicious secure endpoint | +| | might attempt to deactivate a (virtual) secure | +| | interrupt that was signaled to another endpoint | +| | execution context by the SPMC even before secure | +| | interrupt was handled. | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF5 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state, SP state | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Tampering | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Medium (9) | Medium (9) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | At initialization, the TF-A SPMC parses the | +| | partition manifests to find the target execution | +| | context responsible for handling the various | +| | secure physical interrupts. The TF-A SPMC provides | +| | mitigation against above mentioned threats by: | +| | | +| | - Keeping track of each pending virtual interrupt | +| | signaled to an execution context of a secure | +| | secure partition. | +| | - Denying any deactivation call from SP if there is| +| | no pending physical interrupt mapped to the | +| | given virtual interrupt. | +| | - Denying any deactivation call from SP if the | +| | virtual interrupt has not been signaled to the | +| | current execution context. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 22 | ++========================+====================================================+ +| ``Threat`` | **A malicious secure endpoint might not deactivate | +| | a virtual interrupt signaled to it by the SPMC but | +| | perform secure interrupt signal completion. This | +| | attempt to corrupt the internal state of the SPMC | +| | could lead to an unknown state and further lead to | +| | system crash.** | +| | Similarly, a malicious secure endpoint could | +| | deliberately not perform either interrupt | +| | deactivation or interrupt completion signal. Since,| +| | the SPMC can only process one secure interrupt at a| +| | time, this could choke the system where all | +| | interrupts are indefinitely masked which could | +| | potentially lead to system crash or reboot. | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF5 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state, SP state, Scheduling cycles | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Tampering, Denial of Service | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Medium (9) | Medium (9) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC does not provide mitigation against | +| | such threat. This is a limitation of the current | +| | SPMC implementation and needs to be handled in the | +| | future releases. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 23 | ++========================+====================================================+ +| ``Threat`` | **A malicious endpoint could leverage non-secure | +| | interrupts to preempt a secure endpoint, thereby | +| | attempting to render it unable to handle a secure | +| | virtual interrupt targetted for it. This could lead| +| | to priority inversion as secure virtual interrupts | +| | are kept pending while non-secure interrupts are | +| | handled by normal world VMs.** | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF3, DF5 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC, SPMD | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state, SP state, Scheduling cycles | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Denial of Service | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Medium (9) | Medium (9) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC alone does not provide mitigation | +| | against such threats. System integrators must take | +| | necessary high level design decisions that takes | +| | care of interrupt prioritization. The SPMC performs| +| | its role of enabling SPs to specify appropriate | +| | action towards non-secure interrupt with the help | +| | of partition manifest based on the guidance in the | +| | FF-A v1.1 EAC0 specification. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 24 | ++========================+====================================================+ +| ``Threat`` | **A secure endpoint depends on primary scheduler | +| | for CPU cycles. A malicious endpoint could delay | +| | the secure endpoint from being scheduled. Secure | +| | interrupts, if not handled timely, could compromise| +| | the state of SP and SPMC, thereby rendering the | +| | system unresponsive.** | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF3, DF5 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC, SPMD | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state, SP state, Scheduling cycles | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Denial of Service | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Medium (3) | Medium (3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Medium (9) | Medium (9) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC does not provide full mitigation | +| | against such threats. However, based on the | +| | guidance provided in the FF-A v1.1 EAC0 spec, SPMC | +| | provisions CPU cycles to run a secure endpoint | +| | execution context in SPMC schedule mode which | +| | cannot be preempted by a non-secure interrupt. | +| | This reduces the dependency on primary scheduler | +| | for cycle allocation. Moreover, all further | +| | interrupts are masked until pending secure virtual | +| | interrupt on current CPU is handled. This allows SP| +| | execution context to make progress even upon being | +| | interrupted. | ++------------------------+----------------------------------------------------+ + +-------------- -*Copyright (c) 2021, Arm Limited. All rights reserved.* +*Copyright (c) 2021-2022, Arm Limited. All rights reserved.* .. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest .. _Secure Partition Manager: ../components/secure-partition-manager.html diff --git a/drivers/amlogic/crypto/sha_dma.c b/drivers/amlogic/crypto/sha_dma.c index fceb1c0d3..5c16d49c7 100644 --- a/drivers/amlogic/crypto/sha_dma.c +++ b/drivers/amlogic/crypto/sha_dma.c @@ -8,6 +8,7 @@ #include <assert.h> #include <crypto/sha_dma.h> #include <lib/mmio.h> +#include <platform_def.h> #include "aml_private.h" diff --git a/drivers/arm/css/scp/css_pm_scmi.c b/drivers/arm/css/scp/css_pm_scmi.c index 5de2604cb..9fe8b3759 100644 --- a/drivers/arm/css/scp/css_pm_scmi.c +++ b/drivers/arm/css/scp/css_pm_scmi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,7 @@ #include <common/debug.h> #include <drivers/arm/css/css_scp.h> #include <drivers/arm/css/scmi.h> +#include <lib/mmio.h> #include <plat/arm/common/plat_arm.h> #include <plat/arm/css/common/css_pm.h> #include <plat/common/platform.h> @@ -286,15 +287,42 @@ int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level) return HW_OFF; } +/* + * Callback function to raise a SGI designated to trigger the CPU power down + * sequence on all the online secondary cores. + */ +static void css_raise_pwr_down_interrupt(u_register_t mpidr) +{ +#if CSS_SYSTEM_GRACEFUL_RESET + plat_ic_raise_el3_sgi(CSS_CPU_PWR_DOWN_REQ_INTR, mpidr); +#endif +} + void __dead2 css_scp_system_off(int state) { int ret; /* + * Before issuing the system power down command, set the trusted mailbox + * to 0. This will ensure that in the case of a warm/cold reset, the + * primary CPU executes from the cold boot sequence. + */ + mmio_write_64(PLAT_ARM_TRUSTED_MAILBOX_BASE, 0U); + + /* + * Send powerdown request to online secondary core(s) + */ + ret = psci_stop_other_cores(0, css_raise_pwr_down_interrupt); + if (ret != PSCI_E_SUCCESS) { + ERROR("Failed to powerdown secondary core(s)\n"); + } + + /* * Disable GIC CPU interface to prevent pending interrupt from waking * up the AP from WFI. */ plat_arm_gic_cpuif_disable(); + plat_arm_gic_redistif_off(); /* * Issue SCMI command. First issue a graceful @@ -309,6 +337,9 @@ void __dead2 css_scp_system_off(int state) state, ret); panic(); } + + /* Powerdown of primary core */ + psci_pwrdown_cpu(PLAT_MAX_PWR_LVL); wfi(); ERROR("CSS set power state: operation not handled.\n"); panic(); diff --git a/drivers/arm/ethosn/ethosn_smc.c b/drivers/arm/ethosn/ethosn_smc.c index 60364cdb2..915a0d87a 100644 --- a/drivers/arm/ethosn/ethosn_smc.c +++ b/drivers/arm/ethosn/ethosn_smc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,18 +12,17 @@ #include <drivers/arm/ethosn.h> #include <drivers/delay_timer.h> #include <lib/mmio.h> +#include <lib/utils_def.h> #include <plat/arm/common/fconf_ethosn_getter.h> /* - * Number of Arm Ethos-N NPU (NPU) cores available for a - * particular parent device + * Number of Arm(R) Ethos(TM)-N NPU (NPU) devices available */ -#define ETHOSN_NUM_CORES \ - FCONF_GET_PROPERTY(hw_config, ethosn_config, num_cores) +#define ETHOSN_NUM_DEVICES \ + FCONF_GET_PROPERTY(hw_config, ethosn_config, num_devices) -/* Address to an NPU core */ -#define ETHOSN_CORE_ADDR(core_idx) \ - FCONF_GET_PROPERTY(hw_config, ethosn_core_addr, core_idx) +#define ETHOSN_GET_DEVICE(dev_idx) \ + FCONF_GET_PROPERTY(hw_config, ethosn_device, dev_idx) /* NPU core sec registry address */ #define ETHOSN_CORE_SEC_REG(core_addr, reg_offset) \ @@ -40,9 +39,6 @@ #define SEC_SECCTLR_REG U(0x0010) #define SEC_SECCTLR_VAL U(0x3) -#define SEC_DEL_MMUSID_REG U(0x2008) -#define SEC_DEL_MMUSID_VAL U(0x3FFFF) - #define SEC_DEL_ADDR_EXT_REG U(0x201C) #define SEC_DEL_ADDR_EXT_VAL U(0x15) @@ -50,17 +46,63 @@ #define SEC_SYSCTRL0_SOFT_RESET U(3U << 29) #define SEC_SYSCTRL0_HARD_RESET U(1U << 31) -static bool ethosn_is_core_addr_valid(uintptr_t core_addr) +#define SEC_MMUSID_REG_BASE U(0x3008) +#define SEC_MMUSID_OFFSET U(0x1000) + +static bool ethosn_get_device_and_core(uintptr_t core_addr, + const struct ethosn_device_t **dev_match, + const struct ethosn_core_t **core_match) { - for (uint32_t core_idx = 0U; core_idx < ETHOSN_NUM_CORES; core_idx++) { - if (ETHOSN_CORE_ADDR(core_idx) == core_addr) { - return true; + uint32_t dev_idx; + uint32_t core_idx; + + for (dev_idx = 0U; dev_idx < ETHOSN_NUM_DEVICES; ++dev_idx) { + const struct ethosn_device_t *dev = ETHOSN_GET_DEVICE(dev_idx); + + for (core_idx = 0U; core_idx < dev->num_cores; ++core_idx) { + const struct ethosn_core_t *core = &(dev->cores[core_idx]); + + if (core->addr == core_addr) { + *dev_match = dev; + *core_match = core; + return true; + } } } + WARN("ETHOSN: Unknown core address given to SMC call.\n"); return false; } +static void ethosn_configure_smmu_streams(const struct ethosn_device_t *device, + const struct ethosn_core_t *core, + uint32_t asset_alloc_idx) +{ + const struct ethosn_main_allocator_t *main_alloc = + &(core->main_allocator); + const struct ethosn_asset_allocator_t *asset_alloc = + &(device->asset_allocators[asset_alloc_idx]); + const uint32_t streams[9] = { + main_alloc->firmware.stream_id, + main_alloc->working_data.stream_id, + asset_alloc->command_stream.stream_id, + 0U, /* Not used*/ + main_alloc->firmware.stream_id, + asset_alloc->weight_data.stream_id, + asset_alloc->buffer_data.stream_id, + asset_alloc->intermediate_data.stream_id, + asset_alloc->buffer_data.stream_id + }; + size_t i; + + for (i = 0U; i < ARRAY_SIZE(streams); ++i) { + const uintptr_t reg_addr = SEC_MMUSID_REG_BASE + + (SEC_MMUSID_OFFSET * i); + mmio_write_32(ETHOSN_CORE_SEC_REG(core->addr, reg_addr), + streams[i]); + } +} + static void ethosn_delegate_to_ns(uintptr_t core_addr) { mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SECCTLR_REG), @@ -69,9 +111,6 @@ static void ethosn_delegate_to_ns(uintptr_t core_addr) mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_REG), SEC_DEL_VAL); - mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_MMUSID_REG), - SEC_DEL_MMUSID_VAL); - mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_ADDR_EXT_REG), SEC_DEL_ADDR_EXT_VAL); } @@ -112,7 +151,7 @@ static bool ethosn_reset(uintptr_t core_addr, int hard_reset) uintptr_t ethosn_smc_handler(uint32_t smc_fid, u_register_t core_addr, - u_register_t x2, + u_register_t asset_alloc_idx, u_register_t x3, u_register_t x4, void *cookie, @@ -120,6 +159,8 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid, u_register_t flags) { int hard_reset = 0; + const struct ethosn_device_t *device = NULL; + const struct ethosn_core_t *core = NULL; const uint32_t fid = smc_fid & FUNCID_NUM_MASK; /* Only SiP fast calls are expected */ @@ -131,12 +172,14 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid, /* Truncate parameters to 32-bits for SMC32 */ if (GET_SMC_CC(smc_fid) == SMC_32) { core_addr &= 0xFFFFFFFF; - x2 &= 0xFFFFFFFF; + asset_alloc_idx &= 0xFFFFFFFF; x3 &= 0xFFFFFFFF; x4 &= 0xFFFFFFFF; } - if (!is_ethosn_fid(smc_fid)) { + if (!is_ethosn_fid(smc_fid) || + (fid < ETHOSN_FNUM_VERSION || fid > ETHOSN_FNUM_SOFT_RESET)) { + WARN("ETHOSN: Unknown SMC call: 0x%x\n", smc_fid); SMC_RET1(handle, SMC_UNK); } @@ -146,25 +189,41 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid, SMC_RET2(handle, ETHOSN_VERSION_MAJOR, ETHOSN_VERSION_MINOR); } - if (!ethosn_is_core_addr_valid(core_addr)) { - WARN("ETHOSN: Unknown core address given to SMC call.\n"); + if (!ethosn_get_device_and_core(core_addr, &device, &core)) { SMC_RET1(handle, ETHOSN_UNKNOWN_CORE_ADDRESS); } - /* Commands that require a valid addr */ + /* Commands that require a valid core address */ switch (fid) { case ETHOSN_FNUM_IS_SEC: - SMC_RET1(handle, ethosn_is_sec(core_addr)); + SMC_RET1(handle, ethosn_is_sec(core->addr)); + } + + if (!device->has_reserved_memory && + asset_alloc_idx >= device->num_allocators) { + WARN("ETHOSN: Unknown asset allocator index given to SMC call.\n"); + SMC_RET1(handle, ETHOSN_UNKNOWN_ALLOCATOR_IDX); + } + + /* Commands that require a valid device, core and asset allocator */ + switch (fid) { case ETHOSN_FNUM_HARD_RESET: hard_reset = 1; /* Fallthrough */ case ETHOSN_FNUM_SOFT_RESET: - if (!ethosn_reset(core_addr, hard_reset)) { + if (!ethosn_reset(core->addr, hard_reset)) { SMC_RET1(handle, ETHOSN_FAILURE); } - ethosn_delegate_to_ns(core_addr); + + if (!device->has_reserved_memory) { + ethosn_configure_smmu_streams(device, core, + asset_alloc_idx); + } + + ethosn_delegate_to_ns(core->addr); SMC_RET1(handle, ETHOSN_SUCCESS); default: + WARN("ETHOSN: Unimplemented SMC call: 0x%x\n", fid); SMC_RET1(handle, SMC_UNK); } } diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index 939d09718..1925a13ac 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -417,7 +418,7 @@ void gicv2_set_interrupt_type(unsigned int id, unsigned int type) * The proc_num parameter must be the linear index of the target PE in the * system. ******************************************************************************/ -void gicv2_raise_sgi(int sgi_num, int proc_num) +void gicv2_raise_sgi(int sgi_num, bool ns, int proc_num) { unsigned int sgir_val, target; @@ -437,7 +438,7 @@ void gicv2_raise_sgi(int sgi_num, int proc_num) target = driver_data->target_masks[proc_num]; assert(target != 0U); - sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num); + sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, ns, sgi_num); /* * Ensure that any shared variable updates depending on out of band diff --git a/drivers/arm/gic/v3/gic-x00.c b/drivers/arm/gic/v3/gic-x00.c index aaef485ff..83ef32f05 100644 --- a/drivers/arm/gic/v3/gic-x00.c +++ b/drivers/arm/gic/v3/gic-x00.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -16,6 +16,7 @@ #include <assert.h> #include <arch_helpers.h> +#include <common/debug.h> #include <drivers/arm/arm_gicv3_common.h> #include <drivers/arm/gicv3.h> @@ -42,6 +43,8 @@ #define PWRR_ON (0U << PWRR_RDPD_SHIFT) #define PWRR_OFF (1U << PWRR_RDPD_SHIFT) +static bool gic600_errata_wa_2384374 __unused; + #if GICV3_SUPPORT_GIC600 /* GIC-600/700 specific accessor functions */ @@ -170,3 +173,60 @@ void gicv3_rdistif_on(unsigned int proc_num) } #endif } + +#if GIC600_ERRATA_WA_2384374 +/******************************************************************************* + * Apply part 2 of workaround for errata-2384374 as per SDEN: + * https://developer.arm.com/documentation/sden892601/latest/ + ******************************************************************************/ +void gicv3_apply_errata_wa_2384374(uintptr_t gicr_base) +{ + if (gic600_errata_wa_2384374) { + uint32_t gicr_ctlr_val = gicr_read_ctlr(gicr_base); + + gicr_write_ctlr(gicr_base, gicr_ctlr_val | + (GICR_CTLR_DPG0_BIT | GICR_CTLR_DPG1NS_BIT | + GICR_CTLR_DPG1S_BIT)); + gicr_write_ctlr(gicr_base, gicr_ctlr_val & + ~(GICR_CTLR_DPG0_BIT | GICR_CTLR_DPG1NS_BIT | + GICR_CTLR_DPG1S_BIT)); + } +} +#endif /* GIC600_ERRATA_WA_2384374 */ + +void gicv3_check_erratas_applies(uintptr_t gicd_base) +{ + unsigned int gic_prod_id; + uint8_t gic_rev; + + assert(gicd_base != 0UL); + + gicv3_get_component_prodid_rev(gicd_base, &gic_prod_id, &gic_rev); + + /* + * This workaround applicable only to GIC600 and GIC600AE products with + * revision less than r1p6 and r0p2 respectively. + * As per GIC600/GIC600AE specification - + * r1p6 = 0x17 => GICD_IIDR[19:12] + * r0p2 = 0x04 => GICD_IIDR[19:12] + */ + if ((gic_prod_id == GIC_PRODUCT_ID_GIC600) || + (gic_prod_id == GIC_PRODUCT_ID_GIC600AE)) { + if (((gic_prod_id == GIC_PRODUCT_ID_GIC600) && + (gic_rev <= GIC_REV(GIC_VARIANT_R1, GIC_REV_P6))) || + ((gic_prod_id == GIC_PRODUCT_ID_GIC600AE) && + (gic_rev <= GIC_REV(GIC_VARIANT_R0, GIC_REV_P2)))) { +#if GIC600_ERRATA_WA_2384374 + gic600_errata_wa_2384374 = true; + VERBOSE("%s applies\n", + "GIC600/GIC600AE errata workaround 2384374"); +#else + WARN("%s missing\n", + "GIC600/GIC600AE errata workaround 2384374"); +#endif /* GIC600_ERRATA_WA_2384374 */ + } else { + VERBOSE("%s not applies\n", + "GIC600/GIC600AE errata workaround 2384374"); + } + } +} diff --git a/drivers/arm/gic/v3/gic600_multichip.c b/drivers/arm/gic/v3/gic600_multichip.c index 5f42ad994..e85dbc13d 100644 --- a/drivers/arm/gic/v3/gic600_multichip.c +++ b/drivers/arm/gic/v3/gic600_multichip.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -97,16 +98,28 @@ static void set_gicd_chipr_n(uintptr_t base, spi_id_max = GIC600_SPI_ID_MIN; } - spi_block_min = SPI_BLOCK_MIN_VALUE(spi_id_min); - spi_blocks = SPI_BLOCKS_VALUE(spi_id_min, spi_id_max); - switch ((gicd_iidr_val & IIDR_MODEL_MASK)) { case IIDR_MODEL_ARM_GIC_600: + spi_block_min = SPI_BLOCK_MIN_VALUE(spi_id_min); + spi_blocks = SPI_BLOCKS_VALUE(spi_id_min, spi_id_max); + chipr_n_val = GICD_CHIPR_VALUE_GIC_600(chip_addr, spi_block_min, spi_blocks); break; case IIDR_MODEL_ARM_GIC_700: + /* Calculate the SPI_ID_MIN value for ESPI */ + if (spi_id_min >= GIC700_ESPI_ID_MIN) { + spi_block_min = ESPI_BLOCK_MIN_VALUE(spi_id_min); + spi_block_min += SPI_BLOCKS_VALUE(GIC700_SPI_ID_MIN, + GIC700_SPI_ID_MAX); + } else { + spi_block_min = SPI_BLOCK_MIN_VALUE(spi_id_min); + } + + /* Calculate the total number of blocks */ + spi_blocks = SPI_BLOCKS_VALUE(spi_id_min, spi_id_max); + chipr_n_val = GICD_CHIPR_VALUE_GIC_700(chip_addr, spi_block_min, spi_blocks); @@ -202,13 +215,104 @@ static void gic600_multichip_validate_data( } /******************************************************************************* - * Intialize GIC-600 Multichip operation. + * Validates the GIC-700 Multichip data structure passed by the platform. + ******************************************************************************/ +static void gic700_multichip_validate_data( + struct gic600_multichip_data *multichip_data) +{ + unsigned int i, spi_id_min, spi_id_max, blocks_of_32; + unsigned int multichip_spi_blocks = 0U, multichip_espi_blocks = 0U; + + assert(multichip_data != NULL); + + if (multichip_data->chip_count > GIC600_MAX_MULTICHIP) { + ERROR("GIC-700 Multichip count (%u) should not exceed %u\n", + multichip_data->chip_count, GIC600_MAX_MULTICHIP); + panic(); + } + + for (i = 0U; i < multichip_data->chip_count; i++) { + spi_id_min = multichip_data->spi_ids[i][SPI_MIN_INDEX]; + spi_id_max = multichip_data->spi_ids[i][SPI_MAX_INDEX]; + + if ((spi_id_min == 0U) || (spi_id_max == 0U)) { + continue; + } + + /* MIN SPI ID check */ + if ((spi_id_min < GIC700_SPI_ID_MIN) || + ((spi_id_min >= GIC700_SPI_ID_MAX) && + (spi_id_min < GIC700_ESPI_ID_MIN))) { + ERROR("Invalid MIN SPI ID {%u} passed for " + "Chip %u\n", spi_id_min, i); + panic(); + } + + if ((spi_id_min > spi_id_max) || + ((spi_id_max - spi_id_min + 1) % 32 != 0)) { + ERROR("Unaligned SPI IDs {%u, %u} passed for " + "Chip %u\n", spi_id_min, + spi_id_max, i); + panic(); + } + + /* ESPI IDs range check */ + if ((spi_id_min >= GIC700_ESPI_ID_MIN) && + (spi_id_max > GIC700_ESPI_ID_MAX)) { + ERROR("Invalid ESPI IDs {%u, %u} passed for " + "Chip %u\n", spi_id_min, + spi_id_max, i); + panic(); + + } + + /* SPI IDs range check */ + if (((spi_id_min < GIC700_SPI_ID_MAX) && + (spi_id_max > GIC700_SPI_ID_MAX))) { + ERROR("Invalid SPI IDs {%u, %u} passed for " + "Chip %u\n", spi_id_min, + spi_id_max, i); + panic(); + } + + /* SPI IDs overlap check */ + if (spi_id_max < GIC700_SPI_ID_MAX) { + blocks_of_32 = BLOCKS_OF_32(spi_id_min, spi_id_max); + if ((multichip_spi_blocks & blocks_of_32) != 0) { + ERROR("SPI IDs of Chip %u overlapping\n", i); + panic(); + } + multichip_spi_blocks |= blocks_of_32; + } + + /* ESPI IDs overlap check */ + if (spi_id_max > GIC700_ESPI_ID_MIN) { + blocks_of_32 = BLOCKS_OF_32(spi_id_min - GIC700_ESPI_ID_MIN, + spi_id_max - GIC700_ESPI_ID_MIN); + if ((multichip_espi_blocks & blocks_of_32) != 0) { + ERROR("SPI IDs of Chip %u overlapping\n", i); + panic(); + } + multichip_espi_blocks |= blocks_of_32; + } + } +} + +/******************************************************************************* + * Intialize GIC-600 and GIC-700 Multichip operation. ******************************************************************************/ void gic600_multichip_init(struct gic600_multichip_data *multichip_data) { unsigned int i; + uint32_t gicd_iidr_val = gicd_read_iidr(multichip_data->rt_owner_base); - gic600_multichip_validate_data(multichip_data); + if ((gicd_iidr_val & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600) { + gic600_multichip_validate_data(multichip_data); + } + + if ((gicd_iidr_val & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_700) { + gic700_multichip_validate_data(multichip_data); + } /* * Ensure that G0/G1S/G1NS interrupts are disabled. This also ensures diff --git a/drivers/arm/gic/v3/gic600_multichip_private.h b/drivers/arm/gic/v3/gic600_multichip_private.h index 5d1ff6a19..414bd5b84 100644 --- a/drivers/arm/gic/v3/gic600_multichip_private.h +++ b/drivers/arm/gic/v3/gic600_multichip_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,6 +41,11 @@ #define GIC600_SPI_ID_MIN 32 #define GIC600_SPI_ID_MAX 960 +#define GIC700_SPI_ID_MIN 32 +#define GIC700_SPI_ID_MAX 991 +#define GIC700_ESPI_ID_MIN 4096 +#define GIC700_ESPI_ID_MAX 5119 + /* Number of retries for PUP update */ #define GICD_PUP_UPDATE_RETRIES 10000 @@ -53,6 +58,9 @@ #define SPI_BLOCKS_VALUE(spi_id_min, spi_id_max) \ (((spi_id_max) - (spi_id_min) + 1) / \ GIC600_SPI_ID_MIN) +#define ESPI_BLOCK_MIN_VALUE(spi_id_min) \ + (((spi_id_min) - GIC700_ESPI_ID_MIN + 1) / \ + GIC700_SPI_ID_MIN) #define GICD_CHIPR_VALUE_GIC_700(chip_addr, spi_block_min, spi_blocks) \ (((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \ ((spi_block_min) << GIC_700_SPI_BLOCK_MIN_SHIFT) | \ @@ -66,7 +74,8 @@ * Multichip data assertion macros */ /* Set bits from 0 to ((spi_id_max + 1) / 32) */ -#define SPI_BLOCKS_TILL_MAX(spi_id_max) ((1 << (((spi_id_max) + 1) >> 5)) - 1) +#define SPI_BLOCKS_TILL_MAX(spi_id_max) \ + ((1ULL << (((spi_id_max) + 1) >> 5)) - 1) /* Set bits from 0 to (spi_id_min / 32) */ #define SPI_BLOCKS_TILL_MIN(spi_id_min) ((1 << ((spi_id_min) >> 5)) - 1) /* Set bits from (spi_id_min / 32) to ((spi_id_max + 1) / 32) */ diff --git a/drivers/arm/gic/v3/gicv3.mk b/drivers/arm/gic/v3/gicv3.mk index d7e3536db..1d20ff3a3 100644 --- a/drivers/arm/gic/v3/gicv3.mk +++ b/drivers/arm/gic/v3/gicv3.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. # Copyright (c) 2021, NVIDIA Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -12,6 +12,7 @@ GICV3_IMPL_GIC600_MULTICHIP ?= 0 GICV3_OVERRIDE_DISTIF_PWR_OPS ?= 0 GIC_ENABLE_V4_EXTN ?= 0 GIC_EXT_INTID ?= 0 +GIC600_ERRATA_WA_2384374 ?= ${GICV3_SUPPORT_GIC600} GICV3_SOURCES += drivers/arm/gic/v3/gicv3_main.c \ drivers/arm/gic/v3/gicv3_helpers.c \ @@ -47,3 +48,7 @@ $(eval $(call add_define,GIC_ENABLE_V4_EXTN)) # Set support for extended PPI and SPI range $(eval $(call assert_boolean,GIC_EXT_INTID)) $(eval $(call add_define,GIC_EXT_INTID)) + +# Set errata workaround for GIC600/GIC600AE +$(eval $(call assert_boolean,GIC600_ERRATA_WA_2384374)) +$(eval $(call add_define,GIC600_ERRATA_WA_2384374)) diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c index 753d995d7..446d0addb 100644 --- a/drivers/arm/gic/v3/gicv3_helpers.c +++ b/drivers/arm/gic/v3/gicv3_helpers.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,8 @@ #include <common/interrupt_props.h> #include <drivers/arm/gic_common.h> +#include <platform_def.h> + #include "../common/gic_common_private.h" #include "gicv3_private.h" @@ -408,3 +410,34 @@ unsigned int gicv3_get_component_partnum(const uintptr_t gic_frame) return part_id; } + +/******************************************************************************* + * Helper function to return product ID and revision of GIC + * @gicd_base: base address of the GIC distributor + * @gic_prod_id: retrieved product id of GIC + * @gic_rev: retrieved revision of GIC + ******************************************************************************/ +void gicv3_get_component_prodid_rev(const uintptr_t gicd_base, + unsigned int *gic_prod_id, + uint8_t *gic_rev) +{ + unsigned int gicd_iidr; + uint8_t gic_variant; + + gicd_iidr = gicd_read_iidr(gicd_base); + *gic_prod_id = gicd_iidr >> IIDR_PRODUCT_ID_SHIFT; + *gic_prod_id &= IIDR_PRODUCT_ID_MASK; + + gic_variant = gicd_iidr >> IIDR_VARIANT_SHIFT; + gic_variant &= IIDR_VARIANT_MASK; + + *gic_rev = gicd_iidr >> IIDR_REV_SHIFT; + *gic_rev &= IIDR_REV_MASK; + + /* + * pack gic variant and gic_rev in 1 byte + * gic_rev = gic_variant[7:4] and gic_rev[0:3] + */ + *gic_rev = *gic_rev | gic_variant << 0x4; + +} diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 53a8fae3b..bc93f9315 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -169,6 +169,8 @@ void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) flush_dcache_range((uintptr_t)gicv3_driver_data, sizeof(*gicv3_driver_data)); #endif + gicv3_check_erratas_applies(plat_driver_data->gicd_base); + INFO("GICv%u with%s legacy support detected.\n", gic_version, (gicv2_compat == 0U) ? "" : "out"); INFO("ARM GICv%u driver initialized in EL3\n", gic_version); @@ -362,9 +364,17 @@ void gicv3_cpuif_disable(unsigned int proc_num) /* Add DSB to ensure visibility of System register writes */ dsb(); - /* Mark the connected core as asleep */ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; - assert(gicr_base != 0U); + assert(gicr_base != 0UL); + + /* + * dsb() already issued previously after clearing the CPU group + * enabled, apply below workaround to toggle the "DPG*" + * bits of GICR_CTLR register for unblocking event. + */ + gicv3_apply_errata_wa_2384374(gicr_base); + + /* Mark the connected core as asleep */ gicv3_rdistif_mark_core_asleep(gicr_base); } @@ -1085,11 +1095,12 @@ void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, } /******************************************************************************* - * This function raises the specified Secure Group 0 SGI. + * This function raises the specified SGI of the specified group. * * The target parameter must be a valid MPIDR in the system. ******************************************************************************/ -void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target) +void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group, + u_register_t target) { unsigned int tgt, aff3, aff2, aff1, aff0; uint64_t sgi_val; @@ -1119,7 +1130,22 @@ void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target) * interrupt trigger are observed before raising SGI. */ dsbishst(); - write_icc_sgi0r_el1(sgi_val); + + switch (group) { + case GICV3_G0: + write_icc_sgi0r_el1(sgi_val); + break; + case GICV3_G1NS: + write_icc_asgi1r(sgi_val); + break; + case GICV3_G1S: + write_icc_sgi1r(sgi_val); + break; + default: + assert(false); + break; + } + isb(); } diff --git a/drivers/arm/mhu/mhu_wrapper_v2_x.c b/drivers/arm/mhu/mhu_wrapper_v2_x.c index d8b7cfdab..60de1d38c 100644 --- a/drivers/arm/mhu/mhu_wrapper_v2_x.c +++ b/drivers/arm/mhu/mhu_wrapper_v2_x.c @@ -300,3 +300,13 @@ enum mhu_error_t mhu_receive_data(uint8_t *receive_buffer, size_t *size) return MHU_ERR_NONE; } + +size_t mhu_get_max_message_size(void) +{ + struct mhu_v2_x_dev_t *dev = &MHU1_SEH_DEV; + uint32_t num_channels = mhu_v2_x_get_num_channel_implemented(dev); + + assert(num_channels != 0); + + return num_channels * sizeof(uint32_t); +} diff --git a/drivers/arm/rss/rss_comms.c b/drivers/arm/rss/rss_comms.c index 28a492567..5e224e1e5 100644 --- a/drivers/arm/rss/rss_comms.c +++ b/drivers/arm/rss/rss_comms.c @@ -10,199 +10,144 @@ #include <common/debug.h> #include <drivers/arm/mhu.h> #include <drivers/arm/rss_comms.h> -#include <initial_attestation.h> #include <psa/client.h> +#include <rss_comms_protocol.h> -#include <platform_def.h> - -#define TYPE_OFFSET U(16) -#define TYPE_MASK (0xFFFFUL << TYPE_OFFSET) -#define IN_LEN_OFFSET U(8) -#define IN_LEN_MASK (0xFFUL << IN_LEN_OFFSET) -#define OUT_LEN_OFFSET U(0) -#define OUT_LEN_MASK (0xFFUL << OUT_LEN_OFFSET) - -#define PARAM_PACK(type, in_len, out_len) \ - (((((uint32_t)type) << TYPE_OFFSET) & TYPE_MASK) | \ - ((((uint32_t)in_len) << IN_LEN_OFFSET) & IN_LEN_MASK) | \ - ((((uint32_t)out_len) << OUT_LEN_OFFSET) & OUT_LEN_MASK)) - -#define PARAM_UNPACK_IN_LEN(ctrl_param) \ - ((size_t)(((ctrl_param) & IN_LEN_MASK) >> IN_LEN_OFFSET)) - -/* Message types */ -struct __packed packed_psa_call_t { - uint8_t protocol_ver; - uint8_t seq_num; - uint16_t client_id; - psa_handle_t handle; - uint32_t ctrl_param; /* type, in_len, out_len */ - uint16_t io_size[4]; -}; - -struct __packed packed_psa_reply_t { - uint8_t protocol_ver; - uint8_t seq_num; - uint16_t client_id; - int32_t return_val; - uint16_t out_size[4]; -}; - -/* - * In the current implementation the RoT Service request that requires the - * biggest message buffer is the RSS_ATTEST_GET_TOKEN. The maximum required - * buffer size is calculated based on the platform-specific needs of - * this request. +/* Union as message space and reply space are never used at the same time, and this saves space as + * we can overlap them. */ -#define MAX_REQUEST_PAYLOAD_SIZE (PSA_INITIAL_ATTEST_CHALLENGE_SIZE_64 \ - + PLAT_ATTEST_TOKEN_MAX_SIZE) - -/* Buffer to store the messages to be sent/received. */ -static uint8_t message_buf[MAX_REQUEST_PAYLOAD_SIZE] __aligned(4); +union __packed __attribute__((aligned(4))) rss_comms_io_buffer_t { + struct serialized_rss_comms_msg_t msg; + struct serialized_rss_comms_reply_t reply; +}; -static int32_t pack_params(const psa_invec *invecs, - size_t in_len, - uint8_t *buf, - size_t *buf_len) +static uint8_t select_protocol_version(const psa_invec *in_vec, size_t in_len, + const psa_outvec *out_vec, size_t out_len) { - uint32_t i; - size_t payload_size = 0U; + size_t comms_mhu_msg_size; + size_t comms_embed_msg_min_size; + size_t comms_embed_reply_min_size; + size_t in_size_total = 0; + size_t out_size_total = 0; + size_t i; for (i = 0U; i < in_len; ++i) { - if (invecs[i].len > *buf_len - payload_size) { - return -1; - } - memcpy(buf + payload_size, invecs[i].base, invecs[i].len); - payload_size += invecs[i].len; - } - - *buf_len = payload_size; - return 0; -} - -static int serialise_message(const struct packed_psa_call_t *msg, - const psa_invec *invecs, - uint8_t *payload_buf, - size_t *payload_len) -{ - size_t message_len = 0U; - size_t len; - - /* Copy the message header into the payload buffer. */ - len = sizeof(*msg); - if (len > *payload_len) { - ERROR("[RSS-COMMS] Message buffer too small.\n"); - return -1; + in_size_total += in_vec[i].len; } - memcpy(payload_buf, (const void *)msg, len); - message_len += len; - - /* The input data will follow the message header in the payload buffer. */ - len = *payload_len - message_len; - if (pack_params(invecs, PARAM_UNPACK_IN_LEN(msg->ctrl_param), - payload_buf + message_len, &len) != 0) { - ERROR("[RSS-COMMS] Message buffer too small.\n"); - return -1; - } - message_len += len; - - *payload_len = message_len; - return 0; -} - -static void unpack_params(const uint8_t *buf, - psa_outvec *outvecs, - size_t out_len) -{ - size_t i; - for (i = 0U; i < out_len; ++i) { - memcpy(outvecs[i].base, buf, outvecs[i].len); - buf += outvecs[i].len; + out_size_total += out_vec[i].len; } -} - -static void deserialise_reply(struct packed_psa_reply_t *reply, - psa_outvec *outvecs, - size_t outlen, - const uint8_t *message, - size_t message_len) -{ - uint32_t i; - memcpy(reply, message, sizeof(*reply)); - - /* Outvecs */ - for (i = 0U; i < outlen; ++i) { - outvecs[i].len = reply->out_size[i]; + comms_mhu_msg_size = mhu_get_max_message_size(); + + comms_embed_msg_min_size = sizeof(struct serialized_rss_comms_header_t) + + sizeof(struct rss_embed_msg_t) - + PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE; + + comms_embed_reply_min_size = sizeof(struct serialized_rss_comms_header_t) + + sizeof(struct rss_embed_reply_t) - + PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE; + + /* Use embed if we can pack into one message and reply, else use + * pointer_access. The underlying MHU transport protocol uses a + * single uint32_t to track the length, so the amount of data that + * can be in a message is 4 bytes less than mhu_get_max_message_size + * reports. + * + * TODO tune this with real performance numbers, it's possible a + * pointer_access message is less performant than multiple embed + * messages due to ATU configuration costs to allow access to the + * pointers. + */ + if ((comms_embed_msg_min_size + in_size_total > comms_mhu_msg_size - sizeof(uint32_t)) + || (comms_embed_reply_min_size + out_size_total > comms_mhu_msg_size) - sizeof(uint32_t)) { + return RSS_COMMS_PROTOCOL_POINTER_ACCESS; + } else { + return RSS_COMMS_PROTOCOL_EMBED; } - - unpack_params(message + sizeof(*reply), outvecs, outlen); } -psa_status_t psa_call(psa_handle_t handle, int32_t type, - const psa_invec *in_vec, size_t in_len, +psa_status_t psa_call(psa_handle_t handle, int32_t type, const psa_invec *in_vec, size_t in_len, psa_outvec *out_vec, size_t out_len) { + /* Declared statically to avoid using huge amounts of stack space. Maybe revisit if + * functions not being reentrant becomes a problem. + */ + static union rss_comms_io_buffer_t io_buf; enum mhu_error_t err; - static uint32_t seq_num = 1U; - struct packed_psa_call_t msg = { - .protocol_ver = 0U, - .seq_num = seq_num, - /* No need to distinguish callers (currently concurrent calls are not supported). */ - .client_id = 1U, - .handle = handle, - .ctrl_param = PARAM_PACK(type, in_len, out_len), - }; - - struct packed_psa_reply_t reply = {0}; - size_t message_size; - uint32_t i; - - /* Fill msg iovec lengths */ - for (i = 0U; i < in_len; ++i) { - msg.io_size[i] = in_vec[i].len; + psa_status_t status; + static uint8_t seq_num = 1U; + size_t msg_size; + size_t reply_size = sizeof(io_buf.reply); + psa_status_t return_val; + size_t idx; + + if (type > INT16_MAX || type < INT16_MIN || in_len > PSA_MAX_IOVEC + || out_len > PSA_MAX_IOVEC) { + return PSA_ERROR_INVALID_ARGUMENT; } - for (i = 0U; i < out_len; ++i) { - msg.io_size[in_len + i] = out_vec[i].len; + + io_buf.msg.header.seq_num = seq_num, + /* No need to distinguish callers (currently concurrent calls are not supported). */ + io_buf.msg.header.client_id = 1U, + io_buf.msg.header.protocol_ver = select_protocol_version(in_vec, in_len, out_vec, out_len); + + status = rss_protocol_serialize_msg(handle, type, in_vec, in_len, out_vec, + out_len, &io_buf.msg, &msg_size); + if (status != PSA_SUCCESS) { + return status; } - message_size = sizeof(message_buf); - if (serialise_message(&msg, in_vec, message_buf, &message_size)) { - /* Local buffer is probably too small. */ - return PSA_ERROR_INSUFFICIENT_MEMORY; + VERBOSE("[RSS-COMMS] Sending message\n"); + VERBOSE("protocol_ver=%u\n", io_buf.msg.header.protocol_ver); + VERBOSE("seq_num=%u\n", io_buf.msg.header.seq_num); + VERBOSE("client_id=%u\n", io_buf.msg.header.client_id); + for (idx = 0; idx < in_len; idx++) { + VERBOSE("in_vec[%lu].len=%lu\n", idx, in_vec[idx].len); + VERBOSE("in_vec[%lu].buf=%p\n", idx, (void *)in_vec[idx].base); } - err = mhu_send_data(message_buf, message_size); + err = mhu_send_data((uint8_t *)&io_buf.msg, msg_size); if (err != MHU_ERR_NONE) { return PSA_ERROR_COMMUNICATION_FAILURE; } - message_size = sizeof(message_buf); #if DEBUG /* * Poisoning the message buffer (with a known pattern). * Helps in detecting hypothetical RSS communication bugs. */ - memset(message_buf, 0xA5, message_size); + memset(&io_buf.msg, 0xA5, msg_size); #endif - err = mhu_receive_data(message_buf, &message_size); + + err = mhu_receive_data((uint8_t *)&io_buf.reply, &reply_size); if (err != MHU_ERR_NONE) { return PSA_ERROR_COMMUNICATION_FAILURE; } - deserialise_reply(&reply, out_vec, out_len, message_buf, message_size); + VERBOSE("[RSS-COMMS] Received reply\n"); + VERBOSE("protocol_ver=%u\n", io_buf.reply.header.protocol_ver); + VERBOSE("seq_num=%u\n", io_buf.reply.header.seq_num); + VERBOSE("client_id=%u\n", io_buf.reply.header.client_id); + + status = rss_protocol_deserialize_reply(out_vec, out_len, &return_val, + &io_buf.reply, reply_size); + if (status != PSA_SUCCESS) { + return status; + } - seq_num++; + VERBOSE("return_val=%d\n", return_val); + for (idx = 0U; idx < out_len; idx++) { + VERBOSE("out_vec[%lu].len=%lu\n", idx, out_vec[idx].len); + VERBOSE("out_vec[%lu].buf=%p\n", idx, (void *)out_vec[idx].base); + } - VERBOSE("[RSS-COMMS] Received reply\n"); - VERBOSE("protocol_ver=%d\n", reply.protocol_ver); - VERBOSE("seq_num=%d\n", reply.seq_num); - VERBOSE("client_id=%d\n", reply.client_id); - VERBOSE("return_val=%d\n", reply.return_val); - VERBOSE("out_size[0]=%d\n", reply.out_size[0]); + /* Clear the MHU message buffer to remove assets from memory */ + memset(&io_buf, 0x0, sizeof(io_buf)); + + seq_num++; - return reply.return_val; + return return_val; } int rss_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base) diff --git a/drivers/arm/rss/rss_comms.mk b/drivers/arm/rss/rss_comms.mk new file mode 100644 index 000000000..c1c994b64 --- /dev/null +++ b/drivers/arm/rss/rss_comms.mk @@ -0,0 +1,22 @@ +# +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +$(warning "RSS driver is an experimental feature") + +RSS_COMMS_SOURCES := $(addprefix drivers/arm/rss/, \ + rss_comms.c \ + rss_comms_protocol.c \ + rss_comms_protocol_embed.c \ + rss_comms_protocol_pointer_access.c \ + ) + +RSS_COMMS_SOURCES += $(addprefix drivers/arm/mhu/, \ + mhu_v2_x.c \ + mhu_wrapper_v2_x.c \ + ) + +PLAT_INCLUDES += -Idrivers/arm/rss \ + -Idrivers/arm/mhu diff --git a/drivers/arm/rss/rss_comms_protocol.c b/drivers/arm/rss/rss_comms_protocol.c new file mode 100644 index 000000000..a1b1b58cb --- /dev/null +++ b/drivers/arm/rss/rss_comms_protocol.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include <assert.h> + +#include <common/debug.h> +#include "rss_comms_protocol.h" + +psa_status_t rss_protocol_serialize_msg(psa_handle_t handle, + int16_t type, + const psa_invec *in_vec, + uint8_t in_len, + const psa_outvec *out_vec, + uint8_t out_len, + struct serialized_rss_comms_msg_t *msg, + size_t *msg_len) +{ + psa_status_t status; + + assert(msg != NULL); + assert(msg_len != NULL); + assert(in_vec != NULL); + + switch (msg->header.protocol_ver) { + case RSS_COMMS_PROTOCOL_EMBED: + status = rss_protocol_embed_serialize_msg(handle, type, in_vec, in_len, out_vec, + out_len, &msg->msg.embed, msg_len); + if (status != PSA_SUCCESS) { + return status; + } + break; + case RSS_COMMS_PROTOCOL_POINTER_ACCESS: + status = rss_protocol_pointer_access_serialize_msg(handle, type, in_vec, in_len, + out_vec, out_len, + &msg->msg.pointer_access, + msg_len); + if (status != PSA_SUCCESS) { + return status; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + *msg_len += sizeof(struct serialized_rss_comms_header_t); + + return PSA_SUCCESS; +} + +psa_status_t rss_protocol_deserialize_reply(psa_outvec *out_vec, + uint8_t out_len, + psa_status_t *return_val, + const struct serialized_rss_comms_reply_t *reply, + size_t reply_size) +{ + assert(reply != NULL); + assert(return_val != NULL); + + switch (reply->header.protocol_ver) { + case RSS_COMMS_PROTOCOL_EMBED: + return rss_protocol_embed_deserialize_reply(out_vec, out_len, return_val, + &reply->reply.embed, reply_size); + case RSS_COMMS_PROTOCOL_POINTER_ACCESS: + return rss_protocol_pointer_access_deserialize_reply(out_vec, out_len, return_val, + &reply->reply.pointer_access, + reply_size); + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; +} diff --git a/drivers/arm/rss/rss_comms_protocol.h b/drivers/arm/rss/rss_comms_protocol.h new file mode 100644 index 000000000..9a38057cd --- /dev/null +++ b/drivers/arm/rss/rss_comms_protocol.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __RSS_COMMS_PROTOCOL_H__ +#define __RSS_COMMS_PROTOCOL_H__ + +#include <cdefs.h> +#include <stdint.h> + +#include <psa/client.h> +#include "rss_comms_protocol_embed.h" +#include "rss_comms_protocol_pointer_access.h" + +enum rss_comms_protocol_version_t { + RSS_COMMS_PROTOCOL_EMBED = 0, + RSS_COMMS_PROTOCOL_POINTER_ACCESS = 1, +}; + +struct __packed serialized_rss_comms_header_t { + uint8_t protocol_ver; + uint8_t seq_num; + uint16_t client_id; +}; + +/* MHU message passed from Host to RSS to deliver a PSA client call */ +struct __packed serialized_rss_comms_msg_t { + struct serialized_rss_comms_header_t header; + union __packed { + struct rss_embed_msg_t embed; + struct rss_pointer_access_msg_t pointer_access; + } msg; +}; + +/* MHU reply message to hold the PSA client reply result returned by RSS */ +struct __packed serialized_rss_comms_reply_t { + struct serialized_rss_comms_header_t header; + union __packed { + struct rss_embed_reply_t embed; + struct rss_pointer_access_reply_t pointer_access; + } reply; +}; + +/* in_len and out_len are uint8_ts, therefore if there are more than 255 iovecs + * an error may occur. + */ +CASSERT(PSA_MAX_IOVEC <= UINT8_MAX, assert_rss_comms_max_iovec_too_large); + +psa_status_t rss_protocol_serialize_msg(psa_handle_t handle, + int16_t type, + const psa_invec *in_vec, + uint8_t in_len, + const psa_outvec *out_vec, + uint8_t out_len, + struct serialized_rss_comms_msg_t *msg, + size_t *msg_len); + +psa_status_t rss_protocol_deserialize_reply(psa_outvec *out_vec, + uint8_t out_len, + psa_status_t *return_val, + const struct serialized_rss_comms_reply_t *reply, + size_t reply_size); + +#endif /* __RSS_COMMS_PROTOCOL_H__ */ diff --git a/drivers/arm/rss/rss_comms_protocol_embed.c b/drivers/arm/rss/rss_comms_protocol_embed.c new file mode 100644 index 000000000..801b7ccbb --- /dev/null +++ b/drivers/arm/rss/rss_comms_protocol_embed.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <assert.h> +#include <string.h> + +#include <common/debug.h> +#include "rss_comms_protocol_embed.h" + +#define TYPE_OFFSET (16U) +#define TYPE_MASK (0xFFFFUL << TYPE_OFFSET) +#define IN_LEN_OFFSET (8U) +#define IN_LEN_MASK (0xFFUL << IN_LEN_OFFSET) +#define OUT_LEN_OFFSET (0U) +#define OUT_LEN_MASK (0xFFUL << OUT_LEN_OFFSET) + +#define PARAM_PACK(type, in_len, out_len) \ + (((((uint32_t)type) << TYPE_OFFSET) & TYPE_MASK) | \ + ((((uint32_t)in_len) << IN_LEN_OFFSET) & IN_LEN_MASK) | \ + ((((uint32_t)out_len) << OUT_LEN_OFFSET) & OUT_LEN_MASK)) + +psa_status_t rss_protocol_embed_serialize_msg(psa_handle_t handle, + int16_t type, + const psa_invec *in_vec, + uint8_t in_len, + const psa_outvec *out_vec, + uint8_t out_len, + struct rss_embed_msg_t *msg, + size_t *msg_len) +{ + uint32_t payload_size = 0; + uint32_t i; + + assert(msg != NULL); + assert(msg_len != NULL); + assert(in_vec != NULL); + + msg->ctrl_param = PARAM_PACK(type, in_len, out_len); + msg->handle = handle; + + /* Fill msg iovec lengths */ + for (i = 0U; i < in_len; ++i) { + msg->io_size[i] = in_vec[i].len; + } + for (i = 0U; i < out_len; ++i) { + msg->io_size[in_len + i] = out_vec[i].len; + } + + for (i = 0U; i < in_len; ++i) { + if (in_vec[i].len > sizeof(msg->trailer) - payload_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(msg->trailer + payload_size, in_vec[i].base, in_vec[i].len); + payload_size += in_vec[i].len; + } + + /* Output the actual size of the message, to optimize sending */ + *msg_len = sizeof(*msg) - sizeof(msg->trailer) + payload_size; + + return PSA_SUCCESS; +} + +psa_status_t rss_protocol_embed_deserialize_reply(psa_outvec *out_vec, + uint8_t out_len, + psa_status_t *return_val, + const struct rss_embed_reply_t *reply, + size_t reply_size) +{ + uint32_t payload_offset = 0; + uint32_t i; + + assert(reply != NULL); + assert(return_val != NULL); + + for (i = 0U; i < out_len; ++i) { + if (sizeof(reply) - sizeof(reply->trailer) + payload_offset > reply_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memcpy(out_vec[i].base, reply->trailer + payload_offset, out_vec[i].len); + payload_offset += out_vec[i].len; + } + + *return_val = reply->return_val; + + return PSA_SUCCESS; +} diff --git a/drivers/arm/rss/rss_comms_protocol_embed.h b/drivers/arm/rss/rss_comms_protocol_embed.h new file mode 100644 index 000000000..c81c7954e --- /dev/null +++ b/drivers/arm/rss/rss_comms_protocol_embed.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __RSS_COMMS_PROTOCOL_EMBED_H__ +#define __RSS_COMMS_PROTOCOL_EMBED_H__ + +#include <cdefs.h> + +#include <psa/client.h> + +#include <platform_def.h> + + + +struct __packed rss_embed_msg_t { + psa_handle_t handle; + uint32_t ctrl_param; /* type, in_len, out_len */ + uint16_t io_size[PSA_MAX_IOVEC]; + uint8_t trailer[PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE]; +}; + +struct __packed rss_embed_reply_t { + int32_t return_val; + uint16_t out_size[PSA_MAX_IOVEC]; + uint8_t trailer[PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE]; +}; + +psa_status_t rss_protocol_embed_serialize_msg(psa_handle_t handle, + int16_t type, + const psa_invec *in_vec, + uint8_t in_len, + const psa_outvec *out_vec, + uint8_t out_len, + struct rss_embed_msg_t *msg, + size_t *msg_len); + +psa_status_t rss_protocol_embed_deserialize_reply(psa_outvec *out_vec, + uint8_t out_len, + psa_status_t *return_val, + const struct rss_embed_reply_t *reply, + size_t reply_size); + +#endif /* __RSS_COMMS_PROTOCOL_EMBED_H__ */ diff --git a/drivers/arm/rss/rss_comms_protocol_pointer_access.c b/drivers/arm/rss/rss_comms_protocol_pointer_access.c new file mode 100644 index 000000000..5007b9def --- /dev/null +++ b/drivers/arm/rss/rss_comms_protocol_pointer_access.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include <assert.h> + +#include "rss_comms_protocol_pointer_access.h" + +#define TYPE_OFFSET (16U) +#define TYPE_MASK (0xFFFFUL << TYPE_OFFSET) +#define IN_LEN_OFFSET (8U) +#define IN_LEN_MASK (0xFFUL << IN_LEN_OFFSET) +#define OUT_LEN_OFFSET (0U) +#define OUT_LEN_MASK (0xFFUL << OUT_LEN_OFFSET) + +#define PARAM_PACK(type, in_len, out_len) \ + (((((uint32_t)type) << TYPE_OFFSET) & TYPE_MASK) | \ + ((((uint32_t)in_len) << IN_LEN_OFFSET) & IN_LEN_MASK) | \ + ((((uint32_t)out_len) << OUT_LEN_OFFSET) & OUT_LEN_MASK)) + +psa_status_t rss_protocol_pointer_access_serialize_msg(psa_handle_t handle, + int16_t type, + const psa_invec *in_vec, + uint8_t in_len, + const psa_outvec *out_vec, + uint8_t out_len, + struct rss_pointer_access_msg_t *msg, + size_t *msg_len) +{ + unsigned int i; + + assert(msg != NULL); + assert(msg_len != NULL); + assert(in_vec != NULL); + + msg->ctrl_param = PARAM_PACK(type, in_len, out_len); + msg->handle = handle; + + /* Fill msg iovec lengths */ + for (i = 0U; i < in_len; ++i) { + msg->io_sizes[i] = in_vec[i].len; + msg->host_ptrs[i] = (uint64_t)in_vec[i].base; + } + for (i = 0U; i < out_len; ++i) { + msg->io_sizes[in_len + i] = out_vec[i].len; + msg->host_ptrs[in_len + i] = (uint64_t)out_vec[i].base; + } + + *msg_len = sizeof(*msg); + + return PSA_SUCCESS; +} + +psa_status_t rss_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec, + uint8_t out_len, + psa_status_t *return_val, + const struct rss_pointer_access_reply_t *reply, + size_t reply_size) +{ + unsigned int i; + + assert(reply != NULL); + assert(return_val != NULL); + + for (i = 0U; i < out_len; ++i) { + out_vec[i].len = reply->out_sizes[i]; + } + + *return_val = reply->return_val; + + return PSA_SUCCESS; +} diff --git a/drivers/arm/rss/rss_comms_protocol_pointer_access.h b/drivers/arm/rss/rss_comms_protocol_pointer_access.h new file mode 100644 index 000000000..a4d054bd2 --- /dev/null +++ b/drivers/arm/rss/rss_comms_protocol_pointer_access.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__ +#define __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__ + +#include <cdefs.h> + +#include <psa/client.h> + +struct __packed rss_pointer_access_msg_t { + psa_handle_t handle; + uint32_t ctrl_param; + uint32_t io_sizes[PSA_MAX_IOVEC]; + uint64_t host_ptrs[PSA_MAX_IOVEC]; +}; + +struct __packed rss_pointer_access_reply_t { + int32_t return_val; + uint32_t out_sizes[PSA_MAX_IOVEC]; +}; + +psa_status_t rss_protocol_pointer_access_serialize_msg(psa_handle_t handle, + int16_t type, + const psa_invec *in_vec, + uint8_t in_len, + const psa_outvec *out_vec, + uint8_t out_len, + struct rss_pointer_access_msg_t *msg, + size_t *msg_len); + +psa_status_t rss_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec, + uint8_t out_len, + psa_status_t *return_val, + const struct rss_pointer_access_reply_t *reply, + size_t reply_size); + +#endif /* __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__ */ diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c index a99a2c70c..fa9509a0c 100644 --- a/drivers/auth/auth_mod.c +++ b/drivers/auth/auth_mod.c @@ -31,6 +31,7 @@ } while (0) #pragma weak plat_set_nv_ctr2 +#pragma weak plat_convert_pk static int cmp_auth_param_type_desc(const auth_param_type_desc_t *a, @@ -202,6 +203,10 @@ static int auth_signature(const auth_method_param_sig_t *param, NOTICE("ROTPK is not deployed on platform. " "Skipping ROTPK verification.\n"); } else { + /* platform may store the hash of a prefixed, suffixed or modified pk */ + rc = plat_convert_pk(pk_ptr, pk_len, &pk_ptr, &pk_len); + return_if_error(rc); + /* Ask the crypto-module to verify the key hash */ rc = crypto_mod_verify_hash(pk_ptr, pk_len, pk_hash_ptr, pk_hash_len); @@ -301,6 +306,15 @@ int plat_set_nv_ctr2(void *cookie, const auth_img_desc_t *img_desc __unused, return plat_set_nv_ctr(cookie, nv_ctr); } +int plat_convert_pk(void *full_pk_ptr, unsigned int full_pk_len, + void **hashed_pk_ptr, unsigned int *hashed_pk_len) +{ + *hashed_pk_ptr = full_pk_ptr; + *hashed_pk_len = full_pk_len; + + return 0; +} + /* * Return the parent id in the output parameter '*parent_id' * diff --git a/drivers/auth/cca/cot.c b/drivers/auth/cca/cot.c new file mode 100644 index 000000000..d3f3087b9 --- /dev/null +++ b/drivers/auth/cca/cot.c @@ -0,0 +1,675 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stddef.h> + +#include <drivers/auth/auth_mod.h> +#include MBEDTLS_CONFIG_FILE +#include <tools_share/cca_oid.h> + +#include <platform_def.h> + +/* + * Allocate static buffers to store the authentication parameters extracted from + * the certificates. + */ +static unsigned char fw_config_hash_buf[HASH_DER_LEN]; +static unsigned char tb_fw_hash_buf[HASH_DER_LEN]; +static unsigned char tb_fw_config_hash_buf[HASH_DER_LEN]; +static unsigned char hw_config_hash_buf[HASH_DER_LEN]; +static unsigned char soc_fw_hash_buf[HASH_DER_LEN]; +static unsigned char soc_fw_config_hash_buf[HASH_DER_LEN]; +static unsigned char rmm_hash_buf[HASH_DER_LEN]; + +#ifdef IMAGE_BL2 +static unsigned char nt_world_bl_hash_buf[HASH_DER_LEN]; +static unsigned char tos_fw_hash_buf[HASH_DER_LEN]; +static unsigned char tos_fw_config_hash_buf[HASH_DER_LEN]; +static unsigned char nt_fw_config_hash_buf[HASH_DER_LEN]; +#if defined(SPD_spmd) +static unsigned char sp_pkg_hash_buf[MAX_SP_IDS][HASH_DER_LEN]; +#endif /* SPD_spmd */ + +static unsigned char core_swd_pk_buf[PK_DER_LEN]; +static unsigned char plat_pk_buf[PK_DER_LEN]; +#endif /* IMAGE_BL2 */ + +/* + * Parameter type descriptors. + */ +static auth_param_type_desc_t trusted_nv_ctr = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_NV_CTR, TRUSTED_FW_NVCOUNTER_OID); +static auth_param_type_desc_t subject_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, 0); +static auth_param_type_desc_t sig = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_SIG, 0); +static auth_param_type_desc_t sig_alg = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_SIG_ALG, 0); +static auth_param_type_desc_t raw_data = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_RAW_DATA, 0); + +static auth_param_type_desc_t tb_fw_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, TRUSTED_BOOT_FW_HASH_OID); +static auth_param_type_desc_t tb_fw_config_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, TRUSTED_BOOT_FW_CONFIG_HASH_OID); +static auth_param_type_desc_t hw_config_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, HW_CONFIG_HASH_OID); +static auth_param_type_desc_t fw_config_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, FW_CONFIG_HASH_OID); +static auth_param_type_desc_t soc_fw_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SOC_AP_FW_HASH_OID); +static auth_param_type_desc_t soc_fw_config_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SOC_FW_CONFIG_HASH_OID); +static auth_param_type_desc_t rmm_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, RMM_HASH_OID); + +#ifdef IMAGE_BL2 +static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_NV_CTR, NON_TRUSTED_FW_NVCOUNTER_OID); + +static auth_param_type_desc_t prot_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, PROT_PK_OID); +static auth_param_type_desc_t swd_rot_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, SWD_ROT_PK_OID); +static auth_param_type_desc_t core_swd_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, CORE_SWD_PK_OID); +static auth_param_type_desc_t plat_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, PLAT_PK_OID); + +static auth_param_type_desc_t tos_fw_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, TRUSTED_OS_FW_HASH_OID); +static auth_param_type_desc_t tos_fw_config_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, TRUSTED_OS_FW_CONFIG_HASH_OID); +static auth_param_type_desc_t nt_world_bl_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID); +static auth_param_type_desc_t nt_fw_config_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, NON_TRUSTED_FW_CONFIG_HASH_OID); +#if defined(SPD_spmd) +static auth_param_type_desc_t sp_pkg1_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SP_PKG1_HASH_OID); +static auth_param_type_desc_t sp_pkg2_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SP_PKG2_HASH_OID); +static auth_param_type_desc_t sp_pkg3_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SP_PKG3_HASH_OID); +static auth_param_type_desc_t sp_pkg4_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SP_PKG4_HASH_OID); +static auth_param_type_desc_t sp_pkg5_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SP_PKG5_HASH_OID); +static auth_param_type_desc_t sp_pkg6_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SP_PKG6_HASH_OID); +static auth_param_type_desc_t sp_pkg7_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SP_PKG7_HASH_OID); +static auth_param_type_desc_t sp_pkg8_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SP_PKG8_HASH_OID); +#endif /* SPD_spmd */ +#endif /* IMAGE_BL2 */ + +/* CCA Content Certificate */ +static const auth_img_desc_t cca_content_cert = { + .img_id = CCA_CONTENT_CERT_ID, + .img_type = IMG_CERT, + .parent = NULL, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &subject_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { + .type_desc = &tb_fw_hash, + .data = { + .ptr = (void *)tb_fw_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [1] = { + .type_desc = &tb_fw_config_hash, + .data = { + .ptr = (void *)tb_fw_config_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [2] = { + .type_desc = &fw_config_hash, + .data = { + .ptr = (void *)fw_config_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [3] = { + .type_desc = &hw_config_hash, + .data = { + .ptr = (void *)hw_config_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [4] = { + .type_desc = &soc_fw_hash, + .data = { + .ptr = (void *)soc_fw_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [5] = { + .type_desc = &soc_fw_config_hash, + .data = { + .ptr = (void *)soc_fw_config_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [6] = { + .type_desc = &rmm_hash, + .data = { + .ptr = (void *)rmm_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } +}; + +#ifdef IMAGE_BL1 +static const auth_img_desc_t bl2_image = { + .img_id = BL2_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cca_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &tb_fw_hash + } + } + } +}; + +static const auth_img_desc_t tb_fw_config = { + .img_id = TB_FW_CONFIG_ID, + .img_type = IMG_RAW, + .parent = &cca_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &tb_fw_config_hash + } + } + } +}; + +static const auth_img_desc_t fw_config = { + .img_id = FW_CONFIG_ID, + .img_type = IMG_RAW, + .parent = &cca_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &fw_config_hash + } + } + } +}; +#endif /* IMAGE_BL1 */ + +#ifdef IMAGE_BL2 +/* HW Config */ +static const auth_img_desc_t hw_config = { + .img_id = HW_CONFIG_ID, + .img_type = IMG_RAW, + .parent = &cca_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &hw_config_hash + } + } + } +}; + +/* BL31 */ +static const auth_img_desc_t bl31_image = { + .img_id = BL31_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cca_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &soc_fw_hash + } + } + } +}; + +/* BL31 Config */ +static const auth_img_desc_t soc_fw_config = { + .img_id = SOC_FW_CONFIG_ID, + .img_type = IMG_RAW, + .parent = &cca_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &soc_fw_config_hash + } + } + } +}; + +/* RMM */ +static const auth_img_desc_t rmm_image = { + .img_id = RMM_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cca_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &rmm_hash + } + } + } +}; + +/* Core SWD Key Certificate */ +static const auth_img_desc_t core_swd_key_cert = { + .img_id = CORE_SWD_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = NULL, /* SWD ROOT CERT */ + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &swd_rot_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { + .type_desc = &core_swd_pk, + .data = { + .ptr = (void *)core_swd_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } +}; + +/* SPMC Content Certificate */ +static const auth_img_desc_t trusted_os_fw_content_cert = { + .img_id = TRUSTED_OS_FW_CONTENT_CERT_ID, + .img_type = IMG_CERT, + .parent = &core_swd_key_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &core_swd_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { + .type_desc = &tos_fw_hash, + .data = { + .ptr = (void *)tos_fw_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [1] = { + .type_desc = &tos_fw_config_hash, + .data = { + .ptr = (void *)tos_fw_config_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } +}; + +/* SPMC */ +static const auth_img_desc_t bl32_image = { + .img_id = BL32_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &trusted_os_fw_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &tos_fw_hash + } + } + } +}; + +/* SPM Config */ +static const auth_img_desc_t tos_fw_config = { + .img_id = TOS_FW_CONFIG_ID, + .img_type = IMG_RAW, + .parent = &trusted_os_fw_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &tos_fw_config_hash + } + } + } +}; + +/* Platform Key Certificate */ +static const auth_img_desc_t plat_key_cert = { + .img_id = PLAT_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = NULL, /* PLATFORM ROOT CERT */ + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &prot_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &non_trusted_nv_ctr, + .plat_nv_ctr = &non_trusted_nv_ctr + } + } + }, + .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { + .type_desc = &plat_pk, + .data = { + .ptr = (void *)plat_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } +}; + +/* Non-Trusted Firmware */ +static const auth_img_desc_t non_trusted_fw_content_cert = { + .img_id = NON_TRUSTED_FW_CONTENT_CERT_ID, + .img_type = IMG_CERT, + .parent = &plat_key_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &plat_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &non_trusted_nv_ctr, + .plat_nv_ctr = &non_trusted_nv_ctr + } + } + }, + .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { + .type_desc = &nt_world_bl_hash, + .data = { + .ptr = (void *)nt_world_bl_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [1] = { + .type_desc = &nt_fw_config_hash, + .data = { + .ptr = (void *)nt_fw_config_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } +}; + +static const auth_img_desc_t bl33_image = { + .img_id = BL33_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &non_trusted_fw_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &nt_world_bl_hash + } + } + } +}; + +/* NT FW Config */ +static const auth_img_desc_t nt_fw_config = { + .img_id = NT_FW_CONFIG_ID, + .img_type = IMG_RAW, + .parent = &non_trusted_fw_content_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &nt_fw_config_hash + } + } + } +}; + +/* + * Secure Partitions + */ +#if defined(SPD_spmd) +static const auth_img_desc_t sip_sp_content_cert = { + .img_id = SIP_SP_CONTENT_CERT_ID, + .img_type = IMG_CERT, + .parent = &core_swd_key_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &core_swd_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { + .type_desc = &sp_pkg1_hash, + .data = { + .ptr = (void *)sp_pkg_hash_buf[0], + .len = (unsigned int)HASH_DER_LEN + } + }, + [1] = { + .type_desc = &sp_pkg2_hash, + .data = { + .ptr = (void *)sp_pkg_hash_buf[1], + .len = (unsigned int)HASH_DER_LEN + } + }, + [2] = { + .type_desc = &sp_pkg3_hash, + .data = { + .ptr = (void *)sp_pkg_hash_buf[2], + .len = (unsigned int)HASH_DER_LEN + } + }, + [3] = { + .type_desc = &sp_pkg4_hash, + .data = { + .ptr = (void *)sp_pkg_hash_buf[3], + .len = (unsigned int)HASH_DER_LEN + } + } + } +}; + +DEFINE_SIP_SP_PKG(1); +DEFINE_SIP_SP_PKG(2); +DEFINE_SIP_SP_PKG(3); +DEFINE_SIP_SP_PKG(4); + +static const auth_img_desc_t plat_sp_content_cert = { + .img_id = PLAT_SP_CONTENT_CERT_ID, + .img_type = IMG_CERT, + .parent = &plat_key_cert, + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &plat_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &non_trusted_nv_ctr, + .plat_nv_ctr = &non_trusted_nv_ctr + } + } + }, + .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { + .type_desc = &sp_pkg5_hash, + .data = { + .ptr = (void *)sp_pkg_hash_buf[4], + .len = (unsigned int)HASH_DER_LEN + } + }, + [1] = { + .type_desc = &sp_pkg6_hash, + .data = { + .ptr = (void *)sp_pkg_hash_buf[5], + .len = (unsigned int)HASH_DER_LEN + } + }, + [2] = { + .type_desc = &sp_pkg7_hash, + .data = { + .ptr = (void *)sp_pkg_hash_buf[6], + .len = (unsigned int)HASH_DER_LEN + } + }, + [3] = { + .type_desc = &sp_pkg8_hash, + .data = { + .ptr = (void *)sp_pkg_hash_buf[7], + .len = (unsigned int)HASH_DER_LEN + } + } + } +}; + +DEFINE_PLAT_SP_PKG(5); +DEFINE_PLAT_SP_PKG(6); +DEFINE_PLAT_SP_PKG(7); +DEFINE_PLAT_SP_PKG(8); +#endif /* SPD_spmd */ +#endif /* IMAGE_BL2 */ +/* + * Chain of trust definition + */ +#ifdef IMAGE_BL1 +static const auth_img_desc_t * const cot_desc[] = { + [CCA_CONTENT_CERT_ID] = &cca_content_cert, + [BL2_IMAGE_ID] = &bl2_image, + [TB_FW_CONFIG_ID] = &tb_fw_config, + [FW_CONFIG_ID] = &fw_config, +}; +#else /* IMAGE_BL2 */ +static const auth_img_desc_t * const cot_desc[] = { + [CCA_CONTENT_CERT_ID] = &cca_content_cert, + [HW_CONFIG_ID] = &hw_config, + [BL31_IMAGE_ID] = &bl31_image, + [SOC_FW_CONFIG_ID] = &soc_fw_config, + [RMM_IMAGE_ID] = &rmm_image, + [CORE_SWD_KEY_CERT_ID] = &core_swd_key_cert, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = &trusted_os_fw_content_cert, + [BL32_IMAGE_ID] = &bl32_image, + [TOS_FW_CONFIG_ID] = &tos_fw_config, + [PLAT_KEY_CERT_ID] = &plat_key_cert, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = &non_trusted_fw_content_cert, + [BL33_IMAGE_ID] = &bl33_image, + [NT_FW_CONFIG_ID] = &nt_fw_config, +#if defined(SPD_spmd) + [SIP_SP_CONTENT_CERT_ID] = &sip_sp_content_cert, + [PLAT_SP_CONTENT_CERT_ID] = &plat_sp_content_cert, + [SP_PKG1_ID] = &sp_pkg1, + [SP_PKG2_ID] = &sp_pkg2, + [SP_PKG3_ID] = &sp_pkg3, + [SP_PKG4_ID] = &sp_pkg4, + [SP_PKG5_ID] = &sp_pkg5, + [SP_PKG6_ID] = &sp_pkg6, + [SP_PKG7_ID] = &sp_pkg7, + [SP_PKG8_ID] = &sp_pkg8, +#endif +}; +#endif /* IMAGE_BL1 */ + +/* Register the CoT in the authentication module */ +REGISTER_COT(cot_desc); diff --git a/drivers/auth/crypto_mod.c b/drivers/auth/crypto_mod.c index eada3579a..fa1adb4f7 100644 --- a/drivers/auth/crypto_mod.c +++ b/drivers/auth/crypto_mod.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,19 +46,26 @@ void crypto_mod_init(void) { assert(crypto_lib_desc.name != NULL); assert(crypto_lib_desc.init != NULL); -#if TRUSTED_BOARD_BOOT +#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC assert(crypto_lib_desc.verify_signature != NULL); assert(crypto_lib_desc.verify_hash != NULL); -#endif /* TRUSTED_BOARD_BOOT */ -#if MEASURED_BOOT +#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ + +#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC assert(crypto_lib_desc.calc_hash != NULL); -#endif /* MEASURED_BOOT */ +#endif /* CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ /* Initialize the cryptographic library */ crypto_lib_desc.init(); INFO("Using crypto library '%s'\n", crypto_lib_desc.name); } +#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC /* * Function to verify a digital signature * @@ -108,8 +115,11 @@ int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, return crypto_lib_desc.verify_hash(data_ptr, data_len, digest_info_ptr, digest_info_len); } +#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ -#if MEASURED_BOOT +#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC /* * Calculate a hash * @@ -129,7 +139,8 @@ int crypto_mod_calc_hash(enum crypto_md_algo alg, void *data_ptr, return crypto_lib_desc.calc_hash(alg, data_ptr, data_len, output); } -#endif /* MEASURED_BOOT */ +#endif /* CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ /* * Authenticated decryption of data diff --git a/drivers/auth/cryptocell/713/cryptocell_crypto.c b/drivers/auth/cryptocell/713/cryptocell_crypto.c index 077317e7b..3ac16af20 100644 --- a/drivers/auth/cryptocell/713/cryptocell_crypto.c +++ b/drivers/auth/cryptocell/713/cryptocell_crypto.c @@ -8,6 +8,8 @@ #include <stddef.h> #include <string.h> +#include <platform_def.h> + #include <drivers/arm/cryptocell/713/bsv_api.h> #include <drivers/arm/cryptocell/713/bsv_crypto_asym_api.h> #include <drivers/auth/crypto_mod.h> diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk index 3eb41617f..16ce65ffe 100644 --- a/drivers/auth/mbedtls/mbedtls_common.mk +++ b/drivers/auth/mbedtls/mbedtls_common.mk @@ -97,18 +97,6 @@ else TF_MBEDTLS_USE_AES_GCM := 0 endif -ifeq ($(MEASURED_BOOT),1) - ifeq (${TPM_HASH_ALG}, sha256) - TF_MBEDTLS_TPM_HASH_ALG_ID := TF_MBEDTLS_SHA256 - else ifeq (${TPM_HASH_ALG}, sha384) - TF_MBEDTLS_TPM_HASH_ALG_ID := TF_MBEDTLS_SHA384 - else ifeq (${TPM_HASH_ALG}, sha512) - TF_MBEDTLS_TPM_HASH_ALG_ID := TF_MBEDTLS_SHA512 - else - $(error "TPM_HASH_ALG not defined.") - endif -endif - # Needs to be set to drive mbed TLS configuration correctly $(eval $(call add_defines,\ $(sort \ @@ -118,10 +106,6 @@ $(eval $(call add_defines,\ TF_MBEDTLS_USE_AES_GCM \ ))) -ifeq ($(MEASURED_BOOT),1) - $(eval $(call add_define,TF_MBEDTLS_TPM_HASH_ALG_ID)) -endif - $(eval $(call MAKE_LIB,mbedtls)) endif diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c index 0901d045a..d231179f5 100644 --- a/drivers/auth/mbedtls/mbedtls_crypto.c +++ b/drivers/auth/mbedtls/mbedtls_crypto.c @@ -24,7 +24,8 @@ #define LIB_NAME "mbed TLS" -#if MEASURED_BOOT +#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC /* * CRYPTO_MD_MAX_SIZE value is as per current stronger algorithm available * so make sure that mbed TLS MD maximum size must be lesser than this. @@ -32,7 +33,8 @@ CASSERT(CRYPTO_MD_MAX_SIZE >= MBEDTLS_MD_MAX_SIZE, assert_mbedtls_md_size_overflow); -#endif /* MEASURED_BOOT */ +#endif /* CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ /* * AlgorithmIdentifier ::= SEQUENCE { @@ -60,7 +62,8 @@ static void init(void) mbedtls_init(); } -#if TRUSTED_BOARD_BOOT +#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC /* * Verify a signature. * @@ -219,9 +222,11 @@ static int verify_hash(void *data_ptr, unsigned int data_len, return CRYPTO_SUCCESS; } -#endif /* TRUSTED_BOARD_BOOT */ +#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ -#if MEASURED_BOOT +#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC /* * Map a generic crypto message digest algorithm to the corresponding macro used * by Mbed TLS. @@ -264,7 +269,8 @@ static int calc_hash(enum crypto_md_algo md_algo, void *data_ptr, */ return mbedtls_md(md_info, data_ptr, data_len, output); } -#endif /* MEASURED_BOOT */ +#endif /* CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ #if TF_MBEDTLS_USE_AES_GCM /* @@ -368,7 +374,7 @@ static int auth_decrypt(enum crypto_dec_algo dec_algo, void *data_ptr, /* * Register crypto library descriptor */ -#if MEASURED_BOOT && TRUSTED_BOARD_BOOT +#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC #if TF_MBEDTLS_USE_AES_GCM REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash, auth_decrypt); @@ -376,13 +382,13 @@ REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash, REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash, NULL); #endif -#elif TRUSTED_BOARD_BOOT +#elif CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY #if TF_MBEDTLS_USE_AES_GCM REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, auth_decrypt); #else REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL); #endif -#elif MEASURED_BOOT +#elif CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY REGISTER_CRYPTO_LIB(LIB_NAME, init, calc_hash); -#endif /* MEASURED_BOOT && TRUSTED_BOARD_BOOT */ +#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ diff --git a/drivers/auth/mbedtls/mbedtls_x509_parser.c b/drivers/auth/mbedtls/mbedtls_x509_parser.c index 129566bd6..993ef1264 100644 --- a/drivers/auth/mbedtls/mbedtls_x509_parser.c +++ b/drivers/auth/mbedtls/mbedtls_x509_parser.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -114,10 +114,10 @@ static int get_ext(const char *oid, void **ext, unsigned int *ext_len) oid_len = mbedtls_oid_get_numeric_string(oid_str, MAX_OID_STR_LEN, &extn_oid); - if (oid_len == MBEDTLS_ERR_OID_BUF_TOO_SMALL) { + if ((oid_len == MBEDTLS_ERR_OID_BUF_TOO_SMALL) || (oid_len < 0)) { return IMG_PARSER_ERR; } - if ((oid_len == strlen(oid_str)) && !strcmp(oid, oid_str)) { + if (((size_t)oid_len == strlen(oid_str)) && !strcmp(oid, oid_str)) { *ext = (void *)p; *ext_len = (unsigned int)len; return IMG_PARSER_OK; diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c index 08b8e9fb1..e3fb749ba 100644 --- a/drivers/console/multi_console.c +++ b/drivers/console/multi_console.c @@ -5,6 +5,8 @@ */ #include <assert.h> +#include <stddef.h> +#include <stdlib.h> #include <drivers/console.h> @@ -95,10 +97,17 @@ int console_putc(int c) if ((err == ERROR_NO_VALID_CONSOLE) || (ret < err)) err = ret; } - return err; } +int putchar(int c) +{ + if (console_putc(c) == 0) + return c; + else + return EOF; +} + int console_getc(void) { int err = ERROR_NO_VALID_CONSOLE; diff --git a/drivers/measured_boot/event_log/event_log.c b/drivers/measured_boot/event_log/event_log.c index 792f2359c..d661c35e7 100644 --- a/drivers/measured_boot/event_log/event_log.c +++ b/drivers/measured_boot/event_log/event_log.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -84,23 +84,26 @@ static const event2_header_t locality_event_header = { * Record a measurement as a TCG_PCR_EVENT2 event * * @param[in] hash Pointer to hash data of TCG_DIGEST_SIZE bytes + * @param[in] event_type Type of Event, Various Event Types are + * mentioned in tcg.h header * @param[in] metadata_ptr Pointer to event_log_metadata_t structure * * There must be room for storing this new event into the event log buffer. */ -static void event_log_record(const uint8_t *hash, - const event_log_metadata_t *metadata_ptr) +void event_log_record(const uint8_t *hash, uint32_t event_type, + const event_log_metadata_t *metadata_ptr) { void *ptr = log_ptr; - uint32_t name_len; + uint32_t name_len = 0U; assert(hash != NULL); assert(metadata_ptr != NULL); - assert(metadata_ptr->name != NULL); - /* event_log_init() must have been called prior to this. */ + /* event_log_buf_init() must have been called prior to this. */ assert(log_ptr != NULL); - name_len = (uint32_t)strlen(metadata_ptr->name) + 1U; + if (metadata_ptr->name != NULL) { + name_len = (uint32_t)strlen(metadata_ptr->name) + 1U; + } /* Check for space in Event Log buffer */ assert(((uintptr_t)ptr + (uint32_t)EVENT2_HDR_SIZE + name_len) < @@ -115,7 +118,7 @@ static void event_log_record(const uint8_t *hash, ((event2_header_t *)ptr)->pcr_index = metadata_ptr->pcr; /* TCG_PCR_EVENT2.EventType */ - ((event2_header_t *)ptr)->event_type = EV_POST_CODE; + ((event2_header_t *)ptr)->event_type = event_type; /* TCG_PCR_EVENT2.Digests.Count */ ptr = (uint8_t *)ptr + offsetof(event2_header_t, digests); @@ -139,14 +142,25 @@ static void event_log_record(const uint8_t *hash, ((event2_data_t *)ptr)->event_size = name_len; /* Copy event data to TCG_PCR_EVENT2.Event */ - (void)memcpy((void *)(((event2_data_t *)ptr)->event), - (const void *)metadata_ptr->name, name_len); + if (metadata_ptr->name != NULL) { + (void)memcpy((void *)(((event2_data_t *)ptr)->event), + (const void *)metadata_ptr->name, name_len); + } /* End of event data */ log_ptr = (uint8_t *)((uintptr_t)ptr + offsetof(event2_data_t, event) + name_len); } +void event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish) +{ + assert(event_log_start != NULL); + assert(event_log_finish > event_log_start); + + log_ptr = event_log_start; + log_end = (uintptr_t)event_log_finish; +} + /* * Initialise Event Log global variables, used during the recording * of various payload measurements into the Event Log buffer @@ -158,28 +172,20 @@ static void event_log_record(const uint8_t *hash, */ void event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish) { - assert(event_log_start != NULL); - assert(event_log_finish > event_log_start); - - log_ptr = event_log_start; - log_end = (uintptr_t)event_log_finish; + event_log_buf_init(event_log_start, event_log_finish); /* Get pointer to platform's event_log_metadata_t structure */ plat_metadata_ptr = plat_event_log_get_metadata(); assert(plat_metadata_ptr != NULL); } -/* - * Initialises Event Log by writing Specification ID and - * Startup Locality events - */ -void event_log_write_header(void) +void event_log_write_specid_event(void) { - const char locality_signature[] = TCG_STARTUP_LOCALITY_SIGNATURE; void *ptr = log_ptr; - /* event_log_init() must have been called prior to this. */ + /* event_log_buf_init() must have been called prior to this. */ assert(log_ptr != NULL); + assert(((uintptr_t)log_ptr + ID_EVENT_SIZE) < log_end); /* * Add Specification ID Event first @@ -200,8 +206,23 @@ void event_log_write_header(void) * No vendor data */ ((id_event_struct_data_t *)ptr)->vendor_info_size = 0; - ptr = (uint8_t *)((uintptr_t)ptr + + log_ptr = (uint8_t *)((uintptr_t)ptr + offsetof(id_event_struct_data_t, vendor_info)); +} + +/* + * Initialises Event Log by writing Specification ID and + * Startup Locality events + */ +void event_log_write_header(void) +{ + const char locality_signature[] = TCG_STARTUP_LOCALITY_SIGNATURE; + void *ptr; + + event_log_write_specid_event(); + + ptr = log_ptr; + assert(((uintptr_t)log_ptr + LOC_EVENT_SIZE) < log_end); /* * The Startup Locality event should be placed in the log before @@ -219,7 +240,7 @@ void event_log_write_header(void) ((tpmt_ha *)ptr)->algorithm_id = TPM_ALG_ID; /* TCG_PCR_EVENT2.Digests[].Digest[] */ - (void)memset(&((tpmt_ha *)ptr)->digest, 0, TPM_ALG_ID); + (void)memset(&((tpmt_ha *)ptr)->digest, 0, TCG_DIGEST_SIZE); ptr = (uint8_t *)((uintptr_t)ptr + offsetof(tpmt_ha, digest) + TCG_DIGEST_SIZE); @@ -240,6 +261,14 @@ void event_log_write_header(void) log_ptr = (uint8_t *)((uintptr_t)ptr + sizeof(startup_locality_event_t)); } +int event_log_measure(uintptr_t data_base, uint32_t data_size, + unsigned char hash_data[CRYPTO_MD_MAX_SIZE]) +{ + /* Calculate hash */ + return crypto_mod_calc_hash(CRYPTO_MD_ID, + (void *)data_base, data_size, hash_data); +} + /* * Calculate and write hash of image, configuration data, etc. * to Event Log. @@ -265,14 +294,13 @@ int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size, } assert(metadata_ptr->id != EVLOG_INVALID_ID); - /* Calculate hash */ - rc = crypto_mod_calc_hash(CRYPTO_MD_ID, - (void *)data_base, data_size, hash_data); + /* Measure the payload with algorithm selected by EventLog driver */ + rc = event_log_measure(data_base, data_size, hash_data); if (rc != 0) { return rc; } - event_log_record(hash_data, metadata_ptr); + event_log_record(hash_data, EV_POST_CODE, metadata_ptr); return 0; } diff --git a/drivers/measured_boot/event_log/event_log.mk b/drivers/measured_boot/event_log/event_log.mk index 1ff4aa81c..5ea4c554a 100644 --- a/drivers/measured_boot/event_log/event_log.mk +++ b/drivers/measured_boot/event_log/event_log.mk @@ -7,20 +7,25 @@ # Default log level to dump the event log (LOG_LEVEL_INFO) EVENT_LOG_LEVEL ?= 40 -# TPM hash algorithm. +# Measured Boot hash algorithm. # SHA-256 (or stronger) is required for all devices that are TPM 2.0 compliant. -TPM_HASH_ALG := sha256 +ifdef TPM_HASH_ALG + $(warning "TPM_HASH_ALG is deprecated. Please use MBOOT_EL_HASH_ALG instead.") + MBOOT_EL_HASH_ALG := ${TPM_HASH_ALG} +else + MBOOT_EL_HASH_ALG := sha256 +endif -ifeq (${TPM_HASH_ALG}, sha512) +ifeq (${MBOOT_EL_HASH_ALG}, sha512) TPM_ALG_ID := TPM_ALG_SHA512 TCG_DIGEST_SIZE := 64U -else ifeq (${TPM_HASH_ALG}, sha384) +else ifeq (${MBOOT_EL_HASH_ALG}, sha384) TPM_ALG_ID := TPM_ALG_SHA384 TCG_DIGEST_SIZE := 48U else TPM_ALG_ID := TPM_ALG_SHA256 TCG_DIGEST_SIZE := 32U -endif #TPM_HASH_ALG +endif #MBOOT_EL_HASH_ALG # Set definitions for Measured Boot driver. $(eval $(call add_defines,\ diff --git a/drivers/measured_boot/rss/rss_measured_boot.c b/drivers/measured_boot/rss/rss_measured_boot.c index fe2baf055..cf545a705 100644 --- a/drivers/measured_boot/rss/rss_measured_boot.c +++ b/drivers/measured_boot/rss/rss_measured_boot.c @@ -5,6 +5,7 @@ */ #include <assert.h> #include <stdint.h> +#include <string.h> #include <common/debug.h> #include <drivers/auth/crypto_mod.h> @@ -40,10 +41,21 @@ void rss_measured_boot_init(void) /* At this point it is expected that communication channel over MHU * is already initialised by platform init. */ + struct rss_mboot_metadata *metadata_ptr; /* Get pointer to platform's struct rss_mboot_metadata structure */ plat_metadata_ptr = plat_rss_mboot_get_metadata(); assert(plat_metadata_ptr != NULL); + + /* Use a local variable to preserve the value of the global pointer */ + metadata_ptr = plat_metadata_ptr; + + /* Init the non-const members of the metadata structure */ + while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) { + metadata_ptr->sw_type_size = + strlen((const char *)&metadata_ptr->sw_type) + 1; + metadata_ptr++; + } } int rss_mboot_measure_and_record(uintptr_t data_base, uint32_t data_size, diff --git a/drivers/measured_boot/rss/rss_measured_boot.mk b/drivers/measured_boot/rss/rss_measured_boot.mk index 01545afeb..18ee83618 100644 --- a/drivers/measured_boot/rss/rss_measured_boot.mk +++ b/drivers/measured_boot/rss/rss_measured_boot.mk @@ -6,21 +6,18 @@ # Hash algorithm for measured boot # SHA-256 (or stronger) is required. -# TODO: The measurement algorithm incorrectly suggests that the TPM backend -# is used which may not be the case. It is currently being worked on and -# soon TPM_HASH_ALG will be replaced by a more generic name. -TPM_HASH_ALG := sha256 +MBOOT_RSS_HASH_ALG := sha256 -ifeq (${TPM_HASH_ALG}, sha512) +ifeq (${MBOOT_RSS_HASH_ALG}, sha512) MBOOT_ALG_ID := MBOOT_ALG_SHA512 MBOOT_DIGEST_SIZE := 64U -else ifeq (${TPM_HASH_ALG}, sha384) +else ifeq (${MBOOT_RSS_HASH_ALG}, sha384) MBOOT_ALG_ID := MBOOT_ALG_SHA384 MBOOT_DIGEST_SIZE := 48U else MBOOT_ALG_ID := MBOOT_ALG_SHA256 MBOOT_DIGEST_SIZE := 32U -endif #TPM_HASH_ALG +endif #MBOOT_RSS_HASH_ALG # Set definitions for Measured Boot driver. $(eval $(call add_defines,\ diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c327e71d2..8e83464d5 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,6 +16,7 @@ #include <drivers/delay_timer.h> #include <drivers/mmc.h> #include <lib/utils.h> +#include <plat/common/common_def.h> #define MMC_DEFAULT_MAX_RETRIES 5 #define SEND_OP_COND_MAX_RETRIES 100 @@ -25,6 +26,7 @@ static const struct mmc_ops *ops; static unsigned int mmc_ocr_value; static struct mmc_csd_emmc mmc_csd; +static struct sd_switch_status sd_switch_func_status; static unsigned char mmc_ext_csd[512] __aligned(16); static unsigned int mmc_flags; static struct mmc_device_info *mmc_dev_info; @@ -44,6 +46,11 @@ static bool is_cmd23_enabled(void) return ((mmc_flags & MMC_FLAG_CMD23) != 0U); } +static bool is_sd_cmd6_enabled(void) +{ + return ((mmc_flags & MMC_FLAG_SD_CMD6) != 0U); +} + static int mmc_send_cmd(unsigned int idx, unsigned int arg, unsigned int r_type, unsigned int *r_data) { @@ -357,6 +364,33 @@ static int mmc_fill_device_info(void) return 0; } +static int sd_switch(unsigned int mode, unsigned char group, + unsigned char func) +{ + unsigned int group_shift = (group - 1U) * 4U; + unsigned int group_mask = GENMASK(group_shift + 3U, group_shift); + unsigned int arg; + int ret; + + ret = ops->prepare(0, (uintptr_t)&sd_switch_func_status, + sizeof(sd_switch_func_status)); + if (ret != 0) { + return ret; + } + + /* MMC CMD6: SWITCH_FUNC */ + arg = mode | SD_SWITCH_ALL_GROUPS_MASK; + arg &= ~group_mask; + arg |= func << group_shift; + ret = mmc_send_cmd(MMC_CMD(6), arg, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + return ops->read(0, (uintptr_t)&sd_switch_func_status, + sizeof(sd_switch_func_status)); +} + static int sd_send_op_cond(void) { int n; @@ -524,7 +558,39 @@ static int mmc_enumerate(unsigned int clk, unsigned int bus_width) return ret; } - return mmc_fill_device_info(); + ret = mmc_fill_device_info(); + if (ret != 0) { + return ret; + } + + if (is_sd_cmd6_enabled() && + (mmc_dev_info->mmc_dev_type == MMC_IS_SD_HC)) { + /* Try to switch to High Speed Mode */ + ret = sd_switch(SD_SWITCH_FUNC_CHECK, 1U, 1U); + if (ret != 0) { + return ret; + } + + if ((sd_switch_func_status.support_g1 & BIT(9)) == 0U) { + /* High speed not supported, keep default speed */ + return 0; + } + + ret = sd_switch(SD_SWITCH_FUNC_SWITCH, 1U, 1U); + if (ret != 0) { + return ret; + } + + if ((sd_switch_func_status.sel_g2_g1 & 0x1U) == 0U) { + /* Cannot switch to high speed, keep default speed */ + return 0; + } + + mmc_dev_info->max_bus_freq = 50000000U; + ret = ops->set_ios(clk, bus_width); + } + + return ret; } size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size) @@ -694,90 +760,71 @@ size_t mmc_erase_blocks(int lba, size_t size) return size; } -static inline void mmc_rpmb_enable(void) -{ - mmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG, - PART_CFG_BOOT_PARTITION1_ENABLE | - PART_CFG_BOOT_PARTITION1_ACCESS); -} - -static inline void mmc_rpmb_disable(void) -{ - mmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG, - PART_CFG_BOOT_PARTITION1_ENABLE); -} - -size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size) +static int mmc_part_switch(unsigned int part_type) { - size_t size_read; + uint8_t part_config = mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG]; - mmc_rpmb_enable(); - size_read = mmc_read_blocks(lba, buf, size); - mmc_rpmb_disable(); + part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK; + part_config |= part_type; - return size_read; + return mmc_send_part_switch_cmd(part_config); } -size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size) +static unsigned char mmc_current_boot_part(void) { - size_t size_written; - - mmc_rpmb_enable(); - size_written = mmc_write_blocks(lba, buf, size); - mmc_rpmb_disable(); - - return size_written; + return PART_CFG_CURRENT_BOOT_PARTITION(mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG]); } -size_t mmc_rpmb_erase_blocks(int lba, size_t size) +int mmc_part_switch_current_boot(void) { - size_t size_erased; + unsigned char current_boot_part = mmc_current_boot_part(); + int ret; - mmc_rpmb_enable(); - size_erased = mmc_erase_blocks(lba, size); - mmc_rpmb_disable(); + if (current_boot_part != 1U && + current_boot_part != 2U) { + ERROR("Got unexpected value for active boot partition, %u\n", current_boot_part); + return -EIO; + } + + ret = mmc_part_switch(current_boot_part); + if (ret < 0) { + ERROR("Failed to switch to boot partition, %d\n", ret); + } - return size_erased; + return ret; } -static int mmc_part_switch(unsigned int part_type) +int mmc_part_switch_user(void) { - uint8_t part_config = mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG]; + int ret; - part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK; - part_config |= part_type; + ret = mmc_part_switch(PART_CFG_BOOT_PARTITION_NO_ACCESS); + if (ret < 0) { + ERROR("Failed to switch to user partition, %d\n", ret); + } - return mmc_send_part_switch_cmd(part_config); + return ret; } -static unsigned char mmc_current_boot_part(void) +size_t mmc_boot_part_size(void) { - return PART_CFG_CURRENT_BOOT_PARTITION(mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG]); + return mmc_ext_csd[CMD_EXTCSD_BOOT_SIZE_MULT] * SZ_128K; } size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size) { size_t size_read; int ret; - unsigned char current_boot_part = mmc_current_boot_part(); - - if (current_boot_part != 1U && - current_boot_part != 2U) { - ERROR("Got unexpected value for active boot partition, %u\n", current_boot_part); - return 0; - } - ret = mmc_part_switch(current_boot_part); + ret = mmc_part_switch_current_boot(); if (ret < 0) { - ERROR("Failed to switch to boot partition, %d\n", ret); return 0; } size_read = mmc_read_blocks(lba, buf, size); - ret = mmc_part_switch(0); + ret = mmc_part_switch_user(); if (ret < 0) { - ERROR("Failed to switch back to user partition, %d\n", ret); return 0; } diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c index 9f0331ad7..6ef2256ab 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,18 +8,29 @@ #include <errno.h> #include <stddef.h> -#include <platform_def.h> - #include <common/debug.h> #include <drivers/delay_timer.h> #include <drivers/nand.h> #include <lib/utils.h> +#include <platform_def.h> + /* * Define a single nand_device used by specific NAND frameworks. */ static struct nand_device nand_dev; -static uint8_t scratch_buff[PLATFORM_MTD_MAX_PAGE_SIZE]; + +#pragma weak plat_get_scratch_buffer +void plat_get_scratch_buffer(void **buffer_addr, size_t *buf_size) +{ + static uint8_t scratch_buff[PLATFORM_MTD_MAX_PAGE_SIZE]; + + assert(buffer_addr != NULL); + assert(buf_size != NULL); + + *buffer_addr = (void *)scratch_buff; + *buf_size = sizeof(scratch_buff); +} int nand_read(unsigned int offset, uintptr_t buffer, size_t length, size_t *length_read) @@ -34,6 +45,12 @@ int nand_read(unsigned int offset, uintptr_t buffer, size_t length, unsigned int bytes_read; int is_bad; int ret; + uint8_t *scratch_buff; + size_t scratch_buff_size; + + plat_get_scratch_buffer((void **)&scratch_buff, &scratch_buff_size); + + assert(scratch_buff != NULL); VERBOSE("Block %u - %u, page_start %u, nb %u, length %zu, offset %u\n", block, end_block, page_start, nb_pages, length, offset); @@ -41,7 +58,7 @@ int nand_read(unsigned int offset, uintptr_t buffer, size_t length, *length_read = 0UL; if (((start_offset != 0U) || (length % nand_dev.page_size) != 0U) && - (sizeof(scratch_buff) < nand_dev.page_size)) { + (scratch_buff_size < nand_dev.page_size)) { return -EINVAL; } diff --git a/drivers/nxp/ddr/phy-gen2/phy.c b/drivers/nxp/ddr/phy-gen2/phy.c index c8245a846..9e52145d8 100644 --- a/drivers/nxp/ddr/phy-gen2/phy.c +++ b/drivers/nxp/ddr/phy-gen2/phy.c @@ -2216,14 +2216,6 @@ static int load_fw(uint16_t **phy_ptr, size = PHY_GEN2_MAX_IMAGE_SIZE; image_buf = (uintptr_t)phy_gen2_fw_img_buf; - ret = mmap_add_dynamic_region(phy_gen2_fw_img_buf, - phy_gen2_fw_img_buf, - PHY_GEN2_MAX_IMAGE_SIZE, - MT_MEMORY | MT_RW | MT_SECURE); - if (ret != 0) { - ERROR("Failed to add dynamic memory region.\n"); - return ret; - } ret = img_loadr(imem_id, &image_buf, &size); if (ret != 0) { ERROR("Failed to load %d firmware.\n", imem_id); @@ -2592,6 +2584,15 @@ int compute_ddr_phy(struct ddr_info *priv) } } else { #endif + /* Mapping IMG buffer firstly */ + ret = mmap_add_dynamic_region(priv->phy_gen2_fw_img_buf, + priv->phy_gen2_fw_img_buf, + PHY_GEN2_MAX_IMAGE_SIZE, + MT_MEMORY | MT_RW | MT_SECURE); + if (ret != 0) { + ERROR("Failed to add dynamic memory region.\n"); + return ret; + } debug("Load 1D firmware\n"); ret = load_fw(priv->phy, &input, 0, &msg_1d, diff --git a/drivers/partition/gpt.c b/drivers/partition/gpt.c index ee0bddf75..4fe832244 100644 --- a/drivers/partition/gpt.c +++ b/drivers/partition/gpt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -59,6 +59,7 @@ int parse_gpt_entry(gpt_entry_t *gpt_entry, partition_entry_t *entry) gpt_entry->first_lba + 1) * PLAT_PARTITION_BLOCK_SIZE; guidcpy(&entry->part_guid, &gpt_entry->unique_uuid); + guidcpy(&entry->type_guid, &gpt_entry->type_uuid); return 0; } diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c index c84816f41..1881c91b3 100644 --- a/drivers/partition/partition.c +++ b/drivers/partition/partition.c @@ -266,6 +266,19 @@ const partition_entry_t *get_partition_entry(const char *name) return NULL; } +const partition_entry_t *get_partition_entry_by_type(const uuid_t *type_uuid) +{ + int i; + + for (i = 0; i < list.entry_count; i++) { + if (guidcmp(type_uuid, &list.list[i].type_guid) == 0) { + return &list.list[i]; + } + } + + return NULL; +} + const partition_entry_t *get_partition_entry_by_uuid(const uuid_t *part_uuid) { int i; diff --git a/drivers/rpi3/gpio/rpi3_gpio.c b/drivers/rpi3/gpio/rpi3_gpio.c index f938f563f..55a8832c3 100644 --- a/drivers/rpi3/gpio/rpi3_gpio.c +++ b/drivers/rpi3/gpio/rpi3_gpio.c @@ -10,6 +10,7 @@ #include <lib/mmio.h> #include <drivers/delay_timer.h> #include <drivers/rpi3/gpio/rpi3_gpio.h> +#include <platform_def.h> static uintptr_t reg_base; diff --git a/drivers/scmi-msg/base.c b/drivers/scmi-msg/base.c index 2d7203451..2db4d7e9e 100644 --- a/drivers/scmi-msg/base.c +++ b/drivers/scmi-msg/base.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. - * Copyright (c) 2019-2020, Linaro Limited + * Copyright (c) 2019-2022, Linaro Limited */ #include <assert.h> #include <string.h> @@ -131,15 +131,12 @@ static unsigned int count_protocols_in_list(const uint8_t *protocol_list) return count; } -#define MAX_PROTOCOL_IN_LIST 8U - static void discover_list_protocols(struct scmi_msg *msg) { const struct scmi_base_discover_list_protocols_a2p *a2p = NULL; struct scmi_base_discover_list_protocols_p2a p2a = { .status = SCMI_SUCCESS, }; - uint8_t outargs[sizeof(p2a) + MAX_PROTOCOL_IN_LIST] = { 0U }; const uint8_t *list = NULL; unsigned int count = 0U; @@ -148,24 +145,22 @@ static void discover_list_protocols(struct scmi_msg *msg) return; } - assert(msg->out_size > sizeof(outargs)); - a2p = (void *)msg->in; list = plat_scmi_protocol_list(msg->agent_id); count = count_protocols_in_list(list); + if (count > a2p->skip) { - count = MIN(count - a2p->skip, MAX_PROTOCOL_IN_LIST); + count = MIN(count - a2p->skip, msg->out_size - sizeof(p2a)); } else { count = 0U; } p2a.num_protocols = count; - memcpy(outargs, &p2a, sizeof(p2a)); - memcpy(outargs + sizeof(p2a), list + a2p->skip, count); - - scmi_write_response(msg, outargs, sizeof(outargs)); + memcpy(msg->out, &p2a, sizeof(p2a)); + memcpy(msg->out + sizeof(p2a), list + a2p->skip, count); + msg->out_size_out = sizeof(p2a) + round_up(count, sizeof(uint32_t)); } static const scmi_msg_handler_t scmi_base_handler_table[] = { diff --git a/drivers/st/clk/clk-stm32-core.c b/drivers/st/clk/clk-stm32-core.c index e1b694031..bb0312533 100644 --- a/drivers/st/clk/clk-stm32-core.c +++ b/drivers/st/clk/clk-stm32-core.c @@ -143,7 +143,7 @@ int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on { struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); - return _clk_stm32_gate_wait_ready(priv, osc_data->gate_id, ready_on); + return _clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, ready_on); } int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id) @@ -215,24 +215,6 @@ int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id) return 0; } -const char *_clk_stm32_get_name(struct stm32_clk_priv *priv, int id) -{ - return priv->clks[id].name; -} - -const char *clk_stm32_get_name(struct stm32_clk_priv *priv, - unsigned long binding_id) -{ - int id; - - id = clk_get_index(priv, binding_id); - if (id == -EINVAL) { - return NULL; - } - - return _clk_stm32_get_name(priv, id); -} - const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id) { if ((unsigned int)id < priv->num) { @@ -838,8 +820,9 @@ int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, } } - if ((mmio_read_32(address) & mask_rdy) != mask_test) + if ((mmio_read_32(address) & mask_rdy) != mask_test) { return -ETIMEDOUT; + } return 0; } diff --git a/drivers/st/clk/clk-stm32-core.h b/drivers/st/clk/clk-stm32-core.h index 809d05f70..8bfb5134f 100644 --- a/drivers/st/clk/clk-stm32-core.h +++ b/drivers/st/clk/clk-stm32-core.h @@ -54,7 +54,6 @@ struct stm32_clk_ops { }; struct clk_stm32 { - const char *name; uint16_t binding; uint16_t parent; uint8_t flags; @@ -163,8 +162,6 @@ int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id); int clk_oscillator_wait_ready_off(struct stm32_clk_priv *priv, int id); -const char *_clk_stm32_get_name(struct stm32_clk_priv *priv, int id); -const char *clk_stm32_get_name(struct stm32_clk_priv *priv, unsigned long binding_id); int clk_stm32_get_counter(unsigned long binding_id); void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id); @@ -226,7 +223,6 @@ struct clk_stm32_div_cfg { #define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \ [(idx)] = (struct clk_stm32){ \ - .name = #idx,\ .binding = (_binding),\ .parent = (_parent),\ .flags = (_flags),\ @@ -242,7 +238,6 @@ struct clk_stm32_gate_cfg { #define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \ [(idx)] = (struct clk_stm32){ \ - .name = #idx,\ .binding = (_binding),\ .parent = (_parent),\ .flags = (_flags),\ @@ -262,7 +257,6 @@ unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, #define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \ [(idx)] = (struct clk_stm32){ \ - .name = #idx,\ .binding = (_idx),\ .parent = (_parent),\ .clock_cfg = &(struct fixed_factor_cfg){\ @@ -274,7 +268,6 @@ unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, #define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \ [(idx)] = (struct clk_stm32){ \ - .name = #idx,\ .binding = (_binding),\ .parent = (_parent),\ .flags = (_flags),\ @@ -287,7 +280,6 @@ unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, #define STM32_MUX(idx, _binding, _mux_id, _flags) \ [(idx)] = (struct clk_stm32){ \ - .name = #idx,\ .binding = (_binding),\ .parent = (MUX(_mux_id)),\ .flags = (_flags),\ @@ -302,7 +294,6 @@ struct clk_timer_cfg { #define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \ [(idx)] = (struct clk_stm32){ \ - .name = #idx,\ .binding = (_idx),\ .parent = (_parent),\ .flags = (CLK_SET_RATE_PARENT | (_flags)),\ @@ -319,7 +310,6 @@ struct clk_stm32_fixed_rate_cfg { #define CLK_FIXED_RATE(idx, _binding, _rate) \ [(idx)] = (struct clk_stm32){ \ - .name = #idx,\ .binding = (_binding),\ .parent = (CLK_IS_ROOT),\ .clock_cfg = &(struct clk_stm32_fixed_rate_cfg){\ @@ -370,7 +360,6 @@ struct stm32_osc_cfg { #define CLK_OSC(idx, _idx, _parent, _osc_id) \ [(idx)] = (struct clk_stm32){ \ - .name = #idx,\ .binding = (_idx),\ .parent = (_parent),\ .flags = CLK_IS_CRITICAL,\ @@ -382,7 +371,6 @@ struct stm32_osc_cfg { #define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \ [(idx)] = (struct clk_stm32){ \ - .name = #idx,\ .binding = (_idx),\ .parent = (_parent),\ .flags = CLK_IS_CRITICAL,\ diff --git a/drivers/st/clk/clk-stm32mp13.c b/drivers/st/clk/clk-stm32mp13.c index d3607672b..c96092899 100644 --- a/drivers/st/clk/clk-stm32mp13.c +++ b/drivers/st/clk/clk-stm32mp13.c @@ -1705,7 +1705,6 @@ static const struct stm32_clk_ops clk_stm32_pll_ops = { }; #define CLK_PLL(idx, _idx, _parent, _gate, _pll_id, _flags)[idx] = {\ - .name = #idx,\ .binding = _idx,\ .parent = _parent,\ .flags = (_flags),\ @@ -1762,7 +1761,6 @@ static const struct stm32_clk_ops clk_stm32_composite_ops = { #define STM32_COMPOSITE(idx, _binding, _parent, _flags, _gate_id,\ _div_id)[idx] = {\ - .name = #idx,\ .binding = (_binding),\ .parent = (_parent),\ .flags = (_flags),\ diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index 534ee3b1b..aa5db6fc2 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -232,7 +232,6 @@ enum stm32mp1_plltype { struct stm32mp1_pll { uint8_t refclk_min; uint8_t refclk_max; - uint8_t divn_max; }; struct stm32mp1_clk_gate { @@ -543,12 +542,10 @@ static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { [PLL_800] = { .refclk_min = 4, .refclk_max = 16, - .divn_max = 99, }, [PLL_1600] = { .refclk_min = 8, .refclk_max = 16, - .divn_max = 199, }, }; diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c index 80c2f4102..01d1420cf 100644 --- a/drivers/st/clk/stm32mp_clkfunc.c +++ b/drivers/st/clk/stm32mp_clkfunc.c @@ -17,7 +17,6 @@ #include <platform_def.h> -#define DT_UART_COMPAT "st,stm32h7-uart" /* * Get the frequency of an oscillator from its name in device tree. * @param name: oscillator name diff --git a/drivers/st/crypto/stm32_hash.c b/drivers/st/crypto/stm32_hash.c index 6a1d47654..e92f98000 100644 --- a/drivers/st/crypto/stm32_hash.c +++ b/drivers/st/crypto/stm32_hash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,10 +8,6 @@ #include <errno.h> #include <stdint.h> -#include <libfdt.h> - -#include <platform_def.h> - #include <arch_helpers.h> #include <common/debug.h> #include <drivers/clk.h> @@ -20,9 +16,17 @@ #include <drivers/st/stm32mp_reset.h> #include <lib/mmio.h> #include <lib/utils.h> +#include <libfdt.h> #include <plat/common/platform.h> +#include <platform_def.h> + +#if STM32_HASH_VER == 2 #define DT_HASH_COMPAT "st,stm32f756-hash" +#endif +#if STM32_HASH_VER == 4 +#define DT_HASH_COMPAT "st,stm32mp13-hash" +#endif #define HASH_CR 0x00U #define HASH_DIN 0x04U @@ -33,11 +37,22 @@ /* Control Register */ #define HASH_CR_INIT BIT(2) #define HASH_CR_DATATYPE_SHIFT U(4) - +#if STM32_HASH_VER == 2 #define HASH_CR_ALGO_SHA1 0x0U #define HASH_CR_ALGO_MD5 BIT(7) #define HASH_CR_ALGO_SHA224 BIT(18) #define HASH_CR_ALGO_SHA256 (BIT(18) | BIT(7)) +#endif +#if STM32_HASH_VER == 4 +#define HASH_CR_ALGO_SHIFT U(17) +#define HASH_CR_ALGO_SHA1 (0x0U << HASH_CR_ALGO_SHIFT) +#define HASH_CR_ALGO_SHA224 (0x2U << HASH_CR_ALGO_SHIFT) +#define HASH_CR_ALGO_SHA256 (0x3U << HASH_CR_ALGO_SHIFT) +#define HASH_CR_ALGO_SHA384 (0xCU << HASH_CR_ALGO_SHIFT) +#define HASH_CR_ALGO_SHA512_224 (0xDU << HASH_CR_ALGO_SHIFT) +#define HASH_CR_ALGO_SHA512_256 (0xEU << HASH_CR_ALGO_SHIFT) +#define HASH_CR_ALGO_SHA512 (0xFU << HASH_CR_ALGO_SHIFT) +#endif /* Status Flags */ #define HASH_SR_DCIS BIT(1) @@ -51,6 +66,10 @@ #define SHA1_DIGEST_SIZE 20U #define SHA224_DIGEST_SIZE 28U #define SHA256_DIGEST_SIZE 32U +#define SHA384_DIGEST_SIZE 48U +#define SHA512_224_DIGEST_SIZE 28U +#define SHA512_256_DIGEST_SIZE 32U +#define SHA512_DIGEST_SIZE 64U #define RESET_TIMEOUT_US_1MS 1000U #define HASH_TIMEOUT_US 10000U @@ -131,10 +150,12 @@ static void hash_hw_init(enum stm32_hash_algo_mode mode) reg = HASH_CR_INIT | (HASH_DATA_8_BITS << HASH_CR_DATATYPE_SHIFT); switch (mode) { +#if STM32_HASH_VER == 2 case HASH_MD5SUM: reg |= HASH_CR_ALGO_MD5; stm32_hash.digest_size = MD5_DIGEST_SIZE; break; +#endif case HASH_SHA1: reg |= HASH_CR_ALGO_SHA1; stm32_hash.digest_size = SHA1_DIGEST_SIZE; @@ -143,6 +164,16 @@ static void hash_hw_init(enum stm32_hash_algo_mode mode) reg |= HASH_CR_ALGO_SHA224; stm32_hash.digest_size = SHA224_DIGEST_SIZE; break; +#if STM32_HASH_VER == 4 + case HASH_SHA384: + reg |= HASH_CR_ALGO_SHA384; + stm32_hash.digest_size = SHA384_DIGEST_SIZE; + break; + case HASH_SHA512: + reg |= HASH_CR_ALGO_SHA512; + stm32_hash.digest_size = SHA512_DIGEST_SIZE; + break; +#endif /* Default selected algo is SHA256 */ case HASH_SHA256: default: @@ -171,13 +202,12 @@ static int hash_get_digest(uint8_t *digest) memcpy(digest + (i * sizeof(uint32_t)), &dsg, sizeof(uint32_t)); } -#if defined(IMAGE_BL2) /* * Clean hardware context as HASH could be used later * by non-secure software */ hash_hw_init(HASH_SHA256); -#endif + return 0; } @@ -298,17 +328,9 @@ int stm32_hash_register(void) for (node = dt_get_node(&hash_info, -1, DT_HASH_COMPAT); node != -FDT_ERR_NOTFOUND; node = dt_get_node(&hash_info, node, DT_HASH_COMPAT)) { -#if defined(IMAGE_BL2) if (hash_info.status != DT_DISABLED) { break; } -#else - /* BL32 uses hash if it is assigned only to secure world */ - if (hash_info.status == DT_SECURE) { - stm32mp_register_secure_periph_iomem(hash_info.base); - break; - } -#endif } if (node == -FDT_ERR_NOTFOUND) { diff --git a/drivers/st/crypto/stm32_pka.c b/drivers/st/crypto/stm32_pka.c new file mode 100644 index 000000000..e03cf0f42 --- /dev/null +++ b/drivers/st/crypto/stm32_pka.c @@ -0,0 +1,707 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdint.h> + +#include <drivers/clk.h> +#include <drivers/delay_timer.h> +#include <drivers/st/stm32_pka.h> +#include <drivers/st/stm32mp_reset.h> +#include <lib/mmio.h> +#include <lib/utils.h> +#include <libfdt.h> +#include <plat/common/platform.h> + +#include <platform_def.h> + +/* + * For our comprehension in this file + * _len are in BITs + * _size are in BYTEs + * _nbw are in number of PKA_word (PKA_word = u64) + */ + +#define UINT8_LEN 8U +#define UINT64_LEN (UINT8_LEN * sizeof(uint64_t)) +#define WORD_SIZE (sizeof(uint64_t)) +#define OP_NBW_FROM_LEN(len) (DIV_ROUND_UP_2EVAL((len), UINT64_LEN) + 1) +#define OP_NBW_FROM_SIZE(s) OP_NBW_FROM_LEN((s) * UINT8_LEN) +#define OP_SIZE_FROM_SIZE(s) (OP_NBW_FROM_SIZE(s) * WORD_SIZE) + +#define DT_PKA_COMPAT "st,stm32-pka64" + +#define MAX_ECC_SIZE_LEN 640U +#define MAX_EO_NBW OP_NBW_FROM_LEN(MAX_ECC_SIZE_LEN) + +/* PKA registers */ +/* PKA control register */ +#define _PKA_CR 0x0U +/* PKA status register */ +#define _PKA_SR 0x4U +/* PKA clear flag register */ +#define _PKA_CLRFR 0x8U +/* PKA version register */ +#define _PKA_VERR 0x1FF4U +/* PKA identification register */ +#define _PKA_IPIDR 0x1FF8U + +/* PKA control register fields */ +#define _PKA_CR_MODE_MASK GENMASK(13, 8) +#define _PKA_CR_MODE_SHIFT 8U +#define _PKA_CR_MODE_ADD 0x9U +#define _PKA_CR_MODE_ECDSA_VERIF 0x26U +#define _PKA_CR_START BIT(1) +#define _PKA_CR_EN BIT(0) + +/* PKA status register fields */ +#define _PKA_SR_BUSY BIT(16) +#define _PKA_SR_LMF BIT(1) +#define _PKA_SR_INITOK BIT(0) + +/* PKA it flag fields (used in CR, SR and CLRFR) */ +#define _PKA_IT_MASK (GENMASK(21, 19) | BIT(17)) +#define _PKA_IT_SHIFT 17U +#define _PKA_IT_OPERR BIT(21) +#define _PKA_IT_ADDRERR BIT(20) +#define _PKA_IT_RAMERR BIT(19) +#define _PKA_IT_PROCEND BIT(17) + +/* PKA version register fields */ +#define _PKA_VERR_MAJREV_MASK GENMASK(7, 4) +#define _PKA_VERR_MAJREV_SHIFT 4U +#define _PKA_VERR_MINREV_MASK GENMASK(3, 0) +#define _PKA_VERR_MINREV_SHIFT 0U + +/* RAM magic offset */ +#define _PKA_RAM_START 0x400U +#define _PKA_RAM_SIZE 5336U + +/* ECDSA verification */ +#define _PKA_RAM_N_LEN 0x408U /* 64 */ +#define _PKA_RAM_P_LEN 0x4C8U /* 64 */ +#define _PKA_RAM_A_SIGN 0x468U /* 64 */ +#define _PKA_RAM_A 0x470U /* EOS */ +#define _PKA_RAM_P 0x4D0U /* EOS */ +#define _PKA_RAM_XG 0x678U /* EOS */ +#define _PKA_RAM_YG 0x6D0U /* EOS */ +#define _PKA_RAM_XQ 0x12F8U /* EOS */ +#define _PKA_RAM_YQ 0x1350U /* EOS */ +#define _PKA_RAM_SIGN_R 0x10E0U /* EOS */ +#define _PKA_RAM_SIGN_S 0xC68U /* EOS */ +#define _PKA_RAM_HASH_Z 0x13A8U /* EOS */ +#define _PKA_RAM_PRIME_N 0x1088U /* EOS */ +#define _PKA_RAM_ECDSA_VERIFY 0x5D0U /* 64 */ +#define _PKA_RAM_ECDSA_VERIFY_VALID 0xD60DULL +#define _PKA_RAM_ECDSA_VERIFY_INVALID 0xA3B7ULL + +#define PKA_TIMEOUT_US 1000000U +#define TIMEOUT_US_1MS 1000U +#define PKA_RESET_DELAY 20U + +struct curve_parameters { + uint32_t a_sign; /* 0 positive, 1 negative */ + uint8_t *a; /* Curve coefficient |a| */ + size_t a_size; + uint8_t *p; /* Curve modulus value */ + uint32_t p_len; + uint8_t *xg; /* Curve base point G coordinate x */ + size_t xg_size; + uint8_t *yg; /* Curve base point G coordinate y */ + size_t yg_size; + uint8_t *n; /* Curve prime order n */ + uint32_t n_len; +}; + +static const struct curve_parameters curve_def[] = { +#if PKA_USE_NIST_P256 + [PKA_NIST_P256] = { + .p_len = 256U, + .n_len = 256U, + .p = (uint8_t[]){0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, + .n = (uint8_t[]){0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xBC, 0xE6, 0xFA, 0xAD, 0xA7, 0x17, 0x9E, 0x84, + 0xF3, 0xB9, 0xCA, 0xC2, 0xFC, 0x63, 0x25, 0x51}, + .a_sign = 1U, + .a = (uint8_t[]){0x03}, + .a_size = 1U, + .xg = (uint8_t[]){0x6B, 0x17, 0xD1, 0xF2, 0xE1, 0x2C, 0x42, 0x47, + 0xF8, 0xBC, 0xE6, 0xE5, 0x63, 0xA4, 0x40, 0xF2, + 0x77, 0x03, 0x7D, 0x81, 0x2D, 0xEB, 0x33, 0xA0, + 0xF4, 0xA1, 0x39, 0x45, 0xD8, 0x98, 0xC2, 0x96}, + .xg_size = 32U, + .yg = (uint8_t[]){0x4F, 0xE3, 0x42, 0xE2, 0xFE, 0x1A, 0x7F, 0x9B, + 0x8E, 0xE7, 0xEB, 0x4A, 0x7C, 0x0F, 0x9E, 0x16, + 0x2B, 0xCE, 0x33, 0x57, 0x6B, 0x31, 0x5E, 0xCE, + 0xCB, 0xB6, 0x40, 0x68, 0x37, 0xBF, 0x51, 0xF5}, + .yg_size = 32U, + }, +#endif +#if PKA_USE_BRAINPOOL_P256R1 + [PKA_BRAINPOOL_P256R1] = { + .p_len = 256, + .n_len = 256, + .p = (uint8_t[]){0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, + 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72, + 0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28, + 0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x77}, + .n = (uint8_t[]){0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, + 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x71, + 0x8C, 0x39, 0x7A, 0xA3, 0xB5, 0x61, 0xA6, 0xF7, + 0x90, 0x1E, 0x0E, 0x82, 0x97, 0x48, 0x56, 0xA7}, + .a = (uint8_t[]){0x7D, 0x5A, 0x09, 0x75, 0xFC, 0x2C, 0x30, 0x57, + 0xEE, 0xF6, 0x75, 0x30, 0x41, 0x7A, 0xFF, 0xE7, + 0xFB, 0x80, 0x55, 0xC1, 0x26, 0xDC, 0x5C, 0x6C, + 0xE9, 0x4A, 0x4B, 0x44, 0xF3, 0x30, 0xB5, 0xD9}, + .a_size = 32U, + .xg = (uint8_t[]){0x8B, 0xD2, 0xAE, 0xB9, 0xCB, 0x7E, 0x57, 0xCB, + 0x2C, 0x4B, 0x48, 0x2F, 0xFC, 0x81, 0xB7, 0xAF, + 0xB9, 0xDE, 0x27, 0xE1, 0xE3, 0xBD, 0x23, 0xC2, + 0x3A, 0x44, 0x53, 0xBD, 0x9A, 0xCE, 0x32, 0x62}, + .xg_size = 32U, + .yg = (uint8_t[]){0x54, 0x7E, 0xF8, 0x35, 0xC3, 0xDA, 0xC4, 0xFD, + 0x97, 0xF8, 0x46, 0x1A, 0x14, 0x61, 0x1D, 0xC9, + 0xC2, 0x77, 0x45, 0x13, 0x2D, 0xED, 0x8E, 0x54, + 0x5C, 0x1D, 0x54, 0xC7, 0x2F, 0x04, 0x69, 0x97}, + .yg_size = 32U, + }, +#endif +#if PKA_USE_BRAINPOOL_P256T1 + [PKA_BRAINPOOL_P256T1] = { + .p_len = 256, + .n_len = 256, + .p = (uint8_t[]){0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, + 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72, + 0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28, + 0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x77}, + .n = (uint8_t[]){0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, + 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x71, + 0x8C, 0x39, 0x7A, 0xA3, 0xB5, 0x61, 0xA6, 0xF7, + 0x90, 0x1E, 0x0E, 0x82, 0x97, 0x48, 0x56, 0xA7}, + .a = (uint8_t[]){0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, + 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72, + 0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28, + 0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x74}, + .a_size = 32U, + .xg = (uint8_t[]){0xA3, 0xE8, 0xEB, 0x3C, 0xC1, 0xCF, 0xE7, 0xB7, + 0x73, 0x22, 0x13, 0xB2, 0x3A, 0x65, 0x61, 0x49, + 0xAF, 0xA1, 0x42, 0xC4, 0x7A, 0xAF, 0xBC, 0x2B, + 0x79, 0xA1, 0x91, 0x56, 0x2E, 0x13, 0x05, 0xF4}, + .xg_size = 32U, + .yg = (uint8_t[]){0x2D, 0x99, 0x6C, 0x82, 0x34, 0x39, 0xC5, 0x6D, + 0x7F, 0x7B, 0x22, 0xE1, 0x46, 0x44, 0x41, 0x7E, + 0x69, 0xBC, 0xB6, 0xDE, 0x39, 0xD0, 0x27, 0x00, + 0x1D, 0xAB, 0xE8, 0xF3, 0x5B, 0x25, 0xC9, 0xBE}, + .yg_size = 32U, + }, +#endif +#if PKA_USE_NIST_P521 + [PKA_NIST_P521] = { + .p_len = 521, + .n_len = 521, + .p = (uint8_t[]){ 0x01, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .n = (uint8_t[]){ 0x01, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, + 0x51, 0x86, 0x87, 0x83, 0xbf, 0x2f, 0x96, 0x6b, + 0x7f, 0xcc, 0x01, 0x48, 0xf7, 0x09, 0xa5, 0xd0, + 0x3b, 0xb5, 0xc9, 0xb8, 0x89, 0x9c, 0x47, 0xae, + 0xbb, 0x6f, 0xb7, 0x1e, 0x91, 0x38, 0x64, 0x09}, + .a_sign = 1, + .a = (uint8_t[]){0x03}, + .a_size = 1U, + .xg = (uint8_t[]){ 0xc6, + 0x85, 0x8e, 0x06, 0xb7, 0x04, 0x04, 0xe9, 0xcd, + 0x9e, 0x3e, 0xcb, 0x66, 0x23, 0x95, 0xb4, 0x42, + 0x9c, 0x64, 0x81, 0x39, 0x05, 0x3f, 0xb5, 0x21, + 0xf8, 0x28, 0xaf, 0x60, 0x6b, 0x4d, 0x3d, 0xba, + 0xa1, 0x4b, 0x5e, 0x77, 0xef, 0xe7, 0x59, 0x28, + 0xfe, 0x1d, 0xc1, 0x27, 0xa2, 0xff, 0xa8, 0xde, + 0x33, 0x48, 0xb3, 0xc1, 0x85, 0x6a, 0x42, 0x9b, + 0xf9, 0x7e, 0x7e, 0x31, 0xc2, 0xe5, 0xbd, 0x66}, + .xg_size = 65U, + .yg = (uint8_t[]){ 0x01, 0x18, + 0x39, 0x29, 0x6a, 0x78, 0x9a, 0x3b, 0xc0, 0x04, + 0x5c, 0x8a, 0x5f, 0xb4, 0x2c, 0x7d, 0x1b, 0xd9, + 0x98, 0xf5, 0x44, 0x49, 0x57, 0x9b, 0x44, 0x68, + 0x17, 0xaf, 0xbd, 0x17, 0x27, 0x3e, 0x66, 0x2c, + 0x97, 0xee, 0x72, 0x99, 0x5e, 0xf4, 0x26, 0x40, + 0xc5, 0x50, 0xb9, 0x01, 0x3f, 0xad, 0x07, 0x61, + 0x35, 0x3c, 0x70, 0x86, 0xa2, 0x72, 0xc2, 0x40, + 0x88, 0xbe, 0x94, 0x76, 0x9f, 0xd1, 0x66, 0x50}, + .yg_size = 66U, + }, +#endif +}; + +static struct stm32_pka_platdata pka_pdata; + +#pragma weak stm32_pka_get_platdata + +int stm32_pka_get_platdata(struct stm32_pka_platdata *pdata) +{ + return -ENODEV; +} + +static int stm32_pka_parse_fdt(void) +{ + int node; + struct dt_node_info info; + void *fdt; + + if (fdt_get_address(&fdt) == 0) { + return -FDT_ERR_NOTFOUND; + } + + node = dt_get_node(&info, -1, DT_PKA_COMPAT); + if (node < 0) { + ERROR("No PKA entry in DT\n"); + return -FDT_ERR_NOTFOUND; + } + + if (info.status == DT_DISABLED) { + return -FDT_ERR_NOTFOUND; + } + + if ((info.base == 0) || (info.clock < 0) || (info.reset < 0)) { + return -FDT_ERR_BADVALUE; + } + + pka_pdata.base = (uintptr_t)info.base; + pka_pdata.clock_id = (unsigned long)info.clock; + pka_pdata.reset_id = (unsigned int)info.reset; + + return 0; +} + +static int pka_wait_bit(uintptr_t base, uint32_t bit) +{ + uint64_t timeout = timeout_init_us(PKA_TIMEOUT_US); + + while ((mmio_read_32(base + _PKA_SR) & bit) != bit) { + if (timeout_elapsed(timeout)) { + WARN("timeout waiting %x\n", bit); + return -ETIMEDOUT; + } + } + + return 0; + +} + +static void pka_disable(uintptr_t base) +{ + mmio_clrbits_32(base + _PKA_CR, _PKA_CR_EN); +} + +static int pka_enable(uintptr_t base, uint32_t mode) +{ + /* Set mode and disable interrupts */ + mmio_clrsetbits_32(base + _PKA_CR, _PKA_IT_MASK | _PKA_CR_MODE_MASK, + _PKA_CR_MODE_MASK & (mode << _PKA_CR_MODE_SHIFT)); + + mmio_setbits_32(base + _PKA_CR, _PKA_CR_EN); + + return pka_wait_bit(base, _PKA_SR_INITOK); +} + +/* + * Data are already loaded in PKA internal RAM + * MODE is set + * We start process, and wait for its end. + */ +static int stm32_pka_process(uintptr_t base) +{ + mmio_setbits_32(base + _PKA_CR, _PKA_CR_START); + + return pka_wait_bit(base, _PKA_IT_PROCEND); +} + +/** + * @brief Write ECC operand to PKA RAM. + * @note PKA expect to write u64 word, each u64 are: the least significant bit is + * bit 0; the most significant bit is bit 63. + * We write eo_nbw (ECC operand Size) u64, value that depends of the chosen + * prime modulus length in bits. + * First less signicant u64 is written to low address + * Most significant u64 to higher address. + * And at last address we write a u64(0x0) + * @note This function doesn't only manage endianness (as bswap64 do), but also + * complete most significant incomplete u64 with 0 (if data is not a u64 + * multiple), and fill u64 last address with 0. + * @param addr: PKA_RAM address to write the buffer 'data' + * @param data: is a BYTE list with most significant bytes first + * @param data_size: nb of byte in data + * @param eo_nbw: is ECC Operand size in 64bits word (including the extra 0) + * (note it depends of the prime modulus length, not the data size) + * @retval 0 if OK. + * -EINVAL if data_size and eo_nbw are inconsistent, ie data doesn't + * fit in defined eo_nbw, or eo_nbw bigger than hardware limit. + */ +static int write_eo_data(uintptr_t addr, uint8_t *data, unsigned int data_size, + unsigned int eo_nbw) +{ + uint32_t word_index; + int data_index; + + if ((eo_nbw < OP_NBW_FROM_SIZE(data_size)) || (eo_nbw > MAX_EO_NBW)) { + return -EINVAL; + } + + /* Fill value */ + data_index = (int)data_size - 1; + for (word_index = 0U; word_index < eo_nbw; word_index++) { + uint64_t tmp = 0ULL; + unsigned int i = 0U; /* index in the tmp U64 word */ + + /* Stop if end of tmp or end of data */ + while ((i < sizeof(tmp)) && (data_index >= 0)) { + tmp |= (uint64_t)(data[data_index]) << (UINT8_LEN * i); + i++; /* Move byte index in current (u64)tmp */ + data_index--; /* Move to just next most significat byte */ + } + + mmio_write_64(addr + word_index * sizeof(tmp), tmp); + } + + return 0; +} + +static unsigned int get_ecc_op_nbword(enum stm32_pka_ecdsa_curve_id cid) +{ + if (cid >= ARRAY_SIZE(curve_def)) { + ERROR("CID %u is out of boundaries\n", cid); + panic(); + } + + return OP_NBW_FROM_LEN(curve_def[cid].n_len); +} + +static int stm32_pka_ecdsa_verif_configure_curve(uintptr_t base, enum stm32_pka_ecdsa_curve_id cid) +{ + int ret; + unsigned int eo_nbw = get_ecc_op_nbword(cid); + + mmio_write_64(base + _PKA_RAM_N_LEN, curve_def[cid].n_len); + mmio_write_64(base + _PKA_RAM_P_LEN, curve_def[cid].p_len); + mmio_write_64(base + _PKA_RAM_A_SIGN, curve_def[cid].a_sign); + + ret = write_eo_data(base + _PKA_RAM_A, curve_def[cid].a, curve_def[cid].a_size, eo_nbw); + if (ret < 0) { + return ret; + } + + ret = write_eo_data(base + _PKA_RAM_PRIME_N, + curve_def[cid].n, div_round_up(curve_def[cid].n_len, UINT8_LEN), + eo_nbw); + if (ret < 0) { + return ret; + } + + ret = write_eo_data(base + _PKA_RAM_P, curve_def[cid].p, + div_round_up(curve_def[cid].p_len, UINT8_LEN), eo_nbw); + if (ret < 0) { + return ret; + } + + ret = write_eo_data(base + _PKA_RAM_XG, curve_def[cid].xg, curve_def[cid].xg_size, eo_nbw); + if (ret < 0) { + return ret; + } + + ret = write_eo_data(base + _PKA_RAM_YG, curve_def[cid].yg, curve_def[cid].yg_size, eo_nbw); + if (ret < 0) { + return ret; + } + + return 0; +} + +static int stm32_pka_ecdsa_verif_check_return(uintptr_t base) +{ + uint64_t value; + uint32_t sr; + + sr = mmio_read_32(base + _PKA_SR); + if ((sr & (_PKA_IT_OPERR | _PKA_IT_ADDRERR | _PKA_IT_RAMERR)) != 0) { + WARN("Detected error(s): %s%s%s\n", + (sr & _PKA_IT_OPERR) ? "Operation " : "", + (sr & _PKA_IT_ADDRERR) ? "Address " : "", + (sr & _PKA_IT_RAMERR) ? "RAM" : ""); + return -EINVAL; + } + + value = mmio_read_64(base + _PKA_RAM_ECDSA_VERIFY); + if (value == _PKA_RAM_ECDSA_VERIFY_VALID) { + return 0; + } + + if (value == _PKA_RAM_ECDSA_VERIFY_INVALID) { + return -EAUTH; + } + + return -EINVAL; +} + +/** + * @brief Check if BigInt stored in data is 0 + * + * @param data: a BYTE array with most significant bytes first + * @param size: data size + * + * @retval: true: if data represents a 0 value (ie all bytes == 0) + * false: if data represents a non-zero value. + */ +static bool is_zero(uint8_t *data, unsigned int size) +{ + unsigned int i; + + for (i = 0U; i < size; i++) { + if (data[i] != 0U) { + return false; + } + } + + return true; +} + +/** + * @brief Compare two BigInt: + * @param xdata_a: a BYTE array with most significant bytes first + * @param size_a: nb of Byte of 'a' + * @param data_b: a BYTE array with most significant bytes first + * @param size_b: nb of Byte of 'b' + * + * @retval: true if data_a < data_b + * false if data_a >= data_b + */ +static bool is_smaller(uint8_t *data_a, unsigned int size_a, + uint8_t *data_b, unsigned int size_b) +{ + unsigned int i; + + i = MAX(size_a, size_b) + 1U; + do { + uint8_t a, b; + + i--; + if (size_a < i) { + a = 0U; + } else { + a = data_a[size_a - i]; + } + + if (size_b < i) { + b = 0U; + } else { + b = data_b[size_b - i]; + } + + if (a < b) { + return true; + } + + if (a > b) { + return false; + } + } while (i != 0U); + + return false; +} + +static int stm32_pka_ecdsa_check_param(void *sig_r_ptr, unsigned int sig_r_size, + void *sig_s_ptr, unsigned int sig_s_size, + void *pk_x_ptr, unsigned int pk_x_size, + void *pk_y_ptr, unsigned int pk_y_size, + enum stm32_pka_ecdsa_curve_id cid) +{ + /* Public Key check */ + /* Check Xq < p */ + if (!is_smaller(pk_x_ptr, pk_x_size, + curve_def[cid].p, div_round_up(curve_def[cid].p_len, UINT8_LEN))) { + WARN("%s Xq < p inval\n", __func__); + return -EINVAL; + } + + /* Check Yq < p */ + if (!is_smaller(pk_y_ptr, pk_y_size, + curve_def[cid].p, div_round_up(curve_def[cid].p_len, UINT8_LEN))) { + WARN("%s Yq < p inval\n", __func__); + return -EINVAL; + } + + /* Signature check */ + /* Check 0 < r < n */ + if (!is_smaller(sig_r_ptr, sig_r_size, + curve_def[cid].n, div_round_up(curve_def[cid].n_len, UINT8_LEN)) && + !is_zero(sig_r_ptr, sig_r_size)) { + WARN("%s 0< r < n inval\n", __func__); + return -EINVAL; + } + + /* Check 0 < s < n */ + if (!is_smaller(sig_s_ptr, sig_s_size, + curve_def[cid].n, div_round_up(curve_def[cid].n_len, UINT8_LEN)) && + !is_zero(sig_s_ptr, sig_s_size)) { + WARN("%s 0< s < n inval\n", __func__); + return -EINVAL; + } + + return 0; +} + +/* + * @brief Initialize the PKA driver. + * @param None. + * @retval 0 if OK, negative value else. + */ +int stm32_pka_init(void) +{ + int err; +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + uint32_t ver; + uint32_t id; +#endif + + err = stm32_pka_parse_fdt(); + if (err != 0) { + err = stm32_pka_get_platdata(&pka_pdata); + if (err != 0) { + return err; + } + } + + clk_enable(pka_pdata.clock_id); + + if (stm32mp_reset_assert((unsigned long)pka_pdata.reset_id, TIMEOUT_US_1MS) != 0) { + panic(); + } + + udelay(PKA_RESET_DELAY); + if (stm32mp_reset_deassert((unsigned long)pka_pdata.reset_id, TIMEOUT_US_1MS) != 0) { + panic(); + } + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + id = mmio_read_32(pka_pdata.base + _PKA_IPIDR); + ver = mmio_read_32(pka_pdata.base + _PKA_VERR); + + VERBOSE("STM32 PKA[%x] V%u.%u\n", id, + (ver & _PKA_VERR_MAJREV_MASK) >> _PKA_VERR_MAJREV_SHIFT, + (ver & _PKA_VERR_MINREV_MASK) >> _PKA_VERR_MINREV_SHIFT); +#endif + return 0; +} + +int stm32_pka_ecdsa_verif(void *hash, unsigned int hash_size, + void *sig_r_ptr, unsigned int sig_r_size, + void *sig_s_ptr, unsigned int sig_s_size, + void *pk_x_ptr, unsigned int pk_x_size, + void *pk_y_ptr, unsigned int pk_y_size, + enum stm32_pka_ecdsa_curve_id cid) +{ + int ret; + uintptr_t base = pka_pdata.base; + unsigned int eo_nbw = get_ecc_op_nbword(cid); + + if ((hash == NULL) || (sig_r_ptr == NULL) || (sig_s_ptr == NULL) || + (pk_x_ptr == NULL) || (pk_y_ptr == NULL)) { + INFO("%s invalid input param\n", __func__); + return -EINVAL; + } + + ret = stm32_pka_ecdsa_check_param(sig_r_ptr, sig_r_size, + sig_s_ptr, sig_s_size, + pk_x_ptr, pk_x_size, + pk_y_ptr, pk_y_size, + cid); + if (ret < 0) { + INFO("%s check param error %d\n", __func__, ret); + goto out; + } + + if ((mmio_read_32(base + _PKA_SR) & _PKA_SR_BUSY) == _PKA_SR_BUSY) { + INFO("%s busy\n", __func__); + ret = -EBUSY; + goto out; + } + + /* Fill PKA RAM */ + /* With curve id values */ + ret = stm32_pka_ecdsa_verif_configure_curve(base, cid); + if (ret < 0) { + goto out; + } + + /* With pubkey */ + ret = write_eo_data(base + _PKA_RAM_XQ, pk_x_ptr, pk_x_size, eo_nbw); + if (ret < 0) { + goto out; + } + + ret = write_eo_data(base + _PKA_RAM_YQ, pk_y_ptr, pk_y_size, eo_nbw); + if (ret < 0) { + goto out; + } + + /* With hash */ + ret = write_eo_data(base + _PKA_RAM_HASH_Z, hash, hash_size, eo_nbw); + if (ret < 0) { + goto out; + } + + /* With signature */ + ret = write_eo_data(base + _PKA_RAM_SIGN_R, sig_r_ptr, sig_r_size, eo_nbw); + if (ret < 0) { + goto out; + } + + ret = write_eo_data(base + _PKA_RAM_SIGN_S, sig_s_ptr, sig_s_size, eo_nbw); + if (ret < 0) { + goto out; + } + + /* Set mode to ecdsa signature verification */ + ret = pka_enable(base, _PKA_CR_MODE_ECDSA_VERIF); + if (ret < 0) { + WARN("%s set mode pka error %d\n", __func__, ret); + goto out; + } + + /* Start processing and wait end */ + ret = stm32_pka_process(base); + if (ret < 0) { + WARN("%s process error %d\n", __func__, ret); + goto out; + } + + /* Check return status */ + ret = stm32_pka_ecdsa_verif_check_return(base); + + /* Unset end proc */ + mmio_setbits_32(base + _PKA_CLRFR, _PKA_IT_PROCEND); + +out: + /* Disable PKA (will stop all pending proccess and reset RAM) */ + pka_disable(base); + + return ret; +} diff --git a/drivers/st/crypto/stm32_rng.c b/drivers/st/crypto/stm32_rng.c new file mode 100644 index 000000000..a9dc43f8d --- /dev/null +++ b/drivers/st/crypto/stm32_rng.c @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> + +#include <arch_helpers.h> +#include <drivers/clk.h> +#include <drivers/delay_timer.h> +#include <drivers/st/stm32_rng.h> +#include <drivers/st/stm32mp_reset.h> +#include <lib/mmio.h> +#include <libfdt.h> + +#include <platform_def.h> + +#if STM32_RNG_VER == 2 +#define DT_RNG_COMPAT "st,stm32-rng" +#endif +#if STM32_RNG_VER == 4 +#define DT_RNG_COMPAT "st,stm32mp13-rng" +#endif +#define RNG_CR 0x00U +#define RNG_SR 0x04U +#define RNG_DR 0x08U + +#define RNG_CR_RNGEN BIT(2) +#define RNG_CR_IE BIT(3) +#define RNG_CR_CED BIT(5) +#define RNG_CR_CLKDIV GENMASK(19, 16) +#define RNG_CR_CLKDIV_SHIFT 16U +#define RNG_CR_CONDRST BIT(30) + +#define RNG_SR_DRDY BIT(0) +#define RNG_SR_CECS BIT(1) +#define RNG_SR_SECS BIT(2) +#define RNG_SR_CEIS BIT(5) +#define RNG_SR_SEIS BIT(6) + +#define RNG_TIMEOUT_US 100000U +#define RNG_TIMEOUT_STEP_US 10U + +#define TIMEOUT_US_1MS 1000U + +#define RNG_NIST_CONFIG_A 0x00F40F00U +#define RNG_NIST_CONFIG_B 0x01801000U +#define RNG_NIST_CONFIG_C 0x00F00D00U +#define RNG_NIST_CONFIG_MASK GENMASK(25, 8) + +#define RNG_MAX_NOISE_CLK_FREQ 48000000U + +struct stm32_rng_instance { + uintptr_t base; + unsigned long clock; +}; + +static struct stm32_rng_instance stm32_rng; + +static void seed_error_recovery(void) +{ + uint8_t i __maybe_unused; + + /* Recommended by the SoC reference manual */ + mmio_clrbits_32(stm32_rng.base + RNG_SR, RNG_SR_SEIS); + dmbsy(); + +#if STM32_RNG_VER == 2 + /* No Auto-reset on version 2, need to clean FIFO */ + for (i = 12U; i != 0U; i--) { + (void)mmio_read_32(stm32_rng.base + RNG_DR); + } + + dmbsy(); +#endif + + if ((mmio_read_32(stm32_rng.base + RNG_SR) & RNG_SR_SEIS) != 0U) { + ERROR("RNG noise\n"); + panic(); + } +} + +static uint32_t stm32_rng_clock_freq_restrain(void) +{ + unsigned long clock_rate; + uint32_t clock_div = 0U; + + clock_rate = clk_get_rate(stm32_rng.clock); + + /* + * Get the exponent to apply on the CLKDIV field in RNG_CR register + * No need to handle the case when clock-div > 0xF as it is physically + * impossible + */ + while ((clock_rate >> clock_div) > RNG_MAX_NOISE_CLK_FREQ) { + clock_div++; + } + + VERBOSE("RNG clk rate : %lu\n", clk_get_rate(stm32_rng.clock) >> clock_div); + + return clock_div; +} + +static int stm32_rng_enable(void) +{ + uint32_t sr; + uint64_t timeout; + uint32_t clock_div __maybe_unused; + +#if STM32_RNG_VER == 2 + mmio_write_32(stm32_rng.base + RNG_CR, RNG_CR_RNGEN | RNG_CR_CED); +#endif +#if STM32_RNG_VER == 4 + /* Reset internal block and disable CED bit */ + clock_div = stm32_rng_clock_freq_restrain(); + + /* Update configuration fields */ + mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_NIST_CONFIG_MASK, + RNG_NIST_CONFIG_A | RNG_CR_CONDRST | RNG_CR_CED); + + mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_CR_CLKDIV, + (clock_div << RNG_CR_CLKDIV_SHIFT)); + + mmio_clrsetbits_32(stm32_rng.base + RNG_CR, RNG_CR_CONDRST, RNG_CR_RNGEN); +#endif + timeout = timeout_init_us(RNG_TIMEOUT_US); + sr = mmio_read_32(stm32_rng.base + RNG_SR); + while ((sr & RNG_SR_DRDY) == 0U) { + if (timeout_elapsed(timeout)) { + WARN("Timeout waiting\n"); + return -ETIMEDOUT; + } + + if ((sr & (RNG_SR_SECS | RNG_SR_SEIS)) != 0U) { + seed_error_recovery(); + timeout = timeout_init_us(RNG_TIMEOUT_US); + } + + udelay(RNG_TIMEOUT_STEP_US); + sr = mmio_read_32(stm32_rng.base + RNG_SR); + } + + VERBOSE("Init RNG done\n"); + + return 0; +} + +/* + * stm32_rng_read - Read a number of random bytes from RNG + * out: pointer to the output buffer + * size: number of bytes to be read + * Return 0 on success, non-0 on failure + */ +int stm32_rng_read(uint8_t *out, uint32_t size) +{ + uint8_t *buf = out; + size_t len = size; + int nb_tries; + uint32_t data32; + int rc = 0; + unsigned int count; + + if (stm32_rng.base == 0U) { + return -EPERM; + } + + while (len != 0U) { + nb_tries = RNG_TIMEOUT_US / RNG_TIMEOUT_STEP_US; + do { + uint32_t status = mmio_read_32(stm32_rng.base + RNG_SR); + + if ((status & (RNG_SR_SECS | RNG_SR_SEIS)) != 0U) { + seed_error_recovery(); + } + + udelay(RNG_TIMEOUT_STEP_US); + nb_tries--; + if (nb_tries == 0) { + rc = -ETIMEDOUT; + goto bail; + } + } while ((mmio_read_32(stm32_rng.base + RNG_SR) & + RNG_SR_DRDY) == 0U); + + count = 4U; + while (len != 0U) { + data32 = mmio_read_32(stm32_rng.base + RNG_DR); + count--; + + memcpy(buf, &data32, MIN(len, sizeof(uint32_t))); + buf += MIN(len, sizeof(uint32_t)); + len -= MIN(len, sizeof(uint32_t)); + + if (count == 0U) { + break; + } + } + } + +bail: + if (rc != 0) { + memset(out, 0, buf - out); + } + + return rc; +} + +/* + * stm32_rng_init: Initialize rng from DT + * return 0 on success, negative value on failure + */ +int stm32_rng_init(void) +{ + void *fdt; + struct dt_node_info dt_rng; + int node; + + if (stm32_rng.base != 0U) { + /* Driver is already initialized */ + return 0; + } + + if (fdt_get_address(&fdt) == 0) { + panic(); + } + + node = dt_get_node(&dt_rng, -1, DT_RNG_COMPAT); + if (node < 0) { + return 0; + } + + if (dt_rng.status == DT_DISABLED) { + return 0; + } + + assert(dt_rng.base != 0U); + + stm32_rng.base = dt_rng.base; + + if (dt_rng.clock < 0) { + panic(); + } + + stm32_rng.clock = (unsigned long)dt_rng.clock; + clk_enable(stm32_rng.clock); + + if (dt_rng.reset >= 0) { + int ret; + + ret = stm32mp_reset_assert((unsigned long)dt_rng.reset, + TIMEOUT_US_1MS); + if (ret != 0) { + panic(); + } + + udelay(20); + + ret = stm32mp_reset_deassert((unsigned long)dt_rng.reset, + TIMEOUT_US_1MS); + if (ret != 0) { + panic(); + } + } + + return stm32_rng_enable(); +} diff --git a/drivers/st/crypto/stm32_saes.c b/drivers/st/crypto/stm32_saes.c new file mode 100644 index 000000000..02baf2127 --- /dev/null +++ b/drivers/st/crypto/stm32_saes.c @@ -0,0 +1,913 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <assert.h> +#include <endian.h> +#include <errno.h> +#include <stdint.h> + +#include <drivers/clk.h> +#include <drivers/delay_timer.h> +#include <drivers/st/stm32_saes.h> +#include <drivers/st/stm32mp_reset.h> +#include <lib/mmio.h> +#include <lib/utils_def.h> +#include <libfdt.h> + +#include <platform_def.h> + +#define UINT8_BIT 8U +#define AES_BLOCK_SIZE_BIT 128U +#define AES_BLOCK_SIZE (AES_BLOCK_SIZE_BIT / UINT8_BIT) + +#define AES_KEYSIZE_128 16U +#define AES_KEYSIZE_256 32U +#define AES_IVSIZE 16U + +/* SAES control register */ +#define _SAES_CR 0x0U +/* SAES status register */ +#define _SAES_SR 0x04U +/* SAES data input register */ +#define _SAES_DINR 0x08U +/* SAES data output register */ +#define _SAES_DOUTR 0x0CU +/* SAES key registers [0-3] */ +#define _SAES_KEYR0 0x10U +#define _SAES_KEYR1 0x14U +#define _SAES_KEYR2 0x18U +#define _SAES_KEYR3 0x1CU +/* SAES initialization vector registers [0-3] */ +#define _SAES_IVR0 0x20U +#define _SAES_IVR1 0x24U +#define _SAES_IVR2 0x28U +#define _SAES_IVR3 0x2CU +/* SAES key registers [4-7] */ +#define _SAES_KEYR4 0x30U +#define _SAES_KEYR5 0x34U +#define _SAES_KEYR6 0x38U +#define _SAES_KEYR7 0x3CU +/* SAES suspend registers [0-7] */ +#define _SAES_SUSPR0 0x40U +#define _SAES_SUSPR1 0x44U +#define _SAES_SUSPR2 0x48U +#define _SAES_SUSPR3 0x4CU +#define _SAES_SUSPR4 0x50U +#define _SAES_SUSPR5 0x54U +#define _SAES_SUSPR6 0x58U +#define _SAES_SUSPR7 0x5CU +/* SAES Interrupt Enable Register */ +#define _SAES_IER 0x300U +/* SAES Interrupt Status Register */ +#define _SAES_ISR 0x304U +/* SAES Interrupt Clear Register */ +#define _SAES_ICR 0x308U + +/* SAES control register fields */ +#define _SAES_CR_RESET_VALUE 0x0U +#define _SAES_CR_IPRST BIT(31) +#define _SAES_CR_KEYSEL_MASK GENMASK(30, 28) +#define _SAES_CR_KEYSEL_SHIFT 28U +#define _SAES_CR_KEYSEL_SOFT 0x0U +#define _SAES_CR_KEYSEL_DHUK 0x1U +#define _SAES_CR_KEYSEL_BHK 0x2U +#define _SAES_CR_KEYSEL_BHU_XOR_BH_K 0x4U +#define _SAES_CR_KEYSEL_TEST 0x7U +#define _SAES_CR_KSHAREID_MASK GENMASK(27, 26) +#define _SAES_CR_KSHAREID_SHIFT 26U +#define _SAES_CR_KSHAREID_CRYP 0x0U +#define _SAES_CR_KEYMOD_MASK GENMASK(25, 24) +#define _SAES_CR_KEYMOD_SHIFT 24U +#define _SAES_CR_KEYMOD_NORMAL 0x0U +#define _SAES_CR_KEYMOD_WRAPPED 0x1U +#define _SAES_CR_KEYMOD_SHARED 0x2U +#define _SAES_CR_NPBLB_MASK GENMASK(23, 20) +#define _SAES_CR_NPBLB_SHIFT 20U +#define _SAES_CR_KEYPROT BIT(19) +#define _SAES_CR_KEYSIZE BIT(18) +#define _SAES_CR_GCMPH_MASK GENMASK(14, 13) +#define _SAES_CR_GCMPH_SHIFT 13U +#define _SAES_CR_GCMPH_INIT 0U +#define _SAES_CR_GCMPH_HEADER 1U +#define _SAES_CR_GCMPH_PAYLOAD 2U +#define _SAES_CR_GCMPH_FINAL 3U +#define _SAES_CR_DMAOUTEN BIT(12) +#define _SAES_CR_DMAINEN BIT(11) +#define _SAES_CR_CHMOD_MASK (BIT(16) | GENMASK(6, 5)) +#define _SAES_CR_CHMOD_SHIFT 5U +#define _SAES_CR_CHMOD_ECB 0x0U +#define _SAES_CR_CHMOD_CBC 0x1U +#define _SAES_CR_CHMOD_CTR 0x2U +#define _SAES_CR_CHMOD_GCM 0x3U +#define _SAES_CR_CHMOD_GMAC 0x3U +#define _SAES_CR_CHMOD_CCM 0x800U +#define _SAES_CR_MODE_MASK GENMASK(4, 3) +#define _SAES_CR_MODE_SHIFT 3U +#define _SAES_CR_MODE_ENC 0U +#define _SAES_CR_MODE_KEYPREP 1U +#define _SAES_CR_MODE_DEC 2U +#define _SAES_CR_DATATYPE_MASK GENMASK(2, 1) +#define _SAES_CR_DATATYPE_SHIFT 1U +#define _SAES_CR_DATATYPE_NONE 0U +#define _SAES_CR_DATATYPE_HALF_WORD 1U +#define _SAES_CR_DATATYPE_BYTE 2U +#define _SAES_CR_DATATYPE_BIT 3U +#define _SAES_CR_EN BIT(0) + +/* SAES status register fields */ +#define _SAES_SR_KEYVALID BIT(7) +#define _SAES_SR_BUSY BIT(3) +#define _SAES_SR_WRERR BIT(2) +#define _SAES_SR_RDERR BIT(1) +#define _SAES_SR_CCF BIT(0) + +/* SAES interrupt registers fields */ +#define _SAES_I_RNG_ERR BIT(3) +#define _SAES_I_KEY_ERR BIT(2) +#define _SAES_I_RW_ERR BIT(1) +#define _SAES_I_CC BIT(0) + +#define SAES_TIMEOUT_US 100000U +#define TIMEOUT_US_1MS 1000U +#define SAES_RESET_DELAY 20U + +#define IS_CHAINING_MODE(mod, cr) \ + (((cr) & _SAES_CR_CHMOD_MASK) == (_SAES_CR_CHMOD_##mod << _SAES_CR_CHMOD_SHIFT)) + +#define SET_CHAINING_MODE(mod, cr) \ + mmio_clrsetbits_32((cr), _SAES_CR_CHMOD_MASK, _SAES_CR_CHMOD_##mod << _SAES_CR_CHMOD_SHIFT) + +#define pragma weak stm32_saes_get_platdata + +static struct stm32_saes_platdata saes_pdata; + +int stm32_saes_get_platdata(struct stm32_saes_platdata *pdata) +{ + return -ENODEV; +} + +static int stm32_saes_parse_fdt(struct stm32_saes_platdata *pdata) +{ + int node; + struct dt_node_info info; + void *fdt; + + if (fdt_get_address(&fdt) == 0) { + return -FDT_ERR_NOTFOUND; + } + + node = dt_get_node(&info, -1, DT_SAES_COMPAT); + if (node < 0) { + ERROR("No SAES entry in DT\n"); + return -FDT_ERR_NOTFOUND; + } + + if (info.status == DT_DISABLED) { + return -FDT_ERR_NOTFOUND; + } + + if ((info.base == 0U) || (info.clock < 0) || (info.reset < 0)) { + return -FDT_ERR_BADVALUE; + } + + pdata->base = (uintptr_t)info.base; + pdata->clock_id = (unsigned long)info.clock; + pdata->reset_id = (unsigned int)info.reset; + + return 0; +} + +static bool does_chaining_mode_need_iv(uint32_t cr) +{ + return !(IS_CHAINING_MODE(ECB, cr)); +} + +static bool is_encrypt(uint32_t cr) +{ + return (cr & _SAES_CR_MODE_MASK) == (_SAES_CR_MODE_ENC << _SAES_CR_MODE_SHIFT); +} + +static bool is_decrypt(uint32_t cr) +{ + return (cr & _SAES_CR_MODE_MASK) == (_SAES_CR_MODE_DEC << _SAES_CR_MODE_SHIFT); +} + +static int wait_computation_completed(uintptr_t base) +{ + uint64_t timeout = timeout_init_us(SAES_TIMEOUT_US); + + while ((mmio_read_32(base + _SAES_SR) & _SAES_SR_CCF) != _SAES_SR_CCF) { + if (timeout_elapsed(timeout)) { + WARN("%s: timeout\n", __func__); + return -ETIMEDOUT; + } + } + + return 0; +} + +static void clear_computation_completed(uintptr_t base) +{ + mmio_setbits_32(base + _SAES_ICR, _SAES_I_CC); +} + +static int saes_start(struct stm32_saes_context *ctx) +{ + uint64_t timeout; + + /* Reset IP */ + mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); + udelay(SAES_RESET_DELAY); + mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); + + timeout = timeout_init_us(SAES_TIMEOUT_US); + while ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) == _SAES_SR_BUSY) { + if (timeout_elapsed(timeout)) { + WARN("%s: timeout\n", __func__); + return -ETIMEDOUT; + } + } + + return 0; +} + +static void saes_end(struct stm32_saes_context *ctx, int prev_error) +{ + if (prev_error != 0) { + /* Reset IP */ + mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); + udelay(SAES_RESET_DELAY); + mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); + } + + /* Disable the SAES peripheral */ + mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN); +} + +static void saes_write_iv(struct stm32_saes_context *ctx) +{ + /* If chaining mode need to restore IV */ + if (does_chaining_mode_need_iv(ctx->cr)) { + uint8_t i; + + /* Restore the _SAES_IVRx */ + for (i = 0U; i < AES_IVSIZE / sizeof(uint32_t); i++) { + mmio_write_32(ctx->base + _SAES_IVR0 + i * sizeof(uint32_t), ctx->iv[i]); + } + } + +} + +static void saes_write_key(struct stm32_saes_context *ctx) +{ + /* Restore the _SAES_KEYRx if SOFTWARE key */ + if ((ctx->cr & _SAES_CR_KEYSEL_MASK) == (_SAES_CR_KEYSEL_SOFT << _SAES_CR_KEYSEL_SHIFT)) { + uint8_t i; + + for (i = 0U; i < AES_KEYSIZE_128 / sizeof(uint32_t); i++) { + mmio_write_32(ctx->base + _SAES_KEYR0 + i * sizeof(uint32_t), ctx->key[i]); + } + + if ((ctx->cr & _SAES_CR_KEYSIZE) == _SAES_CR_KEYSIZE) { + for (i = 0U; i < (AES_KEYSIZE_256 / 2U) / sizeof(uint32_t); i++) { + mmio_write_32(ctx->base + _SAES_KEYR4 + i * sizeof(uint32_t), + ctx->key[i + 4U]); + } + } + } +} + +static int saes_prepare_key(struct stm32_saes_context *ctx) +{ + /* Disable the SAES peripheral */ + mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN); + + /* Set key size */ + if ((ctx->cr & _SAES_CR_KEYSIZE) != 0U) { + mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_KEYSIZE); + } else { + mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_KEYSIZE); + } + + saes_write_key(ctx); + + /* For ECB/CBC decryption, key preparation mode must be selected to populate the key */ + if ((IS_CHAINING_MODE(ECB, ctx->cr) || IS_CHAINING_MODE(CBC, ctx->cr)) && + is_decrypt(ctx->cr)) { + int ret; + + /* Select Mode 2 */ + mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_MODE_MASK, + _SAES_CR_MODE_KEYPREP << _SAES_CR_MODE_SHIFT); + + /* Enable SAES */ + mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN); + + /* Wait Computation completed */ + ret = wait_computation_completed(ctx->base); + if (ret != 0) { + return ret; + } + + clear_computation_completed(ctx->base); + + /* Set Mode 3 */ + mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_MODE_MASK, + _SAES_CR_MODE_DEC << _SAES_CR_MODE_SHIFT); + } + + return 0; +} + +static int save_context(struct stm32_saes_context *ctx) +{ + if ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_CCF) != 0U) { + /* Device should not be in a processing phase */ + return -EINVAL; + } + + /* Save CR */ + ctx->cr = mmio_read_32(ctx->base + _SAES_CR); + + /* If chaining mode need to save current IV */ + if (does_chaining_mode_need_iv(ctx->cr)) { + uint8_t i; + + /* Save IV */ + for (i = 0U; i < AES_IVSIZE / sizeof(uint32_t); i++) { + ctx->iv[i] = mmio_read_32(ctx->base + _SAES_IVR0 + i * sizeof(uint32_t)); + } + } + + /* Disable the SAES peripheral */ + mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN); + + return 0; +} + +/* To resume the processing of a message */ +static int restore_context(struct stm32_saes_context *ctx) +{ + int ret; + + /* IP should be disabled */ + if ((mmio_read_32(ctx->base + _SAES_CR) & _SAES_CR_EN) != 0U) { + VERBOSE("%s: Device is still enabled\n", __func__); + return -EINVAL; + } + + /* Reset internal state */ + mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST); + + /* Restore the _SAES_CR */ + mmio_write_32(ctx->base + _SAES_CR, ctx->cr); + + /* Preparation decrypt key */ + ret = saes_prepare_key(ctx); + if (ret != 0) { + return ret; + } + + saes_write_iv(ctx); + + /* Enable the SAES peripheral */ + mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN); + + return 0; +} + +/** + * @brief Initialize SAES driver. + * @param None. + * @retval 0 if OK; negative value else. + */ +int stm32_saes_driver_init(void) +{ + int err; + + err = stm32_saes_parse_fdt(&saes_pdata); + if (err != 0) { + err = stm32_saes_get_platdata(&saes_pdata); + if (err != 0) { + return err; + } + } + + clk_enable(saes_pdata.clock_id); + if (stm32mp_reset_assert(saes_pdata.reset_id, TIMEOUT_US_1MS) != 0) { + panic(); + } + + udelay(SAES_RESET_DELAY); + if (stm32mp_reset_deassert(saes_pdata.reset_id, TIMEOUT_US_1MS) != 0) { + panic(); + } + + return 0; +} + +/** + * @brief Start a AES computation. + * @param ctx: SAES process context + * @param is_dec: true if decryption, false if encryption + * @param ch_mode: define the chaining mode + * @param key_select: define where the key comes from. + * @param key: pointer to key (if key_select is KEY_SOFT, else unused) + * @param key_size: key size + * @param iv: pointer to initialization vectore (unsed if ch_mode is ECB) + * @param iv_size: iv size + * @note this function doesn't access to hardware but store in ctx the values + * + * @retval 0 if OK; negative value else. + */ +int stm32_saes_init(struct stm32_saes_context *ctx, bool is_dec, + enum stm32_saes_chaining_mode ch_mode, enum stm32_saes_key_selection key_select, + const void *key, size_t key_size, const void *iv, size_t iv_size) +{ + unsigned int i; + const uint32_t *iv_u32; + const uint32_t *key_u32; + + ctx->assoc_len = 0U; + ctx->load_len = 0U; + + ctx->base = saes_pdata.base; + ctx->cr = _SAES_CR_RESET_VALUE; + + /* We want buffer to be u32 aligned */ + assert((uintptr_t)key % __alignof__(uint32_t) == 0); + assert((uintptr_t)iv % __alignof__(uint32_t) == 0); + + iv_u32 = iv; + key_u32 = key; + + if (is_dec) { + /* Save Mode 3 = decrypt */ + mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_MODE_MASK, + _SAES_CR_MODE_DEC << _SAES_CR_MODE_SHIFT); + } else { + /* Save Mode 1 = crypt */ + mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_MODE_MASK, + _SAES_CR_MODE_ENC << _SAES_CR_MODE_SHIFT); + } + + /* Save chaining mode */ + switch (ch_mode) { + case STM32_SAES_MODE_ECB: + SET_CHAINING_MODE(ECB, (uintptr_t)&(ctx->cr)); + break; + case STM32_SAES_MODE_CBC: + SET_CHAINING_MODE(CBC, (uintptr_t)&(ctx->cr)); + break; + case STM32_SAES_MODE_CTR: + SET_CHAINING_MODE(CTR, (uintptr_t)&(ctx->cr)); + break; + case STM32_SAES_MODE_GCM: + SET_CHAINING_MODE(GCM, (uintptr_t)&(ctx->cr)); + break; + case STM32_SAES_MODE_CCM: + SET_CHAINING_MODE(CCM, (uintptr_t)&(ctx->cr)); + break; + default: + return -EINVAL; + } + + /* We will use HW Byte swap (_SAES_CR_DATATYPE_BYTE) for data. + * so we won't need to + * htobe32(data) before write to DINR + * nor + * be32toh after reading from DOUTR + * + * But note that wrap key only accept _SAES_CR_DATATYPE_NONE + */ + mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_DATATYPE_MASK, + _SAES_CR_DATATYPE_BYTE << _SAES_CR_DATATYPE_SHIFT); + + /* Configure keysize */ + switch (key_size) { + case AES_KEYSIZE_128: + mmio_clrbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSIZE); + break; + case AES_KEYSIZE_256: + mmio_setbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSIZE); + break; + default: + return -EINVAL; + } + + /* Configure key */ + switch (key_select) { + case STM32_SAES_KEY_SOFT: + mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK, + _SAES_CR_KEYSEL_SOFT << _SAES_CR_KEYSEL_SHIFT); + /* Save key */ + switch (key_size) { + case AES_KEYSIZE_128: + /* First 16 bytes == 4 u32 */ + for (i = 0U; i < AES_KEYSIZE_128 / sizeof(uint32_t); i++) { + mmio_write_32((uintptr_t)(ctx->key + i), htobe32(key_u32[3 - i])); + /* /!\ we save the key in HW byte order + * and word order : key[i] is for _SAES_KEYRi + */ + } + break; + case AES_KEYSIZE_256: + for (i = 0U; i < AES_KEYSIZE_256 / sizeof(uint32_t); i++) { + mmio_write_32((uintptr_t)(ctx->key + i), htobe32(key_u32[7 - i])); + /* /!\ we save the key in HW byte order + * and word order : key[i] is for _SAES_KEYRi + */ + } + break; + default: + return -EINVAL; + } + + break; + case STM32_SAES_KEY_DHU: + mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK, + _SAES_CR_KEYSEL_DHUK << _SAES_CR_KEYSEL_SHIFT); + break; + case STM32_SAES_KEY_BH: + mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK, + _SAES_CR_KEYSEL_BHK << _SAES_CR_KEYSEL_SHIFT); + break; + case STM32_SAES_KEY_BHU_XOR_BH: + mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK, + _SAES_CR_KEYSEL_BHU_XOR_BH_K << _SAES_CR_KEYSEL_SHIFT); + break; + case STM32_SAES_KEY_WRAPPED: + mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK, + _SAES_CR_KEYSEL_SOFT << _SAES_CR_KEYSEL_SHIFT); + break; + + default: + return -EINVAL; + } + + /* Save IV */ + if (ch_mode != STM32_SAES_MODE_ECB) { + if ((iv == NULL) || (iv_size != AES_IVSIZE)) { + return -EINVAL; + } + + for (i = 0U; i < AES_IVSIZE / sizeof(uint32_t); i++) { + mmio_write_32((uintptr_t)(ctx->iv + i), htobe32(iv_u32[3 - i])); + /* /!\ We save the iv in HW byte order */ + } + } + + return saes_start(ctx); +} + +/** + * @brief Update (or start) a AES authentificate process of associated data (CCM or GCM). + * @param ctx: SAES process context + * @param last_block: true if last assoc data block + * @param data: pointer to associated data + * @param data_size: data size + * + * @retval 0 if OK; negative value else. + */ +int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data, size_t data_size) +{ + int ret; + uint32_t *data_u32; + unsigned int i = 0U; + + /* We want buffers to be u32 aligned */ + assert((uintptr_t)data % __alignof__(uint32_t) == 0); + data_u32 = (uint32_t *)data; + + /* Init phase */ + ret = restore_context(ctx); + if (ret != 0) { + goto out; + } + + ret = wait_computation_completed(ctx->base); + if (ret != 0) { + return ret; + } + + clear_computation_completed(ctx->base); + + if ((data == NULL) || (data_size == 0U)) { + /* No associated data */ + /* ret already = 0 */ + goto out; + } + + /* There is an header/associated data phase */ + mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK, + _SAES_CR_GCMPH_HEADER << _SAES_CR_GCMPH_SHIFT); + + /* Enable the SAES peripheral */ + mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN); + + while (i < round_down(data_size, AES_BLOCK_SIZE)) { + unsigned int w; /* Word index */ + + w = i / sizeof(uint32_t); + /* No need to htobe() as we configure the HW to swap bytes */ + mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 0U]); + mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 1U]); + mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 2U]); + mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 3U]); + + ret = wait_computation_completed(ctx->base); + if (ret != 0) { + goto out; + } + + clear_computation_completed(ctx->base); + + /* Process next block */ + i += AES_BLOCK_SIZE; + ctx->assoc_len += AES_BLOCK_SIZE_BIT; + } + + /* Manage last block if not a block size multiple */ + if ((last_block) && (i < data_size)) { + /* We don't manage unaligned last block yet */ + ret = -ENODEV; + goto out; + } + +out: + if (ret != 0) { + saes_end(ctx, ret); + } + + return ret; +} + +/** + * @brief Update (or start) a AES authenticate and de/encrypt with payload data (CCM or GCM). + * @param ctx: SAES process context + * @param last_block: true if last payload data block + * @param data_in: pointer to payload + * @param data_out: pointer where to save de/encrypted payload + * @param data_size: payload size + * + * @retval 0 if OK; negative value else. + */ +int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data_in, uint8_t *data_out, size_t data_size) +{ + int ret = 0; + uint32_t *data_in_u32; + uint32_t *data_out_u32; + unsigned int i = 0U; + uint32_t prev_cr; + + /* We want buffers to be u32 aligned */ + assert((uintptr_t)data_in % __alignof__(uint32_t) == 0); + assert((uintptr_t)data_out % __alignof__(uint32_t) == 0); + data_in_u32 = (uint32_t *)data_in; + data_out_u32 = (uint32_t *)data_out; + + prev_cr = mmio_read_32(ctx->base + _SAES_CR); + + if ((data_in == NULL) || (data_size == 0U)) { + /* there is no data */ + goto out; + } + + /* There is a load phase */ + mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK, + _SAES_CR_GCMPH_PAYLOAD << _SAES_CR_GCMPH_SHIFT); + + if ((prev_cr & _SAES_CR_GCMPH_MASK) == + (_SAES_CR_GCMPH_INIT << _SAES_CR_GCMPH_SHIFT)) { + /* Still in initialization phase, no header + * We need to enable the SAES peripheral + */ + mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN); + } + + while (i < round_down(data_size, AES_BLOCK_SIZE)) { + unsigned int w; /* Word index */ + + w = i / sizeof(uint32_t); + /* No need to htobe() as we configure the HW to swap bytes */ + mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 0U]); + mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 1U]); + mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 2U]); + mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 3U]); + + ret = wait_computation_completed(ctx->base); + if (ret != 0) { + goto out; + } + + /* No need to htobe() as we configure the HW to swap bytes */ + data_out_u32[w + 0U] = mmio_read_32(ctx->base + _SAES_DOUTR); + data_out_u32[w + 1U] = mmio_read_32(ctx->base + _SAES_DOUTR); + data_out_u32[w + 2U] = mmio_read_32(ctx->base + _SAES_DOUTR); + data_out_u32[w + 3U] = mmio_read_32(ctx->base + _SAES_DOUTR); + + clear_computation_completed(ctx->base); + + /* Process next block */ + i += AES_BLOCK_SIZE; + ctx->load_len += AES_BLOCK_SIZE_BIT; + } + /* Manage last block if not a block size multiple */ + if ((last_block) && (i < data_size)) { + uint32_t block_in[AES_BLOCK_SIZE / sizeof(uint32_t)] = {0}; + uint32_t block_out[AES_BLOCK_SIZE / sizeof(uint32_t)] = {0}; + + memcpy(block_in, data_in + i, data_size - i); + + /* No need to htobe() as we configure the HW to swap bytes */ + mmio_write_32(ctx->base + _SAES_DINR, block_in[0U]); + mmio_write_32(ctx->base + _SAES_DINR, block_in[1U]); + mmio_write_32(ctx->base + _SAES_DINR, block_in[2U]); + mmio_write_32(ctx->base + _SAES_DINR, block_in[3U]); + + ret = wait_computation_completed(ctx->base); + if (ret != 0) { + VERBOSE("%s %d\n", __func__, __LINE__); + goto out; + } + + /* No need to htobe() as we configure the HW to swap bytes */ + block_out[0U] = mmio_read_32(ctx->base + _SAES_DOUTR); + block_out[1U] = mmio_read_32(ctx->base + _SAES_DOUTR); + block_out[2U] = mmio_read_32(ctx->base + _SAES_DOUTR); + block_out[3U] = mmio_read_32(ctx->base + _SAES_DOUTR); + + clear_computation_completed(ctx->base); + + memcpy(data_out + i, block_out, data_size - i); + + ctx->load_len += (data_size - i) * UINT8_BIT; + } + +out: + if (ret != 0) { + saes_end(ctx, ret); + } + + return ret; +} + +/** + * @brief Get authentication tag for AES authenticated algorithms (CCM or GCM). + * @param ctx: SAES process context + * @param tag: pointer where to save the tag + * @param data_size: tag size + * + * @retval 0 if OK; negative value else. + */ +int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag, + size_t tag_size) +{ + int ret; + uint32_t tag_u32[4]; + uint32_t prev_cr; + + prev_cr = mmio_read_32(ctx->base + _SAES_CR); + + mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK, + _SAES_CR_GCMPH_FINAL << _SAES_CR_GCMPH_SHIFT); + + if ((prev_cr & _SAES_CR_GCMPH_MASK) == (_SAES_CR_GCMPH_INIT << _SAES_CR_GCMPH_SHIFT)) { + /* Still in initialization phase, no header + * We need to enable the SAES peripheral + */ + mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN); + } + + /* No need to htobe() as we configure the HW to swap bytes */ + mmio_write_32(ctx->base + _SAES_DINR, 0); + mmio_write_32(ctx->base + _SAES_DINR, ctx->assoc_len); + mmio_write_32(ctx->base + _SAES_DINR, 0); + mmio_write_32(ctx->base + _SAES_DINR, ctx->load_len); + + ret = wait_computation_completed(ctx->base); + if (ret != 0) { + goto out; + } + + /* No need to htobe() as we configure the HW to swap bytes */ + tag_u32[0] = mmio_read_32(ctx->base + _SAES_DOUTR); + tag_u32[1] = mmio_read_32(ctx->base + _SAES_DOUTR); + tag_u32[2] = mmio_read_32(ctx->base + _SAES_DOUTR); + tag_u32[3] = mmio_read_32(ctx->base + _SAES_DOUTR); + + clear_computation_completed(ctx->base); + + memcpy(tag, tag_u32, MIN(sizeof(tag_u32), tag_size)); + +out: + saes_end(ctx, ret); + + return ret; +} + +/** + * @brief Update (or start) a AES de/encrypt process (ECB, CBC or CTR). + * @param ctx: SAES process context + * @param last_block: true if last payload data block + * @param data_in: pointer to payload + * @param data_out: pointer where to save de/encrypted payload + * @param data_size: payload size + * + * @retval 0 if OK; negative value else. + */ +int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data_in, uint8_t *data_out, size_t data_size) +{ + int ret; + uint32_t *data_in_u32; + uint32_t *data_out_u32; + unsigned int i = 0U; + + /* We want buffers to be u32 aligned */ + assert((uintptr_t)data_in % __alignof__(uint32_t) == 0); + assert((uintptr_t)data_out % __alignof__(uint32_t) == 0); + data_in_u32 = (uint32_t *)data_in; + data_out_u32 = (uint32_t *)data_out; + + if ((!last_block) && + (round_down(data_size, AES_BLOCK_SIZE) != data_size)) { + ERROR("%s: non last block must be multiple of 128 bits\n", + __func__); + ret = -EINVAL; + goto out; + } + + /* In CBC encryption we need to manage specifically last 2 128bits + * blocks if total size in not a block size aligned + * work TODO. Currently return ENODEV. + * Morevoer as we need to know last 2 block, if unaligned and + * call with less than two block, return -EINVAL. + */ + if (last_block && IS_CHAINING_MODE(CBC, ctx->cr) && is_encrypt(ctx->cr) && + (round_down(data_size, AES_BLOCK_SIZE) != data_size)) { + if (data_size < AES_BLOCK_SIZE * 2U) { + ERROR("if CBC, last part size should be at least 2 * AES_BLOCK_SIZE\n"); + ret = -EINVAL; + goto out; + } + /* Moreover the CBC specific padding for encrypt is not yet implemented */ + ret = -ENODEV; + goto out; + } + + ret = restore_context(ctx); + if (ret != 0) { + goto out; + } + + while (i < round_down(data_size, AES_BLOCK_SIZE)) { + unsigned int w; /* Word index */ + + w = i / sizeof(uint32_t); + /* No need to htobe() as we configure the HW to swap bytes */ + mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 0U]); + mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 1U]); + mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 2U]); + mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 3U]); + + ret = wait_computation_completed(ctx->base); + if (ret != 0) { + goto out; + } + + /* No need to htobe() as we configure the HW to swap bytes */ + data_out_u32[w + 0U] = mmio_read_32(ctx->base + _SAES_DOUTR); + data_out_u32[w + 1U] = mmio_read_32(ctx->base + _SAES_DOUTR); + data_out_u32[w + 2U] = mmio_read_32(ctx->base + _SAES_DOUTR); + data_out_u32[w + 3U] = mmio_read_32(ctx->base + _SAES_DOUTR); + + clear_computation_completed(ctx->base); + + /* Process next block */ + i += AES_BLOCK_SIZE; + } + /* Manage last block if not a block size multiple */ + + if ((last_block) && (i < data_size)) { + /* In and out buffer have same size so should be AES_BLOCK_SIZE multiple */ + ret = -ENODEV; + goto out; + } + + if (!last_block) { + ret = save_context(ctx); + } + +out: + /* If last block or error, end of SAES process */ + if (last_block || (ret != 0)) { + saes_end(ctx, ret); + } + + return ret; +} diff --git a/drivers/st/etzpc/etzpc.c b/drivers/st/etzpc/etzpc.c index ff52a22d9..4c3c26d94 100644 --- a/drivers/st/etzpc/etzpc.c +++ b/drivers/st/etzpc/etzpc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -225,20 +225,8 @@ uintptr_t etzpc_get_base_address(void) int etzpc_init(void) { uint32_t hwcfg; - int node; - struct dt_node_info etzpc_info; - node = dt_get_node(&etzpc_info, -1, ETZPC_COMPAT); - if (node < 0) { - return -EIO; - } - - /* Check ETZPC is secure only */ - if (etzpc_info.status != DT_SECURE) { - return -EACCES; - } - - etzpc_dev.base = etzpc_info.base; + etzpc_dev.base = STM32MP1_ETZPC_BASE; hwcfg = mmio_read_32(etzpc_dev.base + ETZPC_HWCFGR); diff --git a/drivers/st/io/io_stm32image.c b/drivers/st/io/io_stm32image.c deleted file mode 100644 index 9fa0c50fd..000000000 --- a/drivers/st/io/io_stm32image.c +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <errno.h> -#include <stdint.h> -#include <string.h> - -#include <platform_def.h> - -#include <common/debug.h> -#include <drivers/io/io_driver.h> -#include <drivers/io/io_storage.h> -#include <drivers/st/io_stm32image.h> -#include <lib/utils.h> -#include <plat/common/platform.h> - -static uintptr_t backend_dev_handle; -static uintptr_t backend_image_spec; -static uint32_t *stm32_img; -static uint8_t first_lba_buffer[MAX_LBA_SIZE] __aligned(4); -static struct stm32image_part_info *current_part; - -/* STM32 Image driver functions */ -static int stm32image_dev_open(const uintptr_t init_params, - io_dev_info_t **dev_info); -static int stm32image_partition_open(io_dev_info_t *dev_info, - const uintptr_t spec, io_entity_t *entity); -static int stm32image_partition_size(io_entity_t *entity, size_t *length); -static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer, - size_t length, size_t *length_read); -static int stm32image_partition_close(io_entity_t *entity); -static int stm32image_dev_init(io_dev_info_t *dev_info, - const uintptr_t init_params); -static int stm32image_dev_close(io_dev_info_t *dev_info); - -/* Identify the device type as a virtual driver */ -static io_type_t device_type_stm32image(void) -{ - return IO_TYPE_STM32IMAGE; -} - -static const io_dev_connector_t stm32image_dev_connector = { - .dev_open = stm32image_dev_open -}; - -static const io_dev_funcs_t stm32image_dev_funcs = { - .type = device_type_stm32image, - .open = stm32image_partition_open, - .size = stm32image_partition_size, - .read = stm32image_partition_read, - .close = stm32image_partition_close, - .dev_init = stm32image_dev_init, - .dev_close = stm32image_dev_close, -}; - -static io_dev_info_t stm32image_dev_info = { - .funcs = &stm32image_dev_funcs, - .info = (uintptr_t)0, -}; - -static struct stm32image_device_info stm32image_dev; - -static int get_part_idx_by_binary_type(uint32_t binary_type) -{ - int i; - - for (i = 0; i < STM32_PART_NUM; i++) { - if (stm32image_dev.part_info[i].binary_type == binary_type) { - return i; - } - } - - return -EINVAL; -} - -/* Open a connection to the STM32IMAGE device */ -static int stm32image_dev_open(const uintptr_t init_params, - io_dev_info_t **dev_info) -{ - int i; - struct stm32image_device_info *device_info = - (struct stm32image_device_info *)init_params; - - assert(dev_info != NULL); - *dev_info = (io_dev_info_t *)&stm32image_dev_info; - - stm32image_dev.device_size = device_info->device_size; - stm32image_dev.lba_size = device_info->lba_size; - - for (i = 0; i < STM32_PART_NUM; i++) { - memcpy(stm32image_dev.part_info[i].name, - device_info->part_info[i].name, MAX_PART_NAME_SIZE); - stm32image_dev.part_info[i].binary_type = - device_info->part_info[i].binary_type; - stm32image_dev.part_info[i].part_offset = - device_info->part_info[i].part_offset; - stm32image_dev.part_info[i].bkp_offset = - device_info->part_info[i].bkp_offset; - } - - return 0; -} - -/* Do some basic package checks */ -static int stm32image_dev_init(io_dev_info_t *dev_info, - const uintptr_t init_params) -{ - int result; - - if ((backend_dev_handle != 0U) || (backend_image_spec != 0U)) { - ERROR("STM32 Image io supports only one session\n"); - return -ENOMEM; - } - - /* Obtain a reference to the image by querying the platform layer */ - result = plat_get_image_source(STM32_IMAGE_ID, &backend_dev_handle, - &backend_image_spec); - if (result != 0) { - ERROR("STM32 image error (%i)\n", result); - return -EINVAL; - } - - return result; -} - -/* Close a connection to the STM32 Image device */ -static int stm32image_dev_close(io_dev_info_t *dev_info) -{ - backend_dev_handle = 0U; - backend_image_spec = 0U; - stm32_img = NULL; - - return 0; -} - -/* Open a partition */ -static int stm32image_partition_open(io_dev_info_t *dev_info, - const uintptr_t spec, io_entity_t *entity) -{ - const struct stm32image_part_info *partition_spec; - int idx; - - assert(entity != NULL); - - partition_spec = (struct stm32image_part_info *)spec; - assert(partition_spec != NULL); - - idx = get_part_idx_by_binary_type(partition_spec->binary_type); - if ((idx < 0) || (idx > STM32_PART_NUM)) { - ERROR("Wrong partition index (%d)\n", idx); - return -EINVAL; - } - - current_part = &stm32image_dev.part_info[idx]; - stm32_img = (uint32_t *)¤t_part->part_offset; - - return 0; -} - -/* Return the size of a partition */ -static int stm32image_partition_size(io_entity_t *entity, size_t *length) -{ - int result; - uintptr_t backend_handle; - size_t bytes_read; - boot_api_image_header_t *header = - (boot_api_image_header_t *)first_lba_buffer; - - assert(entity != NULL); - assert(length != NULL); - - /* Attempt to access the image */ - result = io_open(backend_dev_handle, backend_image_spec, - &backend_handle); - - if (result < 0) { - ERROR("%s: io_open (%i)\n", __func__, result); - return result; - } - - /* Reset magic header value */ - header->magic = 0; - - while (header->magic == 0U) { - result = io_seek(backend_handle, IO_SEEK_SET, *stm32_img); - if (result != 0) { - ERROR("%s: io_seek (%i)\n", __func__, result); - break; - } - - result = io_read(backend_handle, (uintptr_t)header, - MAX_LBA_SIZE, (size_t *)&bytes_read); - if (result != 0) { - if (current_part->bkp_offset == 0U) { - ERROR("%s: io_read (%i)\n", __func__, result); - } - header->magic = 0; - } - - if ((header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) || - (header->binary_type != current_part->binary_type) || - (header->image_length >= stm32image_dev.device_size)) { - VERBOSE("%s: partition %s not found at %x\n", - __func__, current_part->name, *stm32_img); - - if (current_part->bkp_offset == 0U) { - result = -ENOMEM; - break; - } - - /* Header not correct, check next offset for backup */ - *stm32_img += current_part->bkp_offset; - if (*stm32_img > stm32image_dev.device_size) { - /* No backup found, end of device reached */ - WARN("%s : partition %s not found\n", - __func__, current_part->name); - result = -ENOMEM; - break; - } - header->magic = 0; - } - } - - io_close(backend_handle); - - if (result != 0) { - return result; - } - - if (header->image_length < stm32image_dev.lba_size) { - *length = stm32image_dev.lba_size; - } else { - *length = header->image_length; - } - - INFO("STM32 Image size : %lu\n", (unsigned long)*length); - - return 0; -} - -/* Read data from a partition */ -static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer, - size_t length, size_t *length_read) -{ - int result = -EINVAL; - uint8_t *local_buffer; - boot_api_image_header_t *header = - (boot_api_image_header_t *)first_lba_buffer; - size_t hdr_sz = sizeof(boot_api_image_header_t); - - assert(entity != NULL); - assert(buffer != 0U); - assert(length_read != NULL); - - local_buffer = (uint8_t *)buffer; - *length_read = 0U; - - while (*length_read == 0U) { - int offset; - int local_length; - uintptr_t backend_handle; - - if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) { - /* Check for backup as image is corrupted */ - if (current_part->bkp_offset == 0U) { - result = -ENOMEM; - break; - } - - *stm32_img += current_part->bkp_offset; - if (*stm32_img >= stm32image_dev.device_size) { - /* End of device reached */ - result = -ENOMEM; - break; - } - - local_buffer = (uint8_t *)buffer; - - result = stm32image_partition_size(entity, &length); - if (result != 0) { - break; - } - } - - /* Part of image already loaded with the header */ - memcpy(local_buffer, (uint8_t *)first_lba_buffer + hdr_sz, - MAX_LBA_SIZE - hdr_sz); - local_buffer += MAX_LBA_SIZE - hdr_sz; - offset = MAX_LBA_SIZE; - - /* New image length to be read */ - local_length = round_up(length - ((MAX_LBA_SIZE) - hdr_sz), - stm32image_dev.lba_size); - - if ((header->load_address != 0U) && - (header->load_address != buffer)) { - ERROR("Wrong load address\n"); - panic(); - } - - result = io_open(backend_dev_handle, backend_image_spec, - &backend_handle); - - if (result != 0) { - ERROR("%s: io_open (%i)\n", __func__, result); - break; - } - - result = io_seek(backend_handle, IO_SEEK_SET, - *stm32_img + offset); - - if (result != 0) { - ERROR("%s: io_seek (%i)\n", __func__, result); - *length_read = 0; - io_close(backend_handle); - break; - } - - result = io_read(backend_handle, (uintptr_t)local_buffer, - local_length, length_read); - - /* Adding part of size already read from header */ - *length_read += MAX_LBA_SIZE - hdr_sz; - - if (result != 0) { - ERROR("%s: io_read (%i)\n", __func__, result); - *length_read = 0; - header->magic = 0; - continue; - } - - result = stm32mp_check_header(header, buffer); - if (result != 0) { - ERROR("Header check failed\n"); - *length_read = 0; - header->magic = 0; - } - - result = stm32mp_auth_image(header, buffer); - if (result != 0) { - ERROR("Authentication Failed (%i)\n", result); - return result; - } - - inv_dcache_range(round_up((uintptr_t)(local_buffer + length - hdr_sz), - CACHE_WRITEBACK_GRANULE), *length_read - length + hdr_sz); - - io_close(backend_handle); - } - - return result; -} - -/* Close a partition */ -static int stm32image_partition_close(io_entity_t *entity) -{ - current_part = NULL; - - return 0; -} - -/* Register the stm32image driver with the IO abstraction */ -int register_io_dev_stm32image(const io_dev_connector_t **dev_con) -{ - int result; - - assert(dev_con != NULL); - - result = io_register_device(&stm32image_dev_info); - if (result == 0) { - *dev_con = &stm32image_dev_connector; - } - - return result; -} diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c index 40641b5a8..6bdd782ae 100644 --- a/drivers/st/mmc/stm32_sdmmc2.c +++ b/drivers/st/mmc/stm32_sdmmc2.c @@ -129,6 +129,8 @@ #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" #endif +#define SDMMC_FIFO_SIZE 64U + static void stm32_sdmmc2_init(void); static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); @@ -148,6 +150,8 @@ static const struct mmc_ops stm32_sdmmc2_ops = { static struct stm32_sdmmc2_params sdmmc2_params; +static bool next_cmd_is_acmd; + #pragma weak plat_sdmmc2_use_dma bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) { @@ -257,6 +261,20 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) case MMC_CMD(1): arg_reg |= OCR_POWERUP; break; + case MMC_CMD(6): + if ((sdmmc2_params.device_info->mmc_dev_type == MMC_IS_SD_HC) && + (!next_cmd_is_acmd)) { + cmd_reg |= SDMMC_CMDR_CMDTRANS; + if (sdmmc2_params.use_dma) { + flags_data |= SDMMC_STAR_DCRCFAIL | + SDMMC_STAR_DTIMEOUT | + SDMMC_STAR_DATAEND | + SDMMC_STAR_RXOVERR | + SDMMC_STAR_IDMATE | + SDMMC_STAR_DBCKEND; + } + } + break; case MMC_CMD(8): if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { cmd_reg |= SDMMC_CMDR_CMDTRANS; @@ -294,6 +312,8 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) break; } + next_cmd_is_acmd = (cmd->cmd_idx == MMC_CMD(55)); + mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); /* @@ -301,8 +321,7 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) * Skip CMD55 as the next command could be data related, and * the register could have been set in prepare function. */ - if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) && - (cmd->cmd_idx != MMC_CMD(55))) { + if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) && !next_cmd_is_acmd) { mmio_write_32(base + SDMMC_DCTRLR, 0U); } @@ -627,7 +646,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) return -ETIMEDOUT; } - if (size < (8U * sizeof(uint32_t))) { + if (size < (SDMMC_FIFO_SIZE / 2U)) { if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && ((status & SDMMC_STAR_RXFIFOE) == 0U)) { *buffer = mmio_read_32(fifo_reg); @@ -637,7 +656,8 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) uint32_t count; /* Read data from SDMMC Rx FIFO */ - for (count = 0; count < 8U; count++) { + for (count = 0; count < (SDMMC_FIFO_SIZE / 2U); + count += sizeof(uint32_t)) { *buffer = mmio_read_32(fifo_reg); buffer++; } @@ -737,8 +757,6 @@ unsigned long long stm32_sdmmc2_mmc_get_device_size(void) int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) { - int rc; - assert((params != NULL) && ((params->reg_base & MMC_BLOCK_MASK) == 0U) && ((params->bus_width == MMC_BUS_WIDTH_1) || @@ -756,16 +774,20 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) clk_enable(sdmmc2_params.clock_id); - rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); - if (rc != 0) { - panic(); - } - udelay(2); - rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); - if (rc != 0) { - panic(); + if ((int)sdmmc2_params.reset_id >= 0) { + int rc; + + rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); + if (rc != 0) { + panic(); + } + udelay(2); + rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); + if (rc != 0) { + panic(); + } + mdelay(1); } - mdelay(1); sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; diff --git a/drivers/st/uart/aarch32/stm32_console.S b/drivers/st/uart/aarch32/stm32_console.S index e467f0987..e3e0e67d3 100644 --- a/drivers/st/uart/aarch32/stm32_console.S +++ b/drivers/st/uart/aarch32/stm32_console.S @@ -46,10 +46,16 @@ func console_stm32_core_init cmp r0, #0 beq core_init_fail #if !defined(IMAGE_BL2) +#if STM32MP_RECONFIGURE_CONSOLE + /* UART clock rate is set to 0 in BL32, skip init in that case */ + cmp r1, #0 + beq 1f +#else /* STM32MP_RECONFIGURE_CONSOLE */ /* Skip UART initialization if it is already enabled */ ldr r3, [r0, #USART_CR1] ands r3, r3, #USART_CR1_UE bne 1f +#endif /* STM32MP_RECONFIGURE_CONSOLE */ #endif /* IMAGE_BL2 */ /* Check baud rate and uart clock for sanity */ cmp r1, #0 diff --git a/drivers/st/uart/stm32_uart.c b/drivers/st/uart/stm32_uart.c index e2e540511..63970c76d 100644 --- a/drivers/st/uart/stm32_uart.c +++ b/drivers/st/uart/stm32_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,9 @@ #include <string.h> #include <common/bl_common.h> +#include <drivers/clk.h> #include <drivers/delay_timer.h> +#include <drivers/st/stm32_gpio.h> #include <drivers/st/stm32_uart.h> #include <drivers/st/stm32_uart_regs.h> #include <drivers/st/stm32mp_clkfunc.h> @@ -106,7 +108,33 @@ static int uart_set_config(struct stm32_uart_handle_s *huart, { uint32_t tmpreg; unsigned long clockfreq; + unsigned long int_div; uint32_t brrtemp; + uint32_t over_sampling; + + /*---------------------- USART BRR configuration --------------------*/ + clockfreq = uart_get_clock_freq(huart); + if (clockfreq == 0UL) { + return -ENODEV; + } + + int_div = clockfreq / init->baud_rate; + if (int_div < 16U) { + uint32_t usartdiv = uart_div_sampling8(clockfreq, + init->baud_rate, + init->prescaler); + + brrtemp = (usartdiv & USART_BRR_DIV_MANTISSA) | + ((usartdiv & USART_BRR_DIV_FRACTION) >> 1); + over_sampling = USART_CR1_OVER8; + } else { + brrtemp = uart_div_sampling16(clockfreq, + init->baud_rate, + init->prescaler) & + (USART_BRR_DIV_FRACTION | USART_BRR_DIV_MANTISSA); + over_sampling = 0x0U; + } + mmio_write_32(huart->base + USART_BRR, brrtemp); /* * ---------------------- USART CR1 Configuration -------------------- @@ -115,12 +143,12 @@ static int uart_set_config(struct stm32_uart_handle_s *huart, * - set the M bits according to init->word_length value, * - set PCE and PS bits according to init->parity value, * - set TE and RE bits according to init->mode value, - * - set OVER8 bit according to init->over_sampling value. + * - set OVER8 bit according baudrate and clock. */ tmpreg = init->word_length | init->parity | init->mode | - init->over_sampling | + over_sampling | init->fifo_mode; mmio_clrsetbits_32(huart->base + USART_CR1, STM32_UART_CR1_FIELDS, tmpreg); @@ -161,27 +189,6 @@ static int uart_set_config(struct stm32_uart_handle_s *huart, mmio_clrsetbits_32(huart->base + USART_PRESC, USART_PRESC_PRESCALER, init->prescaler); - /*---------------------- USART BRR configuration --------------------*/ - clockfreq = uart_get_clock_freq(huart); - if (clockfreq == 0UL) { - return -ENODEV; - } - - if (init->over_sampling == STM32_UART_OVERSAMPLING_8) { - uint32_t usartdiv = uart_div_sampling8(clockfreq, - init->baud_rate, - init->prescaler); - - brrtemp = (usartdiv & USART_BRR_DIV_MANTISSA) | - ((usartdiv & USART_BRR_DIV_FRACTION) >> 1); - } else { - brrtemp = uart_div_sampling16(clockfreq, - init->baud_rate, - init->prescaler) & - (USART_BRR_DIV_FRACTION | USART_BRR_DIV_MANTISSA); - } - mmio_write_32(huart->base + USART_BRR, brrtemp); - return 0; } @@ -295,12 +302,14 @@ void stm32_uart_stop(uintptr_t base) * @param init: UART initialization parameter. * @retval UART status. */ - int stm32_uart_init(struct stm32_uart_handle_s *huart, uintptr_t base_addr, const struct stm32_uart_init_s *init) { int ret; + int uart_node; + int clk; + void *fdt = NULL; if (huart == NULL || init == NULL || base_addr == 0U) { return -EINVAL; @@ -308,6 +317,32 @@ int stm32_uart_init(struct stm32_uart_handle_s *huart, huart->base = base_addr; + /* Search UART instance in DT */ + if (fdt_get_address(&fdt) == 0) { + return -FDT_ERR_NOTFOUND; + } + + if (fdt == NULL) { + return -FDT_ERR_NOTFOUND; + } + + uart_node = dt_match_instance_by_compatible(DT_UART_COMPAT, base_addr); + if (uart_node == -FDT_ERR_NOTFOUND) { + return -FDT_ERR_NOTFOUND; + } + + /* Pinctrl initialization */ + if (dt_set_pinctrl_config(uart_node) != 0) { + return -FDT_ERR_BADVALUE; + } + + /* Clock initialization */ + clk = fdt_get_clock_id(uart_node); + if (clk < 0) { + return -FDT_ERR_NOTFOUND; + } + clk_enable(clk); + /* Disable the peripheral */ stm32_uart_stop(huart->base); diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index 7db6c0bb2..d8c0a140e 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -225,8 +225,7 @@ static int ufshc_link_startup(uintptr_t base) } continue; } - while ((mmio_read_32(base + HCS) & HCS_DP) == 0) - ; + assert((mmio_read_32(base + HCS) & HCS_DP) == 0); data = mmio_read_32(base + IS); if (data & UFS_INT_ULSS) mmio_write_32(base + IS, UFS_INT_ULSS); @@ -265,7 +264,7 @@ static void get_utrd(utp_utrd_t *utrd) /* clear utrd */ memset((void *)utrd, 0, sizeof(utp_utrd_t)); - base = ufs_params.desc_base + (slot * UFS_DESC_SIZE); + base = ufs_params.desc_base + (slot * sizeof(utrd_header_t)); /* clear the descriptor */ memset((void *)base, 0, UFS_DESC_SIZE); @@ -300,12 +299,6 @@ static int ufs_prepare_cmd(utp_utrd_t *utrd, uint8_t op, uint8_t lun, unsigned int lba_cnt; int prdt_size; - - mmio_write_32(ufs_params.reg_base + UTRLBA, - utrd->header & UINT32_MAX); - mmio_write_32(ufs_params.reg_base + UTRLBAU, - (utrd->upiu >> 32) & UINT32_MAX); - hd = (utrd_header_t *)utrd->header; upiu = (cmd_upiu_t *)utrd->upiu; @@ -403,12 +396,6 @@ static int ufs_prepare_query(utp_utrd_t *utrd, uint8_t op, uint8_t idn, hd = (utrd_header_t *)utrd->header; query_upiu = (query_upiu_t *)utrd->upiu; - mmio_write_32(ufs_params.reg_base + UTRLBA, - utrd->header & UINT32_MAX); - mmio_write_32(ufs_params.reg_base + UTRLBAU, - (utrd->header >> 32) & UINT32_MAX); - - hd->i = 1; hd->ct = CT_UFS_STORAGE; hd->ocs = OCS_MASK; @@ -455,11 +442,6 @@ static void ufs_prepare_nop_out(utp_utrd_t *utrd) utrd_header_t *hd; nop_out_upiu_t *nop_out; - mmio_write_32(ufs_params.reg_base + UTRLBA, - utrd->header & UINT32_MAX); - mmio_write_32(ufs_params.reg_base + UTRLBAU, - (utrd->header >> 32) & UINT32_MAX); - hd = (utrd_header_t *)utrd->header; nop_out = (nop_out_upiu_t *)utrd->upiu; @@ -482,9 +464,7 @@ static void ufs_send_request(int task_tag) mmio_write_32(ufs_params.reg_base + IS, ~0); mmio_write_32(ufs_params.reg_base + UTRLRSR, 1); - do { - data = mmio_read_32(ufs_params.reg_base + UTRLRSR); - } while (data == 0); + assert(mmio_read_32(ufs_params.reg_base + UTRLRSR) == 1); data = UTRIACR_IAEN | UTRIACR_CTR | UTRIACR_IACTH(0x1F) | UTRIACR_IATOVAL(0xFF); @@ -497,6 +477,7 @@ static int ufs_check_resp(utp_utrd_t *utrd, int trans_type) { utrd_header_t *hd; resp_upiu_t *resp; + sense_data_t *sense; unsigned int data; int slot; @@ -519,6 +500,15 @@ static int ufs_check_resp(utp_utrd_t *utrd, int trans_type) inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE); assert(hd->ocs == OCS_SUCCESS); assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type); + + sense = &resp->sd.sense; + if (sense->resp_code == SENSE_DATA_VALID && + sense->sense_key == SENSE_KEY_UNIT_ATTENTION && sense->asc == 0x29 && + sense->ascq == 0) { + WARN("Unit Attention Condition\n"); + return -EAGAIN; + } + (void)resp; (void)slot; return 0; @@ -527,14 +517,18 @@ static int ufs_check_resp(utp_utrd_t *utrd, int trans_type) static void ufs_send_cmd(utp_utrd_t *utrd, uint8_t cmd_op, uint8_t lun, int lba, uintptr_t buf, size_t length) { - int result; + int result, i; - get_utrd(utrd); - - result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length); - assert(result == 0); - ufs_send_request(utrd->task_tag); - result = ufs_check_resp(utrd, RESPONSE_UPIU); + for (i = 0; i < UFS_CMD_RETRIES; ++i) { + get_utrd(utrd); + result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length); + assert(result == 0); + ufs_send_request(utrd->task_tag); + result = ufs_check_resp(utrd, RESPONSE_UPIU); + if (result == 0 || result == -EIO) { + break; + } + } assert(result == 0); (void)result; } @@ -685,14 +679,14 @@ void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size) ufs_query(QUERY_WRITE_DESC, idn, index, 0, buf, size); } -static void ufs_read_capacity(int lun, unsigned int *num, unsigned int *size) +static int ufs_read_capacity(int lun, unsigned int *num, unsigned int *size) { utp_utrd_t utrd; resp_upiu_t *resp; sense_data_t *sense; unsigned char data[CACHE_WRITEBACK_GRANULE << 1]; uintptr_t buf; - int retry; + int retries = UFS_READ_CAPACITY_RETRIES; assert((ufs_params.reg_base != 0) && (ufs_params.desc_base != 0) && @@ -710,22 +704,24 @@ static void ufs_read_capacity(int lun, unsigned int *num, unsigned int *size) dump_upiu(&utrd); #endif resp = (resp_upiu_t *)utrd.resp_upiu; - retry = 0; sense = &resp->sd.sense; - if (sense->resp_code == SENSE_DATA_VALID) { - if ((sense->sense_key == SENSE_KEY_UNIT_ATTENTION) && - (sense->asc == 0x29) && (sense->ascq == 0)) { - retry = 1; - } + if (!((sense->resp_code == SENSE_DATA_VALID) && + (sense->sense_key == SENSE_KEY_UNIT_ATTENTION) && + (sense->asc == 0x29) && (sense->ascq == 0))) { + inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE); + /* last logical block address */ + *num = be32toh(*(unsigned int *)buf); + if (*num) + *num += 1; + /* logical block length in bytes */ + *size = be32toh(*(unsigned int *)(buf + 4)); + + return 0; } - inv_dcache_range(buf, CACHE_WRITEBACK_GRANULE); - /* last logical block address */ - *num = be32toh(*(unsigned int *)buf); - if (*num) - *num += 1; - /* logical block length in bytes */ - *size = be32toh(*(unsigned int *)(buf + 4)); - } while (retry); + + } while (retries-- > 0); + + return -ETIMEDOUT; } size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size) @@ -796,15 +792,26 @@ static void ufs_enum(void) unsigned int blk_num, blk_size; int i, result; + mmio_write_32(ufs_params.reg_base + UTRLBA, + ufs_params.desc_base & UINT32_MAX); + mmio_write_32(ufs_params.reg_base + UTRLBAU, + (ufs_params.desc_base >> 32) & UINT32_MAX); + ufs_verify_init(); ufs_verify_ready(); result = ufs_set_fdevice_init(); assert(result == 0); + blk_num = 0; + blk_size = 0; + /* dump available LUNs */ for (i = 0; i < UFS_MAX_LUNS; i++) { - ufs_read_capacity(i, &blk_num, &blk_size); + result = ufs_read_capacity(i, &blk_num, &blk_size); + if (result != 0) { + WARN("UFS LUN%d dump failed\n", i); + } if (blk_num && blk_size) { INFO("UFS LUN%d contains %d blocks with %d-byte size\n", i, blk_num, blk_size); @@ -851,6 +858,11 @@ int ufs_init(const ufs_ops_t *ops, ufs_params_t *params) if (ufs_params.flags & UFS_FLAGS_SKIPINIT) { + mmio_write_32(ufs_params.reg_base + UTRLBA, + ufs_params.desc_base & UINT32_MAX); + mmio_write_32(ufs_params.reg_base + UTRLBAU, + (ufs_params.desc_base >> 32) & UINT32_MAX); + result = ufshc_dme_get(0x1571, 0, &data); assert(result == 0); result = ufshc_dme_get(0x41, 0, &data); diff --git a/fdts/fvp-base-gicv2-psci-aarch32.dts b/fdts/fvp-base-gicv2-psci-aarch32.dts deleted file mode 100644 index 3a921f436..000000000 --- a/fdts/fvp-base-gicv2-psci-aarch32.dts +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* Configuration: max 4 clusters with up to 4 CPUs */ - -/dts-v1/; - -#define AFF -#define REG_32 - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include "fvp-defs.dtsi" - -/memreserve/ 0x80000000 0x00010000; - -/ { -}; - -/ { - model = "FVP Base"; - compatible = "arm,vfp-base", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - sys_poweroff = <0x84000008>; - sys_reset = <0x84000009>; - max-pwr-lvl = <2>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU_MAP - - idle-states { - entry-method = "arm,psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <40>; - exit-latency-us = <100>; - min-residency-us = <150>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1000>; - min-residency-us = <2500>; - }; - }; - - CPUS - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x7F000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - gic: interrupt-controller@2f000000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0x2f000000 0 0x10000>, - <0x0 0x2c000000 0 0x2000>, - <0x0 0x2c010000 0 0x2000>, - <0x0 0x2c02F000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <100000000>; - }; - - timer@2a810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x2a810000 0x0 0x10000>; - clock-frequency = <100000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - frame@2a830000 { - frame-number = <1>; - interrupts = <0 26 4>; - reg = <0x0 0x2a830000 0x0 0x10000>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - }; - - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - - #include "rtsm_ve-motherboard-aarch32.dtsi" - }; - - panels { - panel@0 { - compatible = "panel"; - mode = "XVGA"; - refresh = <60>; - xres = <1024>; - yres = <768>; - pixclock = <15748>; - left_margin = <152>; - right_margin = <48>; - upper_margin = <23>; - lower_margin = <3>; - hsync_len = <104>; - vsync_len = <4>; - sync = <0>; - vmode = "FB_VMODE_NONINTERLACED"; - tim2 = "TIM2_BCD", "TIM2_IPC"; - cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; - caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; - bpp = <16>; - }; - }; -}; diff --git a/fdts/fvp-base-gicv2-psci.dts b/fdts/fvp-base-gicv2-psci.dts index e99719e19..0361bdca5 100644 --- a/fdts/fvp-base-gicv2-psci.dts +++ b/fdts/fvp-base-gicv2-psci.dts @@ -6,168 +6,13 @@ /* Configuration: max 4 clusters with up to 4 CPUs */ -/dts-v1/; - #define AFF -#include <dt-bindings/interrupt-controller/arm-gic.h> #include "fvp-defs.dtsi" -/memreserve/ 0x80000000 0x00010000; - -/ { -}; - -/ { - model = "FVP Base"; - compatible = "arm,vfp-base", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0xc4000001>; - cpu_off = <0x84000002>; - cpu_on = <0xc4000003>; - sys_poweroff = <0x84000008>; - sys_reset = <0x84000009>; - max-pwr-lvl = <2>; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU_MAP - - idle-states { - entry-method = "arm,psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <40>; - exit-latency-us = <100>; - min-residency-us = <150>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1000>; - min-residency-us = <2500>; - }; - }; - - CPUS - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x7F000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - gic: interrupt-controller@2f000000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0x2f000000 0 0x10000>, - <0x0 0x2c000000 0 0x2000>, - <0x0 0x2c010000 0 0x2000>, - <0x0 0x2c02F000 0 0x2000>; - interrupts = <1 9 0xf04>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <100000000>; - }; - - timer@2a810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x2a810000 0x0 0x10000>; - clock-frequency = <100000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - frame@2a830000 { - frame-number = <1>; - interrupts = <0 26 4>; - reg = <0x0 0x2a830000 0x0 0x10000>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - }; - - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; +/dts-v1/; - #include "rtsm_ve-motherboard.dtsi" - }; +/memreserve/ 0x80000000 0x00010000; - panels { - panel@0 { - compatible = "panel"; - mode = "XVGA"; - refresh = <60>; - xres = <1024>; - yres = <768>; - pixclock = <15748>; - left_margin = <152>; - right_margin = <48>; - upper_margin = <23>; - lower_margin = <3>; - hsync_len = <104>; - vsync_len = <4>; - sync = <0>; - vmode = "FB_VMODE_NONINTERLACED"; - tim2 = "TIM2_BCD", "TIM2_IPC"; - cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; - caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; - bpp = <16>; - }; - }; -}; +#include "fvp-base-gicv2.dtsi" +#include "fvp-base-psci-common.dtsi" diff --git a/fdts/fvp-base-gicv2.dtsi b/fdts/fvp-base-gicv2.dtsi new file mode 100644 index 000000000..8d84208aa --- /dev/null +++ b/fdts/fvp-base-gicv2.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* GICv2 configuration, without V2M */ + +/ { + gic: interrupt-controller@2f000000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, + <0x0 0x2c000000 0 0x2000>, + <0x0 0x2c010000 0 0x2000>, + <0x0 0x2c02F000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; +}; diff --git a/fdts/fvp-base-gicv3-psci-1t.dts b/fdts/fvp-base-gicv3-psci-1t.dts index c5e0424f6..829555b0c 100644 --- a/fdts/fvp-base-gicv3-psci-1t.dts +++ b/fdts/fvp-base-gicv3-psci-1t.dts @@ -6,9 +6,13 @@ /* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */ -/dts-v1/; - #define AFF 00 #include "fvp-defs.dtsi" -#include "fvp-base-gicv3-psci-common.dtsi" + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +#include "fvp-base-gicv3.dtsi" +#include "fvp-base-psci-common.dtsi" diff --git a/fdts/fvp-base-gicv3-psci-aarch32-1t.dts b/fdts/fvp-base-gicv3-psci-aarch32-1t.dts deleted file mode 100644 index a31c70374..000000000 --- a/fdts/fvp-base-gicv3-psci-aarch32-1t.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2019-2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */ - -/dts-v1/; - -#define AFF 00 -#define REG_32 - -#include "fvp-defs.dtsi" -#include "fvp-base-gicv3-psci-aarch32-common.dtsi" diff --git a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi deleted file mode 100644 index 85988e90f..000000000 --- a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/memreserve/ 0x80000000 0x00010000; - -/ { -}; - -/ { - model = "FVP Base"; - compatible = "arm,vfp-base", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - sys_poweroff = <0x84000008>; - sys_reset = <0x84000009>; - max-pwr-lvl = <2>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU_MAP - - idle-states { - entry-method = "arm,psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <40>; - exit-latency-us = <100>; - min-residency-us = <150>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1000>; - min-residency-us = <2500>; - }; - }; - - CPUS - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x7F000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - gic: interrupt-controller@2f000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0 0x10000>, // GICD - <0x0 0x2f100000 0 0x200000>, // GICR - <0x0 0x2c000000 0 0x2000>, // GICC - <0x0 0x2c010000 0 0x2000>, // GICH - <0x0 0x2c02f000 0 0x2000>; // GICV - interrupts = <1 9 4>; - - its: its@2f020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x2f020000 0x0 0x20000>; // GITS - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <100000000>; - }; - - timer@2a810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x2a810000 0x0 0x10000>; - clock-frequency = <100000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - frame@2a830000 { - frame-number = <1>; - interrupts = <0 26 4>; - reg = <0x0 0x2a830000 0x0 0x10000>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - }; - - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 0 0 4>, - <0 0 1 &gic 0 0 0 1 4>, - <0 0 2 &gic 0 0 0 2 4>, - <0 0 3 &gic 0 0 0 3 4>, - <0 0 4 &gic 0 0 0 4 4>, - <0 0 5 &gic 0 0 0 5 4>, - <0 0 6 &gic 0 0 0 6 4>, - <0 0 7 &gic 0 0 0 7 4>, - <0 0 8 &gic 0 0 0 8 4>, - <0 0 9 &gic 0 0 0 9 4>, - <0 0 10 &gic 0 0 0 10 4>, - <0 0 11 &gic 0 0 0 11 4>, - <0 0 12 &gic 0 0 0 12 4>, - <0 0 13 &gic 0 0 0 13 4>, - <0 0 14 &gic 0 0 0 14 4>, - <0 0 15 &gic 0 0 0 15 4>, - <0 0 16 &gic 0 0 0 16 4>, - <0 0 17 &gic 0 0 0 17 4>, - <0 0 18 &gic 0 0 0 18 4>, - <0 0 19 &gic 0 0 0 19 4>, - <0 0 20 &gic 0 0 0 20 4>, - <0 0 21 &gic 0 0 0 21 4>, - <0 0 22 &gic 0 0 0 22 4>, - <0 0 23 &gic 0 0 0 23 4>, - <0 0 24 &gic 0 0 0 24 4>, - <0 0 25 &gic 0 0 0 25 4>, - <0 0 26 &gic 0 0 0 26 4>, - <0 0 27 &gic 0 0 0 27 4>, - <0 0 28 &gic 0 0 0 28 4>, - <0 0 29 &gic 0 0 0 29 4>, - <0 0 30 &gic 0 0 0 30 4>, - <0 0 31 &gic 0 0 0 31 4>, - <0 0 32 &gic 0 0 0 32 4>, - <0 0 33 &gic 0 0 0 33 4>, - <0 0 34 &gic 0 0 0 34 4>, - <0 0 35 &gic 0 0 0 35 4>, - <0 0 36 &gic 0 0 0 36 4>, - <0 0 37 &gic 0 0 0 37 4>, - <0 0 38 &gic 0 0 0 38 4>, - <0 0 39 &gic 0 0 0 39 4>, - <0 0 40 &gic 0 0 0 40 4>, - <0 0 41 &gic 0 0 0 41 4>, - <0 0 42 &gic 0 0 0 42 4>; - - #include "rtsm_ve-motherboard-aarch32.dtsi" - }; - - panels { - panel@0 { - compatible = "panel"; - mode = "XVGA"; - refresh = <60>; - xres = <1024>; - yres = <768>; - pixclock = <15748>; - left_margin = <152>; - right_margin = <48>; - upper_margin = <23>; - lower_margin = <3>; - hsync_len = <104>; - vsync_len = <4>; - sync = <0>; - vmode = "FB_VMODE_NONINTERLACED"; - tim2 = "TIM2_BCD", "TIM2_IPC"; - cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; - caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; - bpp = <16>; - }; - }; -}; diff --git a/fdts/fvp-base-gicv3-psci-aarch32.dts b/fdts/fvp-base-gicv3-psci-aarch32.dts deleted file mode 100644 index 971b2e4d2..000000000 --- a/fdts/fvp-base-gicv3-psci-aarch32.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* Configuration: max 4 clusters with up to 4 CPUs */ - -/dts-v1/; - -#define REG_32 -#define AFF - -#include "fvp-defs.dtsi" -#include "fvp-base-gicv3-psci-aarch32-common.dtsi" diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi deleted file mode 100644 index 3cb613f63..000000000 --- a/fdts/fvp-base-gicv3-psci-common.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <services/sdei_flags.h> - -#define LEVEL 0 -#define EDGE 2 -#define SDEI_NORMAL 0x70 -#define HIGHEST_SEC 0 - -/memreserve/ 0x80000000 0x00010000; - -/ { -}; - -/ { - model = "FVP Base"; - compatible = "arm,vfp-base", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - -#if (ENABLE_RME == 1) - chosen { bootargs = "mem=1G console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";}; -#else - chosen {}; -#endif - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0xc4000001>; - cpu_off = <0x84000002>; - cpu_on = <0xc4000003>; - sys_poweroff = <0x84000008>; - sys_reset = <0x84000009>; - max-pwr-lvl = <2>; - }; - -#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF - firmware { -#if SDEI_IN_FCONF - sdei { - compatible = "arm,sdei-1.0"; - method = "smc"; - private_event_count = <3>; - shared_event_count = <3>; - /* - * Each event descriptor has typically 3 fields: - * 1. Event number - * 2. Interrupt number the event is bound to or - * if event is dynamic, specified as SDEI_DYN_IRQ - * 3. Bit map of event flags - */ - private_events = <1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, - <1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, - <1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; - shared_events = <2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, - <2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, - <2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; - }; -#endif /* SDEI_IN_FCONF */ - -#if SEC_INT_DESC_IN_FCONF - sec_interrupts { - compatible = "arm,secure_interrupt_desc"; - /* Number of G0 and G1 secure interrupts defined by the platform */ - g0_intr_cnt = <2>; - g1s_intr_cnt = <9>; - /* - * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. Each interrupt property descriptor has 3 fields: - * 1. Interrupt number - * 2. Interrupt priority - * 3. Type of interrupt (Edge or Level configured) - */ - g0_intr_desc = < 8 SDEI_NORMAL EDGE>, - <14 HIGHEST_SEC EDGE>; - - g1s_intr_desc = < 9 HIGHEST_SEC EDGE>, - <10 HIGHEST_SEC EDGE>, - <11 HIGHEST_SEC EDGE>, - <12 HIGHEST_SEC EDGE>, - <13 HIGHEST_SEC EDGE>, - <15 HIGHEST_SEC EDGE>, - <29 HIGHEST_SEC LEVEL>, - <56 HIGHEST_SEC LEVEL>, - <57 HIGHEST_SEC LEVEL>; - }; -#endif /* SEC_INT_DESC_IN_FCONF */ - }; -#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */ - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU_MAP - - idle-states { - entry-method = "arm,psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <40>; - exit-latency-us = <100>; - min-residency-us = <150>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1000>; - min-residency-us = <2500>; - }; - }; - - CPUS - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; -#if (ENABLE_RME == 1) - reg = <0x00000000 0x80000000 0 0x7C000000>, - <0x00000008 0x80000000 0 0x80000000>; -#else - reg = <0x00000000 0x80000000 0 0x7F000000>, - <0x00000008 0x80000000 0 0x80000000>; -#endif - }; - - gic: interrupt-controller@2f000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0 0x10000>, // GICD - <0x0 0x2f100000 0 0x200000>, // GICR - <0x0 0x2c000000 0 0x2000>, // GICC - <0x0 0x2c010000 0 0x2000>, // GICH - <0x0 0x2c02f000 0 0x2000>; // GICV - interrupts = <1 9 4>; - - its: its@2f020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x2f020000 0x0 0x20000>; // GITS - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <100000000>; - }; - - timer@2a810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x2a810000 0x0 0x10000>; - clock-frequency = <100000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - frame@2a830000 { - frame-number = <1>; - interrupts = <0 26 4>; - reg = <0x0 0x2a830000 0x0 0x10000>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - }; - - smb@0,0 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #include "rtsm_ve-motherboard.dtsi" - }; - - panels { - panel { - compatible = "panel"; - mode = "XVGA"; - refresh = <60>; - xres = <1024>; - yres = <768>; - pixclock = <15748>; - left_margin = <152>; - right_margin = <48>; - upper_margin = <23>; - lower_margin = <3>; - hsync_len = <104>; - vsync_len = <4>; - sync = <0>; - vmode = "FB_VMODE_NONINTERLACED"; - tim2 = "TIM2_BCD", "TIM2_IPC"; - cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; - caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; - bpp = <16>; - }; - }; -}; diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts index bda4b8dd4..9d5b97915 100644 --- a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts +++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts @@ -13,6 +13,11 @@ #define PE_PER_CPU 2 #endif +#include "fvp-defs-dynamiq.dtsi" + /dts-v1/; -#include "fvp-base-gicv3-psci-dynamiq-common.dtsi" +/memreserve/ 0x80000000 0x00010000; + +#include "fvp-base-gicv3.dtsi" +#include "fvp-base-psci-common.dtsi" diff --git a/fdts/fvp-base-gicv3-psci-dynamiq.dts b/fdts/fvp-base-gicv3-psci-dynamiq.dts index b693f7512..1bf803e22 100644 --- a/fdts/fvp-base-gicv3-psci-dynamiq.dts +++ b/fdts/fvp-base-gicv3-psci-dynamiq.dts @@ -13,6 +13,11 @@ #define PE_PER_CPU 1 #endif +#include "fvp-defs-dynamiq.dtsi" + /dts-v1/; -#include "fvp-base-gicv3-psci-dynamiq-common.dtsi" +/memreserve/ 0x80000000 0x00010000; + +#include "fvp-base-gicv3.dtsi" +#include "fvp-base-psci-common.dtsi" diff --git a/fdts/fvp-base-gicv3-psci.dts b/fdts/fvp-base-gicv3-psci.dts index eb994728a..69db26748 100644 --- a/fdts/fvp-base-gicv3-psci.dts +++ b/fdts/fvp-base-gicv3-psci.dts @@ -6,9 +6,13 @@ /* Configuration: max 4 clusters with up to 4 CPUs */ -/dts-v1/; - #define AFF #include "fvp-defs.dtsi" -#include "fvp-base-gicv3-psci-common.dtsi" + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +#include "fvp-base-gicv3.dtsi" +#include "fvp-base-psci-common.dtsi" diff --git a/fdts/fvp-base-gicv3.dtsi b/fdts/fvp-base-gicv3.dtsi new file mode 100644 index 000000000..fdcfa925b --- /dev/null +++ b/fdts/fvp-base-gicv3.dtsi @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* GICv3 with ITS configuration */ + +/ { + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x2f000000 0x100000>; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = <1 9 4>; + + its: msi-controller@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x20000 0x20000>; // GITS + }; + }; +}; diff --git a/fdts/fvp-base-psci-common.dtsi b/fdts/fvp-base-psci-common.dtsi new file mode 100644 index 000000000..6018f0cc2 --- /dev/null +++ b/fdts/fvp-base-psci-common.dtsi @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause +/* + * ARM Ltd. Fast Models + * + * Architecture Envelope Model (AEM) ARMv8-A + * ARMAEMv8AMPCT + * + * RTSM_VE_AEMv8A.lisa + * + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <services/sdei_flags.h> + +#define LEVEL 0 +#define EDGE 2 +#define SDEI_NORMAL 0x70 +#define HIGHEST_SEC 0 + +#include "rtsm_ve-motherboard.dtsi" + +/ { + model = "FVP Base"; + compatible = "arm,fvp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + +#if (ENABLE_RME == 1) + chosen { bootargs = "mem=1G console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";}; +#else + chosen {}; +#endif + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + max-pwr-lvl = <2>; + }; + +#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF + firmware { +#if SDEI_IN_FCONF + sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + private_event_count = <3>; + shared_event_count = <3>; + /* + * Each event descriptor has typically 3 fields: + * 1. Event number + * 2. Interrupt number the event is bound to or + * if event is dynamic, specified as SDEI_DYN_IRQ + * 3. Bit map of event flags + */ + private_events = <1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, + <1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, + <1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; + shared_events = <2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, + <2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, + <2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; + }; +#endif /* SDEI_IN_FCONF */ + +#if SEC_INT_DESC_IN_FCONF + sec_interrupts { + compatible = "arm,secure_interrupt_desc"; + /* Number of G0 and G1 secure interrupts defined by the platform */ + g0_intr_cnt = <2>; + g1s_intr_cnt = <9>; + /* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. Each interrupt property descriptor has 3 fields: + * 1. Interrupt number + * 2. Interrupt priority + * 3. Type of interrupt (Edge or Level configured) + */ + g0_intr_desc = < 8 SDEI_NORMAL EDGE>, + <14 HIGHEST_SEC EDGE>; + + g1s_intr_desc = < 9 HIGHEST_SEC EDGE>, + <10 HIGHEST_SEC EDGE>, + <11 HIGHEST_SEC EDGE>, + <12 HIGHEST_SEC EDGE>, + <13 HIGHEST_SEC EDGE>, + <15 HIGHEST_SEC EDGE>, + <29 HIGHEST_SEC LEVEL>, + <56 HIGHEST_SEC LEVEL>, + <57 HIGHEST_SEC LEVEL>; + }; +#endif /* SEC_INT_DESC_IN_FCONF */ + }; +#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */ + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU_MAP + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPUS + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; +#if (ENABLE_RME == 1) + reg = <0x00000000 0x80000000 0 0x7C000000>, + <0x00000008 0x80000000 0 0x80000000>; +#else + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; +#endif + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Chipselect 2,00000000 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0x00000000 0x18000000 0 0x00800000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x2a810000 0x100000>; + + frame@2a830000 { + frame-number = <1>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x20000 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + }; + + panel { + compatible = "arm,rtsm-display"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + + bus@8000000 { + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/fdts/fvp-defs.dtsi b/fdts/fvp-defs.dtsi index 1ffe65a2a..9fd33cac7 100644 --- a/fdts/fvp-defs.dtsi +++ b/fdts/fvp-defs.dtsi @@ -43,35 +43,17 @@ device_type = "cpu"; \ compatible = "arm,armv8"; -#ifdef REG_32 -/* 32-bit address */ -#define REG(c, p) \ - reg = <CONC(0x, CONC(c, CONC(p, AFF)))>; -#else -/* 64-bit address */ -#define REG(c, p) \ - reg = <0x0 CONC(0x, CONC(c, CONC(p, AFF)))>; -#endif /* REG_32 */ - #define POST \ enable-method = "psci"; \ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; \ next-level-cache = <&L2_0>; \ }; -#ifdef REG_32 -#define CPU_0 \ - CPU0:cpu@0 { \ - PRE \ - reg = <0x0>; \ - POST -#else #define CPU_0 \ CPU0:cpu@0 { \ PRE \ reg = <0x0 0x0>;\ POST -#endif /* REG_32 */ /* * n - CPU number @@ -79,7 +61,7 @@ #define CPU(n, c, p) \ ADR(n, c, p) \ PRE \ - REG(c, p) \ + reg = <0x0 CONC(0x, CONC(c, CONC(p, AFF)))>; \ POST /* 2 CPUs */ diff --git a/fdts/fvp-ve-Cortex-A5x1.dts b/fdts/fvp-ve-Cortex-A5x1.dts index 9d2d1d552..612b3b2d1 100644 --- a/fdts/fvp-ve-Cortex-A5x1.dts +++ b/fdts/fvp-ve-Cortex-A5x1.dts @@ -1,16 +1,20 @@ /* - * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + /dts-v1/; +#include "rtsm_ve-motherboard.dtsi" + / { model = "V2P-CA5s"; compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; interrupt-parent = <&gic>; - #address-cells = <1>; + #address-cells = <2>; #size-cells = <1>; cpus { @@ -27,12 +31,26 @@ memory@80000000 { device_type = "memory"; - reg = <0x80000000 0x1000000>; + reg = <0 0x80000000 0x1000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + /* Chipselect 2,00000000 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0 0x18000000 0x00800000>; + no-map; + }; }; hdlcd@2a110000 { compatible = "arm,hdlcd"; - reg = <0x2a110000 0x1000>; + reg = <0 0x2a110000 0x1000>; interrupts = <0 85 4>; clocks = <&oscclk3>; clock-names = "pxlclk"; @@ -40,12 +58,12 @@ scu@2c000000 { compatible = "arm,cortex-a5-scu"; - reg = <0x2c000000 0x58>; + reg = <0 0x2c000000 0x58>; }; watchdog@2c000620 { compatible = "arm,cortex-a5-twd-wdt"; - reg = <0x2c000620 0x20>; + reg = <0 0x2c000620 0x20>; interrupts = <1 14 0x304>; }; @@ -54,15 +72,12 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; + reg = <0 0x2c001000 0x1000>, + <0 0x2c000100 0x100>; }; - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0: osc@0 { + mcc { + oscclk0: oscclk0 { /* CPU and internal AXI reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -71,7 +86,7 @@ clock-output-names = "oscclk0"; }; - oscclk1: osc@1 { + oscclk1: oscclk1 { /* Multiplexed AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -80,7 +95,7 @@ clock-output-names = "oscclk1"; }; - osc@2 { + oscclk2 { /* DDR2 */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -89,7 +104,7 @@ clock-output-names = "oscclk2"; }; - oscclk3: osc@3 { + oscclk3: oscclk3 { /* HDLCD */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 3>; @@ -98,7 +113,7 @@ clock-output-names = "oscclk3"; }; - osc@4 { + oscclk4 { /* Test chip gate configuration */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -107,7 +122,7 @@ clock-output-names = "oscclk4"; }; - smbclk: osc@5 { + smbclk: oscclk5 { /* SMB clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; @@ -117,28 +132,36 @@ }; }; - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x04000000>, - <1 0 0x14000000 0x04000000>, - <2 0 0x18000000 0x04000000>, - <3 0 0x1c000000 0x04000000>, - <4 0 0x0c000000 0x04000000>, - <5 0 0x10000000 0x04000000>; + panel { + compatible = "arm,rtsm-display"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + bus@8000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 42 &gic 0 42 4>; - - #include "rtsm_ve-motherboard-aarch32.dtsi" + interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/fdts/fvp-ve-Cortex-A7x1.dts b/fdts/fvp-ve-Cortex-A7x1.dts index 28de91d3c..6ec6adb60 100644 --- a/fdts/fvp-ve-Cortex-A7x1.dts +++ b/fdts/fvp-ve-Cortex-A7x1.dts @@ -1,32 +1,50 @@ /* - * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + /dts-v1/; +#include "rtsm_ve-motherboard.dtsi" + / { model = "V2F-1XV7 Cortex-A7x1 SMM"; compatible = "arm,vexpress,v2f-1xv7", "arm,vexpress"; interrupt-parent = <&gic>; #address-cells = <2>; - #size-cells = <2>; + #size-cells = <1>; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0 0>; + reg = <0>; }; }; memory@0,80000000 { device_type = "memory"; - reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */ + reg = <0 0x80000000 0x80000000>; /* 2GB @ 2GB */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + /* Chipselect 2,00000000 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0 0x18000000 0x00800000>; + no-map; + }; }; gic: interrupt-controller@2c001000 { @@ -34,10 +52,10 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x1000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; + reg = <0 0x2c001000 0x1000>, + <0 0x2c002000 0x1000>, + <0 0x2c004000 0x2000>, + <0 0x2c006000 0x2000>; interrupts = <1 9 0xf04>; }; @@ -49,28 +67,36 @@ clock-output-names = "smclk"; }; - smb { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; + panel { + compatible = "arm,rtsm-display"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + bus@8000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 42 &gic 0 42 4>; - - #include "rtsm_ve-motherboard-aarch32.dtsi" + interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <0 0 43 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/fdts/juno-ethosn.dtsi b/fdts/juno-ethosn.dtsi index e2f33550e..460952482 100644 --- a/fdts/juno-ethosn.dtsi +++ b/fdts/juno-ethosn.dtsi @@ -1,12 +1,13 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /* - * For examples of multi-core and multi-device NPU, refer to the examples given in the - * Arm Ethos-N NPU driver stack. + * This device tree is only an example and some properties have been omitted. + * + * Refer to the Arm(R) Ethos(TM)-N driver stack for complete device tree examples. * https://github.com/ARM-software/ethos-n-driver-stack */ @@ -14,14 +15,62 @@ #address-cells = <2>; #size-cells = <2>; - ethosn0: ethosn@6f300000 { - compatible = "ethosn"; - reg = <0 0x6f300000 0 0x00100000>; + smmu_ethosn0: iommu@6f400000 { + compatible = "arm,smmu-v3"; + reg = <0 0x6f400000 0 0x80000>; status = "okay"; - - core0 { - compatible = "ethosn-core"; - status = "okay"; - }; + /* msi-parent omitted */ + #iommu-cells = <0x1>; }; + + ethosn0: ethosn@6f300000 { + compatible = "ethosn"; + reg = <0 0x6f300000 0 0x00100000>; + status = "okay"; + + core0 { + compatible = "ethosn-core"; + status = "okay"; + + main_allocator { + compatible = "ethosn-main_allocator"; + status = "okay"; + + firmware { + compatible = "ethosn-memory"; + iommus = <&smmu_ethosn0 0>; + }; + + working_data { + compatible = "ethosn-memory"; + iommus = <&smmu_ethosn0 1>; + }; + }; + }; + + asset_allocator { + compatible = "ethosn-asset_allocator"; + status = "okay"; + + command_stream { + compatible = "ethosn-memory"; + iommus = <&smmu_ethosn0 2>; + }; + + weight_data { + compatible = "ethosn-memory"; + iommus = <&smmu_ethosn0 3>; + }; + + buffer_data { + compatible = "ethosn-memory"; + iommus = <&smmu_ethosn0 4>; + }; + + intermediate_data { + compatible = "ethosn-memory"; + iommus = <&smmu_ethosn0 5>; + }; + }; + }; }; diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts index 55c87bfc0..dc3df4180 100644 --- a/fdts/morello-fvp.dts +++ b/fdts/morello-fvp.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #include "morello.dtsi" / { + model = "Arm Morello Fixed Virtual Platform"; chosen { stdout-path = "serial0:115200n8"; @@ -78,16 +79,12 @@ /* The first bank of memory, memory map is actually provided by UEFI. */ memory@80000000 { - #address-cells = <2>; - #size-cells = <2>; device_type = "memory"; /* [0x80000000-0xffffffff] */ reg = <0x00000000 0x80000000 0x0 0x80000000>; }; memory@8080000000 { - #address-cells = <2>; - #size-cells = <2>; device_type = "memory"; /* [0x8080000000-0x83ffffffff] */ reg = <0x00000080 0x80000000 0x1 0x80000000>; @@ -143,8 +140,8 @@ scmi { compatible = "arm,scmi"; mbox-names = "tx", "rx"; - mboxes = <&mailbox 1 0 &mailbox 1 1>; - shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>; + mboxes = <&mailbox 1 0>, <&mailbox 1 1>; + shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; #address-cells = <1>; #size-cells = <0>; diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts index 846463412..5f147b7f7 100644 --- a/fdts/morello-soc.dts +++ b/fdts/morello-soc.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,9 +8,10 @@ #include "morello.dtsi" / { + model = "Arm Morello System Development Platform"; chosen { - stdout-path = "soc_uart0:115200n8"; + stdout-path = "serial0:115200n8"; }; reserved-memory { @@ -59,16 +60,12 @@ /* The first bank of memory, memory map is actually provided by UEFI. */ memory@80000000 { - #address-cells = <2>; - #size-cells = <2>; device_type = "memory"; /* [0x80000000-0xffffffff] */ reg = <0x00000000 0x80000000 0x0 0x7F000000>; }; memory@8080000000 { - #address-cells = <2>; - #size-cells = <2>; device_type = "memory"; /* [0x8080000000-0x83f7ffffff] */ reg = <0x00000080 0x80000000 0x3 0x78000000>; @@ -78,10 +75,10 @@ compatible = "arm,smmu-v3"; reg = <0 0x4f400000 0 0x40000>; interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; msi-parent = <&its2 0>; #iommu-cells = <1>; dma-coherent; @@ -114,10 +111,10 @@ compatible = "arm,smmu-v3"; reg = <0 0x4f000000 0 0x40000>; interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; msi-parent = <&its1 0>; #iommu-cells = <1>; dma-coherent; @@ -150,16 +147,16 @@ compatible = "arm,smmu-v3"; reg = <0 0x2ce00000 0 0x40000>; interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eventq", "cmdq-sync", "gerror"; + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror", "cmdq-sync"; #iommu-cells = <1>; }; dp0: display@2cc00000 { #address-cells = <1>; #size-cells = <0>; - compatible = "arm,mali-d32"; + compatible = "arm,mali-d32", "arm,mali-d71"; reg = <0 0x2cc00000 0 0x20000>; interrupts = <0 69 4>; interrupt-names = "DPU"; @@ -220,8 +217,8 @@ scmi { compatible = "arm,scmi"; mbox-names = "tx", "rx"; - mboxes = <&mailbox 1 0 &mailbox 1 1>; - shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>; + mboxes = <&mailbox 1 0>, <&mailbox 1 1>; + shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; #address-cells = <1>; #size-cells = <0>; scmi_dvfs: protocol@13 { @@ -241,28 +238,28 @@ <0x0 0x300c0000 0 0x80000>; /* GICR */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - its1: its@30040000 { + its1: msi-controller@30040000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x30040000 0x0 0x20000>; }; - its2: its@30060000 { + its2: msi-controller@30060000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x30060000 0x0 0x20000>; }; - its_ccix: its@30080000 { + its_ccix: msi-controller@30080000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x30080000 0x0 0x20000>; }; - its_pcie: its@300a0000 { + its_pcie: msi-controller@300a0000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; diff --git a/fdts/morello.dtsi b/fdts/morello.dtsi index f119820a5..20640c5c9 100644 --- a/fdts/morello.dtsi +++ b/fdts/morello.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,7 +18,7 @@ }; gic: interrupt-controller@2c010000 { - compatible = "arm,gic-600", "arm,gic-v3"; + compatible = "arm,gic-v3"; #address-cells = <2>; #interrupt-cells = <3>; #size-cells = <2>; @@ -70,12 +70,12 @@ #size-cells = <1>; ranges = <0 0x0 0x06000000 0x8000>; - cpu_scp_hpri0: scp-shmem@0 { + cpu_scp_hpri0: scp-sram@0 { compatible = "arm,scmi-shmem"; reg = <0x0 0x80>; }; - cpu_scp_hpri1: scp-shmem@80 { + cpu_scp_hpri1: scp-sram@80 { compatible = "arm,scmi-shmem"; reg = <0x80 0x80>; }; @@ -95,7 +95,7 @@ clock-output-names = "uartclk"; }; - soc_uart0: uart@2a400000 { + soc_uart0: serial@2a400000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x2a400000 0x0 0x1000>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; diff --git a/fdts/n1sdp-multi-chip.dts b/fdts/n1sdp-multi-chip.dts index 8932dfcbd..852b899c1 100644 --- a/fdts/n1sdp-multi-chip.dts +++ b/fdts/n1sdp-multi-chip.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) /* - * Copyright (c) 2019-2020, Arm Limited. + * Copyright (c) 2019-2022, Arm Limited. */ #include "n1sdp-single-chip.dts" @@ -54,19 +54,19 @@ <1 1 10>; }; - smmu_slave_pcie: iommu@4004f400000 { + smmu_secondary_pcie: iommu@4004f400000 { compatible = "arm,smmu-v3"; reg = <0x400 0x4f400000 0 0x40000>; interrupts = <GIC_SPI 715 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 716 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>; interrupt-names = "eventq", "cmdq-sync", "gerror"; - msi-parent = <&its2_slave 0>; + msi-parent = <&its2_secondary 0>; #iommu-cells = <1>; dma-coherent; }; - pcie_slave_ctlr: pcie@40070000000 { + pcie_secondary_ctlr: pcie@40070000000 { compatible = "arm,n1sdp-pcie"; device_type = "pci"; reg = <0x400 0x70000000 0 0x1200000>; @@ -84,8 +84,9 @@ <0 0 0 2 &gic 0 0 0 650 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &gic 0 0 0 651 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic 0 0 0 652 IRQ_TYPE_LEVEL_HIGH>; - msi-map = <0 &its_slave_pcie 0 0x10000>; - iommu-map = <0 &smmu_slave_pcie 0 0x10000>; + msi-map = <0 &its_secondary_pcie 0 0x10000>; + iommu-map = <0 &smmu_secondary_pcie 0 0x10000>; + numa-node-id = <1>; status = "okay"; }; @@ -97,17 +98,25 @@ <0x0 0x300c0000 0 0x80000>, /* GICR */ <0x400 0x300c0000 0 0x80000>; /* GICR */ - its2_slave: its@40030060000 { + its2_secondary: its@40030060000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x30060000 0x0 0x20000>; }; - its_slave_pcie: its@400300a0000 { + its_secondary_pcie: its@400300a0000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x300a0000 0x0 0x20000>; }; }; + +&pcie_ctlr { + numa-node-id = <0>; +}; + +&ccix_pcie_ctlr { + numa-node-id = <0>; +}; diff --git a/fdts/rtsm_ve-motherboard-aarch32.dtsi b/fdts/rtsm_ve-motherboard-aarch32.dtsi deleted file mode 100644 index 7a8af8e74..000000000 --- a/fdts/rtsm_ve-motherboard-aarch32.dtsi +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - - motherboard { - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; - - vram@2,00000000 { - compatible = "arm,vexpress-vram"; - reg = <2 0x00000000 0x00800000>; - }; - - ethernet@2,02000000 { - compatible = "smsc,lan91c111"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - iofpga@3,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - }; - - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&v2m_clk24mhz>; - clock-names = "apb_pclk"; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9 10>; - cd-gpios = <&v2m_sysreg 0 0>; - wp-gpios = <&v2m_sysreg 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&v2m_clk24mhz>; - clock-names = "apb_pclk"; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; - clock-names = "clcdclk", "apb_pclk"; - mode = "XVGA"; - use_dma = <0>; - framebuffer = <0x18000000 0x00180000>; - }; - - virtio_block@130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x1000>; - interrupts = <0x2a>; - }; - }; - - v2m_fixed_3v3: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - mcc { - compatible = "arm,vexpress,config-bus", "simple-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - v2m_oscclk1: osc@1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - /* - * Not supported in FVP models - * - * reset@0 { - * compatible = "arm,vexpress-reset"; - * arm,vexpress-sysreg,func = <5 0>; - * }; - */ - - muxfpga@0 { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - /* - * Not used - Superseded by PSCI sys_poweroff - * - * shutdown@0 { - * compatible = "arm,vexpress-shutdown"; - * arm,vexpress-sysreg,func = <8 0>; - * }; - */ - - /* - * Not used - Superseded by PSCI sys_reset - * - * reboot@0 { - * compatible = "arm,vexpress-reboot"; - * arm,vexpress-sysreg,func = <9 0>; - * }; - */ - - dvimode@0 { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - }; diff --git a/fdts/rtsm_ve-motherboard.dtsi b/fdts/rtsm_ve-motherboard.dtsi index 486f8a985..0a824b349 100644 --- a/fdts/rtsm_ve-motherboard.dtsi +++ b/fdts/rtsm_ve-motherboard.dtsi @@ -1,251 +1,260 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * ARM Ltd. Fast Models * - * SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2012-2022 ARM Ltd. + * + * Versatile Express (VE) system model + * Motherboard component + * + * VEMotherBoard.lisa */ +/ { + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; - motherboard { - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - ranges; + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; - vram@2,00000000 { - compatible = "arm,vexpress-vram"; - reg = <2 0x00000000 0x00800000>; - }; + v2m_fixed_3v3: v2m-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - ethernet@2,02000000 { - compatible = "smsc,lan91c111"; - reg = <2 0x02000000 0x10000>; - interrupts = <0 15 4>; - }; + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; + clock-output-names = "v2m:oscclk1"; }; - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; }; - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; }; - iofpga@3,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - }; - - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <0 11 4>; - clocks = <&v2m_clk24mhz>; - clock-names = "apb_pclk"; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <0 9 4 0 10 4>; - cd-gpios = <&v2m_sysreg 0 0>; - wp-gpios = <&v2m_sysreg 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <0 12 4>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <0 13 4>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: uart@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <0 5 4>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: uart@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <0 6 4>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: uart@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <0 7 4>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: uart@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <0 8 4>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0 0 4>; - clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; - clock-names = "wdogclk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <0 2 4>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <0 3 4>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <0 4 4>; - clocks = <&v2m_clk24mhz>; - clock-names = "apb_pclk"; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupts = <0 14 4>; - clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; - clock-names = "clcdclk", "apb_pclk"; - mode = "XVGA"; - use_dma = <0>; - framebuffer = <0x18000000 0x00180000>; - }; + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; - virtio_block@130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x1000>; - interrupts = <0 0x2a 4>; - }; + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; }; - v2m_fixed_3v3: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; }; + }; - mcc { - compatible = "arm,vexpress,config-bus", "simple-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - v2m_oscclk1: osc { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; + bus@8000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x8000000 0 0x8000000 0x18000000>; + + motherboard-bus@8000000 { + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + flash@0 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; }; - /* - * Not supported in FVP models - * - * reset@0 { - * compatible = "arm,vexpress-reset"; - * arm,vexpress-sysreg,func = <5 0>; - * }; - */ - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; + ethernet@202000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; }; - /* - * Not used - Superseded by PSCI sys_poweroff - * - * shutdown@0 { - * compatible = "arm,vexpress-shutdown"; - * arm,vexpress-sysreg,func = <8 0>; - * }; - */ - - /* - * Not used - Superseded by PSCI sys_reset - * - * reboot@0 { - * compatible = "arm,vexpress-reboot"; - * arm,vexpress-sysreg,func = <9 0>; - * }; - */ - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; + iofpga-bus@300000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x210000>; + + v2m_sysreg: sysreg@10000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@20000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + }; + + aaci@40000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mmc@50000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9>, <10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@60000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@70000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: serial@90000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: serial@a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: serial@b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: serial@c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + watchdog@f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + virtio@130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x200>; + interrupts = <42>; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; + clock-names = "clcdclk", "apb_pclk"; + memory-region = <&vram>; + + port { + clcd_pads: endpoint { + remote-endpoint = <&panel_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; }; }; }; +}; diff --git a/fdts/stm32mp1-cot-descriptors.dtsi b/fdts/stm32mp1-cot-descriptors.dtsi new file mode 100644 index 000000000..eb632ffa8 --- /dev/null +++ b/fdts/stm32mp1-cot-descriptors.dtsi @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2020-2022, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/nv_cntr_ids.h> +#include <common/tbbr/tbbr_img_def.h> +#include <tools_share/tbbr_oid.h> + +cot { + manifests { + compatible = "arm, cert-descs"; + + stm32mp_cfg_cert: stm32mp_cfg_cert { + root-certificate; + image-id = <STM32MP_CONFIG_CERT_ID>; + antirollback-counter = <&trusted_nv_counter>; + + hw_config_hash: hw_config_hash { + oid = HW_CONFIG_HASH_OID; + }; + + fw_config_hash: fw_config_hash { + oid = FW_CONFIG_HASH_OID; + }; + }; + + trusted_key_cert: trusted_key_cert { + root-certificate; + image-id = <TRUSTED_KEY_CERT_ID>; + antirollback-counter = <&trusted_nv_counter>; + + trusted_world_pk: trusted_world_pk { + oid = TRUSTED_WORLD_PK_OID; + }; + non_trusted_world_pk: non_trusted_world_pk { + oid = NON_TRUSTED_WORLD_PK_OID; + }; + }; + + trusted_os_fw_key_cert: trusted_os_fw_key_cert { + image-id = <TRUSTED_OS_FW_KEY_CERT_ID>; + parent = <&trusted_key_cert>; + signing-key = <&trusted_world_pk>; + antirollback-counter = <&trusted_nv_counter>; + + tos_fw_content_pk: tos_fw_content_pk { + oid = TRUSTED_OS_FW_CONTENT_CERT_PK_OID; + }; + }; + + trusted_os_fw_content_cert: trusted_os_fw_content_cert { + image-id = <TRUSTED_OS_FW_CONTENT_CERT_ID>; + parent = <&trusted_os_fw_key_cert>; + signing-key = <&tos_fw_content_pk>; + antirollback-counter = <&trusted_nv_counter>; + + tos_fw_hash: tos_fw_hash { + oid = TRUSTED_OS_FW_HASH_OID; + }; + tos_fw_extra1_hash: tos_fw_extra1_hash { + oid = TRUSTED_OS_FW_EXTRA1_HASH_OID; + }; + tos_fw_extra2_hash: tos_fw_extra2_hash { + oid = TRUSTED_OS_FW_EXTRA2_HASH_OID; + }; + tos_fw_config_hash: tos_fw_config_hash { + oid = TRUSTED_OS_FW_CONFIG_HASH_OID; + }; + }; + + non_trusted_fw_key_cert: non_trusted_fw_key_cert { + image-id = <NON_TRUSTED_FW_KEY_CERT_ID>; + parent = <&trusted_key_cert>; + signing-key = <&non_trusted_world_pk>; + antirollback-counter = <&non_trusted_nv_counter>; + + nt_fw_content_pk: nt_fw_content_pk { + oid = NON_TRUSTED_FW_CONTENT_CERT_PK_OID; + }; + }; + + non_trusted_fw_content_cert: non_trusted_fw_content_cert { + image-id = <NON_TRUSTED_FW_CONTENT_CERT_ID>; + parent = <&non_trusted_fw_key_cert>; + signing-key = <&nt_fw_content_pk>; + antirollback-counter = <&non_trusted_nv_counter>; + + nt_world_bl_hash: nt_world_bl_hash { + oid = NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID; + }; + }; + }; + + images { + compatible = "arm, img-descs"; + + hw_config { + image-id = <HW_CONFIG_ID>; + parent = <&stm32mp_cfg_cert>; + hash = <&hw_config_hash>; + }; + + fw_config { + image-id = <FW_CONFIG_ID>; + parent = <&stm32mp_cfg_cert>; + hash = <&fw_config_hash>; + }; + + bl32_image { + image-id = <BL32_IMAGE_ID>; + parent = <&trusted_os_fw_content_cert>; + hash = <&tos_fw_hash>; + }; + + bl32_extra1_image { + image-id = <BL32_EXTRA1_IMAGE_ID>; + parent = <&trusted_os_fw_content_cert>; + hash = <&tos_fw_extra1_hash>; + }; + + bl32_extra2_image { + image-id = <BL32_EXTRA2_IMAGE_ID>; + parent = <&trusted_os_fw_content_cert>; + hash = <&tos_fw_extra2_hash>; + }; + + tos_fw_config { + image-id = <TOS_FW_CONFIG_ID>; + parent = <&trusted_os_fw_content_cert>; + hash = <&tos_fw_config_hash>; + }; + + bl33_image { + image-id = <BL33_IMAGE_ID>; + parent = <&non_trusted_fw_content_cert>; + hash = <&nt_world_bl_hash>; + }; + }; +}; + +non_volatile_counters: non_volatile_counters { + #address-cells = <1>; + #size-cells = <0>; + + trusted_nv_counter: trusted_nv_counter { + id = <TRUSTED_NV_CTR_ID>; + oid = TRUSTED_FW_NVCOUNTER_OID; + }; + + non_trusted_nv_counter: non_trusted_nv_counter { + id = <NON_TRUSTED_NV_CTR_ID>; + oid = NON_TRUSTED_FW_NVCOUNTER_OID; + }; +}; diff --git a/fdts/stm32mp13-bl2.dtsi b/fdts/stm32mp13-bl2.dtsi index 41d6e2e88..836e9ae4c 100644 --- a/fdts/stm32mp13-bl2.dtsi +++ b/fdts/stm32mp13-bl2.dtsi @@ -9,70 +9,12 @@ /delete-property/ mmc0; /delete-property/ mmc1; #endif - /delete-property/ ethernet0; - /delete-property/ ethernet1; }; - cpus { - cpu@0 { - /delete-property/ operating-points-v2; - }; - }; - - /delete-node/ cpu0-opp-table; - /delete-node/ psci; - soc { - /delete-node/ sram@30000000; - /delete-node/ timer@40000000; - /delete-node/ timer@40001000; - /delete-node/ timer@40002000; - /delete-node/ timer@40003000; - /delete-node/ timer@40004000; - /delete-node/ timer@40005000; - /delete-node/ timer@40009000; - /delete-node/ spi@4000b000; - /delete-node/ audio-controller@4000b000; - /delete-node/ spi@4000c000; - /delete-node/ audio-controller@4000c000; - /delete-node/ audio-controller@4000d000; - /delete-node/ i2c@40012000; - /delete-node/ i2c@40013000; - /delete-node/ timer@44000000; - /delete-node/ timer@44001000; - /delete-node/ spi@44004000; - /delete-node/ audio-controller@44004000; - /delete-node/ sai@4400a000; - /delete-node/ sai@4400b000; - /delete-node/ dfsdm@4400d000; - /delete-node/ can@4400e000; - /delete-node/ can@4400f000; - /delete-node/ dma-controller@48000000; - /delete-node/ dma-controller@48001000; - /delete-node/ dma-router@48002000; - /delete-node/ adc@48003000; - /delete-node/ adc@48004000; - /delete-node/ dma@48005000; - /delete-node/ dma-router@48006000; #if !STM32MP_USB_PROGRAMMER /delete-node/ usb-otg@49000000; #endif - /delete-node/ spi@4c002000; - /delete-node/ spi@4c003000; - /delete-node/ timer@4c007000; - /delete-node/ timer@4c008000; - /delete-node/ timer@4c009000; - /delete-node/ timer@4c00a000; - /delete-node/ timer@4c00b000; - /delete-node/ timer@4c00c000; - /delete-node/ timer@50021000; - /delete-node/ timer@50022000; - /delete-node/ timer@50023000; - /delete-node/ timer@50024000; - /delete-node/ vrefbuf@50025000; - /delete-node/ thermal@50028000; - /delete-node/ hdp@5002a000; - /delete-node/ dma-controller@58000000; #if !STM32MP_RAW_NAND /delete-node/ memory-controller@58002000; #endif @@ -83,25 +25,15 @@ /delete-node/ mmc@58005000; /delete-node/ mmc@58007000; #endif - /delete-node/ crc@58009000; - /delete-node/ stmmac-axi-config; - /delete-node/ eth1@5800a000; #if !STM32MP_USB_PROGRAMMER /delete-node/ usbh-ohci@5800c000; /delete-node/ usbh-ehci@5800d000; #endif - /delete-node/ eth2@5800e000; - /delete-node/ dcmipp@5a000000; - /delete-node/ display-controller@5a001000; #if !STM32MP_USB_PROGRAMMER /delete-node/ usbphyc@5a006000; #endif - /delete-node/ perf@5a007000; - /delete-node/ rtc@5c004000; - /delete-node/ tamp@5c00a000; - /delete-node/ stgen@5c008000; - pin-controller@50002000 { + pinctrl@50002000 { #if !STM32MP_EMMC && !STM32MP_SDMMC /delete-node/ sdmmc1-b4-0; /delete-node/ sdmmc2-b4-0; @@ -124,7 +56,30 @@ bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4"; hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc"; tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021"; - nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9"; +#if TRUSTED_BOARD_BOOT + stm32mp_cfg_cert_uuid = "501d8dd2-8bce-49a5-84eb-559a9f2eaeaf"; + t_key_cert_uuid = "827ee890-f860-e411-a1b4-777a21b4f94c"; + tos_fw_key_cert_uuid = "9477d603-fb60-e411-85dd-b7105b8cee04"; + nt_fw_key_cert_uuid = "8ad5832a-fb60-e411-8aaf-df30bbc49859"; + tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d"; + nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7"; +#endif }; }; + +#if TRUSTED_BOARD_BOOT + tb_fw-config { + compatible = "arm,tb_fw"; + + /* Disable authentication for development */ + disable_auth = <0x0>; + + /* Use SRAM2 to manage the mbedTLS heap */ + mbedtls_heap_addr = <0x0 0x30004000>; /* SRAM2_BASE */ + mbedtls_heap_size = <0x2000>; /* SRAM2_SIZE */ + }; + +#include "stm32mp1-cot-descriptors.dtsi" +#endif + }; diff --git a/fdts/stm32mp13-fw-config.dtsi b/fdts/stm32mp13-fw-config.dtsi index 28f7086c3..4f3bb726b 100644 --- a/fdts/stm32mp13-fw-config.dtsi +++ b/fdts/stm32mp13-fw-config.dtsi @@ -13,7 +13,7 @@ #endif #define DDR_NS_BASE STM32MP_DDR_BASE -#define DDR_SEC_SIZE 0x02000000 +#define DDR_SEC_SIZE STM32MP_DDR_S_SIZE #define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE)) #define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE) diff --git a/fdts/stm32mp13-pinctrl.dtsi b/fdts/stm32mp13-pinctrl.dtsi index 0ad06a4e1..879da9c0d 100644 --- a/fdts/stm32mp13-pinctrl.dtsi +++ b/fdts/stm32mp13-pinctrl.dtsi @@ -17,7 +17,7 @@ }; sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ @@ -27,16 +27,19 @@ drive-push-pull; bias-disable; }; - pins2 { + }; + + sdmmc1_clk_pins_a: sdmmc1-clk-0 { + pins { pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ - slew-rate = <2>; + slew-rate = <1>; drive-push-pull; bias-disable; }; }; sdmmc2_b4_pins_a: sdmmc2-b4-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ @@ -46,9 +49,12 @@ drive-push-pull; bias-pull-up; }; - pins2 { + }; + + sdmmc2_clk_pins_a: sdmmc2-clk-0 { + pins { pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */ - slew-rate = <2>; + slew-rate = <1>; drive-push-pull; bias-pull-up; }; diff --git a/fdts/stm32mp131.dtsi b/fdts/stm32mp131.dtsi index adf7a91d6..543afa5c4 100644 --- a/fdts/stm32mp131.dtsi +++ b/fdts/stm32mp131.dtsi @@ -259,15 +259,6 @@ clocks = <&rcc SYSCFG>; }; - vrefbuf: vrefbuf@50025000 { - compatible = "st,stm32-vrefbuf"; - reg = <0x50025000 0x8>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - clocks = <&rcc VREF>; - status = "disabled"; - }; - hash: hash@54003000 { compatible = "st,stm32mp13-hash"; reg = <0x54003000 0x400>; @@ -333,7 +324,7 @@ resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <120000000>; + max-frequency = <130000000>; status = "disabled"; }; @@ -346,16 +337,10 @@ resets = <&rcc SDMMC2_R>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <120000000>; + max-frequency = <130000000>; status = "disabled"; }; - crc1: crc@58009000 { - compatible = "st,stm32f7-crc"; - reg = <0x58009000 0x400>; - clocks = <&rcc CRC1>; - }; - usbh_ohci: usbh-ohci@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; @@ -383,7 +368,7 @@ status = "disabled"; }; - ddr: ddr@5a003000{ + ddr: ddr@5a003000 { compatible = "st,stm32mp13-ddr"; reg = <0x5a003000 0x550>, <0x5a004000 0x234>; clocks = <&rcc AXIDCG>, @@ -470,17 +455,15 @@ reg = <0xe4 0xc>; st,non-secure-otp; }; + enckey_otp: enckey_otp@170 { + reg = <0x170 0x10>; + }; }; - - tamp: tamp@5c00a000 { - reg = <0x5c00a000 0x400>; - }; - /* * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp135-pinctrl"; diff --git a/fdts/stm32mp133.dtsi b/fdts/stm32mp133.dtsi index 8bbcc6154..bb468c024 100644 --- a/fdts/stm32mp133.dtsi +++ b/fdts/stm32mp133.dtsi @@ -5,17 +5,3 @@ */ #include "stm32mp131.dtsi" - -/ { - soc { - m_can1: can@4400e000 { - reg = <0x4400e000 0x400>, <0x44011000 0x1400>; - status = "disabled"; - }; - - m_can2: can@4400f000 { - reg = <0x4400f000 0x400>, <0x44011000 0x2800>; - status = "disabled"; - }; - }; -}; diff --git a/fdts/stm32mp135.dtsi b/fdts/stm32mp135.dtsi index 415bb9b59..b5ebdd9bf 100644 --- a/fdts/stm32mp135.dtsi +++ b/fdts/stm32mp135.dtsi @@ -5,8 +5,3 @@ */ #include "stm32mp133.dtsi" - -/ { - soc { - }; -}; diff --git a/fdts/stm32mp135f-dk.dts b/fdts/stm32mp135f-dk.dts index 624038110..0f06b671d 100644 --- a/fdts/stm32mp135f-dk.dts +++ b/fdts/stm32mp135f-dk.dts @@ -176,7 +176,7 @@ }; &pka { - secure-status = "okay"; + status = "okay"; }; &pwr_regulators { @@ -228,13 +228,13 @@ frac = < 0x1400 >; }; - pll3_vco_417_8Mhz: pll2-vco-417_8Mhz { + pll3_vco_417_8Mhz: pll3-vco-417_8Mhz { src = < CLK_PLL3_HSE >; divmn = < 1 33 >; frac = < 0x1a04 >; }; - pll4_vco_600Mhz: pll2-vco-600Mhz { + pll4_vco_600Mhz: pll4-vco-600Mhz { src = < CLK_PLL4_HSE >; divmn = < 1 49 >; }; @@ -298,12 +298,12 @@ }; &saes { - secure-status = "okay"; + status = "okay"; }; &sdmmc1 { pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; disable-wp; st,neg-edge; bus-width = <4>; diff --git a/fdts/stm32mp13xc.dtsi b/fdts/stm32mp13xc.dtsi index c03bd43a3..4b30c5c32 100644 --- a/fdts/stm32mp13xc.dtsi +++ b/fdts/stm32mp13xc.dtsi @@ -8,15 +8,6 @@ / { soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; - saes: saes@54005000 { compatible = "st,stm32-saes"; reg = <0x54005000 0x400>; diff --git a/fdts/stm32mp13xf.dtsi b/fdts/stm32mp13xf.dtsi index e467d71af..887c4e006 100644 --- a/fdts/stm32mp13xf.dtsi +++ b/fdts/stm32mp13xf.dtsi @@ -7,15 +7,6 @@ / { soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; - saes: saes@54005000 { compatible = "st,stm32-saes"; reg = <0x54005000 0x400>; diff --git a/fdts/stm32mp15-bl2.dtsi b/fdts/stm32mp15-bl2.dtsi index d00e35b29..5489a624e 100644 --- a/fdts/stm32mp15-bl2.dtsi +++ b/fdts/stm32mp15-bl2.dtsi @@ -46,7 +46,7 @@ /delete-node/ i2c@5c009000; /delete-node/ tamp@5c00a000; - pin-controller@50002000 { + pinctrl@50002000 { #if !STM32MP_RAW_NAND /delete-node/ fmc-0; #endif @@ -69,7 +69,6 @@ }; }; -#if !STM32MP_USE_STM32IMAGE /* * UUID's here are UUID RFC 4122 compliant meaning fieds are stored in * network order (big endian) @@ -85,8 +84,32 @@ bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4"; hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc"; tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021"; - nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9"; +#if TRUSTED_BOARD_BOOT + stm32mp_cfg_cert_uuid = "501d8dd2-8bce-49a5-84eb-559a9f2eaeaf"; + t_key_cert_uuid = "827ee890-f860-e411-a1b4-777a21b4f94c"; + tos_fw_key_cert_uuid = "9477d603-fb60-e411-85dd-b7105b8cee04"; + nt_fw_key_cert_uuid = "8ad5832a-fb60-e411-8aaf-df30bbc49859"; + tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d"; + nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7"; +#endif }; }; -#endif /* !STM32MP_USE_STM32IMAGE */ + +#if TRUSTED_BOARD_BOOT + tb_fw-config { + compatible = "arm,tb_fw"; + + /* Disable authentication for development */ + disable_auth = <0x0>; + + /* + * The following two entries are placeholders for Mbed TLS + * heap information. + */ + mbedtls_heap_addr = <0x0 0x0>; + mbedtls_heap_size = <0x0>; + }; + +#include "stm32mp1-cot-descriptors.dtsi" +#endif }; diff --git a/fdts/stm32mp15-bl32.dtsi b/fdts/stm32mp15-bl32.dtsi index ca4bb3ea5..31b24f647 100644 --- a/fdts/stm32mp15-bl32.dtsi +++ b/fdts/stm32mp15-bl32.dtsi @@ -27,7 +27,7 @@ /delete-node/ stgen@5c008000; /delete-node/ i2c@5c009000; - pin-controller@50002000 { + pinctrl@50002000 { /delete-node/ fmc-0; /delete-node/ qspi-clk-0; /delete-node/ qspi-bk1-0; diff --git a/fdts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi b/fdts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi new file mode 100644 index 000000000..ff184c2bc --- /dev/null +++ b/fdts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2020, DH electronics - All Rights Reserved + * + * STM32MP15xx DHSOM configuration + * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W634GU6NB15I from Winbond + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 32 + * datasheet 0 = W634GU6NB15I / DDR3-1333 + * DDR density 8 + * timing mode optimized + * address mapping : RBC + * Tc > + 85C : J + */ + +#define DDR_MEM_NAME "DDR3L 32bits 2x4Gb 533MHz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x40000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0040008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B1214 +#define DDR_DRAMTMG1 0x000A041C +#define DDR_DRAMTMG2 0x0608090F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x08040608 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02060105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000C01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x01000001 +#define DDR_PERFLPR1 0x08000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00010000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x02100C03 +#define DDR_PCFGQOS1_0 0x00800100 +#define DDR_PCFGWQOS0_0 0x01100C03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PCFGR_1 0x00010000 +#define DDR_PCFGW_1 0x00000000 +#define DDR_PCFGQOS0_1 0x02100C03 +#define DDR_PCFGQOS1_1 0x00800040 +#define DDR_PCFGWQOS0_1 0x01100C03 +#define DDR_PCFGWQOS1_1 0x01000200 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x0F070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x38D488D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000840 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000248 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX1GCR 0x0000CE81 +#define DDR_DX2GCR 0x0000CE81 +#define DDR_DX3GCR 0x0000CE81 + +#include "stm32mp15-ddr.dtsi" diff --git a/fdts/stm32mp15-fw-config.dtsi b/fdts/stm32mp15-fw-config.dtsi index 8aece289a..d58367292 100644 --- a/fdts/stm32mp15-fw-config.dtsi +++ b/fdts/stm32mp15-fw-config.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved */ #include <common/tbbr/tbbr_img_def.h> @@ -14,7 +14,7 @@ #define DDR_NS_BASE STM32MP_DDR_BASE #ifdef AARCH32_SP_OPTEE -/* OP-TEE reserved shared memory: located at DDR top */ +/* OP-TEE reserved shared memory: located at DDR top or null size */ #define DDR_SHARE_SIZE STM32MP_DDR_SHMEM_SIZE #define DDR_SHARE_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SHARE_SIZE)) /* OP-TEE secure memory: located right below OP-TEE reserved shared memory */ @@ -70,8 +70,11 @@ memory-ranges = < DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0 +#if STM32MP15_OPTEE_RSV_SHM DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE - TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)>; + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) +#endif + >; #else memory-ranges = < DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR>; diff --git a/fdts/stm32mp15-pinctrl.dtsi b/fdts/stm32mp15-pinctrl.dtsi index d74dc2b09..7d2be0b83 100644 --- a/fdts/stm32mp15-pinctrl.dtsi +++ b/fdts/stm32mp15-pinctrl.dtsi @@ -114,6 +114,21 @@ drive-push-pull; bias-pull-up; }; + pins2 { + pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; pins2{ pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ bias-pull-up; @@ -182,6 +197,18 @@ }; }; + sdmmc2_d47_pins_c: sdmmc2-d47-2 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + sdmmc2_d47_pins_d: sdmmc2-d47-3 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi index 63cc917bc..a938edc0c 100644 --- a/fdts/stm32mp151.dtsi +++ b/fdts/stm32mp151.dtsi @@ -360,7 +360,7 @@ status = "disabled"; }; - ddr: ddr@5a003000{ + ddr: ddr@5a003000 { compatible = "st,stm32mp1-ddr"; reg = <0x5A003000 0x550 0x5A004000 0x234>; clocks = <&rcc AXIDCG>, @@ -487,6 +487,9 @@ ts_cal2: calib@5e { reg = <0x5e 0x2>; }; + pkh_otp: pkh_otp@60 { + reg = <0x60 0x20>; + }; mac_addr: mac_addr@e4 { reg = <0xe4 0x8>; st,non-secure-otp; @@ -497,8 +500,6 @@ compatible = "st,stm32-etzpc"; reg = <0x5C007000 0x400>; clocks = <&rcc TZPC>; - status = "disabled"; - secure-status = "okay"; }; stgen: stgen@5c008000 { @@ -532,7 +533,7 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-pinctrl"; @@ -663,7 +664,7 @@ }; }; - pinctrl_z: pin-controller-z@54004000 { + pinctrl_z: pinctrl@54004000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts index b967736e4..f0da350bb 100644 --- a/fdts/stm32mp157a-avenger96.dts +++ b/fdts/stm32mp157a-avenger96.dts @@ -115,10 +115,9 @@ vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; regulator-always-on; regulator-over-current-protection; + st,regulator-sink-source; }; vdd_usb: ldo4 { @@ -143,7 +142,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -165,7 +163,6 @@ &iwdg2 { timeout-sec = <32>; status = "okay"; - secure-status = "okay"; }; &pwr_regulators { @@ -174,7 +171,6 @@ }; &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/fdts/stm32mp157a-dhcor-avenger96-fw-config.dts b/fdts/stm32mp157a-dhcor-avenger96-fw-config.dts new file mode 100644 index 000000000..2abbe50e6 --- /dev/null +++ b/fdts/stm32mp157a-dhcor-avenger96-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157a-dhcor-avenger96.dts b/fdts/stm32mp157a-dhcor-avenger96.dts new file mode 100644 index 000000000..82d48aa09 --- /dev/null +++ b/fdts/stm32mp157a-dhcor-avenger96.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + * Copyright (C) 2022 DH electronics GmbH + * + * DHCOR STM32MP1 variant: + * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG + * DHCOR PCB number: 586-100 or newer + * Avenger96 PCB number: 588-200 or newer + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-avenger96.dtsi" + +/ { + model = "Arrow Electronics STM32MP157A Avenger96 board"; + compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som", + "st,stm32mp157"; +}; diff --git a/fdts/stm32mp157c-dhcom-pdk2-fw-config.dts b/fdts/stm32mp157c-dhcom-pdk2-fw-config.dts new file mode 100644 index 000000000..6a5a192ac --- /dev/null +++ b/fdts/stm32mp157c-dhcom-pdk2-fw-config.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (c) 2022 DH electronics GmbH + */ + +#define DDR_SIZE 0x40000000 /* 1GB */ +#include "stm32mp15-fw-config.dtsi" diff --git a/fdts/stm32mp157c-dhcom-pdk2.dts b/fdts/stm32mp157c-dhcom-pdk2.dts new file mode 100644 index 000000000..370a69a4a --- /dev/null +++ b/fdts/stm32mp157c-dhcom-pdk2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> + * Copyright (C) 2022 DH electronics GmbH + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2 + * DHCOM PCB number: 587-200 or newer + * PDK2 PCB number: 516-400 or newer + */ +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-pdk2.dtsi" + +/ { + model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)"; + compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som", + "st,stm32mp157"; +}; + +&cryp1 { + status = "okay"; +}; diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index 659e8bf85..d9285638a 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts @@ -201,7 +201,6 @@ }; &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/fdts/stm32mp157c-odyssey-som.dtsi b/fdts/stm32mp157c-odyssey-som.dtsi index 6bed33968..091e327cf 100644 --- a/fdts/stm32mp157c-odyssey-som.dtsi +++ b/fdts/stm32mp157c-odyssey-som.dtsi @@ -140,10 +140,9 @@ vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; regulator-always-on; regulator-over-current-protection; + st,regulator-sink-source; }; vdd_usb: ldo4 { @@ -170,7 +169,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -205,7 +203,6 @@ }; &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/fdts/stm32mp15xx-dhcom-pdk2.dtsi b/fdts/stm32mp15xx-dhcom-pdk2.dtsi new file mode 100644 index 000000000..1ffc60db6 --- /dev/null +++ b/fdts/stm32mp15xx-dhcom-pdk2.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> + * Copyright (C) 2022 DH electronics GmbH + */ + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/fdts/stm32mp15xx-dhcom-som.dtsi b/fdts/stm32mp15xx-dhcom-som.dtsi new file mode 100644 index 000000000..c9f21b0e6 --- /dev/null +++ b/fdts/stm32mp15xx-dhcom-som.dtsi @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> + * Copyright (C) 2022 DH electronics GmbH + */ + +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include <dt-bindings/clock/stm32mp1-clksrc.h> +#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" + +/ { + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x40000000>; + }; +}; + +&bsec { + board_id: board_id@ec { + reg = <0xec 0x4>; + st,non-secure-otp; + }; +}; + +&cpu0 { + cpu-supply = <&vddcore>; +}; + +&cpu1 { + cpu-supply = <&vddcore>; +}; + +&hash1 { + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-always-on; + regulator-over-current-protection; + st,regulator-sink-source; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + regulator-active-discharge = <1>; + }; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rcc { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_PLL4P + >; + + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 1 /*MCO2*/ + >; + + st,pkcs = < + CLK_CKPER_HSE + CLK_FMC_ACLK + CLK_QSPI_ACLK + CLK_ETH_PLL4P + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_SPI2S1_PLL3Q + CLK_SPI2S23_PLL3Q + CLK_SPI45_HSI + CLK_SPI6_HSI + CLK_I2C46_HSI + CLK_SDMMC3_PLL4P + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_HSI + CLK_UART1_HSI + CLK_UART24_HSI + CLK_UART35_HSI + CLK_UART6_HSI + CLK_UART78_HSI + CLK_SPDIF_PLL4P + CLK_FDCAN_PLL4R + CLK_SAI1_PLL3Q + CLK_SAI2_PLL3Q + CLK_SAI3_PLL3Q + CLK_SAI4_PLL3Q + CLK_RNG1_LSI + CLK_RNG2_LSI + CLK_LPTIM1_PCLK1 + CLK_LPTIM23_PCLK3 + CLK_LPTIM45_LSE + >; + + /* VCO = 1300.0 MHz => P = 650 (CPU) */ + pll1: st,pll@0 { + compatible = "st,stm32mp1-pll"; + reg = <0>; + cfg = <2 80 0 0 0 PQR(1,0,0)>; + frac = <0x800>; + }; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ + pll2: st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = <2 65 1 0 0 PQR(1,1,1)>; + frac = <0x1400>; + }; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ + pll3: st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = <1 33 1 16 36 PQR(1,1,1)>; + frac = <0x1a04>; + }; + + /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */ + pll4: st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = <1 49 5 11 11 PQR(1,1,1)>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + disable-wp; + st,sig-dir; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&sdmmc1_b4_pins_a { + /* + * SD bus pull-up resistors: + * - optional on SoMs with SD voltage translator + * - mandatory on SoMs without SD voltage translator + */ + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + +&sdmmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/fdts/stm32mp15xx-dhcor-avenger96.dtsi b/fdts/stm32mp15xx-dhcor-avenger96.dtsi new file mode 100644 index 000000000..576e0f11a --- /dev/null +++ b/fdts/stm32mp15xx-dhcor-avenger96.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + * Copyright (C) 2022 DH electronics GmbH + */ + +/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */ +#include "stm32mp15xx-dhcor-io1v8.dtsi" + +/ { + aliases { + serial0 = &uart4; + serial1 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 0>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +&sdmmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd_io>; + status = "okay"; +}; + +&uart4 { + /* On Low speed expansion header */ + label = "LS-UART1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + status = "okay"; +}; + +&uart7 { + /* On Low speed expansion header */ + label = "LS-UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/fdts/stm32mp15xx-dhcor-io1v8.dtsi b/fdts/stm32mp15xx-dhcor-io1v8.dtsi new file mode 100644 index 000000000..9937b2854 --- /dev/null +++ b/fdts/stm32mp15xx-dhcor-io1v8.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + */ + +/ { + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&vdd { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; +}; + +&pwr_regulators { + vdd-supply = <&vdd_io>; +}; diff --git a/fdts/stm32mp15xx-dhcor-som.dtsi b/fdts/stm32mp15xx-dhcor-som.dtsi new file mode 100644 index 000000000..c241efc48 --- /dev/null +++ b/fdts/stm32mp15xx-dhcor-som.dtsi @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + * Copyright (C) 2022 DH electronics GmbH + */ + +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include <dt-bindings/clock/stm32mp1-clksrc.h> +#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" + +/ { + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x40000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vddcore>; +}; + +&cpu1 { + cpu-supply = <&vddcore>; +}; + +&hash1 { + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-always-on; + regulator-over-current-protection; + st,regulator-sink-source; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <300000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + regulator-active-discharge = <1>; + }; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rcc { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + + st,pkcs = < + CLK_CKPER_HSE + CLK_FMC_ACLK + CLK_QSPI_ACLK + CLK_ETH_DISABLED + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_SPI2S1_PLL3Q + CLK_SPI2S23_PLL3Q + CLK_SPI45_HSI + CLK_SPI6_HSI + CLK_I2C46_HSI + CLK_SDMMC3_PLL4P + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_HSI + CLK_UART1_HSI + CLK_UART24_HSI + CLK_UART35_HSI + CLK_UART6_HSI + CLK_UART78_HSI + CLK_SPDIF_PLL4P + CLK_FDCAN_PLL4R + CLK_SAI1_PLL3Q + CLK_SAI2_PLL3Q + CLK_SAI3_PLL3Q + CLK_SAI4_PLL3Q + CLK_RNG1_LSI + CLK_RNG2_LSI + CLK_LPTIM1_PCLK1 + CLK_LPTIM23_PCLK3 + CLK_LPTIM45_LSE + >; + + /* VCO = 1300.0 MHz => P = 650 (CPU) */ + pll1: st,pll@0 { + compatible = "st,stm32mp1-pll"; + reg = <0>; + cfg = <2 80 0 0 0 PQR(1,0,0)>; + frac = <0x800>; + }; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ + pll2: st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = <2 65 1 0 0 PQR(1,1,1)>; + frac = <0x1400>; + }; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ + pll3: st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = <1 33 1 16 36 PQR(1,1,1)>; + frac = <0x1a04>; + }; + + /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ + pll4: st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = <3 98 5 7 5 PQR(1,1,1)>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi index 05eb46a68..52d4170fd 100644 --- a/fdts/stm32mp15xx-dkx.dtsi +++ b/fdts/stm32mp15xx-dkx.dtsi @@ -33,11 +33,11 @@ st,digbypass; }; -&cpu0{ +&cpu0 { cpu-supply = <&vddcore>; }; -&cpu1{ +&cpu1 { cpu-supply = <&vddcore>; }; @@ -180,7 +180,6 @@ &iwdg2 { timeout-sec = <32>; status = "okay"; - secure-status = "okay"; }; &pwr_regulators { @@ -189,7 +188,6 @@ }; &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P @@ -304,10 +302,6 @@ status = "okay"; }; -&timers15 { - secure-status = "okay"; -}; - &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; diff --git a/fdts/stm32mp15xx-osd32.dtsi b/fdts/stm32mp15xx-osd32.dtsi index 76a25613a..52a5d380b 100644 --- a/fdts/stm32mp15xx-osd32.dtsi +++ b/fdts/stm32mp15xx-osd32.dtsi @@ -81,10 +81,9 @@ vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; regulator-always-on; regulator-over-current-protection; + st,regulator-sink-source; }; vdd_usb: ldo4 { @@ -110,7 +109,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -169,11 +167,11 @@ st,digbypass; }; -&cpu0{ +&cpu0 { cpu-supply = <&vddcore>; }; -&cpu1{ +&cpu1 { cpu-supply = <&vddcore>; }; @@ -183,7 +181,6 @@ /* CLOCK init */ &rcc { - secure-status = "disabled"; st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/fdts/tc.dts b/fdts/tc.dts index 20992294b..5a8792e83 100644 --- a/fdts/tc.dts +++ b/fdts/tc.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -336,6 +336,15 @@ status = "okay"; }; + rtc0: rtc@1C170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0x1C170000 0x0 0x1000>; + interrupts = <0x0 100 0x4>; + clocks = <&soc_refclk100mhz>; + clock-names = "apb_pclk"; + wakeup-source; + }; + vencoder { compatible = "drm,virtual-encoder"; diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index bdff25b4b..8678bf3d8 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -617,6 +617,12 @@ #define ICC_ASGI1R_EL1_64 p15, 1, c12 #define ICC_SGI0R_EL1_64 p15, 2, c12 +/* Fault registers. The format is: coproc, opt1, CRn, CRm, opt2 */ +#define DFSR p15, 0, c5, c0, 0 +#define IFSR p15, 0, c5, c0, 1 +#define DFAR p15, 0, c6, c0, 0 +#define IFAR p15, 0, c6, c0, 2 + /******************************************************************************* * Definitions of MAIR encodings for device and normal memory ******************************************************************************/ diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h index 033098915..95d056f45 100644 --- a/include/arch/aarch32/arch_helpers.h +++ b/include/arch/aarch32/arch_helpers.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -282,6 +283,7 @@ DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0) DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1) DEFINE_COPROCR_RW_FUNCS_64(icc_sgi0r_el1, ICC_SGI0R_EL1_64) DEFINE_COPROCR_WRITE_FUNC_64(icc_sgi1r, ICC_SGI1R_EL1_64) +DEFINE_COPROCR_WRITE_FUNC_64(icc_asgi1r, ICC_ASGI1R_EL1_64) DEFINE_COPROCR_RW_FUNCS(sdcr, SDCR) DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR) @@ -402,6 +404,8 @@ static inline unsigned int get_current_el(void) #define read_ctr_el0() read_ctr() #define write_icc_sgi0r_el1(_v) write64_icc_sgi0r_el1(_v) +#define write_icc_sgi1r(_v) write64_icc_sgi1r(_v) +#define write_icc_asgi1r(_v) write64_icc_asgi1r(_v) #define read_daif() read_cpsr() #define write_daif(flags) write_cpsr(flags) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index e55d33fd3..f63e9232f 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -79,6 +79,7 @@ ******************************************************************************/ #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 #define ICC_SGI1R S3_0_C12_C11_5 +#define ICC_ASGI1R S3_0_C12_C11_6 #define ICC_SRE_EL1 S3_0_C12_C12_5 #define ICC_SRE_EL2 S3_4_C12_C9_5 #define ICC_SRE_EL3 S3_6_C12_C12_5 @@ -261,6 +262,15 @@ #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) +/* ID_AA64ISAR2_EL1 definitions */ +#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 + +#define ID_AA64ISAR2_GPA3_SHIFT U(8) +#define ID_AA64ISAR2_GPA3_MASK ULL(0xf) + +#define ID_AA64ISAR2_APA3_SHIFT U(12) +#define ID_AA64ISAR2_APA3_MASK ULL(0xf) + /* ID_AA64MMFR0_EL1 definitions */ #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) @@ -353,6 +363,12 @@ #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) +#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) +#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) + +#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) +#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) + /* Memory Tagging Extension is not implemented */ #define MTE_UNIMPLEMENTED U(0) /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ @@ -485,6 +501,7 @@ #define SCR_GPF_BIT (UL(1) << 48) #define SCR_TWEDEL_SHIFT U(30) #define SCR_TWEDEL_MASK ULL(0xf) +#define SCR_TRNDR_BIT (UL(1) << 40) #define SCR_HXEn_BIT (UL(1) << 38) #define SCR_ENTP2_SHIFT U(41) #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 29710e736..932e8850a 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -35,15 +35,30 @@ static inline bool is_armv8_2_ttcnp_present(void) ID_AA64MMFR2_EL1_CNP_MASK) != 0U; } +static inline bool is_feat_pacqarma3_present(void) +{ + uint64_t mask_id_aa64isar2 = + (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | + (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT); + + /* If any of the fields is not zero, QARMA3 algorithm is present */ + return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U; +} + static inline bool is_armv8_3_pauth_present(void) { - uint64_t mask = (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | - (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | - (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | - (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); + uint64_t mask_id_aa64isar1 = + (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | + (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | + (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | + (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); - /* If any of the fields is not zero, PAuth is present */ - return (read_id_aa64isar1_el1() & mask) != 0U; + /* + * If any of the fields is not zero or QARMA3 is present, + * PAuth is present + */ + return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || + is_feat_pacqarma3_present()); } static inline bool is_armv8_4_dit_present(void) @@ -85,7 +100,7 @@ static inline bool is_armv8_6_twed_present(void) static inline bool is_armv8_6_fgt_present(void) { return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) & - ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT_SUPPORTED; + ID_AA64MMFR0_EL1_FGT_MASK) != 0U; } static inline unsigned long int get_armv8_6_ecv_support(void) @@ -129,6 +144,13 @@ static inline bool is_feat_hcx_present(void) ID_AA64MMFR1_EL1_HCX_MASK) == ID_AA64MMFR1_EL1_HCX_SUPPORTED); } +static inline bool is_feat_rng_trap_present(void) +{ + return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) & + ID_AA64PFR1_EL1_RNDR_TRAP_MASK) + == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED); +} + static inline unsigned int get_armv9_2_feat_rme_support(void) { /* @@ -224,4 +246,23 @@ static inline unsigned int get_armv8_4_feat_nv_support(void) ID_AA64MMFR2_EL1_NV_MASK)); } +/******************************************************************************* + * Function to identify the presence of FEAT_BRBE (Branch Record Buffer + * Extension) + ******************************************************************************/ +static inline bool is_feat_brbe_present(void) +{ + return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_BRBE_SHIFT) & + ID_AA64DFR0_BRBE_MASK) == ID_AA64DFR0_BRBE_SUPPORTED); +} + +/******************************************************************************* + * Function to identify the presence of FEAT_TRBE (Trace Buffer Extension) + ******************************************************************************/ +static inline bool is_feat_trbe_present(void) +{ + return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEBUFFER_SHIFT) & + ID_AA64DFR0_TRACEBUFFER_MASK) == ID_AA64DFR0_TRACEBUFFER_SUPPORTED); +} + #endif /* ARCH_FEATURES_H */ diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 10b0a0b97..50a5ad4ad 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -250,6 +250,7 @@ DEFINE_SYSREG_RW_FUNCS(par_el1) DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1) DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) +DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1) DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1) @@ -266,6 +267,8 @@ DEFINE_SYSREG_RW_FUNCS(elr_el3) DEFINE_SYSREG_RW_FUNCS(mdccsr_el0) DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0) DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0) +DEFINE_SYSREG_RW_FUNCS(sp_el1) +DEFINE_SYSREG_RW_FUNCS(sp_el2) DEFINE_SYSOP_FUNC(wfi) DEFINE_SYSOP_FUNC(wfe) @@ -492,6 +495,7 @@ DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r, ICC_ASGI1R) DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0) DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0) diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S index 7706cd831..66c39e5f1 100644 --- a/include/arch/aarch64/asm_macros.S +++ b/include/arch/aarch64/asm_macros.S @@ -215,6 +215,19 @@ .endm /* + * Macro for using speculation barrier instruction introduced by + * FEAT_SB, if it's enabled. + */ + .macro speculation_barrier +#if ENABLE_FEAT_SB + sb +#else + dsb sy + isb +#endif + .endm + + /* * Macro for mitigating against speculative execution beyond ERET. Uses the * speculation barrier instruction introduced by FEAT_SB, if it's enabled. */ diff --git a/include/arch/aarch64/smccc_helpers.h b/include/arch/aarch64/smccc_helpers.h index fac6fd9cf..920f2943e 100644 --- a/include/arch/aarch64/smccc_helpers.h +++ b/include/arch/aarch64/smccc_helpers.h @@ -9,12 +9,26 @@ #include <lib/smccc.h> +/* Definitions to help the assembler access the SMC/ERET args structure */ +#define SMC_ARGS_SIZE 0x40 +#define SMC_ARG0 0x0 +#define SMC_ARG1 0x8 +#define SMC_ARG2 0x10 +#define SMC_ARG3 0x18 +#define SMC_ARG4 0x20 +#define SMC_ARG5 0x28 +#define SMC_ARG6 0x30 +#define SMC_ARG7 0x38 +#define SMC_ARGS_END 0x40 + #ifndef __ASSEMBLER__ #include <stdbool.h> #include <context.h> +#include <platform_def.h> /* For CACHE_WRITEBACK_GRANULE */ + /* Convenience macros to return from SMC handler */ #define SMC_RET0(_h) { \ return (uint64_t) (_h); \ @@ -82,6 +96,49 @@ _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \ } while (false) +typedef struct { + uint64_t _regs[SMC_ARGS_END >> 3]; +} __aligned(CACHE_WRITEBACK_GRANULE) smc_args_t; + +/* + * Ensure that the assembler's view of the size of the tsp_args is the + * same as the compilers. + */ +CASSERT(sizeof(smc_args_t) == SMC_ARGS_SIZE, assert_sp_args_size_mismatch); + +static inline smc_args_t smc_helper(uint32_t func, uint64_t arg0, + uint64_t arg1, uint64_t arg2, + uint64_t arg3, uint64_t arg4, + uint64_t arg5, uint64_t arg6) +{ + smc_args_t ret_args = {0}; + + register uint64_t r0 __asm__("x0") = func; + register uint64_t r1 __asm__("x1") = arg0; + register uint64_t r2 __asm__("x2") = arg1; + register uint64_t r3 __asm__("x3") = arg2; + register uint64_t r4 __asm__("x4") = arg3; + register uint64_t r5 __asm__("x5") = arg4; + register uint64_t r6 __asm__("x6") = arg5; + register uint64_t r7 __asm__("x7") = arg6; + + /* Output registers, also used as inputs ('+' constraint). */ + __asm__ volatile("smc #0" + : "+r"(r0), "+r"(r1), "+r"(r2), "+r"(r3), "+r"(r4), + "+r"(r5), "+r"(r6), "+r"(r7)); + + ret_args._regs[0] = r0; + ret_args._regs[1] = r1; + ret_args._regs[2] = r2; + ret_args._regs[3] = r3; + ret_args._regs[4] = r4; + ret_args._regs[5] = r5; + ret_args._regs[6] = r6; + ret_args._regs[7] = r7; + + return ret_args; +} + #endif /*__ASSEMBLER__*/ #endif /* SMCCC_HELPERS_H */ diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h index 935bf7766..21af112a0 100644 --- a/include/bl31/interrupt_mgmt.h +++ b/include/bl31/interrupt_mgmt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -107,15 +107,23 @@ static inline int32_t validate_ns_interrupt_rm(uint32_t x) static inline int32_t validate_el3_interrupt_rm(uint32_t x) { -#if EL3_EXCEPTION_HANDLING +#if EL3_EXCEPTION_HANDLING && !(defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1)) /* * With EL3 exception handling, EL3 interrupts are always routed to EL3 - * from both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is - * the only valid routing model. + * from both Secure and Non-secure, when the SPMC does not live in S-EL2. + * Therefore INTR_EL3_VALID_RM1 is the only valid routing model. */ if (x == INTR_EL3_VALID_RM1) return 0; #else + /* + * When EL3_EXCEPTION_HANDLING is not defined both routing modes are + * valid. This is the most common case. The exception to this rule is + * when EL3_EXCEPTION_HANDLING is defined but also when the SPMC lives + * at S-EL2. In this case, Group0 Interrupts are trapped to the SPMC + * when running in S-EL0 and S-EL1. The SPMC may handle the interrupt + * itself, delegate it to an SP or forward to EL3 for handling. + */ if ((x == INTR_EL3_VALID_RM0) || (x == INTR_EL3_VALID_RM1)) return 0; #endif diff --git a/include/bl32/pnc/pnc.h b/include/bl32/pnc/pnc.h new file mode 100644 index 000000000..03a32147a --- /dev/null +++ b/include/bl32/pnc/pnc.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PNC_H__ +#define __PNC_H__ + +#define SMC_YIELD 0xbf000000 +#define SMC_ACTION_FROM_S 0xbf000001 +#define SMC_GET_SHAREDMEM 0xbf000002 +#define SMC_CONFIG_SHAREDMEM 0xbf000003 +#define SMC_ACTION_FROM_NS 0xbf000004 + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + +void *pncd_context_switch_to(unsigned long security_state); +int plat_pncd_setup(void); +uintptr_t plat_pncd_smc_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3, + u_register_t x4, void *cookie, void *handle, + u_register_t flags); + +#endif /* __ASSEMBLER__ */ + +#endif /* __PNC_H__ */ diff --git a/include/bl32/sp_min/platform_sp_min.h b/include/bl32/sp_min/platform_sp_min.h index 971f66185..a7dffff9e 100644 --- a/include/bl32/sp_min/platform_sp_min.h +++ b/include/bl32/sp_min/platform_sp_min.h @@ -9,6 +9,8 @@ #include <stdint.h> +#include <common/bl_common.h> + /******************************************************************************* * Mandatory SP_MIN functions ******************************************************************************/ diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 3a06cfbf9..539280e12 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -178,6 +178,7 @@ void dyn_disable_auth(void); extern const char build_message[]; extern const char version_string[]; +const char *get_version(void); void print_entry_point_info(const entry_point_info_t *ep_info); uintptr_t page_align(uintptr_t value, unsigned dir); diff --git a/include/common/debug.h b/include/common/debug.h index a7ca0d788..af47999c3 100644 --- a/include/common/debug.h +++ b/include/common/debug.h @@ -91,9 +91,10 @@ # define VERBOSE(...) no_tf_log(LOG_MARKER_VERBOSE __VA_ARGS__) #endif +const char *get_el_str(unsigned int el); + #if ENABLE_BACKTRACE void backtrace(const char *cookie); -const char *get_el_str(unsigned int el); #else #define backtrace(x) #endif diff --git a/include/common/fdt_fixup.h b/include/common/fdt_fixup.h index c35e9be8d..9531bdb77 100644 --- a/include/common/fdt_fixup.h +++ b/include/common/fdt_fixup.h @@ -32,5 +32,7 @@ int fdt_add_cpus_node(void *dtb, unsigned int afflv0, int fdt_add_cpu_idle_states(void *dtb, const struct psci_cpu_idle_state *state); int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, uintptr_t gicr_base, unsigned int gicr_frame_size); +int fdt_set_mac_address(void *dtb, unsigned int ethernet_idx, + const uint8_t *mac_addr); #endif /* FDT_FIXUP_H */ diff --git a/include/common/tbbr/cot_def.h b/include/common/tbbr/cot_def.h index 800ad07eb..60dfb8a3c 100644 --- a/include/common/tbbr/cot_def.h +++ b/include/common/tbbr/cot_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,8 @@ /* TBBR CoT definitions */ #if defined(SPD_spmd) #define COT_MAX_VERIFIED_PARAMS 8 +#elif defined(ARM_COT_cca) +#define COT_MAX_VERIFIED_PARAMS 8 #else #define COT_MAX_VERIFIED_PARAMS 4 #endif @@ -39,7 +41,7 @@ #error "Invalid value for TF_MBEDTLS_KEY_SIZE" #endif #else /* Only using ECDSA keys. */ -#define PK_DER_LEN 91 +#define PK_DER_LEN 92 #endif #if TF_MBEDTLS_HASH_ALG_ID == TF_MBEDTLS_SHA256 diff --git a/include/drivers/arm/ethosn.h b/include/drivers/arm/ethosn.h index 931073338..dbaf16cd7 100644 --- a/include/drivers/arm/ethosn.h +++ b/include/drivers/arm/ethosn.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -38,7 +38,7 @@ #define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE) /* Service version */ -#define ETHOSN_VERSION_MAJOR U(1) +#define ETHOSN_VERSION_MAJOR U(2) #define ETHOSN_VERSION_MINOR U(0) /* Return codes for function calls */ @@ -48,10 +48,11 @@ /* -3 Reserved for INVALID_PARAMETER */ #define ETHOSN_FAILURE -4 #define ETHOSN_UNKNOWN_CORE_ADDRESS -5 +#define ETHOSN_UNKNOWN_ALLOCATOR_IDX -6 uintptr_t ethosn_smc_handler(uint32_t smc_fid, u_register_t core_addr, - u_register_t x2, + u_register_t asset_alloc_idx, u_register_t x3, u_register_t x4, void *cookie, diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h index b960194db..cfc168d5b 100644 --- a/include/drivers/arm/gicv2.h +++ b/include/drivers/arm/gicv2.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -50,13 +51,15 @@ #define SGIR_TGTLSTFLT_MASK U(0x3) #define SGIR_TGTLST_SHIFT 16 #define SGIR_TGTLST_MASK U(0xff) +#define SGIR_NSATT (U(0x1) << 16) #define SGIR_INTID_MASK ULL(0xf) #define SGIR_TGT_SPECIFIC U(0) -#define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \ +#define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, nsatt, intid) \ ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \ (((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \ + ((nsatt) ? SGIR_NSATT : U(0)) | \ ((intid) & SGIR_INTID_MASK)) /******************************************************************************* @@ -127,6 +130,7 @@ #ifndef __ASSEMBLER__ #include <cdefs.h> +#include <stdbool.h> #include <stdint.h> #include <common/interrupt_props.h> @@ -185,7 +189,7 @@ void gicv2_enable_interrupt(unsigned int id); void gicv2_disable_interrupt(unsigned int id); void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority); void gicv2_set_interrupt_type(unsigned int id, unsigned int type); -void gicv2_raise_sgi(int sgi_num, int proc_num); +void gicv2_raise_sgi(int sgi_num, bool ns, int proc_num); void gicv2_set_spi_routing(unsigned int id, int proc_num); void gicv2_set_interrupt_pending(unsigned int id); void gicv2_clear_interrupt_pending(unsigned int id); diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 5efefb693..5bb22fdf1 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -76,6 +76,8 @@ #endif /* GIC_EXT_INTID */ +#define GIC_REV(r, p) ((r << 4) | p) + /******************************************************************************* * GICv3 and 3.1 specific Distributor interface register offsets and constants ******************************************************************************/ @@ -192,6 +194,15 @@ #define GICR_CTLR_UWP_SHIFT 31 #define GICR_CTLR_UWP_MASK U(0x1) #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT) +#define GICR_CTLR_DPG1S_SHIFT 26 +#define GICR_CTLR_DPG1S_MASK U(0x1) +#define GICR_CTLR_DPG1S_BIT BIT_32(GICR_CTLR_DPG1S_SHIFT) +#define GICR_CTLR_DPG1NS_SHIFT 25 +#define GICR_CTLR_DPG1NS_MASK U(0x1) +#define GICR_CTLR_DPG1NS_BIT BIT_32(GICR_CTLR_DPG1NS_SHIFT) +#define GICR_CTLR_DPG0_SHIFT 24 +#define GICR_CTLR_DPG0_MASK U(0x1) +#define GICR_CTLR_DPG0_BIT BIT_32(GICR_CTLR_DPG0_SHIFT) #define GICR_CTLR_RWP_SHIFT 3 #define GICR_CTLR_RWP_MASK U(0x1) #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT) @@ -224,12 +235,40 @@ #define TYPER_PPI_NUM_MASK U(0x1f) /* GICR_IIDR bit definitions */ -#define IIDR_PRODUCT_ID_MASK U(0xff000000) -#define IIDR_VARIANT_MASK U(0x000f0000) -#define IIDR_REVISION_MASK U(0x0000f000) -#define IIDR_IMPLEMENTER_MASK U(0x00000fff) -#define IIDR_MODEL_MASK (IIDR_PRODUCT_ID_MASK | \ - IIDR_IMPLEMENTER_MASK) +#define IIDR_PRODUCT_ID_MASK U(0xff) +#define IIDR_VARIANT_MASK U(0xf) +#define IIDR_REV_MASK U(0xf) +#define IIDR_IMPLEMENTER_MASK U(0xfff) +#define IIDR_PRODUCT_ID_SHIFT 24 +#define IIDR_VARIANT_SHIFT 16 +#define IIDR_REV_SHIFT 12 +#define IIDR_IMPLEMENTER_SHIFT 0 +#define IIDR_PRODUCT_ID_BIT BIT_32(IIDR_PRODUCT_ID_SHIFT) +#define IIDR_VARIANT_BIT BIT_32(IIDR_VARIANT_SHIFT) +#define IIDR_REV_BIT BIT_32(IIDR_REVISION_SHIFT) +#define IIDR_IMPLEMENTER_BIT BIT_32(IIDR_IMPLEMENTER_SHIFT) + +#define IIDR_MODEL_MASK (IIDR_PRODUCT_ID_MASK << IIDR_PRODUCT_ID_SHIFT | \ + IIDR_IMPLEMENTER_MASK << IIDR_IMPLEMENTER_SHIFT) + +#define GIC_PRODUCT_ID_GIC600 U(0x2) +#define GIC_PRODUCT_ID_GIC600AE U(0x3) +#define GIC_PRODUCT_ID_GIC700 U(0x4) + +/* + * Note that below revisions and variants definations are as per GIC600/GIC600AE + * specification. + */ +#define GIC_REV_P0 U(0x1) +#define GIC_REV_P1 U(0x3) +#define GIC_REV_P2 U(0x4) +#define GIC_REV_P3 U(0x5) +#define GIC_REV_P4 U(0x6) +#define GIC_REV_P6 U(0x7) + +#define GIC_VARIANT_R0 U(0x0) +#define GIC_VARIANT_R1 U(0x1) +#define GIC_VARIANT_R2 U(0x2) /******************************************************************************* * GICv3 and 3.1 CPU interface registers & constants @@ -276,7 +315,7 @@ #define SGIR_IRM_SHIFT 40 #define SGIR_IRM_MASK ULL(0x1) #define SGIR_AFF3_SHIFT 48 -#define SGIR_AFF_MASK ULL(0xf) +#define SGIR_AFF_MASK ULL(0xff) #define SGIR_IRM_TO_AFF U(0) @@ -315,6 +354,12 @@ #include <drivers/arm/gic_common.h> #include <lib/utils_def.h> +typedef enum { + GICV3_G1S, + GICV3_G1NS, + GICV3_G0 +} gicv3_irq_group_t; + static inline uintptr_t gicv3_redist_size(uint64_t typer_val) { #if GIC_ENABLE_V4_EXTN @@ -536,12 +581,25 @@ void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, unsigned int priority); void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, unsigned int type); -void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target); +void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group, + u_register_t target); void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr); void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num); void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num); unsigned int gicv3_set_pmr(unsigned int mask); +void gicv3_get_component_prodid_rev(const uintptr_t gicd_base, + unsigned int *gic_prod_id, + uint8_t *gic_rev); +void gicv3_check_erratas_applies(const uintptr_t gicd_base); +#if GIC600_ERRATA_WA_2384374 +void gicv3_apply_errata_wa_2384374(const uintptr_t gicr_base); +#else +static inline void gicv3_apply_errata_wa_2384374(const uintptr_t gicr_base) +{ +} +#endif /* GIC600_ERRATA_WA_2384374 */ + #endif /* __ASSEMBLER__ */ #endif /* GICV3_H */ diff --git a/include/drivers/arm/mhu.h b/include/drivers/arm/mhu.h index 7745bd9d8..31c6a8119 100644 --- a/include/drivers/arm/mhu.h +++ b/include/drivers/arm/mhu.h @@ -76,4 +76,11 @@ enum mhu_error_t mhu_send_data(const uint8_t *send_buffer, size_t size); */ enum mhu_error_t mhu_receive_data(uint8_t *receive_buffer, size_t *size); +/** + * Gets the maximum amount of bytes that can be transmitted in a single send by MHU. + * + * Returns The amount of bytes that can be sent or received in a single message. + */ +size_t mhu_get_max_message_size(void); + #endif /* MHU_H */ diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h index 73b2b998c..3a23df4b7 100644 --- a/include/drivers/auth/crypto_mod.h +++ b/include/drivers/auth/crypto_mod.h @@ -7,6 +7,10 @@ #ifndef CRYPTO_MOD_H #define CRYPTO_MOD_H +#define CRYPTO_AUTH_VERIFY_ONLY 1 +#define CRYPTO_HASH_CALC_ONLY 2 +#define CRYPTO_AUTH_VERIFY_AND_HASH_CALC 3 + /* Return values */ enum crypto_ret_value { CRYPTO_SUCCESS = 0, @@ -48,6 +52,8 @@ typedef struct crypto_lib_desc_s { /* Verify a digital signature. Return one of the * 'enum crypto_ret_value' options */ +#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC int (*verify_signature)(void *data_ptr, unsigned int data_len, void *sig_ptr, unsigned int sig_len, void *sig_alg, unsigned int sig_alg_len, @@ -56,13 +62,17 @@ typedef struct crypto_lib_desc_s { /* Verify a hash. Return one of the 'enum crypto_ret_value' options */ int (*verify_hash)(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); +#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ -#if MEASURED_BOOT +#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC /* Calculate a hash. Return hash value */ int (*calc_hash)(enum crypto_md_algo md_alg, void *data_ptr, unsigned int data_len, unsigned char output[CRYPTO_MD_MAX_SIZE]); -#endif /* MEASURED_BOOT */ +#endif /* CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ /* * Authenticated decryption. Return one of the @@ -84,25 +94,32 @@ static inline void crypto_mod_init(void) } #endif /* CRYPTO_SUPPORT */ +#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len, void *sig_ptr, unsigned int sig_len, void *sig_alg_ptr, unsigned int sig_alg_len, void *pk_ptr, unsigned int pk_len); int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); +#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ + int crypto_mod_auth_decrypt(enum crypto_dec_algo dec_algo, void *data_ptr, size_t len, const void *key, unsigned int key_len, unsigned int key_flags, const void *iv, unsigned int iv_len, const void *tag, unsigned int tag_len); -#if MEASURED_BOOT +#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC int crypto_mod_calc_hash(enum crypto_md_algo alg, void *data_ptr, unsigned int data_len, unsigned char output[CRYPTO_MD_MAX_SIZE]); -#endif /* MEASURED_BOOT */ +#endif /* CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ + CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ -#if MEASURED_BOOT && TRUSTED_BOARD_BOOT +#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC /* Macro to register a cryptographic library */ #define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \ _calc_hash, _auth_decrypt) \ @@ -114,7 +131,7 @@ int crypto_mod_calc_hash(enum crypto_md_algo alg, void *data_ptr, .calc_hash = _calc_hash, \ .auth_decrypt = _auth_decrypt \ } -#elif TRUSTED_BOARD_BOOT +#elif CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY #define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \ _auth_decrypt) \ const crypto_lib_desc_t crypto_lib_desc = { \ @@ -124,14 +141,14 @@ int crypto_mod_calc_hash(enum crypto_md_algo alg, void *data_ptr, .verify_hash = _verify_hash, \ .auth_decrypt = _auth_decrypt \ } -#elif MEASURED_BOOT +#elif CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY #define REGISTER_CRYPTO_LIB(_name, _init, _calc_hash) \ const crypto_lib_desc_t crypto_lib_desc = { \ .name = _name, \ .init = _init, \ .calc_hash = _calc_hash, \ } -#endif /* MEASURED_BOOT && TRUSTED_BOARD_BOOT */ +#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */ extern const crypto_lib_desc_t crypto_lib_desc; diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h index 8ad6d7a42..01e261a96 100644 --- a/include/drivers/auth/mbedtls/mbedtls_config.h +++ b/include/drivers/auth/mbedtls/mbedtls_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, Arm Limited. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -80,8 +80,7 @@ #define MBEDTLS_SHA512_C #else /* TBB uses SHA-256, what about measured boot? */ -#if defined(TF_MBEDTLS_TPM_HASH_ALG_ID) && \ - (TF_MBEDTLS_TPM_HASH_ALG_ID != TF_MBEDTLS_SHA256) +#if defined(TF_MBEDTLS_MBOOT_USE_SHA512) #define MBEDTLS_SHA512_C #endif #endif @@ -141,4 +140,13 @@ #endif #endif +/* + * Warn if errors from certain functions are ignored. + * + * The warnings are always enabled (where supported) for critical functions + * where ignoring the return value is almost always a bug. This macro extends + * the warnings to more functions. + */ +#define MBEDTLS_CHECK_RETURN_WARNING + #endif /* MBEDTLS_CONFIG_H */ diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h index f2d641c2d..8f30ed050 100644 --- a/include/drivers/io/io_storage.h +++ b/include/drivers/io/io_storage.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,7 +24,6 @@ typedef enum { IO_TYPE_BLOCK, IO_TYPE_MTD, IO_TYPE_MMC, - IO_TYPE_STM32IMAGE, IO_TYPE_ENCRYPTED, IO_TYPE_MAX } io_type_t; diff --git a/include/drivers/measured_boot/event_log/event_log.h b/include/drivers/measured_boot/event_log/event_log.h index 0a19f8af4..eb0e2b129 100644 --- a/include/drivers/measured_boot/event_log/event_log.h +++ b/include/drivers/measured_boot/event_log/event_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,7 @@ #include <common/debug.h> #include <common/tbbr/tbbr_img_def.h> +#include <drivers/auth/crypto_mod.h> #include <drivers/measured_boot/event_log/tcg.h> /* @@ -78,6 +79,14 @@ #define EVLOG_TB_FW_CONFIG_STRING "TB_FW_CONFIG" #define EVLOG_TOS_FW_CONFIG_STRING "TOS_FW_CONFIG" #define EVLOG_RMM_STRING "RMM" +#define EVLOG_SP1_STRING "SP1" +#define EVLOG_SP2_STRING "SP2" +#define EVLOG_SP3_STRING "SP3" +#define EVLOG_SP4_STRING "SP4" +#define EVLOG_SP5_STRING "SP5" +#define EVLOG_SP6_STRING "SP6" +#define EVLOG_SP7_STRING "SP7" +#define EVLOG_SP8_STRING "SP8" typedef struct { unsigned int id; @@ -101,10 +110,16 @@ typedef struct { sizeof(event2_data_t)) /* Functions' declarations */ +void event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish); void event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish); +void event_log_write_specid_event(void); void event_log_write_header(void); void dump_event_log(uint8_t *log_addr, size_t log_size); const event_log_metadata_t *plat_event_log_get_metadata(void); +int event_log_measure(uintptr_t data_base, uint32_t data_size, + unsigned char hash_data[CRYPTO_MD_MAX_SIZE]); +void event_log_record(const uint8_t *hash, uint32_t event_type, + const event_log_metadata_t *metadata_ptr); int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size, uint32_t data_id); size_t event_log_get_cur_size(uint8_t *event_log_start); diff --git a/include/drivers/measured_boot/event_log/tcg.h b/include/drivers/measured_boot/event_log/tcg.h index ab27a0844..4ac2c2ff3 100644 --- a/include/drivers/measured_boot/event_log/tcg.h +++ b/include/drivers/measured_boot/event_log/tcg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -98,7 +98,12 @@ enum { /* 8-15: Defined for use by the Static OS */ PCR_8, /* Debug */ - PCR_16 = 16 + PCR_16 = 16, + + /* D-CRTM-measurements by DRTM implementation */ + PCR_17 = 17, + /* DCE measurements by DRTM implementation */ + PCR_18 = 18 }; #pragma pack(push, 1) diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h index 834a80f4a..e94693dd7 100644 --- a/include/drivers/mmc.h +++ b/include/drivers/mmc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,10 +62,12 @@ #define CMD_EXTCSD_HS_TIMING 185 #define CMD_EXTCSD_PART_SWITCH_TIME 199 #define CMD_EXTCSD_SEC_CNT 212 +#define CMD_EXTCSD_BOOT_SIZE_MULT 226 #define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0) #define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) #define PART_CFG_BOOT_PARTITION1_ACCESS (U(1) << 0) +#define PART_CFG_BOOT_PARTITION_NO_ACCESS U(0) #define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3) #define PART_CFG_BOOT_PART_EN_SHIFT 3 #define PART_CFG_CURRENT_BOOT_PARTITION(x) (((x) & PART_CFG_BOOT_PART_EN_MASK) >> \ @@ -110,6 +112,7 @@ #define MMC_STATE_SLP 10 #define MMC_FLAG_CMD23 (U(1) << 0) +#define MMC_FLAG_SD_CMD6 (U(1) << 1) #define CMD8_CHECK_PATTERN U(0xAA) #define VHS_2_7_3_6_V BIT(8) @@ -117,6 +120,10 @@ #define SD_SCR_BUS_WIDTH_1 BIT(8) #define SD_SCR_BUS_WIDTH_4 BIT(10) +#define SD_SWITCH_FUNC_CHECK 0U +#define SD_SWITCH_FUNC_SWITCH BIT(31) +#define SD_SWITCH_ALL_GROUPS_MASK GENMASK(23, 0) + struct mmc_cmd { unsigned int cmd_idx; unsigned int cmd_arg; @@ -216,6 +223,27 @@ struct mmc_csd_sd_v2 { unsigned int csd_structure: 2; }; +struct sd_switch_status { + unsigned short max_current; + unsigned short support_g6; + unsigned short support_g5; + unsigned short support_g4; + unsigned short support_g3; + unsigned short support_g2; + unsigned short support_g1; + unsigned char sel_g6_g5; + unsigned char sel_g4_g3; + unsigned char sel_g2_g1; + unsigned char data_struct_ver; + unsigned short busy_g6; + unsigned short busy_g5; + unsigned short busy_g4; + unsigned short busy_g3; + unsigned short busy_g2; + unsigned short busy_g1; + unsigned short reserved[17]; +}; + enum mmc_device_type { MMC_IS_EMMC, MMC_IS_SD, @@ -233,9 +261,9 @@ struct mmc_device_info { size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size); size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size); size_t mmc_erase_blocks(int lba, size_t size); -size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size); -size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size); -size_t mmc_rpmb_erase_blocks(int lba, size_t size); +int mmc_part_switch_current_boot(void); +int mmc_part_switch_user(void); +size_t mmc_boot_part_size(void); size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size); int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, unsigned int width, unsigned int flags, diff --git a/include/drivers/nand.h b/include/drivers/nand.h index 1b78ad41b..5e5607c64 100644 --- a/include/drivers/nand.h +++ b/include/drivers/nand.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,6 +33,8 @@ struct nand_device { uintptr_t buffer); }; +void plat_get_scratch_buffer(void **buffer_addr, size_t *buf_size); + /* * Read bytes from NAND device * diff --git a/include/drivers/nxp/gic/gicv3/plat_gic.h b/include/drivers/nxp/gic/gicv3/plat_gic.h index 0c0d0fc89..794b06b61 100644 --- a/include/drivers/nxp/gic/gicv3/plat_gic.h +++ b/include/drivers/nxp/gic/gicv3/plat_gic.h @@ -61,7 +61,6 @@ #define GICR_ICENABLER0_SGI15 0x00008000 #define GICR_CTLR_RWP 0x8 -#define GICR_CTLR_DPG0_MASK 0x2000000 #define GICR_IGROUPR0_SGI15 0x00008000 #define GICR_IGRPMODR0_SGI15 0x00008000 #define GICR_ISENABLER0_SGI15 0x00008000 diff --git a/include/drivers/partition/partition.h b/include/drivers/partition/partition.h index 11e5acf72..6cb59c391 100644 --- a/include/drivers/partition/partition.h +++ b/include/drivers/partition/partition.h @@ -36,6 +36,7 @@ typedef struct partition_entry { uint64_t length; char name[EFI_NAMELEN]; struct efi_guid part_guid; + struct efi_guid type_guid; } partition_entry_t; typedef struct partition_entry_list { @@ -45,6 +46,7 @@ typedef struct partition_entry_list { int load_partition_table(unsigned int image_id); const partition_entry_t *get_partition_entry(const char *name); +const partition_entry_t *get_partition_entry_by_type(const uuid_t *type_guid); const partition_entry_t *get_partition_entry_by_uuid(const uuid_t *part_uuid); const partition_entry_list_t *get_partition_entry_list(void); void partition_init(unsigned int image_id); diff --git a/include/drivers/st/io_stm32image.h b/include/drivers/st/io_stm32image.h deleted file mode 100644 index f9fa3630c..000000000 --- a/include/drivers/st/io_stm32image.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef IO_STM32IMAGE_H -#define IO_STM32IMAGE_H - -#include <drivers/io/io_driver.h> -#include <drivers/partition/partition.h> - -#define MAX_LBA_SIZE 512 -#define MAX_PART_NAME_SIZE (EFI_NAMELEN + 1) -#define STM32_PART_NUM (PLAT_PARTITION_MAX_ENTRIES - STM32_TF_A_COPIES) - -struct stm32image_part_info { - char name[MAX_PART_NAME_SIZE]; - uint32_t binary_type; - uintptr_t part_offset; - uint32_t bkp_offset; -}; - -struct stm32image_device_info { - struct stm32image_part_info part_info[STM32_PART_NUM]; - unsigned long long device_size; - uint32_t lba_size; -}; - -int register_io_dev_stm32image(const io_dev_connector_t **dev_con); - -#endif /* IO_STM32IMAGE_H */ diff --git a/include/drivers/st/stm32_hash.h b/include/drivers/st/stm32_hash.h index df04730d6..bebb4afdf 100644 --- a/include/drivers/st/stm32_hash.h +++ b/include/drivers/st/stm32_hash.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,19 @@ #ifndef STM32_HASH_H #define STM32_HASH_H +#include <stdint.h> + enum stm32_hash_algo_mode { +#if STM32_HASH_VER == 2 HASH_MD5SUM, +#endif HASH_SHA1, HASH_SHA224, - HASH_SHA256 + HASH_SHA256, +#if STM32_HASH_VER == 4 + HASH_SHA384, + HASH_SHA512, +#endif }; int stm32_hash_update(const uint8_t *buffer, size_t length); diff --git a/include/drivers/st/stm32_pka.h b/include/drivers/st/stm32_pka.h new file mode 100644 index 000000000..ad4690ae5 --- /dev/null +++ b/include/drivers/st/stm32_pka.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_PKA_H +#define STM32_PKA_H + +#include <stdint.h> + +#if !PKA_USE_NIST_P256 && !PKA_USE_BRAINPOOL_P256R1 && !PKA_USE_BRAINPOOL_P256T1 && \ + !PKA_USE_NIST_P521 +#error "At least one ECDSA curve needs to be selected" +#endif + +enum stm32_pka_ecdsa_curve_id { +#if PKA_USE_NIST_P256 + PKA_NIST_P256, +#endif +#if PKA_USE_BRAINPOOL_P256R1 + PKA_BRAINPOOL_P256R1, +#endif +#if PKA_USE_BRAINPOOL_P256T1 + PKA_BRAINPOOL_P256T1, +#endif +#if PKA_USE_NIST_P521 + PKA_NIST_P521, +#endif +}; + +struct stm32_pka_platdata { + uintptr_t base; + unsigned long clock_id; + unsigned int reset_id; +}; + +int stm32_pka_init(void); +int stm32_pka_ecdsa_verif(void *hash, unsigned int hash_size, + void *sig_r_ptr, unsigned int sig_r_size, + void *sig_s_ptr, unsigned int sig_s_size, + void *pk_x_ptr, unsigned int pk_x_size, + void *pk_y_ptr, unsigned int pk_y_size, + enum stm32_pka_ecdsa_curve_id cid); + +#endif /* STM32_PKA_H */ diff --git a/include/drivers/st/stm32_rng.h b/include/drivers/st/stm32_rng.h new file mode 100644 index 000000000..6ac064d11 --- /dev/null +++ b/include/drivers/st/stm32_rng.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_RNG_H +#define STM32_RNG_H + +#include <stdint.h> + +int stm32_rng_read(uint8_t *out, uint32_t size); +int stm32_rng_init(void); + +#endif /* STM32_RNG_H */ diff --git a/include/drivers/st/stm32_saes.h b/include/drivers/st/stm32_saes.h new file mode 100644 index 000000000..0a50438b9 --- /dev/null +++ b/include/drivers/st/stm32_saes.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_SAES_H +#define STM32_SAES_H + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#define DT_SAES_COMPAT "st,stm32-saes" + +struct stm32_saes_platdata { + uintptr_t base; + unsigned long clock_id; + unsigned int reset_id; +}; + +enum stm32_saes_chaining_mode { + STM32_SAES_MODE_ECB, + STM32_SAES_MODE_CBC, + STM32_SAES_MODE_CTR, + STM32_SAES_MODE_GCM, + STM32_SAES_MODE_CCM, /* Not use in TF-A */ +}; + +enum stm32_saes_key_selection { + STM32_SAES_KEY_SOFT, + STM32_SAES_KEY_DHU, /* Derived HW unique key */ + STM32_SAES_KEY_BH, /* Boot HW key */ + STM32_SAES_KEY_BHU_XOR_BH, /* XOR of DHUK and BHK */ + STM32_SAES_KEY_WRAPPED +}; + +struct stm32_saes_context { + uintptr_t base; + uint32_t cr; + uint32_t assoc_len; + uint32_t load_len; + uint32_t key[8]; /* In HW byte order */ + uint32_t iv[4]; /* In HW byte order */ +}; + +int stm32_saes_driver_init(void); + +int stm32_saes_init(struct stm32_saes_context *ctx, bool is_decrypt, + enum stm32_saes_chaining_mode ch_mode, enum stm32_saes_key_selection key_select, + const void *key, size_t key_len, const void *iv, size_t iv_len); +int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data_in, uint8_t *data_out, size_t data_len); +int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data, size_t data_len); +int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data_in, uint8_t *data_out, size_t data_len); +int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag, size_t tag_len); +#endif diff --git a/include/drivers/st/stm32_uart.h b/include/drivers/st/stm32_uart.h index 212968f57..866e15890 100644 --- a/include/drivers/st/stm32_uart.h +++ b/include/drivers/st/stm32_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -34,10 +34,6 @@ #define STM32_UART_HWCONTROL_CTS USART_CR3_CTSE #define STM32_UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) -/* UART over sampling */ -#define STM32_UART_OVERSAMPLING_16 0x00000000U -#define STM32_UART_OVERSAMPLING_8 USART_CR1_OVER8 - /* UART prescaler */ #define STM32_UART_PRESCALER_DIV1 0x00000000U #define STM32_UART_PRESCALER_DIV2 0x00000001U @@ -112,13 +108,6 @@ struct stm32_uart_init_s { * value of @ref STM32_UARTHWCONTROL_*. */ - uint32_t over_sampling; /* - * Specifies whether the over sampling - * 8 is enabled or disabled. - * This parameter can be a value of - * @ref STM32_UART_OVERSAMPLING_*. - */ - uint32_t one_bit_sampling; /* * Specifies whether a single sample * or three samples' majority vote is diff --git a/include/drivers/ufs.h b/include/drivers/ufs.h index 4a5e46495..1cd1beeee 100644 --- a/include/drivers/ufs.h +++ b/include/drivers/ufs.h @@ -259,6 +259,12 @@ /* maximum number of retries for a general UIC command */ #define UFS_UIC_COMMAND_RETRIES 3 +/* maximum number of retries for a transfer command */ +#define UFS_CMD_RETRIES 3 + +/* maximum number of retries for reading UFS capacity */ +#define UFS_READ_CAPACITY_RETRIES 10 + /* maximum number of link-startup retries */ #define DME_LINKSTARTUP_RETRIES 10 diff --git a/include/export/common/bl_common_exp.h b/include/export/common/bl_common_exp.h index 8f0901765..2cc7c54b2 100644 --- a/include/export/common/bl_common_exp.h +++ b/include/export/common/bl_common_exp.h @@ -39,8 +39,8 @@ *****************************************************************************/ typedef struct image_info { param_header_t h; - uintptr_t image_base; /* physical address of base of image */ - uint32_t image_size; /* bytes read from image file */ + uintptr_t image_base; /* physical address of base of image */ + uint32_t image_size; /* bytes read from image file */ uint32_t image_max_size; } image_info_t; diff --git a/include/export/common/tbbr/tbbr_img_def_exp.h b/include/export/common/tbbr/tbbr_img_def_exp.h index 98544c0ae..98a00999d 100644 --- a/include/export/common/tbbr/tbbr_img_def_exp.h +++ b/include/export/common/tbbr/tbbr_img_def_exp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -104,7 +104,16 @@ /* Realm Monitor Manager (RMM) */ #define RMM_IMAGE_ID U(34) +/* CCA Content Certificate ID */ +#define CCA_CONTENT_CERT_ID U(35) + +/* Core SWD Key Certificate ID */ +#define CORE_SWD_KEY_CERT_ID U(36) + +/* Platform Key Certificate ID */ +#define PLAT_KEY_CERT_ID U(37) + /* Max Images */ -#define MAX_IMAGE_IDS U(35) +#define MAX_IMAGE_IDS U(38) #endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H */ diff --git a/include/lib/cpus/aarch64/a64fx.h b/include/lib/cpus/aarch64/a64fx.h new file mode 100644 index 000000000..b7342b0fc --- /dev/null +++ b/include/lib/cpus/aarch64/a64fx.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, Fujitsu Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef A64FX_H +#define A64FX_H + +#include <lib/utils_def.h> + +/* A64FX midr for revision 0 */ +#define A64FX_MIDR U(0x461f0010) + +#endif /* A64FX_H */ diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h index 2b8db1420..6af85a863 100644 --- a/include/lib/cpus/aarch64/cortex_a510.h +++ b/include/lib/cpus/aarch64/cortex_a510.h @@ -17,6 +17,8 @@ #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) #define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) #define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) +#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38) /******************************************************************************* * CPU Power Control register specific definitions @@ -33,5 +35,7 @@ * Auxiliary control register specific definitions ******************************************************************************/ #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) +#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) -#endif /* CORTEX_A510_H */ +#endif /* CORTEX_A510_H */
\ No newline at end of file diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h index 09614ee5c..432e17aba 100644 --- a/include/lib/cpus/aarch64/cortex_a710.h +++ b/include/lib/cpus/aarch64/cortex_a710.h @@ -35,12 +35,15 @@ * CPU Auxiliary Control register 2 specific definitions. ******************************************************************************/ #define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) +#define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) /******************************************************************************* * CPU Auxiliary Control register 5 specific definitions. ******************************************************************************/ #define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0 #define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) +#define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) #define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) /******************************************************************************* @@ -51,4 +54,12 @@ #define CPUECTLR2_EL1_PF_MODE_LSB U(11) #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +/******************************************************************************* + * CPU Selected Instruction Private register specific definitions. + ******************************************************************************/ +#define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3 + #endif /* CORTEX_A710_H */ diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h index 4a871689c..a9b45463d 100644 --- a/include/lib/cpus/aarch64/cortex_a77.h +++ b/include/lib/cpus/aarch64/cortex_a77.h @@ -20,6 +20,7 @@ ******************************************************************************/ #define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) +#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) /******************************************************************************* * CPU Power Control register specific definitions. @@ -32,6 +33,7 @@ ******************************************************************************/ #define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A77_ACTLR2_EL1_BIT_0 ULL(1) #define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 #define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h index b1945ed01..35e543c17 100644 --- a/include/lib/cpus/aarch64/cortex_a78c.h +++ b/include/lib/cpus/aarch64/cortex_a78c.h @@ -14,9 +14,18 @@ #define CORTEX_A78C_BHB_LOOP_COUNT U(32) /******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + * ****************************************************************************/ +#define CORTEX_A78C_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A78C_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define CORTEX_A78C_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) + +/******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6) +#define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7) /******************************************************************************* * CPU Power Control register specific definitions @@ -24,4 +33,12 @@ #define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) +/******************************************************************************* + * CPU Implementation Specific Selected Instruction registers + ******************************************************************************/ +#define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3 + #endif /* CORTEX_A78C_H */ diff --git a/include/lib/cpus/aarch64/cortex_hunter_elp_arm.h b/include/lib/cpus/aarch64/cortex_hunter_elp_arm.h new file mode 100644 index 000000000..f9bb0f36a --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_hunter_elp_arm.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_HUNTER_ELP_ARM_H +#define CORTEX_HUNTER_ELP_ARM_H + +#define CORTEX_HUNTER_ELP_ARM_MIDR U(0x410FD821) + +/* Cortex Hunter ELP loop count for CVE-2022-23960 mitigation */ +#define CORTEX_HUNTER_ELP_ARM_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_HUNTER_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_HUNTER_ELP_ARM_H */ diff --git a/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h b/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h deleted file mode 100644 index 9ed5ee3c7..000000000 --- a/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_MAKALU_ELP_ARM_H -#define CORTEX_MAKALU_ELP_ARM_H - -#define CORTEX_MAKALU_ELP_ARM_MIDR U(0x410FD4E0) - -/* Cortex Makalu ELP loop count for CVE-2022-23960 mitigation */ -#define CORTEX_MAKALU_ELP_ARM_BHB_LOOP_COUNT U(132) - -/******************************************************************************* - * CPU Extended Control register specific definitions - ******************************************************************************/ -#define CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4 - -/******************************************************************************* - * CPU Power Control register specific definitions - ******************************************************************************/ -#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) - -#endif /* CORTEX_MAKALU_ELP_ARM_H */ diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h index 92140b1e2..863b8c8d3 100644 --- a/include/lib/cpus/aarch64/cortex_x2.h +++ b/include/lib/cpus/aarch64/cortex_x2.h @@ -40,6 +40,12 @@ #define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) /******************************************************************************* + * CPU Auxiliary Control Register 2 definitions + ******************************************************************************/ +#define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) + +/******************************************************************************* * CPU Auxiliary Control Register 5 definitions ******************************************************************************/ #define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h new file mode 100644 index 000000000..076a87b35 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_x3.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_X3_H +#define CORTEX_X3_H + +#define CORTEX_X3_MIDR U(0x410FD4E0) + +/* Cortex-X3 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X3_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) + +#endif /* CORTEX_X3_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index 0452b3947..cb1be5b26 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -37,7 +37,10 @@ * CPU Auxiliary Control register 2 specific definitions. ******************************************************************************/ #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) /******************************************************************************* * CPU Auxiliary Control register 5 specific definitions. diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h index a904c0420..9c7e967cb 100644 --- a/include/lib/cpus/aarch64/neoverse_v1.h +++ b/include/lib/cpus/aarch64/neoverse_v1.h @@ -16,6 +16,10 @@ * CPU Extended Control register specific definitions. ******************************************************************************/ #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0 +#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2 +#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3 +#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) #define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) @@ -32,7 +36,9 @@ * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1) #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) #define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28) +#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40) #endif /* NEOVERSE_V1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_demeter.h b/include/lib/cpus/aarch64/neoverse_v2.h index f1afae7b0..efb960e5c 100644 --- a/include/lib/cpus/aarch64/neoverse_demeter.h +++ b/include/lib/cpus/aarch64/neoverse_v2.h @@ -4,23 +4,23 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef NEOVERSE_DEMETER_H -#define NEOVERSE_DEMETER_H +#ifndef NEOVERSE_V2_H +#define NEOVERSE_V2_H -#define NEOVERSE_DEMETER_MIDR U(0x410FD4F0) +#define NEOVERSE_V2_MIDR U(0x410FD4F0) -/* Neoverse Demeter loop count for CVE-2022-23960 mitigation */ -#define NEOVERSE_DEMETER_BHB_LOOP_COUNT U(132) +/* Neoverse V2 loop count for CVE-2022-23960 mitigation */ +#define NEOVERSE_V2_BHB_LOOP_COUNT U(132) /******************************************************************************* * CPU Extended Control register specific definitions ******************************************************************************/ -#define NEOVERSE_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) -#endif /* NEOVERSE_DEMETER_H */ +#endif /* NEOVERSE_V2_H */ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index 3a09383a7..6c13166e3 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -509,9 +509,53 @@ void el1_sysregs_context_save(el1_sysregs_t *regs); void el1_sysregs_context_restore(el1_sysregs_t *regs); #if CTX_INCLUDE_EL2_REGS -void el2_sysregs_context_save(el2_sysregs_t *regs); -void el2_sysregs_context_restore(el2_sysregs_t *regs); -#endif +void el2_sysregs_context_save_common(el2_sysregs_t *regs); +void el2_sysregs_context_restore_common(el2_sysregs_t *regs); +#if ENABLE_SPE_FOR_LOWER_ELS +void el2_sysregs_context_save_spe(el2_sysregs_t *regs); +void el2_sysregs_context_restore_spe(el2_sysregs_t *regs); +#endif /* ENABLE_SPE_FOR_LOWER_ELS */ +#if CTX_INCLUDE_MTE_REGS +void el2_sysregs_context_save_mte(el2_sysregs_t *regs); +void el2_sysregs_context_restore_mte(el2_sysregs_t *regs); +#endif /* CTX_INCLUDE_MTE_REGS */ +#if ENABLE_MPAM_FOR_LOWER_ELS +void el2_sysregs_context_save_mpam(el2_sysregs_t *regs); +void el2_sysregs_context_restore_mpam(el2_sysregs_t *regs); +#endif /* ENABLE_MPAM_FOR_LOWER_ELS */ +#if ENABLE_FEAT_FGT +void el2_sysregs_context_save_fgt(el2_sysregs_t *regs); +void el2_sysregs_context_restore_fgt(el2_sysregs_t *regs); +#endif /* ENABLE_FEAT_FGT */ +#if ENABLE_FEAT_ECV +void el2_sysregs_context_save_ecv(el2_sysregs_t *regs); +void el2_sysregs_context_restore_ecv(el2_sysregs_t *regs); +#endif /* ENABLE_FEAT_ECV */ +#if ENABLE_FEAT_VHE +void el2_sysregs_context_save_vhe(el2_sysregs_t *regs); +void el2_sysregs_context_restore_vhe(el2_sysregs_t *regs); +#endif /* ENABLE_FEAT_VHE */ +#if RAS_EXTENSION +void el2_sysregs_context_save_ras(el2_sysregs_t *regs); +void el2_sysregs_context_restore_ras(el2_sysregs_t *regs); +#endif /* RAS_EXTENSION */ +#if CTX_INCLUDE_NEVE_REGS +void el2_sysregs_context_save_nv2(el2_sysregs_t *regs); +void el2_sysregs_context_restore_nv2(el2_sysregs_t *regs); +#endif /* CTX_INCLUDE_NEVE_REGS */ +#if ENABLE_TRF_FOR_NS +void el2_sysregs_context_save_trf(el2_sysregs_t *regs); +void el2_sysregs_context_restore_trf(el2_sysregs_t *regs); +#endif /* ENABLE_TRF_FOR_NS */ +#if ENABLE_FEAT_CSV2_2 +void el2_sysregs_context_save_csv2(el2_sysregs_t *regs); +void el2_sysregs_context_restore_csv2(el2_sysregs_t *regs); +#endif /* ENABLE_FEAT_CSV2_2 */ +#if ENABLE_FEAT_HCX +void el2_sysregs_context_save_hcx(el2_sysregs_t *regs); +void el2_sysregs_context_restore_hcx(el2_sysregs_t *regs); +#endif /* ENABLE_FEAT_HCX */ +#endif /* CTX_INCLUDE_EL2_REGS */ #if CTX_INCLUDE_FPREGS void fpregs_context_save(fp_regs_t *regs); diff --git a/include/lib/fconf/fconf.h b/include/lib/fconf/fconf.h index 917e053bd..131c54285 100644 --- a/include/lib/fconf/fconf.h +++ b/include/lib/fconf/fconf.h @@ -7,6 +7,7 @@ #ifndef FCONF_H #define FCONF_H +#include <stddef.h> #include <stdint.h> /* Public API */ diff --git a/include/lib/libc/aarch32/float.h b/include/lib/libc/aarch32/float.h new file mode 100644 index 000000000..857d76ea5 --- /dev/null +++ b/include/lib/libc/aarch32/float.h @@ -0,0 +1,100 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)float.h 7.1 (Berkeley) 5/8/90 + * $FreeBSD$ + */ + +#ifndef _MACHINE_FLOAT_H_ +#define _MACHINE_FLOAT_H_ 1 + +#include <sys/cdefs.h> + +__BEGIN_DECLS +extern int __flt_rounds(void); +__END_DECLS + +#define FLT_RADIX 2 /* b */ +#ifndef _ARM_HARD_FLOAT +#define FLT_ROUNDS __flt_rounds() +#else +#define FLT_ROUNDS (-1) +#endif +#if __ISO_C_VISIBLE >= 1999 +#define FLT_EVAL_METHOD 0 +#define DECIMAL_DIG 17 /* max precision in decimal digits */ +#endif + +#define FLT_MANT_DIG 24 /* p */ +#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */ +#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ +#define FLT_MIN_EXP (-125) /* emin */ +#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ +#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */ +#define FLT_MAX_EXP 128 /* emax */ +#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ +#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ +#if __ISO_C_VISIBLE >= 2011 +#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */ +#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */ +#define FLT_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define DBL_MANT_DIG 53 +#define DBL_EPSILON 2.2204460492503131E-16 +#define DBL_DIG 15 +#define DBL_MIN_EXP (-1021) +#define DBL_MIN 2.2250738585072014E-308 +#define DBL_MIN_10_EXP (-307) +#define DBL_MAX_EXP 1024 +#define DBL_MAX 1.7976931348623157E+308 +#define DBL_MAX_10_EXP 308 +#if __ISO_C_VISIBLE >= 2011 +#define DBL_TRUE_MIN 4.9406564584124654E-324 +#define DBL_DECIMAL_DIG 17 +#define DBL_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define LDBL_MANT_DIG DBL_MANT_DIG +#define LDBL_EPSILON ((long double)DBL_EPSILON) +#define LDBL_DIG DBL_DIG +#define LDBL_MIN_EXP DBL_MIN_EXP +#define LDBL_MIN ((long double)DBL_MIN) +#define LDBL_MIN_10_EXP DBL_MIN_10_EXP +#define LDBL_MAX_EXP DBL_MAX_EXP +#define LDBL_MAX ((long double)DBL_MAX) +#define LDBL_MAX_10_EXP DBL_MAX_10_EXP +#if __ISO_C_VISIBLE >= 2011 +#define LDBL_TRUE_MIN ((long double)DBL_TRUE_MIN) +#define LDBL_DECIMAL_DIG DBL_DECIMAL_DIG +#define LDBL_HAS_SUBNORM DBL_HAS_SUBNORM +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#endif /* _MACHINE_FLOAT_H_ */ diff --git a/include/lib/libc/aarch32/inttypes_.h b/include/lib/libc/aarch32/inttypes_.h index 11d2d3525..ef3fb8f7d 100644 --- a/include/lib/libc/aarch32/inttypes_.h +++ b/include/lib/libc/aarch32/inttypes_.h @@ -18,4 +18,11 @@ #define PRIx64 "llx" /* uint64_t */ #define PRIX64 "llX" /* uint64_t */ +#define PRIdPTR "d" /* intptr_t */ +#define PRIiPTR "i" /* intptr_t */ +#define PRIoPTR "o" /* intptr_t */ +#define PRIuPTR "u" /* uintptr_t */ +#define PRIxPTR "x" /* uintptr_t */ +#define PRIXPTR "X" /* uintptr_t */ + #endif /* INTTYPES__H */ diff --git a/include/lib/libc/aarch64/float.h b/include/lib/libc/aarch64/float.h new file mode 100644 index 000000000..0829f6f52 --- /dev/null +++ b/include/lib/libc/aarch64/float.h @@ -0,0 +1,94 @@ +/*- + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: @(#)float.h 7.1 (Berkeley) 5/8/90 + * $FreeBSD$ + */ + +#ifndef _MACHINE_FLOAT_H_ +#define _MACHINE_FLOAT_H_ + +#include <sys/cdefs.h> + +__BEGIN_DECLS +extern int __flt_rounds(void); +__END_DECLS + +#define FLT_RADIX 2 /* b */ +#define FLT_ROUNDS __flt_rounds() +#if __ISO_C_VISIBLE >= 1999 +#define FLT_EVAL_METHOD 0 +#define DECIMAL_DIG 17 /* max precision in decimal digits */ +#endif + +#define FLT_MANT_DIG 24 /* p */ +#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */ +#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ +#define FLT_MIN_EXP (-125) /* emin */ +#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ +#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */ +#define FLT_MAX_EXP 128 /* emax */ +#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ +#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ +#if __ISO_C_VISIBLE >= 2011 +#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */ +#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */ +#define FLT_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define DBL_MANT_DIG 53 +#define DBL_EPSILON 2.2204460492503131E-16 +#define DBL_DIG 15 +#define DBL_MIN_EXP (-1021) +#define DBL_MIN 2.2250738585072014E-308 +#define DBL_MIN_10_EXP (-307) +#define DBL_MAX_EXP 1024 +#define DBL_MAX 1.7976931348623157E+308 +#define DBL_MAX_10_EXP 308 +#if __ISO_C_VISIBLE >= 2011 +#define DBL_TRUE_MIN 4.9406564584124654E-324 +#define DBL_DECIMAL_DIG 17 +#define DBL_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define LDBL_MANT_DIG 113 +#define LDBL_EPSILON 1.925929944387235853055977942584927319E-34L +#define LDBL_DIG 33 +#define LDBL_MIN_EXP (-16381) +#define LDBL_MIN 3.362103143112093506262677817321752603E-4932L +#define LDBL_MIN_10_EXP (-4931) +#define LDBL_MAX_EXP (+16384) +#define LDBL_MAX 1.189731495357231765085759326628007016E+4932L +#define LDBL_MAX_10_EXP (+4932) +#if __ISO_C_VISIBLE >= 2011 +#define LDBL_TRUE_MIN 6.475175119438025110924438958227646552E-4966L +#define LDBL_DECIMAL_DIG 36 +#define LDBL_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#endif /* _MACHINE_FLOAT_H_ */ diff --git a/include/lib/libc/aarch64/inttypes_.h b/include/lib/libc/aarch64/inttypes_.h index 197d627bc..f25882f2c 100644 --- a/include/lib/libc/aarch64/inttypes_.h +++ b/include/lib/libc/aarch64/inttypes_.h @@ -18,4 +18,11 @@ #define PRIx64 "lx" /* uint64_t */ #define PRIX64 "lX" /* uint64_t */ +#define PRIdPTR "ld" /* intptr_t */ +#define PRIiPTR "li" /* intptr_t */ +#define PRIoPTR "lo" /* intptr_t */ +#define PRIuPTR "lu" /* uintptr_t */ +#define PRIxPTR "lx" /* uintptr_t */ +#define PRIXPTR "lX" /* uintptr_t */ + #endif /* INTTYPES__H */ diff --git a/include/lib/libc/assert.h b/include/lib/libc/assert.h index 486bbc290..462bb43fa 100644 --- a/include/lib/libc/assert.h +++ b/include/lib/libc/assert.h @@ -9,8 +9,6 @@ #include <cdefs.h> -#include <platform_def.h> - #include <common/debug.h> #ifndef PLAT_LOG_LEVEL_ASSERT @@ -18,9 +16,7 @@ #endif #if ENABLE_ASSERTIONS -# if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE -# define assert(e) ((e) ? (void)0 : __assert(__FILE__, __LINE__, #e)) -# elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO +# if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO # define assert(e) ((e) ? (void)0 : __assert(__FILE__, __LINE__)) # else # define assert(e) ((e) ? (void)0 : __assert()) @@ -29,10 +25,7 @@ #define assert(e) ((void)0) #endif /* ENABLE_ASSERTIONS */ -#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE -void __dead2 __assert(const char *file, unsigned int line, - const char *assertion); -#elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO +#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO void __dead2 __assert(const char *file, unsigned int line); #else void __dead2 __assert(void); diff --git a/include/lib/libc/cdefs.h b/include/lib/libc/cdefs.h index 0d0072254..423f0db7d 100644 --- a/include/lib/libc/cdefs.h +++ b/include/lib/libc/cdefs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,7 @@ #define __packed __attribute__((__packed__)) #define __used __attribute__((__used__)) #define __unused __attribute__((__unused__)) +#define __maybe_unused __attribute__((__unused__)) #define __aligned(x) __attribute__((__aligned__(x))) #define __section(x) __attribute__((__section__(x))) #if RECLAIM_INIT_CODE diff --git a/include/lib/libc/inttypes.h b/include/lib/libc/inttypes.h index 0f9e8c612..6ad1c9e10 100644 --- a/include/lib/libc/inttypes.h +++ b/include/lib/libc/inttypes.h @@ -17,31 +17,25 @@ #define PRId8 "d" /* int8_t */ #define PRId16 "d" /* int16_t */ #define PRId32 "d" /* int32_t */ -#define PRIdPTR "d" /* intptr_t */ #define PRIi8 "i" /* int8_t */ #define PRIi16 "i" /* int16_t */ #define PRIi32 "i" /* int32_t */ -#define PRIiPTR "i" /* intptr_t */ #define PRIo8 "o" /* int8_t */ #define PRIo16 "o" /* int16_t */ #define PRIo32 "o" /* int32_t */ -#define PRIoPTR "o" /* intptr_t */ #define PRIu8 "u" /* uint8_t */ #define PRIu16 "u" /* uint16_t */ #define PRIu32 "u" /* uint32_t */ -#define PRIuPTR "u" /* uintptr_t */ #define PRIx8 "x" /* uint8_t */ #define PRIx16 "x" /* uint16_t */ #define PRIx32 "x" /* uint32_t */ -#define PRIxPTR "x" /* uintptr_t */ #define PRIX8 "X" /* uint8_t */ #define PRIX16 "X" /* uint16_t */ #define PRIX32 "X" /* uint32_t */ -#define PRIXPTR "X" /* uintptr_t */ #endif diff --git a/include/lib/libc/sys/cdefs.h b/include/lib/libc/sys/cdefs.h new file mode 100644 index 000000000..1ace5fbee --- /dev/null +++ b/include/lib/libc/sys/cdefs.h @@ -0,0 +1,922 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Berkeley Software Design, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 + * $FreeBSD$ + */ + +#ifndef _SYS_CDEFS_H_ +#define _SYS_CDEFS_H_ + +#if defined(_KERNEL) && defined(_STANDALONE) +#error "_KERNEL and _STANDALONE are mutually exclusive" +#endif + +/* + * Testing against Clang-specific extensions. + */ +#ifndef __has_attribute +#define __has_attribute(x) 0 +#endif +#ifndef __has_extension +#define __has_extension __has_feature +#endif +#ifndef __has_feature +#define __has_feature(x) 0 +#endif +#ifndef __has_include +#define __has_include(x) 0 +#endif +#ifndef __has_builtin +#define __has_builtin(x) 0 +#endif + +#if defined(__cplusplus) +#define __BEGIN_DECLS extern "C" { +#define __END_DECLS } +#else +#define __BEGIN_DECLS +#define __END_DECLS +#endif + +/* + * This code has been put in place to help reduce the addition of + * compiler specific defines in FreeBSD code. It helps to aid in + * having a compiler-agnostic source tree. + */ + +#if defined(__GNUC__) + +#if __GNUC__ >= 3 +#define __GNUCLIKE_ASM 3 +#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS +#else +#define __GNUCLIKE_ASM 2 +#endif +#define __GNUCLIKE___TYPEOF 1 +#define __GNUCLIKE___SECTION 1 + +#define __GNUCLIKE_CTOR_SECTION_HANDLING 1 + +#define __GNUCLIKE_BUILTIN_CONSTANT_P 1 + +#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) +#define __GNUCLIKE_BUILTIN_VARARGS 1 +#define __GNUCLIKE_BUILTIN_STDARG 1 +#define __GNUCLIKE_BUILTIN_VAALIST 1 +#endif + +#define __GNUC_VA_LIST_COMPATIBILITY 1 + +/* + * Compiler memory barriers, specific to gcc and clang. + */ +#define __compiler_membar() __asm __volatile(" " : : : "memory") + +#define __GNUCLIKE_BUILTIN_NEXT_ARG 1 +#define __GNUCLIKE_MATH_BUILTIN_RELOPS + +#define __GNUCLIKE_BUILTIN_MEMCPY 1 + +/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */ +#define __CC_SUPPORTS_INLINE 1 +#define __CC_SUPPORTS___INLINE 1 +#define __CC_SUPPORTS___INLINE__ 1 + +#define __CC_SUPPORTS___FUNC__ 1 +#define __CC_SUPPORTS_WARNING 1 + +#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */ + +#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 + +#endif /* __GNUC__ */ + +/* + * Macro to test if we're using a specific version of gcc or later. + */ +#if defined(__GNUC__) +#define __GNUC_PREREQ__(ma, mi) \ + (__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi)) +#else +#define __GNUC_PREREQ__(ma, mi) 0 +#endif + +/* + * The __CONCAT macro is used to concatenate parts of symbol names, e.g. + * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. + * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI + * mode -- there must be no spaces between its arguments, and for nested + * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also + * concatenate double-quoted strings produced by the __STRING macro, but + * this only works with ANSI C. + * + * __XSTRING is like __STRING, but it expands any macros in its argument + * first. It is only available with ANSI C. + */ +#if defined(__STDC__) || defined(__cplusplus) +#define __P(protos) protos /* full-blown ANSI C */ +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x /* stringify without expanding x */ +#define __XSTRING(x) __STRING(x) /* expand x, then stringify */ + +#define __const const /* define reserved names to standard */ +#define __signed signed +#define __volatile volatile +#if defined(__cplusplus) +#define __inline inline /* convert to C++ keyword */ +#else +#if !(defined(__CC_SUPPORTS___INLINE)) +#define __inline /* delete GCC keyword */ +#endif /* ! __CC_SUPPORTS___INLINE */ +#endif /* !__cplusplus */ + +#else /* !(__STDC__ || __cplusplus) */ +#define __P(protos) () /* traditional C preprocessor */ +#define __CONCAT(x,y) x/**/y +#define __STRING(x) "x" + +#if !defined(__CC_SUPPORTS___INLINE) +#define __const /* delete pseudo-ANSI C keywords */ +#define __inline +#define __signed +#define __volatile +/* + * In non-ANSI C environments, new programs will want ANSI-only C keywords + * deleted from the program and old programs will want them left alone. + * When using a compiler other than gcc, programs using the ANSI C keywords + * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS. + * When using "gcc -traditional", we assume that this is the intent; if + * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone. + */ +#ifndef NO_ANSI_KEYWORDS +#define const /* delete ANSI C keywords */ +#define inline +#define signed +#define volatile +#endif /* !NO_ANSI_KEYWORDS */ +#endif /* !__CC_SUPPORTS___INLINE */ +#endif /* !(__STDC__ || __cplusplus) */ + +/* + * Compiler-dependent macros to help declare dead (non-returning) and + * pure (no side effects) functions, and unused variables. They are + * null except for versions of gcc that are known to support the features + * properly (old versions of gcc-2 supported the dead and pure features + * in a different (wrong) way). If we do not provide an implementation + * for a given compiler, let the compile fail if it is told to use + * a feature that we cannot live without. + */ +#define __weak_symbol __attribute__((__weak__)) +#if !__GNUC_PREREQ__(2, 5) +#define __dead2 +#define __pure2 +#define __unused +#endif +#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused +/* XXX Find out what to do for __packed, __aligned and __section */ +#endif +#if __GNUC_PREREQ__(2, 7) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#if __GNUC_PREREQ__(4, 3) || __has_attribute(__alloc_size__) +#define __alloc_size(x) __attribute__((__alloc_size__(x))) +#define __alloc_size2(n, x) __attribute__((__alloc_size__(n, x))) +#else +#define __alloc_size(x) +#define __alloc_size2(n, x) +#endif +#if __GNUC_PREREQ__(4, 9) || __has_attribute(__alloc_align__) +#define __alloc_align(x) __attribute__((__alloc_align__(x))) +#else +#define __alloc_align(x) +#endif + +#if !__GNUC_PREREQ__(2, 95) +#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b) +#endif + +/* + * Keywords added in C11. + */ + +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 201112L + +#if !__has_extension(c_alignas) +#if (defined(__cplusplus) && __cplusplus >= 201103L) || \ + __has_extension(cxx_alignas) +#define _Alignas(x) alignas(x) +#else +/* XXX: Only emulates _Alignas(constant-expression); not _Alignas(type-name). */ +#define _Alignas(x) __aligned(x) +#endif +#endif + +#if defined(__cplusplus) && __cplusplus >= 201103L +#define _Alignof(x) alignof(x) +#else +#define _Alignof(x) __alignof(x) +#endif + +#if !defined(__cplusplus) && !__has_extension(c_atomic) && \ + !__has_extension(cxx_atomic) && !__GNUC_PREREQ__(4, 7) +/* + * No native support for _Atomic(). Place object in structure to prevent + * most forms of direct non-atomic access. + */ +#define _Atomic(T) struct { T volatile __val; } +#endif + +#if defined(__cplusplus) && __cplusplus >= 201103L +#define _Noreturn [[noreturn]] +#else +#define _Noreturn __dead2 +#endif + +#if !__has_extension(c_static_assert) +#if (defined(__cplusplus) && __cplusplus >= 201103L) || \ + __has_extension(cxx_static_assert) +#define _Static_assert(x, y) static_assert(x, y) +#elif __GNUC_PREREQ__(4,6) && !defined(__cplusplus) +/* Nothing, gcc 4.6 and higher has _Static_assert built-in */ +#elif defined(__COUNTER__) +#define _Static_assert(x, y) __Static_assert(x, __COUNTER__) +#define __Static_assert(x, y) ___Static_assert(x, y) +#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1] \ + __unused +#else +#define _Static_assert(x, y) struct __hack +#endif +#endif + +#if !__has_extension(c_thread_local) +/* + * XXX: Some compilers (Clang 3.3, GCC 4.7) falsely announce C++11 mode + * without actually supporting the thread_local keyword. Don't check for + * the presence of C++11 when defining _Thread_local. + */ +#if /* (defined(__cplusplus) && __cplusplus >= 201103L) || */ \ + __has_extension(cxx_thread_local) +#define _Thread_local thread_local +#else +#define _Thread_local __thread +#endif +#endif + +#endif /* __STDC_VERSION__ || __STDC_VERSION__ < 201112L */ + +/* + * Emulation of C11 _Generic(). Unlike the previously defined C11 + * keywords, it is not possible to implement this using exactly the same + * syntax. Therefore implement something similar under the name + * __generic(). Unlike _Generic(), this macro can only distinguish + * between a single type, so it requires nested invocations to + * distinguish multiple cases. + */ + +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || \ + __has_extension(c_generic_selections) +#define __generic(expr, t, yes, no) \ + _Generic(expr, t: yes, default: no) +#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus) +#define __generic(expr, t, yes, no) \ + __builtin_choose_expr( \ + __builtin_types_compatible_p(__typeof(expr), t), yes, no) +#endif + +/* + * C99 Static array indices in function parameter declarations. Syntax such as: + * void bar(int myArray[static 10]); + * is allowed in C99 but not in C++. Define __min_size appropriately so + * headers using it can be compiled in either language. Use like this: + * void bar(int myArray[__min_size(10)]); + */ +#if !defined(__cplusplus) && \ + (defined(__clang__) || __GNUC_PREREQ__(4, 6)) && \ + (!defined(__STDC_VERSION__) || (__STDC_VERSION__ >= 199901)) +#define __min_size(x) static (x) +#else +#define __min_size(x) (x) +#endif + +#if __GNUC_PREREQ__(2, 96) +#define __malloc_like __attribute__((__malloc__)) +#define __pure __attribute__((__pure__)) +#else +#define __malloc_like +#define __pure +#endif + +#if __GNUC_PREREQ__(3, 1) +#define __always_inline __attribute__((__always_inline__)) +#else +#define __always_inline +#endif + +#if __GNUC_PREREQ__(3, 1) +#define __noinline __attribute__ ((__noinline__)) +#else +#define __noinline +#endif + +#if __GNUC_PREREQ__(3, 4) +#define __fastcall __attribute__((__fastcall__)) +#define __result_use_check __attribute__((__warn_unused_result__)) +#else +#define __fastcall +#define __result_use_check +#endif + +#if __GNUC_PREREQ__(4, 1) +#define __returns_twice __attribute__((__returns_twice__)) +#else +#define __returns_twice +#endif + +#if __GNUC_PREREQ__(4, 6) || __has_builtin(__builtin_unreachable) +#define __unreachable() __builtin_unreachable() +#else +#define __unreachable() ((void)0) +#endif + +/* XXX: should use `#if __STDC_VERSION__ < 199901'. */ +#if !__GNUC_PREREQ__(2, 7) +#define __func__ NULL +#endif + +#if (defined(__GNUC__) && __GNUC__ >= 2) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901 +#define __LONG_LONG_SUPPORTED +#endif + +/* C++11 exposes a load of C99 stuff */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define __LONG_LONG_SUPPORTED +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS +#endif +#ifndef __STDC_CONSTANT_MACROS +#define __STDC_CONSTANT_MACROS +#endif +#endif + +/* + * GCC 2.95 provides `__restrict' as an extension to C90 to support the + * C99-specific `restrict' type qualifier. We happen to use `__restrict' as + * a way to define the `restrict' type qualifier without disturbing older + * software that is unaware of C99 keywords. + */ +#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95) +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 +#define __restrict +#else +#define __restrict restrict +#endif +#endif + +/* + * GNU C version 2.96 adds explicit branch prediction so that + * the CPU back-end can hint the processor and also so that + * code blocks can be reordered such that the predicted path + * sees a more linear flow, thus improving cache behavior, etc. + * + * The following two macros provide us with a way to utilize this + * compiler feature. Use __predict_true() if you expect the expression + * to evaluate to true, and __predict_false() if you expect the + * expression to evaluate to false. + * + * A few notes about usage: + * + * * Generally, __predict_false() error condition checks (unless + * you have some _strong_ reason to do otherwise, in which case + * document it), and/or __predict_true() `no-error' condition + * checks, assuming you want to optimize for the no-error case. + * + * * Other than that, if you don't know the likelihood of a test + * succeeding from empirical or other `hard' evidence, don't + * make predictions. + * + * * These are meant to be used in places that are run `a lot'. + * It is wasteful to make predictions in code that is run + * seldomly (e.g. at subsystem initialization time) as the + * basic block reordering that this affects can often generate + * larger code. + */ +#if __GNUC_PREREQ__(2, 96) +#define __predict_true(exp) __builtin_expect((exp), 1) +#define __predict_false(exp) __builtin_expect((exp), 0) +#else +#define __predict_true(exp) (exp) +#define __predict_false(exp) (exp) +#endif + +#if __GNUC_PREREQ__(4, 0) +#define __null_sentinel __attribute__((__sentinel__)) +#define __exported __attribute__((__visibility__("default"))) +#define __hidden __attribute__((__visibility__("hidden"))) +#else +#define __null_sentinel +#define __exported +#define __hidden +#endif + +/* + * We define this here since <stddef.h>, <sys/queue.h>, and <sys/types.h> + * require it. + */ +#if __GNUC_PREREQ__(4, 1) +#define __offsetof(type, field) __builtin_offsetof(type, field) +#else +#ifndef __cplusplus +#define __offsetof(type, field) \ + ((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field)) +#else +#define __offsetof(type, field) \ + (__offsetof__ (reinterpret_cast <__size_t> \ + (&reinterpret_cast <const volatile char &> \ + (static_cast<type *> (0)->field)))) +#endif +#endif +#define __rangeof(type, start, end) \ + (__offsetof(type, end) - __offsetof(type, start)) + +/* + * Given the pointer x to the member m of the struct s, return + * a pointer to the containing structure. When using GCC, we first + * assign pointer x to a local variable, to check that its type is + * compatible with member m. + */ +#if __GNUC_PREREQ__(3, 1) +#define __containerof(x, s, m) ({ \ + const volatile __typeof(((s *)0)->m) *__x = (x); \ + __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\ +}) +#else +#define __containerof(x, s, m) \ + __DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m)) +#endif + +/* + * Compiler-dependent macros to declare that functions take printf-like + * or scanf-like arguments. They are null except for versions of gcc + * that are known to support the features properly (old versions of gcc-2 + * didn't permit keeping the keywords out of the application namespace). + */ +#if !__GNUC_PREREQ__(2, 7) +#define __printflike(fmtarg, firstvararg) +#define __scanflike(fmtarg, firstvararg) +#define __format_arg(fmtarg) +#define __strfmonlike(fmtarg, firstvararg) +#define __strftimelike(fmtarg, firstvararg) +#else +#define __printflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf__, fmtarg, firstvararg))) +#define __scanflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) +#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) +#define __strfmonlike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) +#define __strftimelike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) +#endif + +/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ +#if defined(__FreeBSD_cc_version) && __FreeBSD_cc_version >= 300001 && \ + defined(__GNUC__) +#define __printf0like(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf0__, fmtarg, firstvararg))) +#else +#define __printf0like(fmtarg, firstvararg) +#endif + +#if defined(__GNUC__) +#define __strong_reference(sym,aliassym) \ + extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) +#ifdef __STDC__ +#define __weak_reference(sym,alias) \ + __asm__(".weak " #alias); \ + __asm__(".equ " #alias ", " #sym) +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning." #sym); \ + __asm__(".asciz \"" msg "\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@" #verid) +#define __sym_default(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@@@" #verid) +#else +#define __weak_reference(sym,alias) \ + __asm__(".weak alias"); \ + __asm__(".equ alias, sym") +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning.sym"); \ + __asm__(".asciz \"msg\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver impl, sym@verid") +#define __sym_default(impl,sym,verid) \ + __asm__(".symver impl, sym@@@verid") +#endif /* __STDC__ */ +#endif /* __GNUC__ */ + +#define __GLOBL(sym) __asm__(".globl " __XSTRING(sym)) +#define __WEAK(sym) __asm__(".weak " __XSTRING(sym)) + +#if defined(__GNUC__) +#define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"") +#else +/* + * The following definition might not work well if used in header files, + * but it should be better than nothing. If you want a "do nothing" + * version, then it should generate some harmless declaration, such as: + * #define __IDSTRING(name,string) struct __hack + */ +#define __IDSTRING(name,string) static const char name[] __unused = string +#endif + +/* + * Embed the rcs id of a source file in the resulting library. Note that in + * more recent ELF binutils, we use .ident allowing the ID to be stripped. + * Usage: + * __FBSDID("$FreeBSD$"); + */ +#ifndef __FBSDID +#if !defined(STRIP_FBSDID) +#define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __FBSDID(s) struct __hack +#endif +#endif + +#ifndef __RCSID +#ifndef NO__RCSID +#define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __RCSID(s) struct __hack +#endif +#endif + +#ifndef __RCSID_SOURCE +#ifndef NO__RCSID_SOURCE +#define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s) +#else +#define __RCSID_SOURCE(s) struct __hack +#endif +#endif + +#ifndef __SCCSID +#ifndef NO__SCCSID +#define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s) +#else +#define __SCCSID(s) struct __hack +#endif +#endif + +#ifndef __COPYRIGHT +#ifndef NO__COPYRIGHT +#define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s) +#else +#define __COPYRIGHT(s) struct __hack +#endif +#endif + +#ifndef __DECONST +#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var)) +#endif + +#ifndef __DEVOLATILE +#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var)) +#endif + +#ifndef __DEQUALIFY +#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var)) +#endif + +/*- + * The following definitions are an extension of the behavior originally + * implemented in <sys/_posix.h>, but with a different level of granularity. + * POSIX.1 requires that the macros we test be defined before any standard + * header file is included. + * + * Here's a quick run-down of the versions (and some informal names) + * defined(_POSIX_SOURCE) 1003.1-1988 + * encoded as 198808 below + * _POSIX_C_SOURCE == 1 1003.1-1990 + * encoded as 199009 below + * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option + * encoded as 199209 below + * _POSIX_C_SOURCE == 199309 1003.1b-1993 + * (1003.1 Issue 4, Single Unix Spec v1, Unix 93) + * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, + * and the omnibus ISO/IEC 9945-1: 1996 + * (1003.1 Issue 5, Single Unix Spec v2, Unix 95) + * _POSIX_C_SOURCE == 200112 1003.1-2001 (1003.1 Issue 6, Unix 03) + * _POSIX_C_SOURCE == 200809 1003.1-2008 (1003.1 Issue 7) + * IEEE Std 1003.1-2017 (Rev of 1003.1-2008) is + * 1003.1-2008 with two TCs applied with + * _POSIX_C_SOURCE=200809 and _XOPEN_SOURCE=700 + * + * In addition, the X/Open Portability Guide, which is now the Single UNIX + * Specification, defines a feature-test macro which indicates the version of + * that specification, and which subsumes _POSIX_C_SOURCE. + * + * Our macros begin with two underscores to avoid namespace screwage. + */ + +/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1 +#undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */ +#define _POSIX_C_SOURCE 199009 +#endif + +/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199209 +#endif + +/* Deal with various X/Open Portability Guides and Single UNIX Spec. */ +#ifdef _XOPEN_SOURCE +#if _XOPEN_SOURCE - 0 >= 700 +#define __XSI_VISIBLE 700 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809 +#elif _XOPEN_SOURCE - 0 >= 600 +#define __XSI_VISIBLE 600 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200112 +#elif _XOPEN_SOURCE - 0 >= 500 +#define __XSI_VISIBLE 500 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199506 +#endif +#endif + +/* + * Deal with all versions of POSIX. The ordering relative to the tests above is + * important. + */ +#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) +#define _POSIX_C_SOURCE 198808 +#endif +#ifdef _POSIX_C_SOURCE +#if _POSIX_C_SOURCE >= 200809 +#define __POSIX_VISIBLE 200809 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 200112 +#define __POSIX_VISIBLE 200112 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 199506 +#define __POSIX_VISIBLE 199506 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199309 +#define __POSIX_VISIBLE 199309 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199209 +#define __POSIX_VISIBLE 199209 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199009 +#define __POSIX_VISIBLE 199009 +#define __ISO_C_VISIBLE 1990 +#else +#define __POSIX_VISIBLE 198808 +#define __ISO_C_VISIBLE 0 +#endif /* _POSIX_C_SOURCE */ +/* + * Both glibc and OpenBSD enable c11 features when _ISOC11_SOURCE is defined, or + * when compiling with -stdc=c11. A strict reading of the standard would suggest + * doing it only for the former. However, a strict reading also requires C99 + * mode only, so building with C11 is already undefined. Follow glibc's and + * OpenBSD's lead for this non-standard configuration for maximum compatibility. + */ +#if _ISOC11_SOURCE || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) +#undef __ISO_C_VISIBLE +#define __ISO_C_VISIBLE 2011 +#endif +#else +/*- + * Deal with _ANSI_SOURCE: + * If it is defined, and no other compilation environment is explicitly + * requested, then define our internal feature-test macros to zero. This + * makes no difference to the preprocessor (undefined symbols in preprocessing + * expressions are defined to have value zero), but makes it more convenient for + * a test program to print out the values. + * + * If a program mistakenly defines _ANSI_SOURCE and some other macro such as + * _POSIX_C_SOURCE, we will assume that it wants the broader compilation + * environment (and in fact we will never get here). + */ +#if defined(_ANSI_SOURCE) /* Hide almost everything. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1990 +#define __EXT1_VISIBLE 0 +#elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1999 +#define __EXT1_VISIBLE 0 +#elif defined(_C11_SOURCE) /* Localism to specify strict C11 env. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 2011 +#define __EXT1_VISIBLE 0 +#else /* Default environment: show everything. */ +#define __POSIX_VISIBLE 200809 +#define __XSI_VISIBLE 700 +#define __BSD_VISIBLE 1 +#define __ISO_C_VISIBLE 2011 +#define __EXT1_VISIBLE 1 +#endif +#endif + +/* User override __EXT1_VISIBLE */ +#if defined(__STDC_WANT_LIB_EXT1__) +#undef __EXT1_VISIBLE +#if __STDC_WANT_LIB_EXT1__ +#define __EXT1_VISIBLE 1 +#else +#define __EXT1_VISIBLE 0 +#endif +#endif /* __STDC_WANT_LIB_EXT1__ */ + +/* + * Old versions of GCC use non-standard ARM arch symbols; acle-compat.h + * translates them to __ARM_ARCH and the modern feature symbols defined by ARM. + */ +#if defined(__arm__) && !defined(__ARM_ARCH) +#include <machine/acle-compat.h> +#endif + +/* + * Nullability qualifiers: currently only supported by Clang. + */ +#if !(defined(__clang__) && __has_feature(nullability)) +#define _Nonnull +#define _Nullable +#define _Null_unspecified +#define __NULLABILITY_PRAGMA_PUSH +#define __NULLABILITY_PRAGMA_POP +#else +#define __NULLABILITY_PRAGMA_PUSH _Pragma("clang diagnostic push") \ + _Pragma("clang diagnostic ignored \"-Wnullability-completeness\"") +#define __NULLABILITY_PRAGMA_POP _Pragma("clang diagnostic pop") +#endif + +/* + * Type Safety Checking + * + * Clang provides additional attributes to enable checking type safety + * properties that cannot be enforced by the C type system. + */ + +#if __has_attribute(__argument_with_type_tag__) && \ + __has_attribute(__type_tag_for_datatype__) +#define __arg_type_tag(arg_kind, arg_idx, type_tag_idx) \ + __attribute__((__argument_with_type_tag__(arg_kind, arg_idx, type_tag_idx))) +#define __datatype_type_tag(kind, type) \ + __attribute__((__type_tag_for_datatype__(kind, type))) +#else +#define __arg_type_tag(arg_kind, arg_idx, type_tag_idx) +#define __datatype_type_tag(kind, type) +#endif + +/* + * Lock annotations. + * + * Clang provides support for doing basic thread-safety tests at + * compile-time, by marking which locks will/should be held when + * entering/leaving a functions. + * + * Furthermore, it is also possible to annotate variables and structure + * members to enforce that they are only accessed when certain locks are + * held. + */ + +#if __has_extension(c_thread_safety_attributes) +#define __lock_annotate(x) __attribute__((x)) +#else +#define __lock_annotate(x) +#endif + +/* Structure implements a lock. */ +#define __lockable __lock_annotate(lockable) + +/* Function acquires an exclusive or shared lock. */ +#define __locks_exclusive(...) \ + __lock_annotate(exclusive_lock_function(__VA_ARGS__)) +#define __locks_shared(...) \ + __lock_annotate(shared_lock_function(__VA_ARGS__)) + +/* Function attempts to acquire an exclusive or shared lock. */ +#define __trylocks_exclusive(...) \ + __lock_annotate(exclusive_trylock_function(__VA_ARGS__)) +#define __trylocks_shared(...) \ + __lock_annotate(shared_trylock_function(__VA_ARGS__)) + +/* Function releases a lock. */ +#define __unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__)) + +/* Function asserts that an exclusive or shared lock is held. */ +#define __asserts_exclusive(...) \ + __lock_annotate(assert_exclusive_lock(__VA_ARGS__)) +#define __asserts_shared(...) \ + __lock_annotate(assert_shared_lock(__VA_ARGS__)) + +/* Function requires that an exclusive or shared lock is or is not held. */ +#define __requires_exclusive(...) \ + __lock_annotate(exclusive_locks_required(__VA_ARGS__)) +#define __requires_shared(...) \ + __lock_annotate(shared_locks_required(__VA_ARGS__)) +#define __requires_unlocked(...) \ + __lock_annotate(locks_excluded(__VA_ARGS__)) + +/* Function should not be analyzed. */ +#define __no_lock_analysis __lock_annotate(no_thread_safety_analysis) + +/* + * Function or variable should not be sanitized, e.g., by AddressSanitizer. + * GCC has the nosanitize attribute, but as a function attribute only, and + * warns on use as a variable attribute. + */ +#if __has_attribute(no_sanitize) && defined(__clang__) +#ifdef _KERNEL +#define __nosanitizeaddress __attribute__((no_sanitize("kernel-address"))) +#define __nosanitizememory __attribute__((no_sanitize("kernel-memory"))) +#else +#define __nosanitizeaddress __attribute__((no_sanitize("address"))) +#define __nosanitizememory __attribute__((no_sanitize("memory"))) +#endif +#define __nosanitizethread __attribute__((no_sanitize("thread"))) +#else +#define __nosanitizeaddress +#define __nosanitizememory +#define __nosanitizethread +#endif + +/* Guard variables and structure members by lock. */ +#define __guarded_by(x) __lock_annotate(guarded_by(x)) +#define __pt_guarded_by(x) __lock_annotate(pt_guarded_by(x)) + +/* Alignment builtins for better type checking and improved code generation. */ +/* Provide fallback versions for other compilers (GCC/Clang < 10): */ +#if !__has_builtin(__builtin_is_aligned) +#define __builtin_is_aligned(x, align) \ + (((__uintptr_t)x & ((align) - 1)) == 0) +#endif +#if !__has_builtin(__builtin_align_up) +#define __builtin_align_up(x, align) \ + ((__typeof__(x))(((__uintptr_t)(x)+((align)-1))&(~((align)-1)))) +#endif +#if !__has_builtin(__builtin_align_down) +#define __builtin_align_down(x, align) \ + ((__typeof__(x))((x)&(~((align)-1)))) +#endif + +#define __align_up(x, y) __builtin_align_up(x, y) +#define __align_down(x, y) __builtin_align_down(x, y) +#define __is_aligned(x, y) __builtin_is_aligned(x, y) + +#endif /* !_SYS_CDEFS_H_ */ diff --git a/include/lib/libfdt/libfdt.h b/include/lib/libfdt/libfdt.h index 544d3efff..a7f432c80 100644 --- a/include/lib/libfdt/libfdt.h +++ b/include/lib/libfdt/libfdt.h @@ -14,6 +14,7 @@ extern "C" { #endif #define FDT_FIRST_SUPPORTED_VERSION 0x02 +#define FDT_LAST_COMPATIBLE_VERSION 0x10 #define FDT_LAST_SUPPORTED_VERSION 0x11 /* Error codes: informative error codes */ @@ -101,7 +102,11 @@ extern "C" { /* FDT_ERR_BADFLAGS: The function was passed a flags field that * contains invalid flags or an invalid combination of flags. */ -#define FDT_ERR_MAX 18 +#define FDT_ERR_ALIGNMENT 19 + /* FDT_ERR_ALIGNMENT: The device tree base address is not 8-byte + * aligned. */ + +#define FDT_ERR_MAX 19 /* constants */ #define FDT_MAX_PHANDLE 0xfffffffe @@ -122,11 +127,16 @@ static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); /* - * Alignment helpers: - * These helpers access words from a device tree blob. They're - * built to work even with unaligned pointers on platforms (ike - * ARM) that don't like unaligned loads and stores + * External helpers to access words from a device tree blob. They're built + * to work even with unaligned pointers on platforms (such as ARMv5) that don't + * like unaligned loads and stores. */ +static inline uint16_t fdt16_ld(const fdt16_t *p) +{ + const uint8_t *bp = (const uint8_t *)p; + + return ((uint16_t)bp[0] << 8) | bp[1]; +} static inline uint32_t fdt32_ld(const fdt32_t *p) { @@ -184,23 +194,23 @@ int fdt_next_node(const void *fdt, int offset, int *depth); /** * fdt_first_subnode() - get offset of first direct subnode - * * @fdt: FDT blob * @offset: Offset of node to check - * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + * + * Return: offset of first subnode, or -FDT_ERR_NOTFOUND if there is none */ int fdt_first_subnode(const void *fdt, int offset); /** * fdt_next_subnode() - get offset of next direct subnode + * @fdt: FDT blob + * @offset: Offset of previous subnode * * After first calling fdt_first_subnode(), call this function repeatedly to * get direct subnodes of a parent node. * - * @fdt: FDT blob - * @offset: Offset of previous subnode - * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more - * subnodes + * Return: offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes */ int fdt_next_subnode(const void *fdt, int offset); @@ -225,7 +235,6 @@ int fdt_next_subnode(const void *fdt, int offset); * Note that this is implemented as a macro and @node is used as * iterator in the loop. The parent variable be constant or even a * literal. - * */ #define fdt_for_each_subnode(node, fdt, parent) \ for (node = fdt_first_subnode(fdt, parent); \ @@ -269,17 +278,21 @@ fdt_set_hdr_(size_dt_struct); /** * fdt_header_size - return the size of the tree's header * @fdt: pointer to a flattened device tree + * + * Return: size of DTB header in bytes */ size_t fdt_header_size(const void *fdt); /** - * fdt_header_size_ - internal function which takes a version number + * fdt_header_size_ - internal function to get header size from a version number + * @version: devicetree version number + * + * Return: size of DTB header in bytes */ size_t fdt_header_size_(uint32_t version); /** * fdt_check_header - sanity check a device tree header - * @fdt: pointer to data which might be a flattened device tree * * fdt_check_header() checks that the given buffer contains what @@ -404,8 +417,7 @@ static inline uint32_t fdt_get_max_phandle(const void *fdt) * highest phandle value in the device tree blob) will be returned in the * @phandle parameter. * - * Returns: - * 0 on success or a negative error-code on failure + * Return: 0 on success or a negative error-code on failure */ int fdt_generate_phandle(const void *fdt, uint32_t *phandle); @@ -425,9 +437,11 @@ int fdt_num_mem_rsv(const void *fdt); /** * fdt_get_mem_rsv - retrieve one memory reserve map entry * @fdt: pointer to the device tree blob - * @address, @size: pointers to 64-bit variables + * @n: index of reserve map entry + * @address: pointer to 64-bit variable to hold the start address + * @size: pointer to 64-bit variable to hold the size of the entry * - * On success, *address and *size will contain the address and size of + * On success, @address and @size will contain the address and size of * the n-th reserve map entry from the device tree blob, in * native-endian format. * @@ -450,6 +464,8 @@ int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); * namelen characters of name for matching the subnode name. This is * useful for finding subnodes based on a portion of a larger string, * such as a full path. + * + * Return: offset of the subnode or -FDT_ERR_NOTFOUND if name not found. */ #ifndef SWIG /* Not available in Python */ int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, @@ -489,6 +505,8 @@ int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); * * Identical to fdt_path_offset(), but only consider the first namelen * characters of path as the path name. + * + * Return: offset of the node or negative libfdt error value otherwise */ #ifndef SWIG /* Not available in Python */ int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); @@ -588,9 +606,9 @@ int fdt_next_property_offset(const void *fdt, int offset); /** * fdt_for_each_property_offset - iterate over all properties of a node * - * @property_offset: property offset (int, lvalue) - * @fdt: FDT blob (const void *) - * @node: node offset (int) + * @property: property offset (int, lvalue) + * @fdt: FDT blob (const void *) + * @node: node offset (int) * * This is actually a wrapper around a for loop and would be used like so: * @@ -653,6 +671,9 @@ const struct fdt_property *fdt_get_property_by_offset(const void *fdt, * * Identical to fdt_get_property(), but only examine the first namelen * characters of name for matching the property name. + * + * Return: pointer to the structure representing the property, or NULL + * if not found */ #ifndef SWIG /* Not available in Python */ const struct fdt_property *fdt_get_property_namelen(const void *fdt, @@ -745,6 +766,8 @@ const void *fdt_getprop_by_offset(const void *fdt, int offset, * * Identical to fdt_getprop(), but only examine the first namelen * characters of name for matching the property name. + * + * Return: pointer to the property's value or NULL on error */ #ifndef SWIG /* Not available in Python */ const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, @@ -766,10 +789,10 @@ static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset, * @lenp: pointer to an integer variable (will be overwritten) or NULL * * fdt_getprop() retrieves a pointer to the value of the property - * named 'name' of the node at offset nodeoffset (this will be a + * named @name of the node at offset @nodeoffset (this will be a * pointer to within the device blob itself, not a copy of the value). - * If lenp is non-NULL, the length of the property value is also - * returned, in the integer pointed to by lenp. + * If @lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by @lenp. * * returns: * pointer to the property's value @@ -814,8 +837,11 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); * @name: name of the alias th look up * @namelen: number of characters of name to consider * - * Identical to fdt_get_alias(), but only examine the first namelen - * characters of name for matching the alias name. + * Identical to fdt_get_alias(), but only examine the first @namelen + * characters of @name for matching the alias name. + * + * Return: a pointer to the expansion of the alias named @name, if it exists, + * NULL otherwise */ #ifndef SWIG /* Not available in Python */ const char *fdt_get_alias_namelen(const void *fdt, @@ -828,7 +854,7 @@ const char *fdt_get_alias_namelen(const void *fdt, * @name: name of the alias th look up * * fdt_get_alias() retrieves the value of a given alias. That is, the - * value of the property named 'name' in the node /aliases. + * value of the property named @name in the node /aliases. * * returns: * a pointer to the expansion of the alias named 'name', if it exists @@ -1004,14 +1030,13 @@ int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); /** - * fdt_node_check_compatible: check a node's compatible property + * fdt_node_check_compatible - check a node's compatible property * @fdt: pointer to the device tree blob * @nodeoffset: offset of a tree node * @compatible: string to match against * - * * fdt_node_check_compatible() returns 0 if the given node contains a - * 'compatible' property with the given string as one of its elements, + * @compatible property with the given string as one of its elements, * it returns non-zero otherwise, or on error. * * returns: @@ -1075,7 +1100,7 @@ int fdt_node_offset_by_compatible(const void *fdt, int startoffset, * one or more strings, each terminated by \0, as is found in a device tree * "compatible" property. * - * @return: 1 if the string is found in the list, 0 not found, or invalid list + * Return: 1 if the string is found in the list, 0 not found, or invalid list */ int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); @@ -1084,7 +1109,8 @@ int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); * @fdt: pointer to the device tree blob * @nodeoffset: offset of a tree node * @property: name of the property containing the string list - * @return: + * + * Return: * the number of strings in the given property * -FDT_ERR_BADVALUE if the property value is not NUL-terminated * -FDT_ERR_NOTFOUND if the property does not exist @@ -1104,7 +1130,7 @@ int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property); * small-valued cell properties, such as #address-cells, when searching for * the empty string. * - * @return: + * return: * the index of the string in the list of strings * -FDT_ERR_BADVALUE if the property value is not NUL-terminated * -FDT_ERR_NOTFOUND if the property does not exist or does not contain @@ -1128,7 +1154,7 @@ int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, * If non-NULL, the length of the string (on success) or a negative error-code * (on failure) will be stored in the integer pointer to by lenp. * - * @return: + * Return: * A pointer to the string at the given index in the string list or NULL on * failure. On success the length of the string will be stored in the memory * location pointed to by the lenp parameter, if non-NULL. On failure one of @@ -1217,6 +1243,8 @@ int fdt_size_cells(const void *fdt, int nodeoffset); * starting from the given index, and using only the first characters * of the name. It is useful when you want to manipulate only one value of * an array and you have a string that doesn't end with \0. + * + * Return: 0 on success, negative libfdt error value otherwise */ #ifndef SWIG /* Not available in Python */ int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, @@ -1330,8 +1358,13 @@ static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, /** * fdt_setprop_inplace_cell - change the value of a single-cell property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node containing the property + * @name: name of the property to change the value of + * @val: new value of the 32-bit cell * * This is an alternative name for fdt_setprop_inplace_u32() + * Return: 0 on success, negative libfdt error number otherwise. */ static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, const char *name, uint32_t val) @@ -1403,7 +1436,7 @@ int fdt_nop_node(void *fdt, int nodeoffset); /** * fdt_create_with_flags - begin creation of a new fdt - * @fdt: pointer to memory allocated where fdt will be created + * @buf: pointer to memory allocated where fdt will be created * @bufsize: size of the memory space at fdt * @flags: a valid combination of FDT_CREATE_FLAG_ flags, or 0. * @@ -1421,7 +1454,7 @@ int fdt_create_with_flags(void *buf, int bufsize, uint32_t flags); /** * fdt_create - begin creation of a new fdt - * @fdt: pointer to memory allocated where fdt will be created + * @buf: pointer to memory allocated where fdt will be created * @bufsize: size of the memory space at fdt * * fdt_create() is equivalent to fdt_create_with_flags() with flags=0. @@ -1486,7 +1519,8 @@ int fdt_pack(void *fdt); /** * fdt_add_mem_rsv - add one memory reserve map entry * @fdt: pointer to the device tree blob - * @address, @size: 64-bit values (native endian) + * @address: 64-bit start address of the reserve map entry + * @size: 64-bit size of the reserved region * * Adds a reserve map entry to the given blob reserving a region at * address address of length size. @@ -1691,8 +1725,14 @@ static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, /** * fdt_setprop_cell - set a property to a single cell value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) * * This is an alternative name for fdt_setprop_u32() + * + * Return: 0 on success, negative libfdt error value otherwise. */ static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, uint32_t val) @@ -1863,8 +1903,14 @@ static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, /** * fdt_appendprop_cell - append a single cell value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) * * This is an alternative name for fdt_appendprop_u32() + * + * Return: 0 on success, negative libfdt error value otherwise. */ static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, const char *name, uint32_t val) @@ -1967,13 +2013,16 @@ int fdt_delprop(void *fdt, int nodeoffset, const char *name); * fdt_add_subnode_namelen - creates a new node based on substring * @fdt: pointer to the device tree blob * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate + * @name: name of the subnode to create * @namelen: number of characters of name to consider * - * Identical to fdt_add_subnode(), but use only the first namelen - * characters of name as the name of the new node. This is useful for + * Identical to fdt_add_subnode(), but use only the first @namelen + * characters of @name as the name of the new node. This is useful for * creating subnodes based on a portion of a larger string, such as a * full path. + * + * Return: structure block offset of the created subnode (>=0), + * negative libfdt error value otherwise */ #ifndef SWIG /* Not available in Python */ int fdt_add_subnode_namelen(void *fdt, int parentoffset, @@ -1992,7 +2041,7 @@ int fdt_add_subnode_namelen(void *fdt, int parentoffset, * * This function will insert data into the blob, and will therefore * change the offsets of some existing nodes. - + * * returns: * structure block offset of the created nodeequested subnode (>=0), on * success @@ -2067,6 +2116,24 @@ int fdt_del_node(void *fdt, int nodeoffset); */ int fdt_overlay_apply(void *fdt, void *fdto); +/** + * fdt_overlay_target_offset - retrieves the offset of a fragment's target + * @fdt: Base device tree blob + * @fdto: Device tree overlay blob + * @fragment_offset: node offset of the fragment in the overlay + * @pathp: pointer which receives the path of the target (or NULL) + * + * fdt_overlay_target_offset() retrieves the target offset in the base + * device tree of a fragment, no matter how the actual targeting is + * done (through a phandle or a path) + * + * returns: + * the targeted node offset in the base device tree + * Negative error code on error + */ +int fdt_overlay_target_offset(const void *fdt, const void *fdto, + int fragment_offset, char const **pathp); + /**********************************************************************/ /* Debugging / informational functions */ /**********************************************************************/ diff --git a/include/lib/psa/delegated_attestation.h b/include/lib/psa/delegated_attestation.h new file mode 100644 index 000000000..7aaceb3e3 --- /dev/null +++ b/include/lib/psa/delegated_attestation.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* This file describes the Delegated Attestation API */ + +#ifndef DELEGATED_ATTESTATION_H +#define DELEGATED_ATTESTATION_H + +#include <stddef.h> +#include <stdint.h> + +#include "psa/error.h" + +/* RSS Delegated Attestation message types that distinguish its services. */ +#define RSS_DELEGATED_ATTEST_GET_DELEGATED_KEY 1001U +#define RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN 1002U + +/** + * The aim of these APIs to get a derived signing key (private only) for the + * delegated attestation model and obtain the corresponding platform attestation + * token. In the delegated attestation model the final token consist of more + * than one subtokens which are signed by different entities. There is a + * cryptographical binding between the tokens. The derived delegated attestation + * key is bind to the platform token (details below). + * + * Expected usage model: + * - First rss_delegated_attest_get_delegated_key() API need to be called to + * obtain the private part of the delegated attestation key. The public part + * of key is computed by the cryptographic library when the key is + * registered. + * - Secondly the rss_delegated_attest_get_token() must be called to obtain + * platform attestation token. The hash of the public key (computed by + * the hash_algo indicated in the rss_delegated_attest_get_delegated_key() + * call) must be the input of this call. This ensures that nothing but the + * previously derived delegated key is bindable to the platform token. + */ + +/** + * Get a delegated attestation key (DAK). + * + * The aim of the delegated attestation key is to enable other SW components + * within the system to sign an attestation token which is different than the + * initial/platform token. The initial attestation token MUST contain the hash + * of the public delegated key to make a cryptographical binding (hash lock) + * between the key and the token. + * The initial attestation token has two roles in this scenario: + * - Attest the device boot status and security lifecycle. + * - Attest the delegated attestation key. + * The delegated attestation key is derived from a preprovisioned seed. The + * input for the key derivation is the platform boot status. The system can be + * attestated with the two tokens together. + * + * ecc_curve The type of the elliptic curve to which the requested + * attestation key belongs. Please check the note section for + * limitations. + * key_bits The size of the requested attestation key, in bits. + * key_buf Pointer to the buffer where the delegated attestation key will + * be stored. + * key_buf_size Size of allocated buffer for the key, in bytes. + * key_size Size of the key that has been returned, in bytes. + * hash_algo The hash algorithm that will be used later by the owner of the + * requested delegated key for binding it to the platform + * attestation token. + * + * Returns error code as specified in psa_status_t. + * + * Notes: + * - Currently, only the PSA_ECC_FAMILY_SECP_R1 curve type is supported. + * - The delegated attestation key must be derived before requesting for the + * platform attestation token as they are cryptographically linked together. + */ +psa_status_t +rss_delegated_attest_get_delegated_key(uint8_t ecc_curve, + uint32_t key_bits, + uint8_t *key_buf, + size_t key_buf_size, + size_t *key_size, + uint32_t hash_algo); + +/** + * Get platform attestation token + * + * dak_pub_hash Pointer to buffer where the hash of the public DAK is + * stored. + * dak_pub_hash_size Size of the hash value, in bytes. + * token_buf Pointer to the buffer where the platform attestation token + * will be stored. + * token_buf_size Size of allocated buffer for token, in bytes. + * token_size Size of the token that has been returned, in bytes. + * + * Returns error code as specified in psa_status_t. + * + * A delegated attestation key must be derived before requesting for the + * platform attestation token as they are cryptographically linked together. + * Otherwise, the token request will fail and the PSA_ERROR_INVALID_ARGUMENT + * code will be returned. + */ +psa_status_t +rss_delegated_attest_get_token(const uint8_t *dak_pub_hash, + size_t dak_pub_hash_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size); + +#endif /* DELEGATED_ATTESTATION_H */ diff --git a/include/lib/psa/initial_attestation.h b/include/lib/psa/initial_attestation.h deleted file mode 100644 index 93169f018..000000000 --- a/include/lib/psa/initial_attestation.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2018-2022, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef PSA_INITIAL_ATTESTATION_H -#define PSA_INITIAL_ATTESTATION_H - -#include <limits.h> -#include <stddef.h> -#include <stdint.h> - -#include "psa/error.h" - -/* - * Initial attestation API version is: 1.0.0 - */ -#define PSA_INITIAL_ATTEST_API_VERSION_MAJOR (1) -#define PSA_INITIAL_ATTEST_API_VERSION_MINOR (0) - -/* The allowed size of input challenge in bytes. */ -#define PSA_INITIAL_ATTEST_CHALLENGE_SIZE_32 32U -#define PSA_INITIAL_ATTEST_CHALLENGE_SIZE_48 48U -#define PSA_INITIAL_ATTEST_CHALLENGE_SIZE_64 64U - -/* Initial Attestation message types that distinguish Attest services. */ -#define RSS_ATTEST_GET_TOKEN 1001U -#define RSS_ATTEST_GET_TOKEN_SIZE 1002U -#define RSS_ATTEST_GET_DELEGATED_KEY 1003U - -/** - * Get the platform attestation token. - * - * auth_challenge Pointer to buffer where challenge input is stored. This - * must be the hash of the public part of the delegated - * attestation key. - * challenge_size Size of challenge object in bytes. - * token_buf Pointer to the buffer where attestation token will be - * stored. - * token_buf_size Size of allocated buffer for token, in bytes. - * token_size Size of the token that has been returned, in bytes. - * - * Returns error code as specified in psa_status_t. - */ -psa_status_t -psa_initial_attest_get_token(const uint8_t *auth_challenge, - size_t challenge_size, - uint8_t *token_buf, - size_t token_buf_size, - size_t *token_size); - -#endif /* PSA_INITIAL_ATTESTATION_H */ diff --git a/include/lib/psa/psa_manifest/sid.h b/include/lib/psa/psa_manifest/sid.h index 947e58f09..0bdeed474 100644 --- a/include/lib/psa/psa_manifest/sid.h +++ b/include/lib/psa/psa_manifest/sid.h @@ -8,14 +8,10 @@ #ifndef PSA_MANIFEST_SID_H #define PSA_MANIFEST_SID_H -/******** PSA_SP_INITIAL_ATTESTATION ********/ -#define RSS_ATTESTATION_SERVICE_SID (0x00000020U) -#define RSS_ATTESTATION_SERVICE_VERSION (1U) -#define RSS_ATTESTATION_SERVICE_HANDLE (0x40000103U) - /******** PSA_SP_MEASURED_BOOT ********/ -#define RSS_MEASURED_BOOT_SID (0x000000E0U) -#define RSS_MEASURED_BOOT_VERSION (1U) -#define RSS_MEASURED_BOOT_HANDLE (0x40000104U) +#define RSS_MEASURED_BOOT_HANDLE (0x40000110U) + +/******** PSA_SP_DELAGATED_ATTESTATION ********/ +#define RSS_DELEGATED_SERVICE_HANDLE (0x40000111U) #endif /* PSA_MANIFEST_SID_H */ diff --git a/include/lib/psci/psci_lib.h b/include/lib/psci/psci_lib.h index 1ac45adf7..3edc50b6c 100644 --- a/include/lib/psci/psci_lib.h +++ b/include/lib/psci/psci_lib.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -91,6 +91,9 @@ void psci_prepare_next_non_secure_ctx( entry_point_info_t *next_image_info); int psci_stop_other_cores(unsigned int wait_ms, void (*stop_func)(u_register_t mpidr)); +bool psci_is_last_on_cpu_safe(void); +void psci_pwrdown_cpu(unsigned int power_level); + #endif /* __ASSEMBLER__ */ #endif /* PSCI_LIB_H */ diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 1a39f24c7..cce91afe2 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,10 +37,16 @@ #define FUNCID_OEN_MASK U(0x3f) #define FUNCID_OEN_WIDTH U(6) +#define FUNCID_SVE_HINT_SHIFT U(16) +#define FUNCID_SVE_HINT_MASK U(1) +#define FUNCID_SVE_HINT_WIDTH U(1) + #define FUNCID_NUM_SHIFT U(0) #define FUNCID_NUM_MASK U(0xffff) #define FUNCID_NUM_WIDTH U(16) +#define FUNCID_MASK U(0xffffffff) + #define GET_SMC_NUM(id) (((id) >> FUNCID_NUM_SHIFT) & \ FUNCID_NUM_MASK) #define GET_SMC_TYPE(id) (((id) >> FUNCID_TYPE_SHIFT) & \ @@ -120,6 +126,12 @@ * 0 0 SMC_FROM_SECURE * 0 1 SMC_FROM_NON_SECURE * 1 1 SMC_FROM_REALM + * + * Bit 16 of flags records the caller's SMC + * SVE hint bit according to SMCCCv1.3. + * It can be consumed by dispatchers using + * is_sve_hint_set macro. + * */ #define SMC_FROM_SECURE (U(0) << 0) @@ -146,6 +158,9 @@ #define is_caller_secure(_f) (!is_caller_non_secure(_f)) #endif /* ENABLE_RME */ +#define is_sve_hint_set(_f) (((_f) & (FUNCID_SVE_HINT_MASK \ + << FUNCID_SVE_HINT_SHIFT)) != U(0)) + /* The macro below is used to identify a Standard Service SMC call */ #define is_std_svc_call(_fid) (GET_SMC_OEN(_fid) == OEN_STD_START) diff --git a/include/lib/xlat_tables/xlat_tables_compat.h b/include/lib/xlat_tables/xlat_tables_compat.h index 90768db5d..5f281957a 100644 --- a/include/lib/xlat_tables/xlat_tables_compat.h +++ b/include/lib/xlat_tables/xlat_tables_compat.h @@ -1,11 +1,16 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#ifndef XLAT_TABLES_COMPAT_H +#define XLAT_TABLES_COMPAT_H + #if XLAT_TABLES_LIB_V2 #include <lib/xlat_tables/xlat_tables_v2.h> #else #include <lib/xlat_tables/xlat_tables.h> #endif + +#endif /* XLAT_TABLES_COMPAT_H */ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index a8211bdc6..ab0e4ff2c 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -79,6 +79,7 @@ * - SCP TZC DRAM: If present, DRAM reserved for SCP use * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled * - REALM DRAM: Reserved for Realm world if RME is enabled + * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use * * RME enabled(64MB) RME not enabled(16MB) @@ -87,11 +88,16 @@ * | AP TZC (~28MB) | | AP TZC (~14MB) | * -------------------- ------------------- * | | | | - * | REALM (32MB) | | EL3 TZC (2MB) | - * -------------------- ------------------- - * | | | | - * | EL3 TZC (3MB) | | SCP TZC | - * -------------------- 0xFFFF_FFFF------------------- + * | REALM (RMM) | | EL3 TZC (2MB) | + * | (32MB - 4KB) | ------------------- + * -------------------- | | + * | | | SCP TZC | + * | TF-A <-> RMM | 0xFFFF_FFFF------------------- + * | SHARED (4KB) | + * -------------------- + * | | + * | EL3 TZC (3MB) | + * -------------------- * | L1 GPT + SCP TZC | * | (~1MB) | * 0xFFFF_FFFF -------------------- @@ -106,12 +112,17 @@ */ #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ -#define ARM_REALM_SIZE UL(0x02000000) /* 32MB */ + +/* 32MB - ARM_EL3_RMM_SHARED_SIZE */ +#define ARM_REALM_SIZE (UL(0x02000000) - \ + ARM_EL3_RMM_SHARED_SIZE) +#define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ #else #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ #define ARM_L1_GPT_SIZE UL(0) #define ARM_REALM_SIZE UL(0) +#define ARM_EL3_RMM_SHARED_SIZE UL(0) #endif /* ENABLE_RME */ #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ @@ -128,13 +139,20 @@ #define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ ARM_L1_GPT_SIZE - 1U) -#define ARM_REALM_BASE (ARM_DRAM1_BASE + \ - ARM_DRAM1_SIZE - \ - (ARM_SCP_TZC_DRAM1_SIZE + \ - ARM_EL3_TZC_DRAM1_SIZE + \ - ARM_REALM_SIZE + \ - ARM_L1_GPT_SIZE)) +#define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ + ARM_REALM_SIZE) + #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) + +#define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_L1_GPT_SIZE + \ + ARM_EL3_RMM_SHARED_SIZE + \ + ARM_EL3_TZC_DRAM1_SIZE)) + +#define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ + ARM_EL3_RMM_SHARED_SIZE - 1U) #endif /* ENABLE_RME */ #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ @@ -148,6 +166,7 @@ #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ (ARM_SCP_TZC_DRAM1_SIZE + \ ARM_EL3_TZC_DRAM1_SIZE + \ + ARM_EL3_RMM_SHARED_SIZE + \ ARM_REALM_SIZE + \ ARM_L1_GPT_SIZE)) #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ @@ -197,6 +216,7 @@ #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ ARM_TZC_DRAM1_SIZE) + #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ ARM_NS_DRAM1_SIZE - 1U) #ifdef PLAT_ARM_DRAM1_BASE @@ -290,9 +310,14 @@ MT_MEMORY | MT_RW | MT_SECURE) #if ENABLE_RME +/* + * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. + * Else we end up requiring more pagetables in BL2 for ROMLIB build. + */ #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ PLAT_ARM_RMM_BASE, \ - PLAT_ARM_RMM_SIZE, \ + (PLAT_ARM_RMM_SIZE + \ + ARM_EL3_RMM_SHARED_SIZE), \ MT_MEMORY | MT_RW | MT_REALM) @@ -301,6 +326,12 @@ ARM_L1_GPT_SIZE, \ MT_MEMORY | MT_RW | EL3_PAS) +#define ARM_MAP_EL3_RMM_SHARED_MEM \ + MAP_REGION_FLAT( \ + ARM_EL3_RMM_SHARED_BASE, \ + ARM_EL3_RMM_SHARED_SIZE, \ + MT_MEMORY | MT_RW | MT_REALM) + #endif /* ENABLE_RME */ /* @@ -520,9 +551,20 @@ * BL2 specific defines. ******************************************************************************/ #if BL2_AT_EL3 +#if ENABLE_PIE +/* + * As the BL31 image size appears to be increased when built with the ENABLE_PIE + * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. + */ +#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ + (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ + 0x3000) +#else /* Put BL2 towards the middle of the Trusted SRAM */ #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ - (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) + (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ + 0x2000) +#endif /* ENABLE_PIE */ #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) #else @@ -584,6 +626,8 @@ #if ENABLE_RME #define RMM_BASE (ARM_REALM_BASE) #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) +#define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) +#define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) #endif #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME diff --git a/include/plat/arm/common/arm_pas_def.h b/include/plat/arm/common/arm_pas_def.h index 4fee41b3f..c199302e8 100644 --- a/include/plat/arm/common/arm_pas_def.h +++ b/include/plat/arm/common/arm_pas_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -61,6 +61,10 @@ #define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE) #define ARM_PAS_2_SIZE (ARM_NS_DRAM1_SIZE) +/* Shared area between EL3 and RMM */ +#define ARM_PAS_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) +#define ARM_PAS_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) + /* Secure TZC region */ #define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE) #define ARM_PAS_3_SIZE (ARM_AP_TZC_DRAM1_SIZE) @@ -76,8 +80,13 @@ ARM_PAS_3_SIZE, \ GPT_GPI_SECURE) +/* + * REALM and Shared area share the same PAS, so consider them a single + * PAS region to configure in GPT. + */ #define ARM_PAS_REALM GPT_MAP_REGION_GRANULE(ARM_REALM_BASE, \ - ARM_REALM_SIZE, \ + (ARM_PAS_SHARED_SIZE + \ + ARM_REALM_SIZE), \ GPT_GPI_REALM) #define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \ diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h index 2eeed95f0..025d10efc 100644 --- a/include/plat/arm/common/arm_sip_svc.h +++ b/include/plat/arm/common/arm_sip_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019,2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019,2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,7 +26,7 @@ /* DEBUGFS_SMC_64 0xC2000030U */ /* - * Arm Ethos-N NPU SiP SMC function IDs + * Arm(R) Ethos(TM)-N NPU SiP SMC function IDs * 0xC2000050-0xC200005F * 0x82000050-0x8200005F */ diff --git a/include/plat/arm/common/fconf_arm_sp_getter.h b/include/plat/arm/common/fconf_arm_sp_getter.h index aa628dfd3..96ed96383 100644 --- a/include/plat/arm/common/fconf_arm_sp_getter.h +++ b/include/plat/arm/common/fconf_arm_sp_getter.h @@ -7,6 +7,7 @@ #ifndef FCONF_ARM_SP_GETTER_H #define FCONF_ARM_SP_GETTER_H +#include <common/tbbr/tbbr_img_def.h> #include <lib/fconf/fconf.h> #include <tools_share/uuid.h> diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h index fcdc31f8b..5b9a7ed9d 100644 --- a/include/plat/arm/common/fconf_ethosn_getter.h +++ b/include/plat/arm/common/fconf_ethosn_getter.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,27 +8,52 @@ #define FCONF_ETHOSN_GETTER_H #include <assert.h> +#include <stdbool.h> #include <lib/fconf/fconf.h> #define hw_config__ethosn_config_getter(prop) ethosn_config.prop -#define hw_config__ethosn_core_addr_getter(idx) __extension__ ({ \ - assert(idx < ethosn_config.num_cores); \ - ethosn_config.core[idx].addr; \ +#define hw_config__ethosn_device_getter(dev_idx) __extension__ ({ \ + assert(dev_idx < ethosn_config.num_devices); \ + ðosn_config.devices[dev_idx]; \ }) -#define ETHOSN_STATUS_DISABLED U(0) -#define ETHOSN_STATUS_ENABLED U(1) +#define ETHOSN_DEV_NUM_MAX U(2) +#define ETHOSN_DEV_CORE_NUM_MAX U(8) +#define ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX U(16) -#define ETHOSN_CORE_NUM_MAX U(64) +struct ethosn_allocator_t { + uint32_t stream_id; +}; + +struct ethosn_main_allocator_t { + struct ethosn_allocator_t firmware; + struct ethosn_allocator_t working_data; +}; + +struct ethosn_asset_allocator_t { + struct ethosn_allocator_t command_stream; + struct ethosn_allocator_t weight_data; + struct ethosn_allocator_t buffer_data; + struct ethosn_allocator_t intermediate_data; +}; struct ethosn_core_t { uint64_t addr; + struct ethosn_main_allocator_t main_allocator; }; -struct ethosn_config_t { +struct ethosn_device_t { + bool has_reserved_memory; uint32_t num_cores; - struct ethosn_core_t core[ETHOSN_CORE_NUM_MAX]; + struct ethosn_core_t cores[ETHOSN_DEV_CORE_NUM_MAX]; + uint32_t num_allocators; + struct ethosn_asset_allocator_t asset_allocators[ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX]; +}; + +struct ethosn_config_t { + uint32_t num_devices; + struct ethosn_device_t devices[ETHOSN_DEV_NUM_MAX]; }; int fconf_populate_arm_ethosn(uintptr_t config); diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 9618700a2..6c0d91d1f 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -57,7 +57,8 @@ typedef struct arm_tzc_regions_info { {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ PLAT_ARM_TZC_NS_DEV_ACCESS}, \ - {ARM_REALM_BASE, ARM_REALM_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + /* Realm and Shared area share the same PAS */ \ + {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ PLAT_ARM_TZC_NS_DEV_ACCESS}, \ {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ PLAT_ARM_TZC_NS_DEV_ACCESS} @@ -296,6 +297,7 @@ void plat_arm_interconnect_exit_coherency(void); void plat_arm_program_trusted_mailbox(uintptr_t address); bool plat_arm_bl1_fwu_needed(void); __dead2 void plat_arm_error_handler(int err); +__dead2 void plat_arm_system_reset(void); /* * Optional functions in ARM standard platforms diff --git a/include/plat/arm/css/common/css_pm.h b/include/plat/arm/css/common/css_pm.h index e5357f50b..84e6b38de 100644 --- a/include/plat/arm/css/common/css_pm.h +++ b/include/plat/arm/css/common/css_pm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,9 @@ #include <lib/psci/psci.h> +/* SGI used to trigger per-core power down request */ +#define CSS_CPU_PWR_DOWN_REQ_INTR ARM_IRQ_SEC_SGI_7 + /* Macros to read the CSS power domain state */ #define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] #define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] @@ -37,6 +40,9 @@ void __dead2 css_system_reset(void); void css_cpu_standby(plat_local_state_t cpu_state); void css_get_sys_suspend_power_state(psci_power_state_t *req_state); int css_node_hw_state(u_register_t mpidr, unsigned int power_level); +void css_setup_cpu_pwr_down_intr(void); +int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags, + void *handle, void *cookie); /* * This mapping array has to be exported by the platform. Each element at diff --git a/include/plat/common/plat_drtm.h b/include/plat/common/plat_drtm.h new file mode 100644 index 000000000..e96e71958 --- /dev/null +++ b/include/plat/common/plat_drtm.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DRTM_H +#define PLAT_DRTM_H + +#include <stdint.h> +#include <lib/xlat_tables/xlat_tables_compat.h> + +typedef struct { + uint8_t max_num_mem_prot_regions; + uint8_t dma_protection_support; +} plat_drtm_dma_prot_features_t; + +typedef struct { + bool tpm_based_hash_support; + uint32_t firmware_hash_algorithm; +} plat_drtm_tpm_features_t; + +typedef struct { + uint64_t region_address; + uint64_t region_size_type; +} __attribute__((packed)) drtm_mem_region_t; + +/* + * Memory region descriptor table structure as per DRTM beta0 section 3.13 + * Table 11 MEMORY_REGION_DESCRIPTOR_TABLE + */ +typedef struct { + uint16_t revision; + uint16_t reserved; + uint32_t num_regions; + drtm_mem_region_t region[]; +} __attribute__((packed)) drtm_memory_region_descriptor_table_t; + +/* platform specific address map functions */ +const mmap_region_t *plat_get_addr_mmap(void); + +/* platform-specific DMA protection functions */ +bool plat_has_non_host_platforms(void); +bool plat_has_unmanaged_dma_peripherals(void); +unsigned int plat_get_total_smmus(void); +void plat_enumerate_smmus(const uintptr_t **smmus_out, + size_t *smmu_count_out); +const plat_drtm_dma_prot_features_t *plat_drtm_get_dma_prot_features(void); +uint64_t plat_drtm_dma_prot_get_max_table_bytes(void); + +/* platform-specific TPM functions */ +const plat_drtm_tpm_features_t *plat_drtm_get_tpm_features(void); + +/* + * TODO: Implement these functions as per the platform use case, + * as of now none of the platform uses these functions + */ +uint64_t plat_drtm_get_min_size_normal_world_dce(void); +uint64_t plat_drtm_get_tcb_hash_table_size(void); +uint64_t plat_drtm_get_imp_def_dlme_region_size(void); +uint64_t plat_drtm_get_tcb_hash_features(void); + +/* DRTM error handling functions */ +int plat_set_drtm_error(uint64_t error_code); +int plat_get_drtm_error(uint64_t *error_code); + +/* + * Platform-specific function to ensure passed region lies within + * Non-Secure region of DRAM + */ +int plat_drtm_validate_ns_region(uintptr_t region_start, + size_t region_size); + +#endif /* PLAT_DRTM_H */ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index b62a63158..8407bbda8 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,10 +13,16 @@ #if defined(SPD_spmd) #include <services/spm_core_manifest.h> #endif -#if TRNG_SUPPORT -#include "plat_trng.h" +#if ENABLE_RME +#include <services/rmm_core_manifest.h> #endif #include <drivers/fwu/fwu_metadata.h> +#if TRNG_SUPPORT +#include "plat_trng.h" +#endif /* TRNG_SUPPORT */ +#if DRTM_SUPPORT +#include "plat_drtm.h" +#endif /* DRTM_SUPPORT */ /******************************************************************************* * Forward declarations @@ -101,6 +107,8 @@ int plat_ic_has_interrupt_type(unsigned int type); void plat_ic_set_interrupt_type(unsigned int id, unsigned int type); void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority); void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target); +void plat_ic_raise_ns_sgi(int sgi_num, u_register_t target); +void plat_ic_raise_s_el1_sgi(int sgi_num, u_register_t target); void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, u_register_t mpidr); void plat_ic_set_interrupt_pending(unsigned int id); @@ -113,11 +121,14 @@ unsigned int plat_ic_get_interrupt_id(unsigned int raw); ******************************************************************************/ uintptr_t plat_get_my_stack(void); void plat_report_exception(unsigned int exception_type); +void plat_report_prefetch_abort(unsigned int fault_address); +void plat_report_data_abort(unsigned int fault_address); int plat_crash_console_init(void); int plat_crash_console_putc(int c); void plat_crash_console_flush(void); void plat_error_handler(int err) __dead2; void plat_panic_handler(void) __dead2; +void plat_system_reset(void) __dead2; const char *plat_log_get_prefix(unsigned int log_level); void bl2_plat_preload_setup(void); int plat_try_next_boot_source(void); @@ -305,10 +316,14 @@ plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, /******************************************************************************* * Mandatory BL31 functions when ENABLE_RME=1 ******************************************************************************/ -int plat_get_cca_attest_token(uintptr_t buf, size_t *len, - uintptr_t hash, size_t hash_size); -int plat_get_cca_realm_attest_key(uintptr_t buf, size_t *len, - unsigned int type); +#if ENABLE_RME +int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len, + uintptr_t hash, size_t hash_size); +int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len, + unsigned int type); +size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared); +int plat_rmmd_load_manifest(rmm_manifest_t *manifest); +#endif /******************************************************************************* * Optional BL31 functions (may be overridden) @@ -329,6 +344,8 @@ int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr); int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr); int plat_set_nv_ctr2(void *cookie, const struct auth_img_desc_s *img_desc, unsigned int nv_ctr); +int plat_convert_pk(void *full_pk_ptr, unsigned int full_pk_len, + void **hashed_pk_ptr, unsigned int *hash_pk_len); int get_mbedtls_heap_helper(void **heap_addr, size_t *heap_size); int plat_get_enc_key_info(enum fw_enc_status_t fw_enc_status, uint8_t *key, size_t *key_len, unsigned int *flags, diff --git a/include/plat/marvell/armada/a8k/common/plat_marvell.h b/include/plat/marvell/armada/a8k/common/plat_marvell.h index 5d805a7f1..bec21a0dc 100644 --- a/include/plat/marvell/armada/a8k/common/plat_marvell.h +++ b/include/plat/marvell/armada/a8k/common/plat_marvell.h @@ -10,6 +10,7 @@ #include <stdint.h> +#include <common/bl_common.h> #include <lib/cassert.h> #include <lib/el3_runtime/cpu_data.h> #include <lib/utils.h> diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h new file mode 100644 index 000000000..69b314f08 --- /dev/null +++ b/include/services/drtm_svc.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * DRTM service + * + * Authors: + * Lucian Paul-Trifu <lucian.paultrifu@gmail.com> + * Brian Nezvadovitz <brinez@microsoft.com> 2021-02-01 + * + */ + +#ifndef ARM_DRTM_SVC_H +#define ARM_DRTM_SVC_H + +/* + * SMC function IDs for DRTM Service + * Upper word bits set: Fast call, SMC64, Standard Secure Svc. Call (OEN = 4) + */ +#define DRTM_FID(func_num) \ + ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + (SMC_64 << FUNCID_CC_SHIFT) | \ + (OEN_STD_START << FUNCID_OEN_SHIFT) | \ + ((func_num) << FUNCID_NUM_SHIFT)) + +#define DRTM_FNUM_SVC_VERSION U(0x110) +#define DRTM_FNUM_SVC_FEATURES U(0x111) +#define DRTM_FNUM_SVC_UNPROTECT_MEM U(0x113) +#define DRTM_FNUM_SVC_DYNAMIC_LAUNCH U(0x114) +#define DRTM_FNUM_SVC_CLOSE_LOCALITY U(0x115) +#define DRTM_FNUM_SVC_GET_ERROR U(0x116) +#define DRTM_FNUM_SVC_SET_ERROR U(0x117) +#define DRTM_FNUM_SVC_SET_TCB_HASH U(0x118) +#define DRTM_FNUM_SVC_LOCK_TCB_HASH U(0x119) + +#define ARM_DRTM_SVC_VERSION DRTM_FID(DRTM_FNUM_SVC_VERSION) +#define ARM_DRTM_SVC_FEATURES DRTM_FID(DRTM_FNUM_SVC_FEATURES) +#define ARM_DRTM_SVC_UNPROTECT_MEM DRTM_FID(DRTM_FNUM_SVC_UNPROTECT_MEM) +#define ARM_DRTM_SVC_DYNAMIC_LAUNCH DRTM_FID(DRTM_FNUM_SVC_DYNAMIC_LAUNCH) +#define ARM_DRTM_SVC_CLOSE_LOCALITY DRTM_FID(DRTM_FNUM_SVC_CLOSE_LOCALITY) +#define ARM_DRTM_SVC_GET_ERROR DRTM_FID(DRTM_FNUM_SVC_GET_ERROR) +#define ARM_DRTM_SVC_SET_ERROR DRTM_FID(DRTM_FNUM_SVC_SET_ERROR) +#define ARM_DRTM_SVC_SET_TCB_HASH DRTM_FID(DRTM_FNUM_SVC_SET_TCB_HASH) +#define ARM_DRTM_SVC_LOCK_TCB_HASH DRTM_FID(DRTM_FNUM_SVC_LOCK_TCB_HASH) + +#define ARM_DRTM_FEATURES_TPM U(0x1) +#define ARM_DRTM_FEATURES_MEM_REQ U(0x2) +#define ARM_DRTM_FEATURES_DMA_PROT U(0x3) +#define ARM_DRTM_FEATURES_BOOT_PE_ID U(0x4) +#define ARM_DRTM_FEATURES_TCB_HASHES U(0x5) + +#define is_drtm_fid(_fid) \ + (((_fid) >= ARM_DRTM_SVC_VERSION) && ((_fid) <= ARM_DRTM_SVC_LOCK_TCB_HASH)) + +/* ARM DRTM Service Calls version numbers */ +#define ARM_DRTM_VERSION_MAJOR U(0) +#define ARM_DRTM_VERSION_MAJOR_SHIFT 16 +#define ARM_DRTM_VERSION_MAJOR_MASK U(0x7FFF) +#define ARM_DRTM_VERSION_MINOR U(1) +#define ARM_DRTM_VERSION_MINOR_SHIFT 0 +#define ARM_DRTM_VERSION_MINOR_MASK U(0xFFFF) + +#define ARM_DRTM_VERSION \ + ((((ARM_DRTM_VERSION_MAJOR) & ARM_DRTM_VERSION_MAJOR_MASK) << \ + ARM_DRTM_VERSION_MAJOR_SHIFT) \ + | (((ARM_DRTM_VERSION_MINOR) & ARM_DRTM_VERSION_MINOR_MASK) << \ + ARM_DRTM_VERSION_MINOR_SHIFT)) + +#define ARM_DRTM_FUNC_SHIFT U(63) +#define ARM_DRTM_FUNC_MASK ULL(0x1) +#define ARM_DRTM_FUNC_ID U(0x0) +#define ARM_DRTM_FEAT_ID U(0x1) +#define ARM_DRTM_FEAT_ID_MASK ULL(0xff) + +/* + * Definitions for DRTM features as per DRTM beta0 section 3.3, + * Table 6 DRTM_FEATURES + */ +#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT U(33) +#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK ULL(0xF) +#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT ULL(0x1) + +#define ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT U(32) +#define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK ULL(0x1) +#define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED ULL(0x0) +#define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED ULL(0x1) + +#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT U(0) +#define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK ULL(0xFFFFFFFF) +#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256 ULL(0xB) +#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384 ULL(0xC) +#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512 ULL(0xD) + +#define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT U(32) +#define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK ULL(0xFFFFFFFF) + +#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT U(0) +#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK ULL(0xFFFFFFFF) + +#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT U(8) +#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xF) + +#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT U(0) +#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK ULL(0xFF) +#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE ULL(0x1) +#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_REGION ULL(0x2) + +#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT U(0) +#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK ULL(0xFF) + +#define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val) \ + do { \ + reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \ + << ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)) | (((val) & \ + ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK) << \ + ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)); \ + } while (false) + +#define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val) \ + do { \ + reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK \ + << ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)) | (((val) & \ + ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK) << \ + ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)); \ + } while (false) + +#define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val) \ + do { \ + reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK \ + << ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)) | (((val) & \ + ARM_DRTM_TPM_FEATURES_FW_HASH_MASK) << \ + ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)); \ + } while (false) + +#define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val) \ + do { \ + reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK \ + << ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)) | (((val) & \ + ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK) << \ + ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)); \ + } while (false) + +#define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK << \ + ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)) | \ + (((val) & ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK) \ + << ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)); \ + } while (false) + +#define ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK << \ + ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)) | \ + (((val) & ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK) \ + << ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)); \ + } while (false) + +#define ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK << \ + ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)) | \ + (((val) & ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK) \ + << ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)); \ + } while (false) + +#define ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK << \ + ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)) | \ + (((val) & \ + ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK) << \ + ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)); \ + } while (false) + +/* Definitions for DRTM address map */ +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT U(55) +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK ULL(0x3) +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC ULL(0) +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WC ULL(1) +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WT ULL(2) +#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WB ULL(3) + +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT U(52) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK ULL(0x7) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL ULL(0) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR ULL(1) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE ULL(2) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NV ULL(3) +#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_RSVD ULL(4) + +#define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT U(0) +#define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK ULL(0xFFFFFFFFFFFFF) + +#define ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK << \ + ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)) | \ + (((val) & \ + ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK) << \ + ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)); \ + } while (false) + +#define ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK << \ + ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)) | \ + (((val) & ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK) \ + << ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)); \ + } while (false) + +#define ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(reg, val) \ + do { \ + reg = (((reg) & \ + ~(ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK << \ + ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)) | \ + (((val) & ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK) \ + << ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)); \ + } while (false) + +/* Initialization routine for the DRTM service */ +int drtm_setup(void); + +/* Handler to be called to handle DRTM SMC calls */ +uint64_t drtm_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); + +#endif /* ARM_DRTM_SVC_H */ diff --git a/include/services/rmm_core_manifest.h b/include/services/rmm_core_manifest.h new file mode 100644 index 000000000..2f2585860 --- /dev/null +++ b/include/services/rmm_core_manifest.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RMM_CORE_MANIFEST_H +#define RMM_CORE_MANIFEST_H + +#include <assert.h> +#include <stddef.h> +#include <stdint.h> + +#include <lib/cassert.h> + +#define RMMD_MANIFEST_VERSION_MAJOR U(0) +#define RMMD_MANIFEST_VERSION_MINOR U(1) + +/* + * Manifest version encoding: + * - Bit[31] RES0 + * - Bits [30:16] Major version + * - Bits [15:0] Minor version + */ +#define _RMMD_MANIFEST_VERSION(_major, _minor) \ + ((((_major) & 0x7FFF) << 16) | ((_minor) & 0xFFFF)) + +#define RMMD_MANIFEST_VERSION _RMMD_MANIFEST_VERSION( \ + RMMD_MANIFEST_VERSION_MAJOR, \ + RMMD_MANIFEST_VERSION_MINOR) + +#define RMMD_GET_MANIFEST_VERSION_MAJOR(_version) \ + ((_version >> 16) & 0x7FFF) + +#define RMMD_GET_MANIFEST_VERSION_MINOR(_version) \ + (_version & 0xFFFF) + +/* Boot manifest core structure as per v0.1 */ +typedef struct rmm_manifest { + uint32_t version; /* Manifest version */ + uintptr_t plat_data; /* Manifest platform data */ +} rmm_manifest_t; + +CASSERT(offsetof(rmm_manifest_t, version) == 0, + rmm_manifest_t_version_unaligned); +CASSERT(offsetof(rmm_manifest_t, plat_data) == 8, + rmm_manifest_t_plat_data_unaligned); + +#endif /* RMM_CORE_MANIFEST_H */ diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h index 2fbdddd43..de7181c85 100644 --- a/include/services/rmmd_svc.h +++ b/include/services/rmmd_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,17 +10,18 @@ #include <lib/smccc.h> #include <lib/utils_def.h> -/* Construct RMM fastcall std FID from function number */ -#define RMM_FID(smc_cc, func_num) \ - ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ - ((smc_cc) << FUNCID_CC_SHIFT) | \ - (OEN_STD_START << FUNCID_OEN_SHIFT) | \ - ((func_num) << FUNCID_NUM_SHIFT)) - -/* The macros below are used to identify RMI calls from the SMC function ID */ +/* STD calls FNUM Min/Max ranges */ #define RMI_FNUM_MIN_VALUE U(0x150) #define RMI_FNUM_MAX_VALUE U(0x18F) +/* Construct RMI fastcall std FID from offset */ +#define SMC64_RMI_FID(_offset) \ + ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + (SMC_64 << FUNCID_CC_SHIFT) | \ + (OEN_STD_START << FUNCID_OEN_SHIFT) | \ + (((RMI_FNUM_MIN_VALUE + (_offset)) & FUNCID_NUM_MASK) \ + << FUNCID_NUM_SHIFT)) + #define is_rmi_fid(fid) __extension__ ({ \ __typeof__(fid) _fid = (fid); \ ((GET_SMC_NUM(_fid) >= RMI_FNUM_MIN_VALUE) && \ @@ -31,15 +32,25 @@ ((_fid & 0x00FE0000) == 0U)); }) /* - * RMI_FNUM_REQ_COMPLETE is the only function in the RMI rnage that originates + * RMI_FNUM_REQ_COMPLETE is the only function in the RMI range that originates * from the Realm world and is handled by the RMMD. The RMI functions are * always invoked by the Normal world, forwarded by RMMD and handled by the - * RMM + * RMM. */ -#define RMI_FNUM_REQ_COMPLETE U(0x18F) -#define RMMD_RMI_REQ_COMPLETE RMM_FID(SMC_64, RMI_FNUM_REQ_COMPLETE) + /* 0x18F */ +#define RMM_RMI_REQ_COMPLETE SMC64_RMI_FID(U(0x3F)) + +/* RMM_BOOT_COMPLETE arg0 error codes */ +#define E_RMM_BOOT_SUCCESS (0) +#define E_RMM_BOOT_UNKNOWN (-1) +#define E_RMM_BOOT_VERSION_MISMATCH (-2) +#define E_RMM_BOOT_CPUS_OUT_OF_RANGE (-3) +#define E_RMM_BOOT_CPU_ID_OUT_OF_RANGE (-4) +#define E_RMM_BOOT_INVALID_SHARED_BUFFER (-5) +#define E_RMM_BOOT_MANIFEST_VERSION_NOT_SUPPORTED (-6) +#define E_RMM_BOOT_MANIFEST_DATA_ERROR (-7) -/* The SMC in the range 0x8400 0190 - 0x8400 01AF are reserved for RSIs.*/ +/* The SMC in the range 0x8400 0191 - 0x8400 01AF are reserved for RSIs.*/ /* * EL3 - RMM SMCs used for requesting RMMD services. These SMCs originate in Realm @@ -50,6 +61,14 @@ #define RMMD_EL3_FNUM_MIN_VALUE U(0x1B0) #define RMMD_EL3_FNUM_MAX_VALUE U(0x1CF) +/* Construct RMM_EL3 fastcall std FID from offset */ +#define SMC64_RMMD_EL3_FID(_offset) \ + ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + (SMC_64 << FUNCID_CC_SHIFT) | \ + (OEN_STD_START << FUNCID_OEN_SHIFT) | \ + (((RMMD_EL3_FNUM_MIN_VALUE + (_offset)) & FUNCID_NUM_MASK) \ + << FUNCID_NUM_SHIFT)) + /* The macros below are used to identify GTSI calls from the SMC function ID */ #define is_rmmd_el3_fid(fid) __extension__ ({ \ __typeof__(fid) _fid = (fid); \ @@ -60,37 +79,17 @@ (GET_SMC_OEN(_fid) == OEN_STD_START) && \ ((_fid & 0x00FE0000) == 0U)); }) -/* RMMD Service Function NUmbers */ -#define GTSI_DELEGATE U(0x1B0) -#define GTSI_UNDELEGATE U(0x1B1) -#define ATTEST_GET_REALM_KEY U(0x1B2) -#define ATTEST_GET_PLAT_TOKEN U(0x1B3) - -#define RMMD_GTSI_DELEGATE RMM_FID(SMC_64, GTSI_DELEGATE) -#define RMMD_GTSI_UNDELEGATE RMM_FID(SMC_64, GTSI_UNDELEGATE) + /* 0x1B0 - 0x1B1 */ +#define RMM_GTSI_DELEGATE SMC64_RMMD_EL3_FID(U(0)) +#define RMM_GTSI_UNDELEGATE SMC64_RMMD_EL3_FID(U(1)) /* Return error codes from RMM-EL3 SMCs */ -#define RMMD_OK 0 -#define RMMD_ERR_BAD_ADDR -2 -#define RMMD_ERR_BAD_PAS -3 -#define RMMD_ERR_NOMEM -4 -#define RMMD_ERR_INVAL -5 -#define RMMD_ERR_UNK -6 - -/* - * Retrieve Platform token from EL3. - * The arguments to this SMC are : - * arg0 - Function ID. - * arg1 - Platform attestation token buffer Physical address. (The challenge - * object is passed in this buffer.) - * arg2 - Platform attestation token buffer size (in bytes). - * arg3 - Challenge object size (in bytes). It has be one of the defined SHA hash - * sizes. - * The return arguments are : - * ret0 - Status / error. - * ret1 - Size of the platform token if successful. - */ -#define RMMD_ATTEST_GET_PLAT_TOKEN RMM_FID(SMC_64, ATTEST_GET_PLAT_TOKEN) +#define E_RMM_OK 0 +#define E_RMM_UNK -1 +#define E_RMM_BAD_ADDR -2 +#define E_RMM_BAD_PAS -3 +#define E_RMM_NOMEM -4 +#define E_RMM_INVAL -5 /* Acceptable SHA sizes for Challenge object */ #define SHA256_DIGEST_SIZE 32U @@ -110,11 +109,58 @@ * ret0 - Status / error. * ret1 - Size of the realm attestation key if successful. */ -#define RMMD_ATTEST_GET_REALM_KEY RMM_FID(SMC_64, ATTEST_GET_REALM_KEY) + /* 0x1B2 */ +#define RMM_ATTEST_GET_REALM_KEY SMC64_RMMD_EL3_FID(U(2)) + +/* + * Retrieve Platform token from EL3. + * The arguments to this SMC are : + * arg0 - Function ID. + * arg1 - Platform attestation token buffer Physical address. (The challenge + * object is passed in this buffer.) + * arg2 - Platform attestation token buffer size (in bytes). + * arg3 - Challenge object size (in bytes). It has to be one of the defined + * SHA hash sizes. + * The return arguments are : + * ret0 - Status / error. + * ret1 - Size of the platform token if successful. + */ + /* 0x1B3 */ +#define RMM_ATTEST_GET_PLAT_TOKEN SMC64_RMMD_EL3_FID(U(3)) /* ECC Curve types for attest key generation */ #define ATTEST_KEY_CURVE_ECC_SECP384R1 0 +/* + * RMM_BOOT_COMPLETE originates on RMM when the boot finishes (either cold + * or warm boot). This is handled by the RMM-EL3 interface SMC handler. + * + * RMM_BOOT_COMPLETE FID is located at the end of the available range. + */ + /* 0x1CF */ +#define RMM_BOOT_COMPLETE SMC64_RMMD_EL3_FID(U(0x1F)) + +/* + * The major version number of the RMM Boot Interface implementation. + * Increase this whenever the semantics of the boot arguments change making it + * backwards incompatible. + */ +#define RMM_EL3_IFC_VERSION_MAJOR (U(0)) + +/* + * The minor version number of the RMM Boot Interface implementation. + * Increase this when a bug is fixed, or a feature is added without + * breaking compatibility. + */ +#define RMM_EL3_IFC_VERSION_MINOR (U(1)) + +#define RMM_EL3_INTERFACE_VERSION \ + (((RMM_EL3_IFC_VERSION_MAJOR << 16) & 0x7FFFF) | \ + RMM_EL3_IFC_VERSION_MINOR) + +#define RMM_EL3_IFC_VERSION_GET_MAJOR(_version) (((_version) >> 16) \ + & 0x7FFF) +#define RMM_EL3_IFC_VERSION_GET_MAJOR_MINOR(_version) ((_version) & 0xFFFF) #ifndef __ASSEMBLER__ #include <stdint.h> diff --git a/include/services/sdei.h b/include/services/sdei.h index 063ed6f28..c12a182f0 100644 --- a/include/services/sdei.h +++ b/include/services/sdei.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -137,4 +137,7 @@ void sdei_init(void); /* Public API to dispatch an event to Normal world */ int sdei_dispatch_event(int ev_num); +/* Public API to check how many SDEI events are registered. */ +int sdei_get_registered_event_count(void); + #endif /* SDEI_H */ diff --git a/include/services/trng_svc.h b/include/services/trng_svc.h index ed4d557ca..92417c22d 100644 --- a/include/services/trng_svc.h +++ b/include/services/trng_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ #define ARM_TRNG_FEATURES U(0x84000051) #define ARM_TRNG_GET_UUID U(0x84000052) #define ARM_TRNG_RND32 U(0x84000053) -#define ARM_TRNG_RND64 U(0xc4000053) +#define ARM_TRNG_RND64 U(0xC4000053) /* TRNG version numbers */ #define TRNG_VERSION_MAJOR (0x1) @@ -30,19 +30,17 @@ #define TRNG_E_NO_ENTROPY (-3) #define TRNG_E_NOT_IMPLEMENTED (-4) -#if TRNG_SUPPORT +/* TRNG Entropy Bit Numbers */ +#define TRNG_RND32_ENTROPY_MAXBITS (96U) +#define TRNG_RND64_ENTROPY_MAXBITS (192U) + +/* Public API to perform the initial TRNG entropy setup */ void trng_setup(void); + +/* Public API to verify function id is part of TRNG */ bool is_trng_fid(uint32_t smc_fid); -#else -static inline void trng_setup(void) -{ -} - -static inline bool is_trng_fid(uint32_t smc_fid) -{ - return false; -} -#endif + +/* Handler to be called to handle TRNG smc calls */ uintptr_t trng_smc_handler( uint32_t smc_fid, u_register_t x1, diff --git a/include/services/trp/platform_trp.h b/include/services/trp/platform_trp.h index b34da8512..1c963c851 100644 --- a/include/services/trp/platform_trp.h +++ b/include/services/trp/platform_trp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,9 +7,11 @@ #ifndef PLATFORM_TRP_H #define PLATFORM_TRP_H +#include <services/rmm_core_manifest.h> + /******************************************************************************* * Mandatory TRP functions (only if platform contains a TRP) ******************************************************************************/ -void trp_early_platform_setup(void); +void trp_early_platform_setup(rmm_manifest_t *manifest); #endif /* PLATFORM_TRP_H */ diff --git a/include/services/trp/trp_helpers.h b/include/services/trp/trp_helpers.h new file mode 100644 index 000000000..8e786e21b --- /dev/null +++ b/include/services/trp/trp_helpers.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TRP_HELPERS_H +#define TRP_HELPERS_H + +/* Definitions to help the assembler access the SMC/ERET args structure */ +#define TRP_ARGS_SIZE TRP_ARGS_END +#define TRP_ARG0 0x0 +#define TRP_ARG1 0x8 +#define TRP_ARG2 0x10 +#define TRP_ARG3 0x18 +#define TRP_ARG4 0x20 +#define TRP_ARG5 0x28 +#define TRP_ARG6 0x30 +#define TRP_ARG7 0x38 +#define TRP_ARGS_END 0x40 + +#ifndef __ASSEMBLER__ + +#include <platform_def.h> + +/* Data structure to hold SMC arguments */ +typedef struct trp_args { + uint64_t regs[TRP_ARGS_END >> 3]; +} __aligned(CACHE_WRITEBACK_GRANULE) trp_args_t; + +trp_args_t *set_smc_args(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); + +__dead2 void trp_boot_abort(uint64_t err); + +#endif /* __ASSEMBLER __ */ +#endif /* TRP_HELPERS_H */ diff --git a/include/tools_share/cca_oid.h b/include/tools_share/cca_oid.h new file mode 100644 index 000000000..e586b8c64 --- /dev/null +++ b/include/tools_share/cca_oid.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CCA_OID_H +#define CCA_OID_H + +/* Reuse the Object IDs defined by TBBR for certificate extensions. */ +#include "tbbr_oid.h" + +/* + * Assign arbitrary Object ID values that do not conflict with any of the + * TBBR reserved OIDs. + */ +/* Platform root-of-trust public key */ +#define PROT_PK_OID "1.3.6.1.4.1.4128.2100.1102" +/* Secure World root-of-trust public key */ +#define SWD_ROT_PK_OID "1.3.6.1.4.1.4128.2100.1103" +/* Core Secure World public key */ +#define CORE_SWD_PK_OID "1.3.6.1.4.1.4128.2100.1104" +/* Platform public key */ +#define PLAT_PK_OID "1.3.6.1.4.1.4128.2100.1105" +/* Realm Monitor Manager (RMM) Hash */ +#define RMM_HASH_OID "1.3.6.1.4.1.4128.2100.1106" + +#endif /* CCA_OID_H */ diff --git a/include/tools_share/firmware_image_package.h b/include/tools_share/firmware_image_package.h index bd5b14b9d..b73eec79c 100644 --- a/include/tools_share/firmware_image_package.h +++ b/include/tools_share/firmware_image_package.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,12 @@ {{0x4f, 0x51, 0x1d, 0x11}, {0x2b, 0xe5}, {0x4e, 0x49}, 0xb4, 0xc5, {0x83, 0xc2, 0xf7, 0x15, 0x84, 0x0a} } #define UUID_TRUSTED_FWU_CERT \ {{0x71, 0x40, 0x8a, 0xb2}, {0x18, 0xd6}, {0x87, 0x4c}, 0x8b, 0x2e, {0xc6, 0xdc, 0xcd, 0x50, 0xf0, 0x96} } +#define UUID_CCA_CONTENT_CERT \ + {{0x36, 0xd8, 0x3d, 0x85}, {0x76, 0x1d}, {0x4d, 0xaf}, 0x96, 0xf1, {0xcd, 0x99, 0xd6, 0x56, 0x9b, 0x00} } +#define UUID_CORE_SWD_KEY_CERT \ + {{0x52, 0x22, 0x2d, 0x31}, {0x82, 0x0f}, {0x49, 0x4d}, 0x8b, 0xbc, {0xea, 0x68, 0x25, 0xd3, 0xc3, 0x5a} } +#define UUID_PLAT_KEY_CERT \ + {{0xd4, 0x3c, 0xd9, 0x02}, {0x5b, 0x9f}, {0x41, 0x2e}, 0x8a, 0xc6, {0x92, 0xb6, 0xd1, 0x8b, 0xe6, 0x0d} } #define UUID_TRUSTED_BOOT_FIRMWARE_BL2 \ {{0x5f, 0xf9, 0xec, 0x0b}, {0x4d, 0x22}, {0x3e, 0x4d}, 0xa5, 0x44, {0xc3, 0x9d, 0x81, 0xc7, 0x3f, 0x0a} } #define UUID_SCP_FIRMWARE_SCP_BL2 \ diff --git a/lib/aarch64/cache_helpers.S b/lib/aarch64/cache_helpers.S index 6faf545a1..314ed6efd 100644 --- a/lib/aarch64/cache_helpers.S +++ b/lib/aarch64/cache_helpers.S @@ -36,12 +36,26 @@ loop_\op: exit_loop_\op: ret .endm + +.macro check_plat_can_cmo +#if CONDITIONAL_CMO + mov x3, x30 + mov x2, x0 + bl plat_can_cmo + mov x30, x3 + cbnz x0, 1f + ret +1: + mov x0, x2 +#endif +.endm /* ------------------------------------------ * Clean+Invalidate from base address till * size. 'x0' = addr, 'x1' = size * ------------------------------------------ */ func flush_dcache_range + check_plat_can_cmo do_dcache_maintenance_by_mva civac endfunc flush_dcache_range @@ -51,6 +65,7 @@ endfunc flush_dcache_range * ------------------------------------------ */ func clean_dcache_range + check_plat_can_cmo do_dcache_maintenance_by_mva cvac endfunc clean_dcache_range @@ -60,6 +75,7 @@ endfunc clean_dcache_range * ------------------------------------------ */ func inv_dcache_range + check_plat_can_cmo do_dcache_maintenance_by_mva ivac endfunc inv_dcache_range @@ -79,6 +95,7 @@ endfunc inv_dcache_range func flush_dcache_to_popa_range /* Exit early if size is zero */ cbz x1, exit_loop_dc_cipapa + check_plat_can_cmo dcache_line_size x2, x3 sub x3, x2, #1 bic x0, x0, x3 @@ -200,11 +217,13 @@ dcsw_loop_table: func dcsw_op_louis + check_plat_can_cmo dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT endfunc dcsw_op_louis func dcsw_op_all + check_plat_can_cmo dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT endfunc dcsw_op_all @@ -228,6 +247,7 @@ endfunc dcsw_op_all * --------------------------------------------------------------- */ func dcsw_op_level1 + check_plat_can_cmo dcsw_op_level #(1 << LEVEL_SHIFT) endfunc dcsw_op_level1 @@ -239,6 +259,7 @@ endfunc dcsw_op_level1 * --------------------------------------------------------------- */ func dcsw_op_level2 + check_plat_can_cmo dcsw_op_level #(2 << LEVEL_SHIFT) endfunc dcsw_op_level2 @@ -250,5 +271,6 @@ endfunc dcsw_op_level2 * --------------------------------------------------------------- */ func dcsw_op_level3 + check_plat_can_cmo dcsw_op_level #(3 << LEVEL_SHIFT) endfunc dcsw_op_level3 diff --git a/lib/compiler-rt/builtins/arm/aeabi_ldivmod.S b/lib/compiler-rt/builtins/arm/aeabi_ldivmod.S index 038ae5d72..d0d06be6f 100644 --- a/lib/compiler-rt/builtins/arm/aeabi_ldivmod.S +++ b/lib/compiler-rt/builtins/arm/aeabi_ldivmod.S @@ -1,9 +1,8 @@ //===-- aeabi_ldivmod.S - EABI ldivmod implementation ---------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/compiler-rt/builtins/arm/aeabi_memcpy.S b/lib/compiler-rt/builtins/arm/aeabi_memcpy.S new file mode 100644 index 000000000..93e1b05d5 --- /dev/null +++ b/lib/compiler-rt/builtins/arm/aeabi_memcpy.S @@ -0,0 +1,29 @@ +//===-- aeabi_memcpy.S - EABI memcpy implementation -----------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "../assembly.h" + +// void __aeabi_memcpy(void *dest, void *src, size_t n) { memcpy(dest, src, n); } + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_memcpy) +#ifdef USE_THUMB_1 + push {r7, lr} + bl memcpy + pop {r7, pc} +#else + b memcpy +#endif +END_COMPILERRT_FUNCTION(__aeabi_memcpy) + +DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memcpy4, __aeabi_memcpy) +DEFINE_AEABI_FUNCTION_ALIAS(__aeabi_memcpy8, __aeabi_memcpy) + +NO_EXEC_STACK_DIRECTIVE + diff --git a/lib/compiler-rt/builtins/arm/aeabi_uldivmod.S b/lib/compiler-rt/builtins/arm/aeabi_uldivmod.S index be343b6bc..4fc97704d 100644 --- a/lib/compiler-rt/builtins/arm/aeabi_uldivmod.S +++ b/lib/compiler-rt/builtins/arm/aeabi_uldivmod.S @@ -1,9 +1,8 @@ //===-- aeabi_uldivmod.S - EABI uldivmod implementation -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// diff --git a/lib/compiler-rt/builtins/assembly.h b/lib/compiler-rt/builtins/assembly.h index 29d9f8844..69a3d8620 100644 --- a/lib/compiler-rt/builtins/assembly.h +++ b/lib/compiler-rt/builtins/assembly.h @@ -1,23 +1,27 @@ -/* ===-- assembly.h - compiler-rt assembler support macros -----------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file defines macros for use in compiler-rt assembler source. - * This file is not part of the interface of this library. - * - * ===----------------------------------------------------------------------=== - */ +//===-- assembly.h - compiler-rt assembler support macros -----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines macros for use in compiler-rt assembler source. +// This file is not part of the interface of this library. +// +//===----------------------------------------------------------------------===// #ifndef COMPILERRT_ASSEMBLY_H #define COMPILERRT_ASSEMBLY_H -#if defined(__POWERPC__) || defined(__powerpc__) || defined(__ppc__) -#define SEPARATOR @ +#if defined(__linux__) && defined(__CET__) +#if __has_include(<cet.h>) +#include <cet.h> +#endif +#endif + +#if defined(__APPLE__) && defined(__aarch64__) +#define SEPARATOR %% #else #define SEPARATOR ; #endif @@ -37,14 +41,15 @@ #define HIDDEN(name) .hidden name #define LOCAL_LABEL(name) .L_##name #define FILE_LEVEL_DIRECTIVE -#if defined(__arm__) +#if defined(__arm__) || defined(__aarch64__) #define SYMBOL_IS_FUNC(name) .type name,%function #else #define SYMBOL_IS_FUNC(name) .type name,@function #endif #define CONST_SECTION .section .rodata -#if defined(__GNU__) || defined(__ANDROID__) || defined(__FreeBSD__) +#if defined(__GNU__) || defined(__FreeBSD__) || defined(__Fuchsia__) || \ + defined(__linux__) #define NO_EXEC_STACK_DIRECTIVE .section .note.GNU-stack,"",%progbits #else #define NO_EXEC_STACK_DIRECTIVE @@ -66,11 +71,103 @@ #endif +#if defined(__arm__) || defined(__aarch64__) +#define FUNC_ALIGN \ + .text SEPARATOR \ + .balign 16 SEPARATOR +#else +#define FUNC_ALIGN +#endif + +// BTI and PAC gnu property note +#define NT_GNU_PROPERTY_TYPE_0 5 +#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 +#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI 1 +#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC 2 + +#if defined(__ARM_FEATURE_BTI_DEFAULT) +#define BTI_FLAG GNU_PROPERTY_AARCH64_FEATURE_1_BTI +#else +#define BTI_FLAG 0 +#endif + +#if __ARM_FEATURE_PAC_DEFAULT & 3 +#define PAC_FLAG GNU_PROPERTY_AARCH64_FEATURE_1_PAC +#else +#define PAC_FLAG 0 +#endif + +#define GNU_PROPERTY(type, value) \ + .pushsection .note.gnu.property, "a" SEPARATOR \ + .p2align 3 SEPARATOR \ + .word 4 SEPARATOR \ + .word 16 SEPARATOR \ + .word NT_GNU_PROPERTY_TYPE_0 SEPARATOR \ + .asciz "GNU" SEPARATOR \ + .word type SEPARATOR \ + .word 4 SEPARATOR \ + .word value SEPARATOR \ + .word 0 SEPARATOR \ + .popsection + +#if BTI_FLAG != 0 +#define BTI_C hint #34 +#define BTI_J hint #36 +#else +#define BTI_C +#define BTI_J +#endif + +#if (BTI_FLAG | PAC_FLAG) != 0 +#define GNU_PROPERTY_BTI_PAC \ + GNU_PROPERTY(GNU_PROPERTY_AARCH64_FEATURE_1_AND, BTI_FLAG | PAC_FLAG) +#else +#define GNU_PROPERTY_BTI_PAC +#endif + +#if defined(__clang__) || defined(__GCC_HAVE_DWARF2_CFI_ASM) +#define CFI_START .cfi_startproc +#define CFI_END .cfi_endproc +#else +#define CFI_START +#define CFI_END +#endif + #if defined(__arm__) + +// Determine actual [ARM][THUMB[1][2]] ISA using compiler predefined macros: +// - for '-mthumb -march=armv6' compiler defines '__thumb__' +// - for '-mthumb -march=armv7' compiler defines '__thumb__' and '__thumb2__' +#if defined(__thumb2__) || defined(__thumb__) +#define DEFINE_CODE_STATE .thumb SEPARATOR +#define DECLARE_FUNC_ENCODING .thumb_func SEPARATOR +#if defined(__thumb2__) +#define USE_THUMB_2 +#define IT(cond) it cond +#define ITT(cond) itt cond +#define ITE(cond) ite cond +#else +#define USE_THUMB_1 +#define IT(cond) +#define ITT(cond) +#define ITE(cond) +#endif // defined(__thumb__2) +#else // !defined(__thumb2__) && !defined(__thumb__) +#define DEFINE_CODE_STATE .arm SEPARATOR +#define DECLARE_FUNC_ENCODING +#define IT(cond) +#define ITT(cond) +#define ITE(cond) +#endif + +#if defined(USE_THUMB_1) && defined(USE_THUMB_2) +#error "USE_THUMB_1 and USE_THUMB_2 can't be defined together." +#endif + #if defined(__ARM_ARCH_4T__) || __ARM_ARCH >= 5 #define ARM_HAS_BX #endif -#if !defined(__ARM_FEATURE_CLZ) && __ARM_ARCH_ISA_THUMB != 1 && \ +#if !defined(__ARM_FEATURE_CLZ) && !defined(USE_THUMB_1) && \ (__ARM_ARCH >= 6 || (__ARM_ARCH == 5 && !defined(__ARM_ARCH_5__))) #define __ARM_FEATURE_CLZ #endif @@ -92,40 +189,47 @@ JMP(ip) #endif -#if __ARM_ARCH_ISA_THUMB == 2 -#define IT(cond) it cond -#define ITT(cond) itt cond -#else -#define IT(cond) -#define ITT(cond) -#endif - -#if __ARM_ARCH_ISA_THUMB == 2 +#if defined(USE_THUMB_2) #define WIDE(op) op.w #else #define WIDE(op) op #endif +#else // !defined(__arm) +#define DECLARE_FUNC_ENCODING +#define DEFINE_CODE_STATE #endif -#define GLUE2(a, b) a##b -#define GLUE(a, b) GLUE2(a, b) +#define GLUE2_(a, b) a##b +#define GLUE(a, b) GLUE2_(a, b) +#define GLUE2(a, b) GLUE2_(a, b) +#define GLUE3_(a, b, c) a##b##c +#define GLUE3(a, b, c) GLUE3_(a, b, c) +#define GLUE4_(a, b, c, d) a##b##c##d +#define GLUE4(a, b, c, d) GLUE4_(a, b, c, d) + #define SYMBOL_NAME(name) GLUE(__USER_LABEL_PREFIX__, name) #ifdef VISIBILITY_HIDDEN #define DECLARE_SYMBOL_VISIBILITY(name) \ HIDDEN(SYMBOL_NAME(name)) SEPARATOR +#define DECLARE_SYMBOL_VISIBILITY_UNMANGLED(name) \ + HIDDEN(name) SEPARATOR #else #define DECLARE_SYMBOL_VISIBILITY(name) +#define DECLARE_SYMBOL_VISIBILITY_UNMANGLED(name) #endif #define DEFINE_COMPILERRT_FUNCTION(name) \ + DEFINE_CODE_STATE \ FILE_LEVEL_DIRECTIVE SEPARATOR \ .globl SYMBOL_NAME(name) SEPARATOR \ SYMBOL_IS_FUNC(SYMBOL_NAME(name)) SEPARATOR \ DECLARE_SYMBOL_VISIBILITY(name) \ + DECLARE_FUNC_ENCODING \ SYMBOL_NAME(name): #define DEFINE_COMPILERRT_THUMB_FUNCTION(name) \ + DEFINE_CODE_STATE \ FILE_LEVEL_DIRECTIVE SEPARATOR \ .globl SYMBOL_NAME(name) SEPARATOR \ SYMBOL_IS_FUNC(SYMBOL_NAME(name)) SEPARATOR \ @@ -134,18 +238,32 @@ SYMBOL_NAME(name): #define DEFINE_COMPILERRT_PRIVATE_FUNCTION(name) \ + DEFINE_CODE_STATE \ FILE_LEVEL_DIRECTIVE SEPARATOR \ .globl SYMBOL_NAME(name) SEPARATOR \ SYMBOL_IS_FUNC(SYMBOL_NAME(name)) SEPARATOR \ HIDDEN(SYMBOL_NAME(name)) SEPARATOR \ + DECLARE_FUNC_ENCODING \ SYMBOL_NAME(name): #define DEFINE_COMPILERRT_PRIVATE_FUNCTION_UNMANGLED(name) \ + DEFINE_CODE_STATE \ .globl name SEPARATOR \ SYMBOL_IS_FUNC(name) SEPARATOR \ HIDDEN(name) SEPARATOR \ + DECLARE_FUNC_ENCODING \ name: +#define DEFINE_COMPILERRT_OUTLINE_FUNCTION_UNMANGLED(name) \ + DEFINE_CODE_STATE \ + FUNC_ALIGN \ + .globl name SEPARATOR \ + SYMBOL_IS_FUNC(name) SEPARATOR \ + DECLARE_SYMBOL_VISIBILITY_UNMANGLED(name) SEPARATOR \ + CFI_START SEPARATOR \ + DECLARE_FUNC_ENCODING \ + name: SEPARATOR BTI_C + #define DEFINE_COMPILERRT_FUNCTION_ALIAS(name, target) \ .globl SYMBOL_NAME(name) SEPARATOR \ SYMBOL_IS_FUNC(SYMBOL_NAME(name)) SEPARATOR \ @@ -162,8 +280,13 @@ #ifdef __ELF__ #define END_COMPILERRT_FUNCTION(name) \ .size SYMBOL_NAME(name), . - SYMBOL_NAME(name) +#define END_COMPILERRT_OUTLINE_FUNCTION(name) \ + CFI_END SEPARATOR \ + .size SYMBOL_NAME(name), . - SYMBOL_NAME(name) #else #define END_COMPILERRT_FUNCTION(name) +#define END_COMPILERRT_OUTLINE_FUNCTION(name) \ + CFI_END #endif -#endif /* COMPILERRT_ASSEMBLY_H */ +#endif // COMPILERRT_ASSEMBLY_H diff --git a/lib/compiler-rt/builtins/ctzdi2.c b/lib/compiler-rt/builtins/ctzdi2.c index db3c6fdc0..26c908d87 100644 --- a/lib/compiler-rt/builtins/ctzdi2.c +++ b/lib/compiler-rt/builtins/ctzdi2.c @@ -1,29 +1,35 @@ -/* ===-- ctzdi2.c - Implement __ctzdi2 -------------------------------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file implements __ctzdi2 for the compiler_rt library. - * - * ===----------------------------------------------------------------------=== - */ +//===-- ctzdi2.c - Implement __ctzdi2 -------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements __ctzdi2 for the compiler_rt library. +// +//===----------------------------------------------------------------------===// #include "int_lib.h" -/* Returns: the number of trailing 0-bits */ +// Returns: the number of trailing 0-bits -/* Precondition: a != 0 */ +#if !defined(__clang__) && \ + ((defined(__sparc__) && defined(__arch64__)) || defined(__mips64) || \ + (defined(__riscv) && __SIZEOF_POINTER__ >= 8)) +// On 64-bit architectures with neither a native clz instruction nor a native +// ctz instruction, gcc resolves __builtin_ctz to __ctzdi2 rather than +// __ctzsi2, leading to infinite recursion. +#define __builtin_ctz(a) __ctzsi2(a) +extern int __ctzsi2(si_int); +#endif -COMPILER_RT_ABI si_int -__ctzdi2(di_int a) -{ - dwords x; - x.all = a; - const si_int f = -(x.s.low == 0); - return __builtin_ctz((x.s.high & f) | (x.s.low & ~f)) + - (f & ((si_int)(sizeof(si_int) * CHAR_BIT))); +// Precondition: a != 0 + +COMPILER_RT_ABI int __ctzdi2(di_int a) { + dwords x; + x.all = a; + const si_int f = -(x.s.low == 0); + return ctzsi((x.s.high & f) | (x.s.low & ~f)) + + (f & ((si_int)(sizeof(si_int) * CHAR_BIT))); } diff --git a/lib/compiler-rt/builtins/divdi3.c b/lib/compiler-rt/builtins/divdi3.c index b8eebcb20..d71e138d9 100644 --- a/lib/compiler-rt/builtins/divdi3.c +++ b/lib/compiler-rt/builtins/divdi3.c @@ -1,29 +1,22 @@ -/* ===-- divdi3.c - Implement __divdi3 -------------------------------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file implements __divdi3 for the compiler_rt library. - * - * ===----------------------------------------------------------------------=== - */ +//===-- divdi3.c - Implement __divdi3 -------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements __divdi3 for the compiler_rt library. +// +//===----------------------------------------------------------------------===// #include "int_lib.h" -/* Returns: a / b */ +// Returns: a / b -COMPILER_RT_ABI di_int -__divdi3(di_int a, di_int b) -{ - const int bits_in_dword_m1 = (int)(sizeof(di_int) * CHAR_BIT) - 1; - di_int s_a = a >> bits_in_dword_m1; /* s_a = a < 0 ? -1 : 0 */ - di_int s_b = b >> bits_in_dword_m1; /* s_b = b < 0 ? -1 : 0 */ - a = (a ^ s_a) - s_a; /* negate if s_a == -1 */ - b = (b ^ s_b) - s_b; /* negate if s_b == -1 */ - s_a ^= s_b; /*sign of quotient */ - return (__udivmoddi4(a, b, (du_int*)0) ^ s_a) - s_a; /* negate if s_a == -1 */ -} +#define fixint_t di_int +#define fixuint_t du_int +#define COMPUTE_UDIV(a, b) __udivmoddi4((a), (b), (du_int *)0) +#include "int_div_impl.inc" + +COMPILER_RT_ABI di_int __divdi3(di_int a, di_int b) { return __divXi3(a, b); } diff --git a/lib/compiler-rt/builtins/divmoddi4.c b/lib/compiler-rt/builtins/divmoddi4.c index 0d4df67a6..e7cbbb1aa 100644 --- a/lib/compiler-rt/builtins/divmoddi4.c +++ b/lib/compiler-rt/builtins/divmoddi4.c @@ -1,25 +1,28 @@ -/*===-- divmoddi4.c - Implement __divmoddi4 --------------------------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file implements __divmoddi4 for the compiler_rt library. - * - * ===----------------------------------------------------------------------=== - */ +//===-- divmoddi4.c - Implement __divmoddi4 -------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements __divmoddi4 for the compiler_rt library. +// +//===----------------------------------------------------------------------===// #include "int_lib.h" -/* Returns: a / b, *rem = a % b */ +// Returns: a / b, *rem = a % b -COMPILER_RT_ABI di_int -__divmoddi4(di_int a, di_int b, di_int* rem) -{ - di_int d = __divdi3(a,b); - *rem = a - (d*b); - return d; +COMPILER_RT_ABI di_int __divmoddi4(di_int a, di_int b, di_int *rem) { + const int bits_in_dword_m1 = (int)(sizeof(di_int) * CHAR_BIT) - 1; + di_int s_a = a >> bits_in_dword_m1; // s_a = a < 0 ? -1 : 0 + di_int s_b = b >> bits_in_dword_m1; // s_b = b < 0 ? -1 : 0 + a = (a ^ s_a) - s_a; // negate if s_a == -1 + b = (b ^ s_b) - s_b; // negate if s_b == -1 + s_b ^= s_a; // sign of quotient + du_int r; + di_int q = (__udivmoddi4(a, b, &r) ^ s_b) - s_b; // negate if s_b == -1 + *rem = (r ^ s_a) - s_a; // negate if s_a == -1 + return q; } diff --git a/lib/compiler-rt/builtins/int_div_impl.inc b/lib/compiler-rt/builtins/int_div_impl.inc new file mode 100644 index 000000000..dc1f97cbe --- /dev/null +++ b/lib/compiler-rt/builtins/int_div_impl.inc @@ -0,0 +1,95 @@ +//===-- int_div_impl.inc - Integer division ---------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Helpers used by __udivsi3, __umodsi3, __udivdi3, and __umodsi3. +// +//===----------------------------------------------------------------------===// + +#define clz(a) (sizeof(a) == sizeof(unsigned long long) ? __builtin_clzll(a) : clzsi(a)) + +// Adapted from Figure 3-40 of The PowerPC Compiler Writer's Guide +static __inline fixuint_t __udivXi3(fixuint_t n, fixuint_t d) { + const unsigned N = sizeof(fixuint_t) * CHAR_BIT; + // d == 0 cases are unspecified. + unsigned sr = (d ? clz(d) : N) - (n ? clz(n) : N); + // 0 <= sr <= N - 1 or sr is very large. + if (sr > N - 1) // n < d + return 0; + if (sr == N - 1) // d == 1 + return n; + ++sr; + // 1 <= sr <= N - 1. Shifts do not trigger UB. + fixuint_t r = n >> sr; + n <<= N - sr; + fixuint_t carry = 0; + for (; sr > 0; --sr) { + r = (r << 1) | (n >> (N - 1)); + n = (n << 1) | carry; + // Branch-less version of: + // carry = 0; + // if (r >= d) r -= d, carry = 1; + const fixint_t s = (fixint_t)(d - r - 1) >> (N - 1); + carry = s & 1; + r -= d & s; + } + n = (n << 1) | carry; + return n; +} + +// Mostly identical to __udivXi3 but the return values are different. +static __inline fixuint_t __umodXi3(fixuint_t n, fixuint_t d) { + const unsigned N = sizeof(fixuint_t) * CHAR_BIT; + // d == 0 cases are unspecified. + unsigned sr = (d ? clz(d) : N) - (n ? clz(n) : N); + // 0 <= sr <= N - 1 or sr is very large. + if (sr > N - 1) // n < d + return n; + if (sr == N - 1) // d == 1 + return 0; + ++sr; + // 1 <= sr <= N - 1. Shifts do not trigger UB. + fixuint_t r = n >> sr; + n <<= N - sr; + fixuint_t carry = 0; + for (; sr > 0; --sr) { + r = (r << 1) | (n >> (N - 1)); + n = (n << 1) | carry; + // Branch-less version of: + // carry = 0; + // if (r >= d) r -= d, carry = 1; + const fixint_t s = (fixint_t)(d - r - 1) >> (N - 1); + carry = s & 1; + r -= d & s; + } + return r; +} + +#ifdef COMPUTE_UDIV +static __inline fixint_t __divXi3(fixint_t a, fixint_t b) { + const int N = (int)(sizeof(fixint_t) * CHAR_BIT) - 1; + fixint_t s_a = a >> N; // s_a = a < 0 ? -1 : 0 + fixint_t s_b = b >> N; // s_b = b < 0 ? -1 : 0 + fixuint_t a_u = (fixuint_t)(a ^ s_a) + (-s_a); // negate if s_a == -1 + fixuint_t b_u = (fixuint_t)(b ^ s_b) + (-s_b); // negate if s_b == -1 + s_a ^= s_b; // sign of quotient + return (COMPUTE_UDIV(a_u, b_u) ^ s_a) + (-s_a); // negate if s_a == -1 +} +#endif // COMPUTE_UDIV + +#ifdef ASSIGN_UMOD +static __inline fixint_t __modXi3(fixint_t a, fixint_t b) { + const int N = (int)(sizeof(fixint_t) * CHAR_BIT) - 1; + fixint_t s = b >> N; // s = b < 0 ? -1 : 0 + fixuint_t b_u = (fixuint_t)(b ^ s) + (-s); // negate if s == -1 + s = a >> N; // s = a < 0 ? -1 : 0 + fixuint_t a_u = (fixuint_t)(a ^ s) + (-s); // negate if s == -1 + fixuint_t res; + ASSIGN_UMOD(res, a_u, b_u); + return (res ^ s) + (-s); // negate if s == -1 +} +#endif // ASSIGN_UMOD diff --git a/lib/compiler-rt/builtins/int_endianness.h b/lib/compiler-rt/builtins/int_endianness.h index 7995ddbb9..291c6b58c 100644 --- a/lib/compiler-rt/builtins/int_endianness.h +++ b/lib/compiler-rt/builtins/int_endianness.h @@ -1,51 +1,49 @@ -/* ===-- int_endianness.h - configuration header for compiler-rt ------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file is a configuration header for compiler-rt. - * This file is not part of the interface of this library. - * - * ===----------------------------------------------------------------------=== - */ +//===-- int_endianness.h - configuration header for compiler-rt -----------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file is a configuration header for compiler-rt. +// This file is not part of the interface of this library. +// +//===----------------------------------------------------------------------===// #ifndef INT_ENDIANNESS_H #define INT_ENDIANNESS_H -#if defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && \ +#if defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && \ defined(__ORDER_LITTLE_ENDIAN__) -/* Clang and GCC provide built-in endianness definitions. */ +// Clang and GCC provide built-in endianness definitions. #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ #define _YUGA_LITTLE_ENDIAN 0 -#define _YUGA_BIG_ENDIAN 1 +#define _YUGA_BIG_ENDIAN 1 #elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ #define _YUGA_LITTLE_ENDIAN 1 -#define _YUGA_BIG_ENDIAN 0 -#endif /* __BYTE_ORDER__ */ +#define _YUGA_BIG_ENDIAN 0 +#endif // __BYTE_ORDER__ -#else /* Compilers other than Clang or GCC. */ +#else // Compilers other than Clang or GCC. #if defined(__SVR4) && defined(__sun) #include <sys/byteorder.h> #if defined(_BIG_ENDIAN) #define _YUGA_LITTLE_ENDIAN 0 -#define _YUGA_BIG_ENDIAN 1 +#define _YUGA_BIG_ENDIAN 1 #elif defined(_LITTLE_ENDIAN) #define _YUGA_LITTLE_ENDIAN 1 -#define _YUGA_BIG_ENDIAN 0 -#else /* !_LITTLE_ENDIAN */ +#define _YUGA_BIG_ENDIAN 0 +#else // !_LITTLE_ENDIAN #error "unknown endianness" -#endif /* !_LITTLE_ENDIAN */ +#endif // !_LITTLE_ENDIAN -#endif /* Solaris and AuroraUX. */ +#endif // Solaris -/* .. */ +// .. #if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || \ defined(__minix) @@ -53,64 +51,64 @@ #if _BYTE_ORDER == _BIG_ENDIAN #define _YUGA_LITTLE_ENDIAN 0 -#define _YUGA_BIG_ENDIAN 1 +#define _YUGA_BIG_ENDIAN 1 #elif _BYTE_ORDER == _LITTLE_ENDIAN #define _YUGA_LITTLE_ENDIAN 1 -#define _YUGA_BIG_ENDIAN 0 -#endif /* _BYTE_ORDER */ +#define _YUGA_BIG_ENDIAN 0 +#endif // _BYTE_ORDER -#endif /* *BSD */ +#endif // *BSD -#if defined(__OpenBSD__) || defined(__Bitrig__) +#if defined(__OpenBSD__) #include <machine/endian.h> #if _BYTE_ORDER == _BIG_ENDIAN #define _YUGA_LITTLE_ENDIAN 0 -#define _YUGA_BIG_ENDIAN 1 +#define _YUGA_BIG_ENDIAN 1 #elif _BYTE_ORDER == _LITTLE_ENDIAN #define _YUGA_LITTLE_ENDIAN 1 -#define _YUGA_BIG_ENDIAN 0 -#endif /* _BYTE_ORDER */ +#define _YUGA_BIG_ENDIAN 0 +#endif // _BYTE_ORDER -#endif /* OpenBSD and Bitrig. */ +#endif // OpenBSD -/* .. */ +// .. -/* Mac OSX has __BIG_ENDIAN__ or __LITTLE_ENDIAN__ automatically set by the - * compiler (at least with GCC) */ -#if defined(__APPLE__) || defined(__ellcc__ ) +// Mac OSX has __BIG_ENDIAN__ or __LITTLE_ENDIAN__ automatically set by the +// compiler (at least with GCC) +#if defined(__APPLE__) || defined(__ellcc__) #ifdef __BIG_ENDIAN__ #if __BIG_ENDIAN__ #define _YUGA_LITTLE_ENDIAN 0 -#define _YUGA_BIG_ENDIAN 1 +#define _YUGA_BIG_ENDIAN 1 #endif -#endif /* __BIG_ENDIAN__ */ +#endif // __BIG_ENDIAN__ #ifdef __LITTLE_ENDIAN__ #if __LITTLE_ENDIAN__ #define _YUGA_LITTLE_ENDIAN 1 -#define _YUGA_BIG_ENDIAN 0 +#define _YUGA_BIG_ENDIAN 0 #endif -#endif /* __LITTLE_ENDIAN__ */ +#endif // __LITTLE_ENDIAN__ -#endif /* Mac OSX */ +#endif // Mac OSX -/* .. */ +// .. #if defined(_WIN32) #define _YUGA_LITTLE_ENDIAN 1 -#define _YUGA_BIG_ENDIAN 0 +#define _YUGA_BIG_ENDIAN 0 -#endif /* Windows */ +#endif // Windows -#endif /* Clang or GCC. */ +#endif // Clang or GCC. -/* . */ +// . #if !defined(_YUGA_LITTLE_ENDIAN) || !defined(_YUGA_BIG_ENDIAN) #error Unable to determine endian -#endif /* Check we found an endianness correctly. */ +#endif // Check we found an endianness correctly. -#endif /* INT_ENDIANNESS_H */ +#endif // INT_ENDIANNESS_H diff --git a/lib/compiler-rt/builtins/int_lib.h b/lib/compiler-rt/builtins/int_lib.h index 80a7c41a4..fb791ebc4 100644 --- a/lib/compiler-rt/builtins/int_lib.h +++ b/lib/compiler-rt/builtins/int_lib.h @@ -1,49 +1,33 @@ -/* ===-- int_lib.h - configuration header for compiler-rt -----------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file is a configuration header for compiler-rt. - * This file is not part of the interface of this library. - * - * ===----------------------------------------------------------------------=== - */ - -/* - * Portions copyright (c) 2017-2018, ARM Limited and Contributors. - * All rights reserved. - */ +//===-- int_lib.h - configuration header for compiler-rt -----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file is a configuration header for compiler-rt. +// This file is not part of the interface of this library. +// +//===----------------------------------------------------------------------===// #ifndef INT_LIB_H #define INT_LIB_H -/* Assumption: Signed integral is 2's complement. */ -/* Assumption: Right shift of signed negative is arithmetic shift. */ -/* Assumption: Endianness is little or big (not mixed). */ +// Assumption: Signed integral is 2's complement. +// Assumption: Right shift of signed negative is arithmetic shift. +// Assumption: Endianness is little or big (not mixed). -#if defined(__ELF__) -#define FNALIAS(alias_name, original_name) \ - void alias_name() __attribute__((__alias__(#original_name))) -#define COMPILER_RT_ALIAS(aliasee) __attribute__((__alias__(#aliasee))) -#else -#define FNALIAS(alias, name) _Pragma("GCC error(\"alias unsupported on this file format\")") -#define COMPILER_RT_ALIAS(aliasee) _Pragma("GCC error(\"alias unsupported on this file format\")") -#endif - -/* ABI macro definitions */ +// ABI macro definitions #if __ARM_EABI__ -# ifdef COMPILER_RT_ARMHF_TARGET -# define COMPILER_RT_ABI -# else -# define COMPILER_RT_ABI __attribute__((__pcs__("aapcs"))) -# endif +#ifdef COMPILER_RT_ARMHF_TARGET +#define COMPILER_RT_ABI +#else +#define COMPILER_RT_ABI __attribute__((__pcs__("aapcs"))) +#endif #else -# define COMPILER_RT_ABI +#define COMPILER_RT_ABI #endif #define AEABI_RTABI __attribute__((__pcs__("aapcs"))) @@ -60,42 +44,89 @@ #define UNUSED __attribute__((unused)) #endif -/* - * Kernel and boot environment can't use normal headers, - * so use the equivalent system headers. - */ -# include <limits.h> -# include <stdint.h> +#define STR(a) #a +#define XSTR(a) STR(a) +#define SYMBOL_NAME(name) XSTR(__USER_LABEL_PREFIX__) #name + +#if defined(__ELF__) || defined(__MINGW32__) || defined(__wasm__) || \ + defined(_AIX) +#define COMPILER_RT_ALIAS(name, aliasname) \ + COMPILER_RT_ABI __typeof(name) aliasname __attribute__((__alias__(#name))); +#elif defined(__APPLE__) +#if defined(VISIBILITY_HIDDEN) +#define COMPILER_RT_ALIAS_VISIBILITY(name) \ + __asm__(".private_extern " SYMBOL_NAME(name)); +#else +#define COMPILER_RT_ALIAS_VISIBILITY(name) +#endif +#define COMPILER_RT_ALIAS(name, aliasname) \ + __asm__(".globl " SYMBOL_NAME(aliasname)); \ + COMPILER_RT_ALIAS_VISIBILITY(aliasname) \ + __asm__(SYMBOL_NAME(aliasname) " = " SYMBOL_NAME(name)); \ + COMPILER_RT_ABI __typeof(name) aliasname; +#elif defined(_WIN32) +#define COMPILER_RT_ALIAS(name, aliasname) +#else +#error Unsupported target +#endif + +#if (defined(__FreeBSD__) || defined(__NetBSD__)) && \ + (defined(_KERNEL) || defined(_STANDALONE)) +// +// Kernel and boot environment can't use normal headers, +// so use the equivalent system headers. +// NB: FreeBSD (and OpenBSD) deprecate machine/limits.h in +// favour of sys/limits.h, so prefer the former, but fall +// back on the latter if not available since NetBSD only has +// the latter. +// +#if defined(__has_include) && __has_include(<sys/limits.h>) +#include <sys/limits.h> +#else +#include <machine/limits.h> +#endif +#include <sys/stdint.h> +#include <sys/types.h> +#else +// Include the standard compiler builtin headers we use functionality from. +#include <float.h> +#include <limits.h> +#include <stdbool.h> +#include <stdint.h> +#endif -/* Include the commonly used internal type definitions. */ +// Include the commonly used internal type definitions. #include "int_types.h" -COMPILER_RT_ABI si_int __paritysi2(si_int a); -COMPILER_RT_ABI si_int __paritydi2(di_int a); +// Include internal utility function declarations. +#include "int_util.h" + +COMPILER_RT_ABI int __paritysi2(si_int a); +COMPILER_RT_ABI int __paritydi2(di_int a); COMPILER_RT_ABI di_int __divdi3(di_int a, di_int b); COMPILER_RT_ABI si_int __divsi3(si_int a, si_int b); COMPILER_RT_ABI su_int __udivsi3(su_int n, su_int d); -COMPILER_RT_ABI su_int __udivmodsi4(su_int a, su_int b, su_int* rem); -COMPILER_RT_ABI du_int __udivmoddi4(du_int a, du_int b, du_int* rem); +COMPILER_RT_ABI su_int __udivmodsi4(su_int a, su_int b, su_int *rem); +COMPILER_RT_ABI du_int __udivmoddi4(du_int a, du_int b, du_int *rem); #ifdef CRT_HAS_128BIT -COMPILER_RT_ABI si_int __clzti2(ti_int a); -COMPILER_RT_ABI tu_int __udivmodti4(tu_int a, tu_int b, tu_int* rem); +COMPILER_RT_ABI int __clzti2(ti_int a); +COMPILER_RT_ABI tu_int __udivmodti4(tu_int a, tu_int b, tu_int *rem); #endif -/* Definitions for builtins unavailable on MSVC */ +// Definitions for builtins unavailable on MSVC #if defined(_MSC_VER) && !defined(__clang__) #include <intrin.h> -uint32_t __inline __builtin_ctz(uint32_t value) { +int __inline __builtin_ctz(uint32_t value) { unsigned long trailing_zero = 0; if (_BitScanForward(&trailing_zero, value)) return trailing_zero; return 32; } -uint32_t __inline __builtin_clz(uint32_t value) { +int __inline __builtin_clz(uint32_t value) { unsigned long leading_zero = 0; if (_BitScanReverse(&leading_zero, value)) return 31 - leading_zero; @@ -103,14 +134,14 @@ uint32_t __inline __builtin_clz(uint32_t value) { } #if defined(_M_ARM) || defined(_M_X64) -uint32_t __inline __builtin_clzll(uint64_t value) { +int __inline __builtin_clzll(uint64_t value) { unsigned long leading_zero = 0; if (_BitScanReverse64(&leading_zero, value)) return 63 - leading_zero; return 64; } #else -uint32_t __inline __builtin_clzll(uint64_t value) { +int __inline __builtin_clzll(uint64_t value) { if (value == 0) return 64; uint32_t msh = (uint32_t)(value >> 32); @@ -122,6 +153,19 @@ uint32_t __inline __builtin_clzll(uint64_t value) { #endif #define __builtin_clzl __builtin_clzll -#endif /* defined(_MSC_VER) && !defined(__clang__) */ -#endif /* INT_LIB_H */ +bool __inline __builtin_sadd_overflow(int x, int y, int *result) { + if ((x < 0) != (y < 0)) { + *result = x + y; + return false; + } + int tmp = (unsigned int)x + (unsigned int)y; + if ((tmp < 0) != (x < 0)) + return true; + *result = tmp; + return false; +} + +#endif // defined(_MSC_VER) && !defined(__clang__) + +#endif // INT_LIB_H diff --git a/lib/compiler-rt/builtins/int_math.h b/lib/compiler-rt/builtins/int_math.h index fc81fb7f0..48b9580f5 100644 --- a/lib/compiler-rt/builtins/int_math.h +++ b/lib/compiler-rt/builtins/int_math.h @@ -1,34 +1,31 @@ -/* ===-- int_math.h - internal math inlines ---------------------------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===-----------------------------------------------------------------------=== - * - * This file is not part of the interface of this library. - * - * This file defines substitutes for the libm functions used in some of the - * compiler-rt implementations, defined in such a way that there is not a direct - * dependency on libm or math.h. Instead, we use the compiler builtin versions - * where available. This reduces our dependencies on the system SDK by foisting - * the responsibility onto the compiler. - * - * ===-----------------------------------------------------------------------=== - */ +//===-- int_math.h - internal math inlines --------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file is not part of the interface of this library. +// +// This file defines substitutes for the libm functions used in some of the +// compiler-rt implementations, defined in such a way that there is not a direct +// dependency on libm or math.h. Instead, we use the compiler builtin versions +// where available. This reduces our dependencies on the system SDK by foisting +// the responsibility onto the compiler. +// +//===----------------------------------------------------------------------===// #ifndef INT_MATH_H #define INT_MATH_H #ifndef __has_builtin -# define __has_builtin(x) 0 +#define __has_builtin(x) 0 #endif #if defined(_MSC_VER) && !defined(__clang__) #include <math.h> #include <stdlib.h> -#include <ymath.h> #endif #if defined(_MSC_VER) && !defined(__clang__) @@ -42,24 +39,23 @@ #define crt_isinf(x) !_finite((x)) #define crt_isnan(x) _isnan((x)) #else -/* Define crt_isfinite in terms of the builtin if available, otherwise provide - * an alternate version in terms of our other functions. This supports some - * versions of GCC which didn't have __builtin_isfinite. - */ +// Define crt_isfinite in terms of the builtin if available, otherwise provide +// an alternate version in terms of our other functions. This supports some +// versions of GCC which didn't have __builtin_isfinite. #if __has_builtin(__builtin_isfinite) -# define crt_isfinite(x) __builtin_isfinite((x)) +#define crt_isfinite(x) __builtin_isfinite((x)) #elif defined(__GNUC__) -# define crt_isfinite(x) \ - __extension__(({ \ - __typeof((x)) x_ = (x); \ - !crt_isinf(x_) && !crt_isnan(x_); \ - })) +#define crt_isfinite(x) \ + __extension__(({ \ + __typeof((x)) x_ = (x); \ + !crt_isinf(x_) && !crt_isnan(x_); \ + })) #else -# error "Do not know how to check for infinity" -#endif /* __has_builtin(__builtin_isfinite) */ +#error "Do not know how to check for infinity" +#endif // __has_builtin(__builtin_isfinite) #define crt_isinf(x) __builtin_isinf((x)) #define crt_isnan(x) __builtin_isnan((x)) -#endif /* _MSC_VER */ +#endif // _MSC_VER #if defined(_MSC_VER) && !defined(__clang__) #define crt_copysign(x, y) copysign((x), (y)) @@ -82,33 +78,21 @@ #endif #if defined(_MSC_VER) && !defined(__clang__) -#define crt_fmax(x, y) __max((x), (y)) -#define crt_fmaxf(x, y) __max((x), (y)) #define crt_fmaxl(x, y) __max((x), (y)) #else -#define crt_fmax(x, y) __builtin_fmax((x), (y)) -#define crt_fmaxf(x, y) __builtin_fmaxf((x), (y)) #define crt_fmaxl(x, y) __builtin_fmaxl((x), (y)) #endif #if defined(_MSC_VER) && !defined(__clang__) -#define crt_logb(x) logb((x)) -#define crt_logbf(x) logbf((x)) #define crt_logbl(x) logbl((x)) #else -#define crt_logb(x) __builtin_logb((x)) -#define crt_logbf(x) __builtin_logbf((x)) #define crt_logbl(x) __builtin_logbl((x)) #endif #if defined(_MSC_VER) && !defined(__clang__) -#define crt_scalbn(x, y) scalbn((x), (y)) -#define crt_scalbnf(x, y) scalbnf((x), (y)) #define crt_scalbnl(x, y) scalbnl((x), (y)) #else -#define crt_scalbn(x, y) __builtin_scalbn((x), (y)) -#define crt_scalbnf(x, y) __builtin_scalbnf((x), (y)) #define crt_scalbnl(x, y) __builtin_scalbnl((x), (y)) #endif -#endif /* INT_MATH_H */ +#endif // INT_MATH_H diff --git a/lib/compiler-rt/builtins/int_types.h b/lib/compiler-rt/builtins/int_types.h index 660385ecd..7a72de480 100644 --- a/lib/compiler-rt/builtins/int_types.h +++ b/lib/compiler-rt/builtins/int_types.h @@ -1,148 +1,174 @@ -/* ===-- int_lib.h - configuration header for compiler-rt -----------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file is not part of the interface of this library. - * - * This file defines various standard types, most importantly a number of unions - * used to access parts of larger types. - * - * ===----------------------------------------------------------------------=== - */ +//===-- int_lib.h - configuration header for compiler-rt -----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file is not part of the interface of this library. +// +// This file defines various standard types, most importantly a number of unions +// used to access parts of larger types. +// +//===----------------------------------------------------------------------===// #ifndef INT_TYPES_H #define INT_TYPES_H #include "int_endianness.h" -/* si_int is defined in Linux sysroot's asm-generic/siginfo.h */ +// si_int is defined in Linux sysroot's asm-generic/siginfo.h #ifdef si_int #undef si_int #endif -typedef int si_int; -typedef unsigned su_int; +typedef int32_t si_int; +typedef uint32_t su_int; +#if UINT_MAX == 0xFFFFFFFF +#define clzsi __builtin_clz +#define ctzsi __builtin_ctz +#elif ULONG_MAX == 0xFFFFFFFF +#define clzsi __builtin_clzl +#define ctzsi __builtin_ctzl +#else +#error could not determine appropriate clzsi macro for this system +#endif -typedef long long di_int; -typedef unsigned long long du_int; +typedef int64_t di_int; +typedef uint64_t du_int; -typedef union -{ - di_int all; - struct - { +typedef union { + di_int all; + struct { #if _YUGA_LITTLE_ENDIAN - su_int low; - si_int high; + su_int low; + si_int high; #else - si_int high; - su_int low; -#endif /* _YUGA_LITTLE_ENDIAN */ - }s; + si_int high; + su_int low; +#endif // _YUGA_LITTLE_ENDIAN + } s; } dwords; -typedef union -{ - du_int all; - struct - { +typedef union { + du_int all; + struct { #if _YUGA_LITTLE_ENDIAN - su_int low; - su_int high; + su_int low; + su_int high; #else - su_int high; - su_int low; -#endif /* _YUGA_LITTLE_ENDIAN */ - }s; + su_int high; + su_int low; +#endif // _YUGA_LITTLE_ENDIAN + } s; } udwords; -/* MIPS64 issue: PR 20098 */ -#if (defined(__LP64__) || defined(__wasm__)) && \ - !(defined(__mips__) && defined(__clang__)) +#if defined(__LP64__) || defined(__wasm__) || defined(__mips64) || \ + defined(__riscv) || defined(_WIN64) #define CRT_HAS_128BIT #endif +// MSVC doesn't have a working 128bit integer type. Users should really compile +// compiler-rt with clang, but if they happen to be doing a standalone build for +// asan or something else, disable the 128 bit parts so things sort of work. +#if defined(_MSC_VER) && !defined(__clang__) +#undef CRT_HAS_128BIT +#endif + #ifdef CRT_HAS_128BIT -typedef int ti_int __attribute__ ((mode (TI))); -typedef unsigned tu_int __attribute__ ((mode (TI))); - -typedef union -{ - ti_int all; - struct - { +typedef int ti_int __attribute__((mode(TI))); +typedef unsigned tu_int __attribute__((mode(TI))); + +typedef union { + ti_int all; + struct { #if _YUGA_LITTLE_ENDIAN - du_int low; - di_int high; + du_int low; + di_int high; #else - di_int high; - du_int low; -#endif /* _YUGA_LITTLE_ENDIAN */ - }s; + di_int high; + du_int low; +#endif // _YUGA_LITTLE_ENDIAN + } s; } twords; -typedef union -{ - tu_int all; - struct - { +typedef union { + tu_int all; + struct { #if _YUGA_LITTLE_ENDIAN - du_int low; - du_int high; + du_int low; + du_int high; #else - du_int high; - du_int low; -#endif /* _YUGA_LITTLE_ENDIAN */ - }s; + du_int high; + du_int low; +#endif // _YUGA_LITTLE_ENDIAN + } s; } utwords; static __inline ti_int make_ti(di_int h, di_int l) { - twords r; - r.s.high = h; - r.s.low = l; - return r.all; + twords r; + r.s.high = h; + r.s.low = l; + return r.all; } static __inline tu_int make_tu(du_int h, du_int l) { - utwords r; - r.s.high = h; - r.s.low = l; - return r.all; + utwords r; + r.s.high = h; + r.s.low = l; + return r.all; } -#endif /* CRT_HAS_128BIT */ +#endif // CRT_HAS_128BIT + +// FreeBSD's boot environment does not support using floating-point and poisons +// the float and double keywords. +#if defined(__FreeBSD__) && defined(_STANDALONE) +#define CRT_HAS_FLOATING_POINT 0 +#else +#define CRT_HAS_FLOATING_POINT 1 +#endif -typedef union -{ - su_int u; - float f; +#if CRT_HAS_FLOATING_POINT +typedef union { + su_int u; + float f; } float_bits; -typedef union -{ - udwords u; - double f; +typedef union { + udwords u; + double f; } double_bits; +#endif -typedef struct -{ +typedef struct { #if _YUGA_LITTLE_ENDIAN - udwords low; - udwords high; + udwords low; + udwords high; #else - udwords high; - udwords low; -#endif /* _YUGA_LITTLE_ENDIAN */ + udwords high; + udwords low; +#endif // _YUGA_LITTLE_ENDIAN } uqwords; -typedef union -{ - uqwords u; - long double f; +// Check if the target supports 80 bit extended precision long doubles. +// Notably, on x86 Windows, MSVC only provides a 64-bit long double, but GCC +// still makes it 80 bits. Clang will match whatever compiler it is trying to +// be compatible with. On 32-bit x86 Android, long double is 64 bits, while on +// x86_64 Android, long double is 128 bits. +#if (defined(__i386__) || defined(__x86_64__)) && \ + !(defined(_MSC_VER) || defined(__ANDROID__)) +#define HAS_80_BIT_LONG_DOUBLE 1 +#elif defined(__m68k__) || defined(__ia64__) +#define HAS_80_BIT_LONG_DOUBLE 1 +#else +#define HAS_80_BIT_LONG_DOUBLE 0 +#endif + +#if CRT_HAS_FLOATING_POINT +typedef union { + uqwords u; + long double f; } long_double_bits; #if __STDC_VERSION__ >= 199901L @@ -153,14 +179,20 @@ typedef long double _Complex Lcomplex; #define COMPLEX_REAL(x) __real__(x) #define COMPLEX_IMAGINARY(x) __imag__(x) #else -typedef struct { float real, imaginary; } Fcomplex; +typedef struct { + float real, imaginary; +} Fcomplex; -typedef struct { double real, imaginary; } Dcomplex; +typedef struct { + double real, imaginary; +} Dcomplex; -typedef struct { long double real, imaginary; } Lcomplex; +typedef struct { + long double real, imaginary; +} Lcomplex; #define COMPLEX_REAL(x) (x).real #define COMPLEX_IMAGINARY(x) (x).imaginary #endif -#endif /* INT_TYPES_H */ - +#endif +#endif // INT_TYPES_H diff --git a/lib/compiler-rt/builtins/int_util.h b/lib/compiler-rt/builtins/int_util.h new file mode 100644 index 000000000..c372c2edc --- /dev/null +++ b/lib/compiler-rt/builtins/int_util.h @@ -0,0 +1,47 @@ +//===-- int_util.h - internal utility functions ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file is not part of the interface of this library. +// +// This file defines non-inline utilities which are available for use in the +// library. The function definitions themselves are all contained in int_util.c +// which will always be compiled into any compiler-rt library. +// +//===----------------------------------------------------------------------===// + +#ifndef INT_UTIL_H +#define INT_UTIL_H + +/// \brief Trigger a program abort (or panic for kernel code). +#define compilerrt_abort() __compilerrt_abort_impl(__FILE__, __LINE__, __func__) + +NORETURN void __compilerrt_abort_impl(const char *file, int line, + const char *function); + +#define COMPILE_TIME_ASSERT(expr) COMPILE_TIME_ASSERT1(expr, __COUNTER__) +#define COMPILE_TIME_ASSERT1(expr, cnt) COMPILE_TIME_ASSERT2(expr, cnt) +#define COMPILE_TIME_ASSERT2(expr, cnt) \ + typedef char ct_assert_##cnt[(expr) ? 1 : -1] UNUSED + +// Force unrolling the code specified to be repeated N times. +#define REPEAT_0_TIMES(code_to_repeat) /* do nothing */ +#define REPEAT_1_TIMES(code_to_repeat) code_to_repeat +#define REPEAT_2_TIMES(code_to_repeat) \ + REPEAT_1_TIMES(code_to_repeat) \ + code_to_repeat +#define REPEAT_3_TIMES(code_to_repeat) \ + REPEAT_2_TIMES(code_to_repeat) \ + code_to_repeat +#define REPEAT_4_TIMES(code_to_repeat) \ + REPEAT_3_TIMES(code_to_repeat) \ + code_to_repeat + +#define REPEAT_N_TIMES_(N, code_to_repeat) REPEAT_##N##_TIMES(code_to_repeat) +#define REPEAT_N_TIMES(N, code_to_repeat) REPEAT_N_TIMES_(N, code_to_repeat) + +#endif // INT_UTIL_H diff --git a/lib/compiler-rt/builtins/lshrdi3.c b/lib/compiler-rt/builtins/lshrdi3.c index 67b2a7668..607215258 100644 --- a/lib/compiler-rt/builtins/lshrdi3.c +++ b/lib/compiler-rt/builtins/lshrdi3.c @@ -1,45 +1,38 @@ -/* ===-- lshrdi3.c - Implement __lshrdi3 -----------------------------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file implements __lshrdi3 for the compiler_rt library. - * - * ===----------------------------------------------------------------------=== - */ +//===-- lshrdi3.c - Implement __lshrdi3 -----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements __lshrdi3 for the compiler_rt library. +// +//===----------------------------------------------------------------------===// #include "int_lib.h" -/* Returns: logical a >> b */ +// Returns: logical a >> b -/* Precondition: 0 <= b < bits_in_dword */ +// Precondition: 0 <= b < bits_in_dword -COMPILER_RT_ABI di_int -__lshrdi3(di_int a, si_int b) -{ - const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT); - udwords input; - udwords result; - input.all = a; - if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */ - { - result.s.high = 0; - result.s.low = input.s.high >> (b - bits_in_word); - } - else /* 0 <= b < bits_in_word */ - { - if (b == 0) - return a; - result.s.high = input.s.high >> b; - result.s.low = (input.s.high << (bits_in_word - b)) | (input.s.low >> b); - } - return result.all; +COMPILER_RT_ABI di_int __lshrdi3(di_int a, int b) { + const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT); + udwords input; + udwords result; + input.all = a; + if (b & bits_in_word) /* bits_in_word <= b < bits_in_dword */ { + result.s.high = 0; + result.s.low = input.s.high >> (b - bits_in_word); + } else /* 0 <= b < bits_in_word */ { + if (b == 0) + return a; + result.s.high = input.s.high >> b; + result.s.low = (input.s.high << (bits_in_word - b)) | (input.s.low >> b); + } + return result.all; } #if defined(__ARM_EABI__) -AEABI_RTABI di_int __aeabi_llsr(di_int a, si_int b) COMPILER_RT_ALIAS(__lshrdi3); +COMPILER_RT_ALIAS(__lshrdi3, __aeabi_llsr) #endif diff --git a/lib/compiler-rt/builtins/popcountdi2.c b/lib/compiler-rt/builtins/popcountdi2.c index 5e8a62f07..20dd0b023 100644 --- a/lib/compiler-rt/builtins/popcountdi2.c +++ b/lib/compiler-rt/builtins/popcountdi2.c @@ -1,36 +1,32 @@ -/* ===-- popcountdi2.c - Implement __popcountdi2 ----------------------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file implements __popcountdi2 for the compiler_rt library. - * - * ===----------------------------------------------------------------------=== - */ +//===-- popcountdi2.c - Implement __popcountdi2 ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements __popcountdi2 for the compiler_rt library. +// +//===----------------------------------------------------------------------===// #include "int_lib.h" -/* Returns: count of 1 bits */ +// Returns: count of 1 bits -COMPILER_RT_ABI si_int -__popcountdi2(di_int a) -{ - du_int x2 = (du_int)a; - x2 = x2 - ((x2 >> 1) & 0x5555555555555555uLL); - /* Every 2 bits holds the sum of every pair of bits (32) */ - x2 = ((x2 >> 2) & 0x3333333333333333uLL) + (x2 & 0x3333333333333333uLL); - /* Every 4 bits holds the sum of every 4-set of bits (3 significant bits) (16) */ - x2 = (x2 + (x2 >> 4)) & 0x0F0F0F0F0F0F0F0FuLL; - /* Every 8 bits holds the sum of every 8-set of bits (4 significant bits) (8) */ - su_int x = (su_int)(x2 + (x2 >> 32)); - /* The lower 32 bits hold four 16 bit sums (5 significant bits). */ - /* Upper 32 bits are garbage */ - x = x + (x >> 16); - /* The lower 16 bits hold two 32 bit sums (6 significant bits). */ - /* Upper 16 bits are garbage */ - return (x + (x >> 8)) & 0x0000007F; /* (7 significant bits) */ +COMPILER_RT_ABI int __popcountdi2(di_int a) { + du_int x2 = (du_int)a; + x2 = x2 - ((x2 >> 1) & 0x5555555555555555uLL); + // Every 2 bits holds the sum of every pair of bits (32) + x2 = ((x2 >> 2) & 0x3333333333333333uLL) + (x2 & 0x3333333333333333uLL); + // Every 4 bits holds the sum of every 4-set of bits (3 significant bits) (16) + x2 = (x2 + (x2 >> 4)) & 0x0F0F0F0F0F0F0F0FuLL; + // Every 8 bits holds the sum of every 8-set of bits (4 significant bits) (8) + su_int x = (su_int)(x2 + (x2 >> 32)); + // The lower 32 bits hold four 16 bit sums (5 significant bits). + // Upper 32 bits are garbage + x = x + (x >> 16); + // The lower 16 bits hold two 32 bit sums (6 significant bits). + // Upper 16 bits are garbage + return (x + (x >> 8)) & 0x0000007F; // (7 significant bits) } diff --git a/lib/compiler-rt/builtins/popcountsi2.c b/lib/compiler-rt/builtins/popcountsi2.c index 44544ff49..4d346c45d 100644 --- a/lib/compiler-rt/builtins/popcountsi2.c +++ b/lib/compiler-rt/builtins/popcountsi2.c @@ -1,33 +1,29 @@ -/* ===-- popcountsi2.c - Implement __popcountsi2 ---------------------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file implements __popcountsi2 for the compiler_rt library. - * - * ===----------------------------------------------------------------------=== - */ +//===-- popcountsi2.c - Implement __popcountsi2 ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements __popcountsi2 for the compiler_rt library. +// +//===----------------------------------------------------------------------===// #include "int_lib.h" -/* Returns: count of 1 bits */ +// Returns: count of 1 bits -COMPILER_RT_ABI si_int -__popcountsi2(si_int a) -{ - su_int x = (su_int)a; - x = x - ((x >> 1) & 0x55555555); - /* Every 2 bits holds the sum of every pair of bits */ - x = ((x >> 2) & 0x33333333) + (x & 0x33333333); - /* Every 4 bits holds the sum of every 4-set of bits (3 significant bits) */ - x = (x + (x >> 4)) & 0x0F0F0F0F; - /* Every 8 bits holds the sum of every 8-set of bits (4 significant bits) */ - x = (x + (x >> 16)); - /* The lower 16 bits hold two 8 bit sums (5 significant bits).*/ - /* Upper 16 bits are garbage */ - return (x + (x >> 8)) & 0x0000003F; /* (6 significant bits) */ +COMPILER_RT_ABI int __popcountsi2(si_int a) { + su_int x = (su_int)a; + x = x - ((x >> 1) & 0x55555555); + // Every 2 bits holds the sum of every pair of bits + x = ((x >> 2) & 0x33333333) + (x & 0x33333333); + // Every 4 bits holds the sum of every 4-set of bits (3 significant bits) + x = (x + (x >> 4)) & 0x0F0F0F0F; + // Every 8 bits holds the sum of every 8-set of bits (4 significant bits) + x = (x + (x >> 16)); + // The lower 16 bits hold two 8 bit sums (5 significant bits). + // Upper 16 bits are garbage + return (x + (x >> 8)) & 0x0000003F; // (6 significant bits) } diff --git a/lib/compiler-rt/builtins/udivmoddi4.c b/lib/compiler-rt/builtins/udivmoddi4.c index 0c8b4ff46..123e5fb05 100644 --- a/lib/compiler-rt/builtins/udivmoddi4.c +++ b/lib/compiler-rt/builtins/udivmoddi4.c @@ -1,231 +1,200 @@ -/* ===-- udivmoddi4.c - Implement __udivmoddi4 -----------------------------=== - * - * The LLVM Compiler Infrastructure - * - * This file is dual licensed under the MIT and the University of Illinois Open - * Source Licenses. See LICENSE.TXT for details. - * - * ===----------------------------------------------------------------------=== - * - * This file implements __udivmoddi4 for the compiler_rt library. - * - * ===----------------------------------------------------------------------=== - */ +//===-- udivmoddi4.c - Implement __udivmoddi4 -----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements __udivmoddi4 for the compiler_rt library. +// +//===----------------------------------------------------------------------===// #include "int_lib.h" -/* Effects: if rem != 0, *rem = a % b - * Returns: a / b - */ +// Effects: if rem != 0, *rem = a % b +// Returns: a / b -/* Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide */ +// Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide -COMPILER_RT_ABI du_int -__udivmoddi4(du_int a, du_int b, du_int* rem) -{ - const unsigned n_uword_bits = sizeof(su_int) * CHAR_BIT; - const unsigned n_udword_bits = sizeof(du_int) * CHAR_BIT; - udwords n; - n.all = a; - udwords d; - d.all = b; - udwords q; - udwords r; - unsigned sr; - /* special cases, X is unknown, K != 0 */ - if (n.s.high == 0) - { - if (d.s.high == 0) - { - /* 0 X - * --- - * 0 X - */ - if (rem) - *rem = n.s.low % d.s.low; - return n.s.low / d.s.low; - } - /* 0 X - * --- - * K X - */ - if (rem) - *rem = n.s.low; - return 0; +#if defined(_MSC_VER) && !defined(__clang__) +// MSVC throws a warning about mod 0 here, disable it for builds that +// warn-as-error +#pragma warning(push) +#pragma warning(disable : 4723 4724) +#endif + +COMPILER_RT_ABI du_int __udivmoddi4(du_int a, du_int b, du_int *rem) { + const unsigned n_uword_bits = sizeof(su_int) * CHAR_BIT; + const unsigned n_udword_bits = sizeof(du_int) * CHAR_BIT; + udwords n; + n.all = a; + udwords d; + d.all = b; + udwords q; + udwords r; + unsigned sr; + // special cases, X is unknown, K != 0 + if (n.s.high == 0) { + if (d.s.high == 0) { + // 0 X + // --- + // 0 X + if (rem) + *rem = n.s.low % d.s.low; + return n.s.low / d.s.low; } - /* n.s.high != 0 */ - if (d.s.low == 0) - { - if (d.s.high == 0) - { - /* K X - * --- - * 0 0 - */ - if (rem) - *rem = n.s.high % d.s.low; - return n.s.high / d.s.low; - } - /* d.s.high != 0 */ - if (n.s.low == 0) - { - /* K 0 - * --- - * K 0 - */ - if (rem) - { - r.s.high = n.s.high % d.s.high; - r.s.low = 0; - *rem = r.all; - } - return n.s.high / d.s.high; - } - /* K K - * --- - * K 0 - */ - if ((d.s.high & (d.s.high - 1)) == 0) /* if d is a power of 2 */ - { - if (rem) - { - r.s.low = n.s.low; - r.s.high = n.s.high & (d.s.high - 1); - *rem = r.all; - } - return n.s.high >> __builtin_ctz(d.s.high); - } - /* K K - * --- - * K 0 - */ - sr = __builtin_clz(d.s.high) - __builtin_clz(n.s.high); - /* 0 <= sr <= n_uword_bits - 2 or sr large */ - if (sr > n_uword_bits - 2) - { - if (rem) - *rem = n.all; - return 0; - } - ++sr; - /* 1 <= sr <= n_uword_bits - 1 */ - /* q.all = n.all << (n_udword_bits - sr); */ + // 0 X + // --- + // K X + if (rem) + *rem = n.s.low; + return 0; + } + // n.s.high != 0 + if (d.s.low == 0) { + if (d.s.high == 0) { + // K X + // --- + // 0 0 + if (rem) + *rem = n.s.high % d.s.low; + return n.s.high / d.s.low; + } + // d.s.high != 0 + if (n.s.low == 0) { + // K 0 + // --- + // K 0 + if (rem) { + r.s.high = n.s.high % d.s.high; + r.s.low = 0; + *rem = r.all; + } + return n.s.high / d.s.high; + } + // K K + // --- + // K 0 + if ((d.s.high & (d.s.high - 1)) == 0) /* if d is a power of 2 */ { + if (rem) { + r.s.low = n.s.low; + r.s.high = n.s.high & (d.s.high - 1); + *rem = r.all; + } + return n.s.high >> ctzsi(d.s.high); + } + // K K + // --- + // K 0 + sr = clzsi(d.s.high) - clzsi(n.s.high); + // 0 <= sr <= n_uword_bits - 2 or sr large + if (sr > n_uword_bits - 2) { + if (rem) + *rem = n.all; + return 0; + } + ++sr; + // 1 <= sr <= n_uword_bits - 1 + // q.all = n.all << (n_udword_bits - sr); + q.s.low = 0; + q.s.high = n.s.low << (n_uword_bits - sr); + // r.all = n.all >> sr; + r.s.high = n.s.high >> sr; + r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); + } else /* d.s.low != 0 */ { + if (d.s.high == 0) { + // K X + // --- + // 0 K + if ((d.s.low & (d.s.low - 1)) == 0) /* if d is a power of 2 */ { + if (rem) + *rem = n.s.low & (d.s.low - 1); + if (d.s.low == 1) + return n.all; + sr = ctzsi(d.s.low); + q.s.high = n.s.high >> sr; + q.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); + return q.all; + } + // K X + // --- + // 0 K + sr = 1 + n_uword_bits + clzsi(d.s.low) - clzsi(n.s.high); + // 2 <= sr <= n_udword_bits - 1 + // q.all = n.all << (n_udword_bits - sr); + // r.all = n.all >> sr; + if (sr == n_uword_bits) { + q.s.low = 0; + q.s.high = n.s.low; + r.s.high = 0; + r.s.low = n.s.high; + } else if (sr < n_uword_bits) /* 2 <= sr <= n_uword_bits - 1 */ { q.s.low = 0; q.s.high = n.s.low << (n_uword_bits - sr); - /* r.all = n.all >> sr; */ r.s.high = n.s.high >> sr; r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); + } else /* n_uword_bits + 1 <= sr <= n_udword_bits - 1 */ { + q.s.low = n.s.low << (n_udword_bits - sr); + q.s.high = (n.s.high << (n_udword_bits - sr)) | + (n.s.low >> (sr - n_uword_bits)); + r.s.high = 0; + r.s.low = n.s.high >> (sr - n_uword_bits); + } + } else { + // K X + // --- + // K K + sr = clzsi(d.s.high) - clzsi(n.s.high); + // 0 <= sr <= n_uword_bits - 1 or sr large + if (sr > n_uword_bits - 1) { + if (rem) + *rem = n.all; + return 0; + } + ++sr; + // 1 <= sr <= n_uword_bits + // q.all = n.all << (n_udword_bits - sr); + q.s.low = 0; + if (sr == n_uword_bits) { + q.s.high = n.s.low; + r.s.high = 0; + r.s.low = n.s.high; + } else { + q.s.high = n.s.low << (n_uword_bits - sr); + r.s.high = n.s.high >> sr; + r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); + } } - else /* d.s.low != 0 */ - { - if (d.s.high == 0) - { - /* K X - * --- - * 0 K - */ - if ((d.s.low & (d.s.low - 1)) == 0) /* if d is a power of 2 */ - { - if (rem) - *rem = n.s.low & (d.s.low - 1); - if (d.s.low == 1) - return n.all; - sr = __builtin_ctz(d.s.low); - q.s.high = n.s.high >> sr; - q.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); - return q.all; - } - /* K X - * --- - * 0 K - */ - sr = 1 + n_uword_bits + __builtin_clz(d.s.low) - __builtin_clz(n.s.high); - /* 2 <= sr <= n_udword_bits - 1 - * q.all = n.all << (n_udword_bits - sr); - * r.all = n.all >> sr; - */ - if (sr == n_uword_bits) - { - q.s.low = 0; - q.s.high = n.s.low; - r.s.high = 0; - r.s.low = n.s.high; - } - else if (sr < n_uword_bits) // 2 <= sr <= n_uword_bits - 1 - { - q.s.low = 0; - q.s.high = n.s.low << (n_uword_bits - sr); - r.s.high = n.s.high >> sr; - r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); - } - else // n_uword_bits + 1 <= sr <= n_udword_bits - 1 - { - q.s.low = n.s.low << (n_udword_bits - sr); - q.s.high = (n.s.high << (n_udword_bits - sr)) | - (n.s.low >> (sr - n_uword_bits)); - r.s.high = 0; - r.s.low = n.s.high >> (sr - n_uword_bits); - } - } - else - { - /* K X - * --- - * K K - */ - sr = __builtin_clz(d.s.high) - __builtin_clz(n.s.high); - /* 0 <= sr <= n_uword_bits - 1 or sr large */ - if (sr > n_uword_bits - 1) - { - if (rem) - *rem = n.all; - return 0; - } - ++sr; - /* 1 <= sr <= n_uword_bits */ - /* q.all = n.all << (n_udword_bits - sr); */ - q.s.low = 0; - if (sr == n_uword_bits) - { - q.s.high = n.s.low; - r.s.high = 0; - r.s.low = n.s.high; - } - else - { - q.s.high = n.s.low << (n_uword_bits - sr); - r.s.high = n.s.high >> sr; - r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr); - } - } - } - /* Not a special case - * q and r are initialized with: - * q.all = n.all << (n_udword_bits - sr); - * r.all = n.all >> sr; - * 1 <= sr <= n_udword_bits - 1 - */ - su_int carry = 0; - for (; sr > 0; --sr) - { - /* r:q = ((r:q) << 1) | carry */ - r.s.high = (r.s.high << 1) | (r.s.low >> (n_uword_bits - 1)); - r.s.low = (r.s.low << 1) | (q.s.high >> (n_uword_bits - 1)); - q.s.high = (q.s.high << 1) | (q.s.low >> (n_uword_bits - 1)); - q.s.low = (q.s.low << 1) | carry; - /* carry = 0; - * if (r.all >= d.all) - * { - * r.all -= d.all; - * carry = 1; - * } - */ - const di_int s = (di_int)(d.all - r.all - 1) >> (n_udword_bits - 1); - carry = s & 1; - r.all -= d.all & s; - } - q.all = (q.all << 1) | carry; - if (rem) - *rem = r.all; - return q.all; + } + // Not a special case + // q and r are initialized with: + // q.all = n.all << (n_udword_bits - sr); + // r.all = n.all >> sr; + // 1 <= sr <= n_udword_bits - 1 + su_int carry = 0; + for (; sr > 0; --sr) { + // r:q = ((r:q) << 1) | carry + r.s.high = (r.s.high << 1) | (r.s.low >> (n_uword_bits - 1)); + r.s.low = (r.s.low << 1) | (q.s.high >> (n_uword_bits - 1)); + q.s.high = (q.s.high << 1) | (q.s.low >> (n_uword_bits - 1)); + q.s.low = (q.s.low << 1) | carry; + // carry = 0; + // if (r.all >= d.all) + // { + // r.all -= d.all; + // carry = 1; + // } + const di_int s = (di_int)(d.all - r.all - 1) >> (n_udword_bits - 1); + carry = s & 1; + r.all -= d.all & s; + } + q.all = (q.all << 1) | carry; + if (rem) + *rem = r.all; + return q.all; } + +#if defined(_MSC_VER) && !defined(__clang__) +#pragma warning(pop) +#endif diff --git a/lib/compiler-rt/compiler-rt.mk b/lib/compiler-rt/compiler-rt.mk index 40c669f98..2338908f3 100644 --- a/lib/compiler-rt/compiler-rt.mk +++ b/lib/compiler-rt/compiler-rt.mk @@ -34,6 +34,7 @@ COMPILER_RT_SRCS := lib/compiler-rt/builtins/popcountdi2.c \ ifeq (${ARCH},aarch32) COMPILER_RT_SRCS += lib/compiler-rt/builtins/arm/aeabi_ldivmod.S \ lib/compiler-rt/builtins/arm/aeabi_uldivmod.S \ + lib/compiler-rt/builtins/arm/aeabi_memcpy.S \ lib/compiler-rt/builtins/ctzdi2.c \ lib/compiler-rt/builtins/divdi3.c \ lib/compiler-rt/builtins/divmoddi4.c \ diff --git a/lib/cpus/aarch64/a64fx.S b/lib/cpus/aarch64/a64fx.S new file mode 100644 index 000000000..54c20c32b --- /dev/null +++ b/lib/cpus/aarch64/a64fx.S @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2022, Fujitsu Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch.h> +#include <asm_macros.S> +#include <assert_macros.S> +#include <a64fx.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +func a64fx_core_pwr_dwn +endfunc a64fx_core_pwr_dwn + +func a64fx_cluster_pwr_dwn +endfunc a64fx_cluster_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for A64FX. Must follow AAPCS. + */ +func a64fx_errata_report + ret +endfunc a64fx_errata_report +#endif + + /* --------------------------------------------- + * This function provides cpu specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.a64fx_regs, "aS" +a64fx_regs: /* The ascii list of register names to be reported */ + .asciz "" + +func a64fx_cpu_reg_dump + adr x6, a64fx_regs + ret +endfunc a64fx_cpu_reg_dump + +declare_cpu_ops a64fx, A64FX_MIDR, CPU_NO_RESET_FUNC \ + a64fx_core_pwr_dwn, \ + a64fx_cluster_pwr_dwn + diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index f44407775..f7f8027c8 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -265,6 +265,103 @@ func check_errata_2172148 endfunc check_errata_2172148 /* ---------------------------------------------------- + * Errata Workaround for Cortex-A510 Errata #2347730. + * This applies to revisions r0p0 - r0p3, r1p0, r1p1. + * It is fixed in r1p2. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * ---------------------------------------------------- + */ +func errata_cortex_a510_2347730_wa + mov x17, x30 + bl check_errata_2347730 + cbz x0, 1f + + /* + * Set CPUACTLR_EL1[17] to 1'b1, which disables + * specific microarchitectural clock gating + * behaviour. + */ + mrs x1, CORTEX_A510_CPUACTLR_EL1 + orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_17 + msr CORTEX_A510_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_cortex_a510_2347730_wa + +func check_errata_2347730 + /* Applies to revisions r1p1 and lower. */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2347730 + + /*--------------------------------------------------- + * Errata Workaround for Cortex-A510 Errata #2371937. + * This applies to revisions r1p1 and lower, and is + * fixed in r1p2. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x1, x17 + *--------------------------------------------------- + */ +func errata_cortex_a510_2371937_wa + mov x17, x30 + bl check_errata_2371937 + cbz x0, 1f + + /* + * Cacheable atomic operations can be forced + * to be executed near by setting + * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found + * in [40:38] of CPUECTLR_EL1. + */ + mrs x0, CORTEX_A510_CPUECTLR_EL1 + mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR + bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3 + msr CORTEX_A510_CPUECTLR_EL1, x0 +1: + ret x17 +endfunc errata_cortex_a510_2371937_wa + +func check_errata_2371937 + /* Applies to r1p1 and lower */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2371937 + + /* ------------------------------------------------------ + * Errata Workaround for Cortex-A510 Errata #2666669 + * This applies to revisions r1p1 and lower, and is fixed + * in r1p2. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x1, x17 + * ------------------------------------------------------ + */ +func errata_cortex_a510_2666669_wa + mov x17, x30 + bl check_errata_2666669 + cbz x0, 1f + + /* + * Workaround will set IMP_CPUACTLR_EL1[38] + * to 0b1. + */ + mrs x1, CORTEX_A510_CPUACTLR_EL1 + orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_38 + msr CORTEX_A510_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_cortex_a510_2666669_wa + +func check_errata_2666669 + /* Applies to r1p1 and lower */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2666669 + + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- */ @@ -295,12 +392,15 @@ func cortex_a510_errata_report * checking functions of each errata. */ report_errata ERRATA_A510_1922240, cortex_a510, 1922240 - report_errata ERRATA_A510_2288014, cortex_a510, 2288014 - report_errata ERRATA_A510_2042739, cortex_a510, 2042739 report_errata ERRATA_A510_2041909, cortex_a510, 2041909 - report_errata ERRATA_A510_2250311, cortex_a510, 2250311 - report_errata ERRATA_A510_2218950, cortex_a510, 2218950 + report_errata ERRATA_A510_2042739, cortex_a510, 2042739 report_errata ERRATA_A510_2172148, cortex_a510, 2172148 + report_errata ERRATA_A510_2218950, cortex_a510, 2218950 + report_errata ERRATA_A510_2250311, cortex_a510, 2250311 + report_errata ERRATA_A510_2288014, cortex_a510, 2288014 + report_errata ERRATA_A510_2347730, cortex_a510, 2347730 + report_errata ERRATA_A510_2371937, cortex_a510, 2371937 + report_errata ERRATA_A510_2666669, cortex_a510, 2666669 report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941 ldp x8, x30, [sp], #16 @@ -352,11 +452,26 @@ func cortex_a510_reset_func bl errata_cortex_a510_2218950_wa #endif +#if ERRATA_A510_2371937 + mov x0, x18 + bl errata_cortex_a510_2371937_wa +#endif + #if ERRATA_A510_2172148 mov x0, x18 bl errata_cortex_a510_2172148_wa #endif +#if ERRATA_A510_2347730 + mov x0, x18 + bl errata_cortex_a510_2347730_wa +#endif + +#if ERRATA_A510_2666669 + mov x0, x18 + bl errata_cortex_a510_2666669_wa +#endif + isb ret x19 endfunc cortex_a510_reset_func diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S index 783830450..0e0388bcd 100644 --- a/lib/cpus/aarch64/cortex_a55.S +++ b/lib/cpus/aarch64/cortex_a55.S @@ -16,6 +16,8 @@ #error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif + .globl cortex_a55_reset_func + .globl cortex_a55_core_pwr_dwn /* -------------------------------------------------- * Errata Workaround for Cortex A55 Errata #768277. * This applies only to revision r0p0 of Cortex A55. diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index 5d8e9a603..fed3f33a8 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -280,6 +280,79 @@ func check_errata_2136059 b cpu_rev_var_ls endfunc check_errata_2136059 +/* ---------------------------------------------------------------- + * Errata workaround for Cortex-A710 Erratum 2147715. + * This applies to revision r2p0, and is fixed in r2p1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x1, x17 + * ---------------------------------------------------------------- + */ +func errata_a710_2147715_wa + mov x17, x30 + bl check_errata_2147715 + cbz x0, 1f + + /* Apply workaround; set CPUACTLR_EL1[22] + * to 1, which will cause the CFP instruction + * to invalidate all branch predictor resources + * regardless of context. + */ + mrs x1, CORTEX_A710_CPUACTLR_EL1 + orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 + msr CORTEX_A710_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_a710_2147715_wa + +func check_errata_2147715 + mov x1, #0x20 + mov x2, #0x20 + b cpu_rev_var_range +endfunc check_errata_2147715 + +/* --------------------------------------------------------------- + * Errata Workaround for Cortex-A710 Erratum 2216384. + * This applies to revision r0p0, r1p0 and r2p0. + * It is fixed in r2p1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------------------- + */ +func errata_a710_2216384_wa + /* Compare x0 against revision r2p0 */ + mov x17, x30 + bl check_errata_2216384 + cbz x0, 1f + + /* Apply workaround: set CPUACTLR5_EL1[17] + * to 1 and the following instruction + * patching sequence. + */ + mrs x1, CORTEX_A710_CPUACTLR5_EL1 + orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 + msr CORTEX_A710_CPUACTLR5_EL1, x1 + + ldr x0,=0x5 + msr CORTEX_A710_CPUPSELR_EL3, x0 + ldr x0,=0x10F600E000 + msr CORTEX_A710_CPUPOR_EL3, x0 + ldr x0,=0x10FF80E000 + msr CORTEX_A710_CPUPMR_EL3, x0 + ldr x0,=0x80000000003FF + msr CORTEX_A710_CPUPCR_EL3, x0 + isb +1: + ret x17 +endfunc errata_a710_2216384_wa + +func check_errata_2216384 + /* Applies to r0p0, r1p0 and r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2216384 + /* --------------------------------------------------------------- * Errata Workaround for Cortex-A710 Erratum 2282622. * This applies to revision r0p0, r1p0 and r2p0. @@ -310,6 +383,34 @@ func check_errata_2282622 b cpu_rev_var_ls endfunc check_errata_2282622 +/* ------------------------------------------------------------------------ + * Errata Workaround for Cortex-A710 Erratum 2291219 on power down request. + * This applies to revision <= r2p0 and is fixed in r2p1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * ------------------------------------------------------------------------ + */ +func errata_a710_2291219_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2291219 + cbz x0, 1f + + /* Set bit 36 in ACTLR2_EL1 */ + mrs x1, CORTEX_A710_CPUACTLR2_EL1 + orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_36 + msr CORTEX_A710_CPUACTLR2_EL1, x1 +1: + ret x17 +endfunc errata_a710_2291219_wa + +func check_errata_2291219 + /* Applies to <= r2p0. */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2291219 + /* --------------------------------------------------------------- * Errata Workaround for Cortex-A710 Erratum 2008768. * This applies to revision r0p0, r1p0 and r2p0. @@ -353,6 +454,34 @@ func check_errata_2008768 b cpu_rev_var_ls endfunc check_errata_2008768 +/* ------------------------------------------------------- + * Errata Workaround for Cortex-A710 Erratum 2371105. + * This applies to revisions <= r2p0 and is fixed in r2p1. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * ------------------------------------------------------- + */ +func errata_a710_2371105_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2371105 + cbz x0, 1f + + /* Set bit 40 in CPUACTLR2_EL1 */ + mrs x1, CORTEX_A710_CPUACTLR2_EL1 + orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_40 + msr CORTEX_A710_CPUACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_a710_2371105_wa + +func check_errata_2371105 + /* Applies to <= r2p0. */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2371105 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -375,6 +504,13 @@ func cortex_a710_core_pwr_dwn mov x30, x4 #endif +#if ERRATA_A710_2291219 + mov x15, x30 + bl cpu_get_rev_var + bl errata_a710_2291219_wa + mov x30, x15 +#endif /* ERRATA_A710_2291219 */ + /* --------------------------------------------------- * Enable CPU power down bit in power control register * --------------------------------------------------- @@ -410,6 +546,10 @@ func cortex_a710_errata_report report_errata ERRATA_A710_2136059, cortex_a710, 2136059 report_errata ERRATA_A710_2282622, cortex_a710, 2282622 report_errata ERRATA_A710_2008768, cortex_a710, 2008768 + report_errata ERRATA_A710_2147715, cortex_a710, 2147715 + report_errata ERRATA_A710_2216384, cortex_a710, 2216384 + report_errata ERRATA_A710_2291219, cortex_a710, 2291219 + report_errata ERRATA_A710_2371105, cortex_a710, 2371105 report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960 report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941 @@ -471,16 +611,31 @@ func cortex_a710_reset_func bl errata_a710_2136059_wa #endif +#if ERRATA_A710_2147715 + mov x0, x18 + bl errata_a710_2147715_wa +#endif + +#if ERRATA_A710_2216384 + mov x0, x18 + bl errata_a710_2216384_wa +#endif /* ERRATA_A710_2216384 */ + #if ERRATA_A710_2282622 mov x0, x18 bl errata_a710_2282622_wa #endif +#if ERRATA_A710_2371105 + mov x0, x18 + bl errata_a710_2371105_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* * The Cortex-A710 generic vectors are overridden to apply errata - * mitigation on exception entry from lower ELs. - */ + * mitigation on exception entry from lower ELs. + */ adr x0, wa_cve_vbar_cortex_a710 msr vbar_el3, x0 #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ diff --git a/lib/cpus/aarch64/cortex_makalu.S b/lib/cpus/aarch64/cortex_a715.S index 7603210c5..7603210c5 100644 --- a/lib/cpus/aarch64/cortex_makalu.S +++ b/lib/cpus/aarch64/cortex_a715.S diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 50bd8cd90..36507defe 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,6 +17,9 @@ #if HW_ASSISTED_COHERENCY == 0 #error "Cortex-A76 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif + .globl cortex_a76_reset_func + .globl cortex_a76_core_pwr_dwn + .globl cortex_a76_disable_wa_cve_2018_3639 /* 64-bit only core */ #if CTX_INCLUDE_AARCH32_REGS == 1 @@ -583,6 +586,30 @@ func check_errata_1946160 b cpu_rev_var_range endfunc check_errata_1946160 + /* ---------------------------------------------------- + * Errata Workaround for Cortex-A76 Errata #2743102 + * This applies to revisions <= r4p1 and is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * ---------------------------------------------------- + */ +func errata_a76_2743102_wa + mov x17, x30 + bl check_errata_2743102 + cbz x0, 1f + + /* dsb before isb of power down sequence */ + dsb sy +1: + ret x17 +endfunc errata_a76_2743102_wa + +func check_errata_2743102 + /* Applies to all revisions <= r4p1 */ + mov x1, #0x41 + b cpu_rev_var_ls +endfunc check_errata_2743102 + func check_errata_cve_2018_3639 #if WORKAROUND_CVE_2018_3639 mov x0, #ERRATA_APPLIES @@ -745,6 +772,12 @@ func cortex_a76_core_pwr_dwn mrs x0, CORTEX_A76_CPUPWRCTLR_EL1 orr x0, x0, #CORTEX_A76_CORE_PWRDN_EN_MASK msr CORTEX_A76_CPUPWRCTLR_EL1, x0 +#if ERRATA_A76_2743102 + mov x15, x30 + bl cpu_get_rev_var + bl errata_a76_2743102_wa + mov x30, x15 +#endif /* ERRATA_A76_2743102 */ isb ret endfunc cortex_a76_core_pwr_dwn @@ -765,6 +798,7 @@ func cortex_a76_errata_report */ report_errata ERRATA_A76_1073348, cortex_a76, 1073348 report_errata ERRATA_A76_1130799, cortex_a76, 1130799 + report_errata ERRATA_A76_1165522, cortex_a76, 1165522 report_errata ERRATA_A76_1220197, cortex_a76, 1220197 report_errata ERRATA_A76_1257314, cortex_a76, 1257314 report_errata ERRATA_A76_1262606, cortex_a76, 1262606 @@ -772,9 +806,9 @@ func cortex_a76_errata_report report_errata ERRATA_A76_1275112, cortex_a76, 1275112 report_errata ERRATA_A76_1286807, cortex_a76, 1286807 report_errata ERRATA_A76_1791580, cortex_a76, 1791580 - report_errata ERRATA_A76_1165522, cortex_a76, 1165522 report_errata ERRATA_A76_1868343, cortex_a76, 1868343 report_errata ERRATA_A76_1946160, cortex_a76, 1946160 + report_errata ERRATA_A76_2743102, cortex_a76, 2743102 report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639 report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953 report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184 diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S index e7365e28c..2882df7bd 100644 --- a/lib/cpus/aarch64/cortex_a77.S +++ b/lib/cpus/aarch64/cortex_a77.S @@ -199,6 +199,58 @@ func check_errata_1791578 b cpu_rev_var_ls endfunc check_errata_1791578 + /* -------------------------------------------------- + * Errata Workaround for Cortex A77 Errata #2356587. + * This applies to revisions r0p0, r1p0, and r1p1 and is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a77_2356587_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2356587 + cbz x0, 1f + + /* Set bit 0 in ACTLR2_EL1 */ + mrs x1, CORTEX_A77_ACTLR2_EL1 + orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0 + msr CORTEX_A77_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_a77_2356587_wa + +func check_errata_2356587 + /* Applies to r0p0, r1p0, and r1p1 right now */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2356587 + + /* ----------------------------------------------------------------- + * Errata Workaround for Cortex A77 Errata #2743100 + * This applies to revisions r0p0, r1p0, and r1p1 and is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * ----------------------------------------------------------------- + */ +func errata_a77_2743100_wa + mov x17, x30 + bl check_errata_2743100 + cbz x0, 1f + + /* dsb before isb of power down sequence */ + dsb sy +1: + ret x17 +endfunc errata_a77_2743100_wa + +func check_errata_2743100 + /* Applies to r0p0, r1p0, and r1p1 right now */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2743100 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -208,6 +260,35 @@ func check_errata_cve_2022_23960 ret endfunc check_errata_cve_2022_23960 + /* -------------------------------------------------- + * Errata Workaround for Cortex A77 Errata #1800714. + * This applies to revision <= r1p1 of Cortex A77. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a77_1800714_wa + /* Compare x0 against revision <= r1p1 */ + mov x17, x30 + bl check_errata_1800714 + cbz x0, 1f + + /* Disable allocation of splintered pages in the L2 TLB */ + mrs x1, CORTEX_A77_CPUECTLR_EL1 + orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53 + msr CORTEX_A77_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a77_1800714_wa + +func check_errata_1800714 + /* Applies to everything <= r1p1 */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_1800714 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A77. * Shall clobber: x0-x19 @@ -238,6 +319,11 @@ func cortex_a77_reset_func bl errata_a77_1791578_wa #endif +#if ERRATA_A77_2356587 + mov x0, x18 + bl errata_a77_2356587_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* * The Cortex-A77 generic vectors are overridden to apply errata @@ -247,6 +333,11 @@ func cortex_a77_reset_func msr vbar_el3, x0 #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ +#if ERRATA_A77_1800714 + mov x0, x18 + bl errata_a77_1800714_wa +#endif + isb ret x19 endfunc cortex_a77_reset_func @@ -263,6 +354,12 @@ func cortex_a77_core_pwr_dwn mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT msr CORTEX_A77_CPUPWRCTLR_EL1, x0 +#if ERRATA_A77_2743100 + mov x15, x30 + bl cpu_get_rev_var + bl errata_a77_2743100_wa + mov x30, x15 +#endif /* ERRATA_A77_2743100 */ isb ret endfunc cortex_a77_core_pwr_dwn @@ -282,9 +379,12 @@ func cortex_a77_errata_report * checking functions of each errata. */ report_errata ERRATA_A77_1508412, cortex_a77, 1508412 + report_errata ERRATA_A77_1791578, cortex_a77, 1791578 + report_errata ERRATA_A77_1800714, cortex_a77, 1800714 report_errata ERRATA_A77_1925769, cortex_a77, 1925769 report_errata ERRATA_A77_1946167, cortex_a77, 1946167 - report_errata ERRATA_A77_1791578, cortex_a77, 1791578 + report_errata ERRATA_A77_2356587, cortex_a77, 2356587 + report_errata ERRATA_A77_2743100, cortex_a77, 2743100 report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index be94e911f..dd3487ab6 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -17,6 +17,9 @@ #error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +.globl cortex_a78_reset_func +.globl cortex_a78_core_pwr_dwn + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78 #endif /* WORKAROUND_CVE_2022_23960 */ diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S index 0712109bb..49cebfe59 100644 --- a/lib/cpus/aarch64/cortex_a78c.S +++ b/lib/cpus/aarch64/cortex_a78c.S @@ -17,10 +17,141 @@ #error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* -------------------------------------------------- + * Errata Workaround for Cortex A78C Erratum 2376749. + * This applies to revision r0p1 and r0p2 of the A78C + * and is currently open. It is a Cat B erratum. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x4, x17 + * -------------------------------------------------- + */ +func errata_a78c_2376749_wa + /* Check revision */ + mov x17, x30 + bl check_errata_2376749 + cbz x0, 1f + /* Set CPUACTLR2_EL1[0] to 1. */ + mrs x1, CORTEX_A78C_CPUACTLR2_EL1 + orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0 + msr CORTEX_A78C_CPUACTLR2_EL1, x1 +1: + ret x17 +endfunc errata_a78c_2376749_wa + +func check_errata_2376749 + /* Applies to r0p1 and r0p2*/ + mov x1, #0x01 + mov x2, #0x02 + b cpu_rev_var_range +endfunc check_errata_2376749 + +/* -------------------------------------------------- + * Errata Workaround for Cortex A78C Erratum 2395411. + * This applies to revision r0p1 and r0p2 of the A78C + * and is currently open. It is a Cat B erratum. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x4, x17 + * -------------------------------------------------- + */ +func errata_a78c_2395411_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2395411 + cbz x0, 1f + + /* Set CPUACTRL2_EL1[40] to 1. */ + mrs x1, CORTEX_A78C_CPUACTLR2_EL1 + orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40 + msr CORTEX_A78C_CPUACTLR2_EL1, x1 +1: + ret x17 +endfunc errata_a78c_2395411_wa + +func check_errata_2395411 + /* Applies to r0p1 and r0p2 */ + mov x1, #0x01 + mov x2, #0x02 + b cpu_rev_var_range +endfunc check_errata_2395411 + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c #endif /* WORKAROUND_CVE_2022_23960 */ +/* -------------------------------------------------- + * Errata Workaround for A78C Erratum 2132064. + * This applies to revisions r0p1 and r0p2 of A78C + * and is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a78c_2132064_wa + /* Compare x0 against revisions r0p0 - r0p1 */ + mov x17, x30 + bl check_errata_2132064 + cbz x0, 1f + + /* -------------------------------------------------------- + * Place the data prefetcher in the most conservative mode + * to reduce prefetches by writing the following bits to + * the value indicated: ecltr[7:6], PF_MODE = 2'b11 + * -------------------------------------------------------- + */ + mrs x0, CORTEX_A78C_CPUECTLR_EL1 + orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6 + orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7 + msr CORTEX_A78C_CPUECTLR_EL1, x0 + isb +1: + ret x17 +endfunc errata_a78c_2132064_wa + +func check_errata_2132064 + /* Applies to revisions r0p1 and r0p2. */ + mov x1, #CPU_REV(0, 1) + mov x2, #CPU_REV(0, 2) + b cpu_rev_var_range +endfunc check_errata_2132064 + +/* -------------------------------------------------------------------- + * Errata Workaround for A78C Erratum 2242638. + * This applies to revisions r0p1 and r0p2 of the Cortex A78C + * processor and is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------------------------- + */ +func errata_a78c_2242638_wa + /* Compare x0 against revisions r0p1 - r0p2 */ + mov x17, x30 + bl check_errata_2242638 + cbz x0, 1f + + ldr x0, =0x5 + msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 + ldr x0, =0x10F600E000 + msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 + ldr x0, =0x10FF80E000 + msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 + ldr x0, =0x80000000003FF + msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 + + isb +1: + ret x17 +endfunc errata_a78c_2242638_wa + +func check_errata_2242638 + /* Applies to revisions r0p1-r0p2. */ + mov x1, #CPU_REV(0, 1) + mov x2, #CPU_REV(0, 2) + b cpu_rev_var_range +endfunc check_errata_2242638 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -35,6 +166,30 @@ endfunc check_errata_cve_2022_23960 * ------------------------------------------------- */ func cortex_a78c_reset_func + mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_A78C_2132064 + mov x0, x18 + bl errata_a78c_2132064_wa +#endif + +#if ERRATA_A78C_2242638 + mov x0, x18 + bl errata_a78c_2242638_wa +#endif + +#if ERRATA_A78C_2376749 + mov x0, x18 + bl errata_a78c_2376749_wa +#endif + +#if ERRATA_A78C_2395411 + mov x0, x18 + bl errata_a78c_2395411_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* * The Cortex-A78c generic vectors are overridden to apply errata @@ -43,8 +198,9 @@ func cortex_a78c_reset_func adr x0, wa_cve_vbar_cortex_a78c msr vbar_el3, x0 #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ + isb - ret + ret x19 endfunc cortex_a78c_reset_func /* ---------------------------------------------------- @@ -77,6 +233,10 @@ func cortex_a78c_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 + report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638 + report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749 + report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411 report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/aarch64/cortex_hunter_elp_arm.S b/lib/cpus/aarch64/cortex_hunter_elp_arm.S new file mode 100644 index 000000000..5f86d4e2a --- /dev/null +++ b/lib/cpus/aarch64/cortex_hunter_elp_arm.S @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_hunter_elp_arm.h> +#include <cpu_macros.S> +#include <plat_macros.S> +#include "wa_cve_2022_23960_bhb_vector.S" + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Hunter ELP must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Hunter ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +#if WORKAROUND_CVE_2022_23960 + wa_cve_2022_23960_bhb_vector_table CORTEX_HUNTER_ELP_ARM_BHB_LOOP_COUNT, cortex_hunter_elp_arm +#endif /* WORKAROUND_CVE_2022_23960 */ + +func check_errata_cve_2022_23960 +#if WORKAROUND_CVE_2022_23960 + mov x0, #ERRATA_APPLIES +#else + mov x0, #ERRATA_MISSING +#endif + ret +endfunc check_errata_cve_2022_23960 + +func cortex_hunter_elp_arm_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + +#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 + /* + * The Cortex Hunter ELP generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + adr x0, wa_cve_vbar_cortex_hunter_elp_arm + msr vbar_el3, x0 +#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ + + isb + ret +endfunc cortex_hunter_elp_arm_reset_func + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_hunter_elp_arm_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_hunter_elp_arm_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex Hunter ELP. Must follow AAPCS. + */ +func cortex_hunter_elp_arm_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata WORKAROUND_CVE_2022_23960, cortex_hunter_elp_arm, cve_2022_23960 + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_hunter_elp_arm_errata_report +#endif + + /* --------------------------------------------- + * This function provides Cortex Hunter ELP-specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_hunter_elp_arm_regs, "aS" +cortex_hunter_elp_arm_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_hunter_elp_arm_cpu_reg_dump + adr x6, cortex_hunter_elp_arm_regs + mrs x8, CORTEX_HUNTER_ELP_ARM_CPUECTLR_EL1 + ret +endfunc cortex_hunter_elp_arm_cpu_reg_dump + +declare_cpu_ops cortex_hunter_elp_arm, CORTEX_HUNTER_ELP_ARM_MIDR, \ + cortex_hunter_elp_arm_reset_func, \ + cortex_hunter_elp_arm_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_makalu_elp_arm.S b/lib/cpus/aarch64/cortex_makalu_elp_arm.S deleted file mode 100644 index f4d2df09c..000000000 --- a/lib/cpus/aarch64/cortex_makalu_elp_arm.S +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <asm_macros.S> -#include <common/bl_common.h> -#include <cortex_makalu_elp_arm.h> -#include <cpu_macros.S> -#include <plat_macros.S> -#include "wa_cve_2022_23960_bhb_vector.S" - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - -#if WORKAROUND_CVE_2022_23960 - wa_cve_2022_23960_bhb_vector_table CORTEX_MAKALU_ELP_ARM_BHB_LOOP_COUNT, cortex_makalu_elp_arm -#endif /* WORKAROUND_CVE_2022_23960 */ - - /* ---------------------------------------------------- - * HW will do the cache maintenance while powering down - * ---------------------------------------------------- - */ -func cortex_makalu_elp_arm_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_makalu_elp_arm_core_pwr_dwn - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - -func cortex_makalu_elp_arm_reset_func - /* Disable speculative loads */ - msr SSBS, xzr - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Cortex Makalu ELP generic vectors are overridden to apply - * errata mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_cortex_makalu_elp_arm - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret -endfunc cortex_makalu_elp_arm_reset_func - -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Makalu ELP. Must follow AAPCS. - */ -func cortex_makalu_elp_arm_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata WORKAROUND_CVE_2022_23960, cortex_makalu_elp_arm, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_makalu_elp_arm_errata_report -#endif - - /* --------------------------------------------- - * This function provides Cortex Makalu ELP- - * specific register information for crash - * reporting. It needs to return with x6 - * pointing to a list of register names in ascii - * and x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_makalu_elp_arm_regs, "aS" -cortex_makalu_elp_arm_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_makalu_elp_arm_cpu_reg_dump - adr x6, cortex_makalu_elp_arm_regs - mrs x8, CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 - ret -endfunc cortex_makalu_elp_arm_cpu_reg_dump - -declare_cpu_ops cortex_makalu_elp_arm, CORTEX_MAKALU_ELP_ARM_MIDR, \ - cortex_makalu_elp_arm_reset_func, \ - cortex_makalu_elp_arm_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index 3e0810ba0..c810be6b0 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -267,6 +267,34 @@ func check_errata_2147715 b cpu_rev_var_range endfunc check_errata_2147715 +/* ------------------------------------------------------- + * Errata Workaround for Cortex-X2 Erratum 2371105. + * This applies to revisions <= r2p0 and is fixed in r2p1. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * ------------------------------------------------------- + */ +func errata_x2_2371105_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2371105 + cbz x0, 1f + + /* Set bit 40 in CPUACTLR2_EL1 */ + mrs x1, CORTEX_X2_CPUACTLR2_EL1 + orr x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40 + msr CORTEX_X2_CPUACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_x2_2371105_wa + +func check_errata_2371105 + /* Applies to <= r2p0. */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2371105 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -304,6 +332,7 @@ func cortex_x2_errata_report report_errata ERRATA_X2_2083908, cortex_x2, 2083908 report_errata ERRATA_X2_2147715, cortex_x2, 2147715 report_errata ERRATA_X2_2216384, cortex_x2, 2216384 + report_errata ERRATA_X2_2371105, cortex_x2, 2371105 report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960 report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941 @@ -361,6 +390,11 @@ func cortex_x2_reset_func bl errata_x2_2147715_wa #endif +#if ERRATA_X2_2371105 + mov x0, x18 + bl errata_x2_2371105_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* * The Cortex-X2 generic vectors are overridden to apply errata diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S new file mode 100644 index 000000000..bf1b6ec4a --- /dev/null +++ b/lib/cpus/aarch64/cortex_x3.S @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_x3.h> +#include <cpu_macros.S> +#include <plat_macros.S> +#include "wa_cve_2022_23960_bhb_vector.S" + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +#if WORKAROUND_CVE_2022_23960 + wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 +#endif /* WORKAROUND_CVE_2022_23960 */ + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_x3_core_pwr_dwn +#if ERRATA_X3_2313909 + mov x15, x30 + bl cpu_get_rev_var + bl errata_cortex_x3_2313909_wa + mov x30, x15 +#endif /* ERRATA_X3_2313909 */ + + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_X3_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_x3_core_pwr_dwn + +func check_errata_cve_2022_23960 +#if WORKAROUND_CVE_2022_23960 + mov x0, #ERRATA_APPLIES +#else + mov x0, #ERRATA_MISSING +#endif + ret +endfunc check_errata_cve_2022_23960 + +func cortex_x3_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + +#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 + /* + * The Cortex-X3 generic vectors are overridden to apply + * errata mitigation on exception entry from lower ELs. + */ + adr x0, wa_cve_vbar_cortex_x3 + msr vbar_el3, x0 +#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ + + isb + ret +endfunc cortex_x3_reset_func + +/* ---------------------------------------------------------------------- + * Errata Workaround for Cortex-X3 Erratum 2313909 on power down request. + * This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * ---------------------------------------------------------------------- + */ +func errata_cortex_x3_2313909_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2313909 + cbz x0, 1f + + /* Set bit 36 in ACTLR2_EL1 */ + mrs x1, CORTEX_X3_CPUACTLR2_EL1 + orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36 + msr CORTEX_X3_CPUACTLR2_EL1, x1 +1: + ret x17 +endfunc errata_cortex_x3_2313909_wa + +func check_errata_2313909 + /* Applies to r0p0 and r1p0 */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_2313909 + +#if REPORT_ERRATA + /* + * Errata printing function for Cortex-X3. Must follow AAPCS. + */ +func cortex_x3_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_X3_2313909, cortex_x3, 2313909 + report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960 + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_x3_errata_report +#endif + + /* --------------------------------------------- + * This function provides Cortex-X3- + * specific register information for crash + * reporting. It needs to return with x6 + * pointing to a list of register names in ascii + * and x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_x3_regs, "aS" +cortex_x3_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_x3_cpu_reg_dump + adr x6, cortex_x3_regs + mrs x8, CORTEX_X3_CPUECTLR_EL1 + ret +endfunc cortex_x3_cpu_reg_dump + +declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ + cortex_x3_reset_func, \ + cortex_x3_core_pwr_dwn diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index b75b0c17f..ec62519f5 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -468,6 +468,30 @@ func check_errata_1946160 b cpu_rev_var_range endfunc check_errata_1946160 + /* ---------------------------------------------------- + * Errata Workaround for Neoverse N1 Errata #2743102 + * This applies to revisions <= r4p1 and is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * ---------------------------------------------------- + */ +func errata_n1_2743102_wa + mov x17, x30 + bl check_errata_2743102 + cbz x0, 1f + + /* dsb before isb of power down sequence */ + dsb sy +1: + ret x17 +endfunc errata_n1_2743102_wa + +func check_errata_2743102 + /* Applies to all revisions <= r4p1 */ + mov x1, #0x41 + b cpu_rev_var_ls +endfunc check_errata_2743102 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -613,6 +637,12 @@ func neoverse_n1_core_pwr_dwn mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 +#if ERRATA_N1_2743102 + mov x15, x30 + bl cpu_get_rev_var + bl errata_n1_2743102_wa + mov x30, x15 +#endif /* ERRATA_N1_2743102 */ isb ret endfunc neoverse_n1_core_pwr_dwn @@ -645,6 +675,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1542419, neoverse_n1, 1542419 report_errata ERRATA_N1_1868343, neoverse_n1, 1868343 report_errata ERRATA_N1_1946160, neoverse_n1, 1946160 + report_errata ERRATA_N1_2743102, neoverse_n1, 2743102 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960 diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 5b796dc07..5861decbb 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -338,6 +338,96 @@ func check_errata_2280757 b cpu_rev_var_ls endfunc check_errata_2280757 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2326639. + * This applies to revision r0p0 of Neoverse N2, + * fixed in r0p1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2326639_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2326639 + cbz x0, 1f + + /* Set bit 36 in ACTLR2_EL1 */ + mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 + orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 + msr NEOVERSE_N2_CPUACTLR2_EL1, x1 +1: + ret x17 +endfunc errata_n2_2326639_wa + +func check_errata_2326639 + /* Applies to r0p0, fixed in r0p1 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2326639 + +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2376738. + * This applies to revision r0p0 of Neoverse N2, + * fixed in r0p1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current CPU. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2376738_wa + mov x17, x30 + bl check_errata_2376738 + cbz x0, 1f + + /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM + * ST to behave like PLD/PFRM LD and not cause + * invalidations to other PE caches. + */ + mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 + msr NEOVERSE_N2_CPUACTLR2_EL1, x1 +1: + ret x17 +endfunc errata_n2_2376738_wa + +func check_errata_2376738 + /* Applies to r0p0, fixed in r0p1 */ + mov x1, 0x00 + b cpu_rev_var_ls +endfunc check_errata_2376738 + +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2388450. + * This applies to revision r0p0 of Neoverse N2, + * fixed in r0p1. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2388450_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2388450 + cbz x0, 1f + + /*Set bit 40 in ACTLR2_EL1 */ + mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 + orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 + msr NEOVERSE_N2_CPUACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_n2_2388450_wa + +func check_errata_2388450 + /* Applies to r0p0, fixed in r0p1 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2388450 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -367,6 +457,10 @@ func neoverse_n2_reset_func orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 + /* Get the CPU revision and stash it in x18. */ + bl cpu_get_rev_var + mov x18, x0 + #if ERRATA_DSU_2313941 bl errata_dsu_2313941_wa #endif @@ -417,6 +511,16 @@ func neoverse_n2_reset_func bl errata_n2_2280757_wa #endif +#if ERRATA_N2_2376738 + mov x0, x18 + bl errata_n2_2376738_wa +#endif + +#if ERRATA_N2_2388450 + mov x0, x18 + bl errata_n2_2388450_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -438,9 +542,6 @@ func neoverse_n2_reset_func msr NEOVERSE_N2_CPUECTLR_EL1, x0 #endif - bl cpu_get_rev_var - mov x18, x0 - #if ERRATA_N2_2002655 mov x0, x18 bl errata_n2_2002655_wa @@ -460,6 +561,13 @@ func neoverse_n2_reset_func endfunc neoverse_n2_reset_func func neoverse_n2_core_pwr_dwn +#if ERRATA_N2_2326639 + mov x15, x30 + bl cpu_get_rev_var + bl errata_n2_2326639_wa + mov x30, x15 +#endif /* ERRATA_N2_2326639 */ + /* --------------------------------------------------- * Enable CPU power down bit in power control register * No need to do cache maintenance here. @@ -496,6 +604,9 @@ func neoverse_n2_errata_report report_errata ERRATA_N2_2138958, neoverse_n2, 2138958 report_errata ERRATA_N2_2242400, neoverse_n2, 2242400 report_errata ERRATA_N2_2280757, neoverse_n2, 2280757 + report_errata ERRATA_N2_2326639, neoverse_n2, 2326639 + report_errata ERRATA_N2_2376738, neoverse_n2, 2376738 + report_errata ERRATA_N2_2388450, neoverse_n2, 2388450 report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960 report_errata ERRATA_DSU_2313941, neoverse_n2, dsu_2313941 diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 6adb3a89d..3282fbc6a 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -27,6 +27,82 @@ #endif /* WORKAROUND_CVE_2022_23960 */ /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #1618635. + * This applies to revision r0p0 and is fixed in + * r1p0. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_1618635_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_1618635 + cbz x0, 1f + + /* Inserts a DMB SY before and after MRS PAR_EL1 */ + ldr x0, =0x0 + msr NEOVERSE_V1_CPUPSELR_EL3, x0 + ldr x0, = 0xEE070F14 + msr NEOVERSE_V1_CPUPOR_EL3, x0 + ldr x0, = 0xFFFF0FFF + msr NEOVERSE_V1_CPUPMR_EL3, x0 + ldr x0, =0x4005027FF + msr NEOVERSE_V1_CPUPCR_EL3, x0 + + /* Inserts a DMB SY before STREX imm offset */ + ldr x0, =0x1 + msr NEOVERSE_V1_CPUPSELR_EL3, x0 + ldr x0, =0x00e8400000 + msr NEOVERSE_V1_CPUPOR_EL3, x0 + ldr x0, =0x00fff00000 + msr NEOVERSE_V1_CPUPMR_EL3, x0 + ldr x0, = 0x4001027FF + msr NEOVERSE_V1_CPUPCR_EL3, x0 + + /* Inserts a DMB SY before STREX[BHD}/STLEX* */ + ldr x0, =0x2 + msr NEOVERSE_V1_CPUPSELR_EL3, x0 + ldr x0, =0x00e8c00040 + msr NEOVERSE_V1_CPUPOR_EL3, x0 + ldr x0, =0x00fff00040 + msr NEOVERSE_V1_CPUPMR_EL3, x0 + ldr x0, = 0x4001027FF + msr NEOVERSE_V1_CPUPCR_EL3, x0 + + /* Inserts a DMB SY after STREX imm offset */ + ldr x0, =0x3 + msr NEOVERSE_V1_CPUPSELR_EL3, x0 + ldr x0, =0x00e8400000 + msr NEOVERSE_V1_CPUPOR_EL3, x0 + ldr x0, =0x00fff00000 + msr NEOVERSE_V1_CPUPMR_EL3, x0 + ldr x0, = 0x4004027FF + msr NEOVERSE_V1_CPUPCR_EL3, x0 + + /* Inserts a DMB SY after STREX[BHD}/STLEX* */ + ldr x0, =0x4 + msr NEOVERSE_V1_CPUPSELR_EL3, x0 + ldr x0, =0x00e8c00040 + msr NEOVERSE_V1_CPUPOR_EL3, x0 + ldr x0, =0x00fff00040 + msr NEOVERSE_V1_CPUPMR_EL3, x0 + ldr x0, = 0x4004027FF + msr NEOVERSE_V1_CPUPCR_EL3, x0 + + /* Synchronize to enable patches */ + isb +1: + ret x17 +endfunc errata_neoverse_v1_1618635_wa + +func check_errata_1618635 + /* Applies to revision r0p0. */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_1618635 + + /* -------------------------------------------------- * Errata Workaround for Neoverse V1 Errata #1774420. * This applies to revisions r0p0 and r1p0, fixed in r1p1. * x0: variant[4:7] and revision[0:3] of current cpu. @@ -330,6 +406,62 @@ func check_errata_2216392 b cpu_rev_var_range endfunc check_errata_2216392 + /* ----------------------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #2294912. + * This applies to revisions r0p0, r1p0, and r1p1 and is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * ----------------------------------------------------------------- + */ +func errata_neoverse_v1_2294912_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2294912 + cbz x0, 1f + + /* Set bit 0 in ACTLR2_EL1 */ + mrs x1, NEOVERSE_V1_ACTLR2_EL1 + orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_0 + msr NEOVERSE_V1_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_neoverse_v1_2294912_wa + +func check_errata_2294912 + /* Applies to r0p0, r1p0, and r1p1 right now */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2294912 + + /* --------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #2372203. + * This applies to revisions <= r1p1 and is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * ---------------------------------------------------- + */ +func errata_neoverse_v1_2372203_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2372203 + cbz x0, 1f + + /* Set bit 40 in ACTLR2_EL1 */ + mrs x1, NEOVERSE_V1_ACTLR2_EL1 + orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_40 + msr NEOVERSE_V1_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_neoverse_v1_2372203_wa + +func check_errata_2372203 + /* Applies to <= r1p1. */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2372203 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -369,15 +501,18 @@ func neoverse_v1_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_V1_1618635, neoverse_v1, 1618635 report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 report_errata ERRATA_V1_1852267, neoverse_v1, 1852267 report_errata ERRATA_V1_1925756, neoverse_v1, 1925756 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 report_errata ERRATA_V1_1966096, neoverse_v1, 1966096 - report_errata ERRATA_V1_2139242, neoverse_v1, 2139242 report_errata ERRATA_V1_2108267, neoverse_v1, 2108267 + report_errata ERRATA_V1_2139242, neoverse_v1, 2139242 report_errata ERRATA_V1_2216392, neoverse_v1, 2216392 + report_errata ERRATA_V1_2294912, neoverse_v1, 2294912 + report_errata ERRATA_V1_2372203, neoverse_v1, 2372203 report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960 ldp x8, x30, [sp], #16 @@ -392,6 +527,15 @@ func neoverse_v1_reset_func msr SSBS, xzr isb + /* Get the CPU revision and stash it in x18. */ + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_V1_1618635 + mov x0, x18 + bl errata_neoverse_v1_1618635_wa +#endif + #if ERRATA_V1_1774420 mov x0, x18 bl errata_neoverse_v1_1774420_wa @@ -437,6 +581,16 @@ func neoverse_v1_reset_func bl errata_neoverse_v1_2216392_wa #endif +#if ERRATA_V1_2294912 + mov x0, x18 + bl errata_neoverse_v1_2294912_wa +#endif + +#if ERRATA_V1_2372203 + mov x0, x18 + bl errata_neoverse_v1_2372203_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* * The Neoverse-V1 generic vectors are overridden to apply errata diff --git a/lib/cpus/aarch64/neoverse_demeter.S b/lib/cpus/aarch64/neoverse_v2.S index 41cb4ee46..4ea887ff6 100644 --- a/lib/cpus/aarch64/neoverse_demeter.S +++ b/lib/cpus/aarch64/neoverse_v2.S @@ -7,40 +7,40 @@ #include <arch.h> #include <asm_macros.S> #include <common/bl_common.h> -#include <neoverse_demeter.h> +#include <neoverse_v2.h> #include <cpu_macros.S> #include <plat_macros.S> #include "wa_cve_2022_23960_bhb_vector.S" /* Hardware handled coherency */ #if HW_ASSISTED_COHERENCY == 0 -#error "Neoverse Demeter must be compiled with HW_ASSISTED_COHERENCY enabled" +#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif /* 64-bit only core */ #if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Neoverse Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif #if WORKAROUND_CVE_2022_23960 - wa_cve_2022_23960_bhb_vector_table NEOVERSE_DEMETER_BHB_LOOP_COUNT, neoverse_demeter + wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 #endif /* WORKAROUND_CVE_2022_23960 */ /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- */ -func neoverse_demeter_core_pwr_dwn +func neoverse_v2_core_pwr_dwn /* --------------------------------------------------- * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, NEOVERSE_DEMETER_CPUPWRCTLR_EL1 - orr x0, x0, #NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr NEOVERSE_DEMETER_CPUPWRCTLR_EL1, x0 + mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 + orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 isb ret -endfunc neoverse_demeter_core_pwr_dwn +endfunc neoverse_v2_core_pwr_dwn func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 @@ -51,27 +51,27 @@ func check_errata_cve_2022_23960 ret endfunc check_errata_cve_2022_23960 -func neoverse_demeter_reset_func +func neoverse_v2_reset_func /* Disable speculative loads */ msr SSBS, xzr #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* - * The Neoverse Demeter vectors are overridden to apply + * The Neoverse V2 vectors are overridden to apply * errata mitigation on exception entry from lower ELs. */ - adr x0, wa_cve_vbar_neoverse_demeter + adr x0, wa_cve_vbar_neoverse_v2 msr vbar_el3, x0 #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ isb ret -endfunc neoverse_demeter_reset_func +endfunc neoverse_v2_reset_func #if REPORT_ERRATA /* - * Errata printing function for Neoverse Demeter. Must follow AAPCS. + * Errata printing function for Neoverse V2. Must follow AAPCS. */ -func neoverse_demeter_errata_report +func neoverse_v2_errata_report stp x8, x30, [sp, #-16]! bl cpu_get_rev_var @@ -81,15 +81,15 @@ func neoverse_demeter_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ - report_errata WORKAROUND_CVE_2022_23960, neoverse_demeter, cve_2022_23960 + report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960 ldp x8, x30, [sp], #16 ret -endfunc neoverse_demeter_errata_report +endfunc neoverse_v2_errata_report #endif /* --------------------------------------------- - * This function provides Neoverse Demeter- + * This function provides Neoverse V2- * specific register information for crash * reporting. It needs to return with x6 * pointing to a list of register names in ascii @@ -97,16 +97,16 @@ endfunc neoverse_demeter_errata_report * reported. * --------------------------------------------- */ -.section .rodata.neoverse_demeter_regs, "aS" -neoverse_demeter_regs: /* The ascii list of register names to be reported */ +.section .rodata.neoverse_v2_regs, "aS" +neoverse_v2_regs: /* The ascii list of register names to be reported */ .asciz "cpuectlr_el1", "" -func neoverse_demeter_cpu_reg_dump - adr x6, neoverse_demeter_regs - mrs x8, NEOVERSE_DEMETER_CPUECTLR_EL1 +func neoverse_v2_cpu_reg_dump + adr x6, neoverse_v2_regs + mrs x8, NEOVERSE_V2_CPUECTLR_EL1 ret -endfunc neoverse_demeter_cpu_reg_dump +endfunc neoverse_v2_cpu_reg_dump -declare_cpu_ops neoverse_demeter, NEOVERSE_DEMETER_MIDR, \ - neoverse_demeter_reset_func, \ - neoverse_demeter_core_pwr_dwn +declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ + neoverse_v2_reset_func, \ + neoverse_v2_core_pwr_dwn diff --git a/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S b/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S index e0e41cc47..ceb93f139 100644 --- a/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S +++ b/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S @@ -9,11 +9,11 @@ #if WORKAROUND_CVE_2022_23960 /* * This macro applies the mitigation for CVE-2022-23960. - * The macro saves x2-x3 to the CPU context. + * The macro saves x2 to the CPU context. * SP should point to the CPU context. */ .macro apply_cve_2022_23960_bhb_wa _bhb_loop_count - stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + str x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] /* CVE-BHB-NUM loop count */ mov x2, \_bhb_loop_count @@ -24,8 +24,7 @@ 2: subs x2, x2, #1 bne 1b - dsb sy - isb - ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + speculation_barrier + ldr x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] .endm #endif /* WORKAROUND_CVE_2022_23960 */ diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index e14bb24f5..f19c16e49 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -287,6 +287,10 @@ ERRATA_A76_1868343 ?=0 # only to revisions r3p0 - r4p1 of the Cortex A76 cpu. ERRATA_A76_1946160 ?=0 +# Flag to apply erratum 2743102 workaround during powerdown. This erratum +# applies to all revisions <= r4p1 of the Cortex A76 cpu and is still open. +ERRATA_A76_2743102 ?=0 + # Flag to apply erratum 1508412 workaround during reset. This erratum applies # only to revision <= r1p0 of the Cortex A77 cpu. ERRATA_A77_1508412 ?=0 @@ -303,6 +307,18 @@ ERRATA_A77_1946167 ?=0 # to revisions r0p0, r1p0, and r1p1, it is still open. ERRATA_A77_1791578 ?=0 +# Flag to apply erratum 2356587 workaround during reset. This erratum applies +# to revisions r0p0, r1p0, and r1p1, it is still open. +ERRATA_A77_2356587 ?=0 + +# Flag to apply erratum 1800714 workaround during reset. This erratum applies +# to revisions <= r1p1 of the Cortex A77 cpu. +ERRATA_A77_1800714 ?=0 + +# Flag to apply erratum 2743100 workaround during power down. This erratum +# applies to revisions r0p0, r1p0, and r1p1, it is still open. +ERRATA_A77_2743100 ?=0 + # Flag to apply erratum 1688305 workaround during reset. This erratum applies # to revisions r0p0 - r1p0 of the A78 cpu. ERRATA_A78_1688305 ?=0 @@ -357,6 +373,22 @@ ERRATA_A78_AE_2376748 ?=0 # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. ERRATA_A78_AE_2395408 ?=0 +# Flag to apply erratum 2132064 workaround during reset. This erratum applies +# to revisions r0p1 and r0p2 of the A78C cpu. It is still open. +ERRATA_A78C_2132064 ?=0 + +# Flag to apply erratum 2242638 workaround during reset. This erratum applies +# to revisions r0p1 and r0p2 of the A78C cpu. It is still open. +ERRATA_A78C_2242638 ?=0 + +# Flag to apply erratum 2376749 workaround during reset. This erratum applies +# to revisions r0p1 and r0p2 of the A78C cpu. It is still open. +ERRATA_A78C_2376749 ?=0 + +# Flag to apply erratum 2395411 workaround during reset. This erratum applies +# to revisions r0p1 and r0p2 of the A78C cpu. It is still open. +ERRATA_A78C_2395411 ?=0 + # Flag to apply erratum 1821534 workaround during reset. This erratum applies # to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1. ERRATA_X1_1821534 ?=0 @@ -426,10 +458,18 @@ ERRATA_N1_1868343 ?=0 # exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround. ERRATA_N1_1946160 ?=0 +# Flag to apply erratum 2743102 workaround during powerdown. This erratum +# applies to all revisions <= r4p1 of the Neoverse N1 cpu and is still open. +ERRATA_N1_2743102 ?=0 + # Flag to apply erratum 2002655 workaround during reset. This erratum applies # to revisions r0p0 of the Neoverse-N2 cpu, it is still open. ERRATA_N2_2002655 ?=0 +# Flag to apply erratum 1618635 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse V1 cpu and was fixed in the revision r1p0. +ERRATA_V1_1618635 ?=0 + # Flag to apply erratum 1774420 workaround during reset. This erratum applies # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. ERRATA_V1_1774420 ?=0 @@ -468,6 +508,14 @@ ERRATA_V1_2108267 ?=0 # issue exists in r0p0 as well but there is no workaround for that revision. ERRATA_V1_2216392 ?=0 +# Flag to apply erratum 2294912 workaround during reset. This erratum applies +# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. +ERRATA_V1_2294912 ?=0 + +# Flag to apply erratum 2372203 workaround during reset. This erratum applies +# to revisions r0p0, r1p0 and r1p1 of the Neoverse V1 cpu and is still open. +ERRATA_V1_2372203 ?=0 + # Flag to apply erratum 1987031 workaround during reset. This erratum applies # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_1987031 ?=0 @@ -500,14 +548,30 @@ ERRATA_A710_2267065 ?=0 # to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. ERRATA_A710_2136059 ?=0 +# Flag to apply erratum 2147715 workaround during reset. This erratum applies +# to revision r2p0 of the Cortex-A710 CPU and is fixed in revision r2p1. +ERRATA_A710_2147715 ?=0 + +# Flag to apply erratum 2216384 workaround during reset. This erratum applies +# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. +ERRATA_A710_2216384 ?=0 + # Flag to apply erratum 2282622 workaround during reset. This erratum applies # to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. ERRATA_A710_2282622 ?=0 +# Flag to apply erratum 2291219 workaround during reset. This erratum applies +# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. +ERRATA_A710_2291219 ?=0 + # Flag to apply erratum 2008768 workaround during reset. This erratum applies # to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. ERRATA_A710_2008768 ?=0 +# Flag to apply erratum 2371105 workaround during reset. This erratum applies +# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1. +ERRATA_A710_2371105 ?=0 + # Flag to apply erratum 2067956 workaround during reset. This erratum applies # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2067956 ?=0 @@ -544,6 +608,18 @@ ERRATA_N2_2242400 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2280757 ?=0 +# Flag to apply erraturm 2326639 workaroud during powerdown. This erratum +# applies to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. +ERRATA_N2_2326639 ?=0 + +# Flag to apply erratum 2376738 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1. +ERRATA_N2_2376738 ?=0 + +# Flag to apply erratum 2388450 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1. +ERRATA_N2_2388450 ?=0 + # Flag to apply erratum 2002765 workaround during reset. This erratum applies # to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open. ERRATA_X2_2002765 ?=0 @@ -575,6 +651,14 @@ ERRATA_X2_2216384 ?=0 # only to revision r2p0 of the Cortex-X2 cpu, it is fixed in r2p1. ERRATA_X2_2147715 ?=0 +# Flag to apply erratum 2371105 workaround during reset. This erratum applies +# to revision r0p0, r1p0 and r2p0 of the Cortex-X2 cpu and is fixed in r2p1. +ERRATA_X2_2371105 ?=0 + +# Flag to apply erratum 2313909 workaround on powerdown. This erratum applies +# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1. +ERRATA_X3_2313909 ?=0 + # Flag to apply erratum 1922240 workaround during reset. This erratum applies # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1. ERRATA_A510_1922240 ?=0 @@ -605,6 +689,19 @@ ERRATA_A510_2218950 ?=0 # to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1. ERRATA_A510_2172148 ?=0 +# Flag to apply erratum 2347730 workaround during reset. This erratum applies +# to revisions r0p0, r0p1, r0p2, r0p3, r1p0 and r1p1 of the Cortex-A510 CPU, +# and is fixed in r1p2. +ERRATA_A510_2347730 ?=0 + +# Flag to apply erratum 2371937 workaround during reset. This erratum applies +# to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is fixed in r1p2. +ERRATA_A510_2371937 ?=0 + +# Flag to apply erratum 2666669 workaround during reset. This erratum applies +# to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is fixed in r1p2. +ERRATA_A510_2666669 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -827,6 +924,10 @@ $(eval $(call add_define,ERRATA_A76_1868343)) $(eval $(call assert_boolean,ERRATA_A76_1946160)) $(eval $(call add_define,ERRATA_A76_1946160)) +# Process ERRATA_A76_2743102 flag +$(eval $(call assert_boolean,ERRATA_A76_2743102)) +$(eval $(call add_define,ERRATA_A76_2743102)) + # Process ERRATA_A77_1508412 flag $(eval $(call assert_boolean,ERRATA_A77_1508412)) $(eval $(call add_define,ERRATA_A77_1508412)) @@ -843,6 +944,18 @@ $(eval $(call add_define,ERRATA_A77_1946167)) $(eval $(call assert_boolean,ERRATA_A77_1791578)) $(eval $(call add_define,ERRATA_A77_1791578)) +# Process ERRATA_A77_2356587 flag +$(eval $(call assert_boolean,ERRATA_A77_2356587)) +$(eval $(call add_define,ERRATA_A77_2356587)) + +# Process ERRATA_A77_1800714 flag +$(eval $(call assert_boolean,ERRATA_A77_1800714)) +$(eval $(call add_define,ERRATA_A77_1800714)) + +# Process ERRATA_A77_2743100 flag +$(eval $(call assert_boolean,ERRATA_A77_2743100)) +$(eval $(call add_define,ERRATA_A77_2743100)) + # Process ERRATA_A78_1688305 flag $(eval $(call assert_boolean,ERRATA_A78_1688305)) $(eval $(call add_define,ERRATA_A78_1688305)) @@ -895,6 +1008,22 @@ $(eval $(call add_define,ERRATA_A78_AE_2376748)) $(eval $(call assert_boolean,ERRATA_A78_AE_2395408)) $(eval $(call add_define,ERRATA_A78_AE_2395408)) +# Process ERRATA_A78C_2132064 flag +$(eval $(call assert_boolean,ERRATA_A78C_2132064)) +$(eval $(call add_define,ERRATA_A78C_2132064)) + +# Process ERRATA_A78C_2242638 flag +$(eval $(call assert_boolean,ERRATA_A78C_2242638)) +$(eval $(call add_define,ERRATA_A78C_2242638)) + +# Process ERRATA_A78C_2376749 flag +$(eval $(call assert_boolean,ERRATA_A78C_2376749)) +$(eval $(call add_define,ERRATA_A78C_2376749)) + +# Process ERRATA_A78C_2395411 flag +$(eval $(call assert_boolean,ERRATA_A78C_2395411)) +$(eval $(call add_define,ERRATA_A78C_2395411)) + # Process ERRATA_X1_1821534 flag $(eval $(call assert_boolean,ERRATA_X1_1821534)) $(eval $(call add_define,ERRATA_X1_1821534)) @@ -963,10 +1092,18 @@ $(eval $(call add_define,ERRATA_N1_1868343)) $(eval $(call assert_boolean,ERRATA_N1_1946160)) $(eval $(call add_define,ERRATA_N1_1946160)) +# Process ERRATA_N1_2743102 flag +$(eval $(call assert_boolean,ERRATA_N1_2743102)) +$(eval $(call add_define,ERRATA_N1_2743102)) +# # Process ERRATA_N2_2002655 flag $(eval $(call assert_boolean,ERRATA_N2_2002655)) $(eval $(call add_define,ERRATA_N2_2002655)) +# Process ERRATA_V1_1618635 flag +$(eval $(call assert_boolean,ERRATA_V1_1618635)) +$(eval $(call add_define,ERRATA_V1_1618635)) + # Process ERRATA_V1_1774420 flag $(eval $(call assert_boolean,ERRATA_V1_1774420)) $(eval $(call add_define,ERRATA_V1_1774420)) @@ -1003,6 +1140,14 @@ $(eval $(call add_define,ERRATA_V1_2108267)) $(eval $(call assert_boolean,ERRATA_V1_2216392)) $(eval $(call add_define,ERRATA_V1_2216392)) +# Process ERRATA_V1_2294912 flag +$(eval $(call assert_boolean,ERRATA_V1_2294912)) +$(eval $(call add_define,ERRATA_V1_2294912)) + +# Process ERRATA_V1_2372203 flag +$(eval $(call assert_boolean,ERRATA_V1_2372203)) +$(eval $(call add_define,ERRATA_V1_2372203)) + # Process ERRATA_A710_1987031 flag $(eval $(call assert_boolean,ERRATA_A710_1987031)) $(eval $(call add_define,ERRATA_A710_1987031)) @@ -1035,14 +1180,30 @@ $(eval $(call add_define,ERRATA_A710_2267065)) $(eval $(call assert_boolean,ERRATA_A710_2136059)) $(eval $(call add_define,ERRATA_A710_2136059)) +# Process ERRATA_A710_2147715 flag +$(eval $(call assert_boolean,ERRATA_A710_2147715)) +$(eval $(call add_define,ERRATA_A710_2147715)) + +# Process ERRATA_A710_2216384 flag +$(eval $(call assert_boolean,ERRATA_A710_2216384)) +$(eval $(call add_define,ERRATA_A710_2216384)) + # Process ERRATA_A710_2282622 flag $(eval $(call assert_boolean,ERRATA_A710_2282622)) $(eval $(call add_define,ERRATA_A710_2282622)) +# Process ERRATA_A710_2291219 flag +$(eval $(call assert_boolean,ERRATA_A710_2291219)) +$(eval $(call add_define,ERRATA_A710_2291219)) + # Process ERRATA_A710_2008768 flag $(eval $(call assert_boolean,ERRATA_A710_2008768)) $(eval $(call add_define,ERRATA_A710_2008768)) +# Process ERRATA_A710_2371105 flag +$(eval $(call assert_boolean,ERRATA_A710_2371105)) +$(eval $(call add_define,ERRATA_A710_2371105)) + # Process ERRATA_N2_2067956 flag $(eval $(call assert_boolean,ERRATA_N2_2067956)) $(eval $(call add_define,ERRATA_N2_2067956)) @@ -1079,6 +1240,18 @@ $(eval $(call add_define,ERRATA_N2_2242400)) $(eval $(call assert_boolean,ERRATA_N2_2280757)) $(eval $(call add_define,ERRATA_N2_2280757)) +# Process ERRATA_N2_2326639 flag +$(eval $(call assert_boolean,ERRATA_N2_2326639)) +$(eval $(call add_define,ERRATA_N2_2326639)) + +# Process ERRATA_N2_2376738 flag +$(eval $(call assert_boolean,ERRATA_N2_2376738)) +$(eval $(call add_define,ERRATA_N2_2376738)) + +# Process ERRATA_N2_2388450 flag +$(eval $(call assert_boolean,ERRATA_N2_2388450)) +$(eval $(call add_define,ERRATA_N2_2388450)) + # Process ERRATA_X2_2002765 flag $(eval $(call assert_boolean,ERRATA_X2_2002765)) $(eval $(call add_define,ERRATA_X2_2002765)) @@ -1107,6 +1280,14 @@ $(eval $(call add_define,ERRATA_X2_2216384)) $(eval $(call assert_boolean,ERRATA_X2_2147715)) $(eval $(call add_define,ERRATA_X2_2147715)) +# Process ERRATA_X2_2371105 flag +$(eval $(call assert_boolean,ERRATA_X2_2371105)) +$(eval $(call add_define,ERRATA_X2_2371105)) + +# Process ERRATA_X3_2313909 flag +$(eval $(call assert_boolean,ERRATA_X3_2313909)) +$(eval $(call add_define,ERRATA_X3_2313909)) + # Process ERRATA_A510_1922240 flag $(eval $(call assert_boolean,ERRATA_A510_1922240)) $(eval $(call add_define,ERRATA_A510_1922240)) @@ -1135,7 +1316,19 @@ $(eval $(call add_define,ERRATA_A510_2218950)) $(eval $(call assert_boolean,ERRATA_A510_2172148)) $(eval $(call add_define,ERRATA_A510_2172148)) -# Process ERRATA_DSU_798953 flag +# Process ERRATA_A510_2347730 flag +$(eval $(call assert_boolean,ERRATA_A510_2347730)) +$(eval $(call add_define,ERRATA_A510_2347730)) + +# Process ERRATA_A510_2371937 flag +$(eval $(call assert_boolean,ERRATA_A510_2371937)) +$(eval $(call add_define,ERRATA_A510_2371937)) + +# Process ERRATA_A510_2666669 flag +$(eval $(call assert_boolean,ERRATA_A510_2666669)) +$(eval $(call add_define,ERRATA_A510_2666669)) + +#Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 69acc2f9d..6b88a9086 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -11,8 +11,52 @@ #include <el3_common_macros.S> #if CTX_INCLUDE_EL2_REGS - .global el2_sysregs_context_save - .global el2_sysregs_context_restore + .global el2_sysregs_context_save_common + .global el2_sysregs_context_restore_common +#if ENABLE_SPE_FOR_LOWER_ELS + .global el2_sysregs_context_save_spe + .global el2_sysregs_context_restore_spe +#endif /* ENABLE_SPE_FOR_LOWER_ELS */ +#if CTX_INCLUDE_MTE_REGS + .global el2_sysregs_context_save_mte + .global el2_sysregs_context_restore_mte +#endif /* CTX_INCLUDE_MTE_REGS */ +#if ENABLE_MPAM_FOR_LOWER_ELS + .global el2_sysregs_context_save_mpam + .global el2_sysregs_context_restore_mpam +#endif /* ENABLE_MPAM_FOR_LOWER_ELS */ +#if ENABLE_FEAT_FGT + .global el2_sysregs_context_save_fgt + .global el2_sysregs_context_restore_fgt +#endif /* ENABLE_FEAT_FGT */ +#if ENABLE_FEAT_ECV + .global el2_sysregs_context_save_ecv + .global el2_sysregs_context_restore_ecv +#endif /* ENABLE_FEAT_ECV */ +#if ENABLE_FEAT_VHE + .global el2_sysregs_context_save_vhe + .global el2_sysregs_context_restore_vhe +#endif /* ENABLE_FEAT_VHE */ +#if RAS_EXTENSION + .global el2_sysregs_context_save_ras + .global el2_sysregs_context_restore_ras +#endif /* RAS_EXTENSION */ +#if CTX_INCLUDE_NEVE_REGS + .global el2_sysregs_context_save_nv2 + .global el2_sysregs_context_restore_nv2 +#endif /* CTX_INCLUDE_NEVE_REGS */ +#if ENABLE_TRF_FOR_NS + .global el2_sysregs_context_save_trf + .global el2_sysregs_context_restore_trf +#endif /* ENABLE_TRF_FOR_NS */ +#if ENABLE_FEAT_CSV2_2 + .global el2_sysregs_context_save_csv2 + .global el2_sysregs_context_restore_csv2 +#endif /* ENABLE_FEAT_CSV2_2 */ +#if ENABLE_FEAT_HCX + .global el2_sysregs_context_save_hcx + .global el2_sysregs_context_restore_hcx +#endif /* ENABLE_FEAT_HCX */ #endif /* CTX_INCLUDE_EL2_REGS */ .global el1_sysregs_context_save @@ -29,11 +73,16 @@ #if CTX_INCLUDE_EL2_REGS /* ----------------------------------------------------- - * The following function strictly follows the AArch64 + * The following functions strictly follow the AArch64 * PCS to use x9-x16 (temporary caller-saved registers) - * to save EL2 system register context. It assumes that - * 'x0' is pointing to a 'el2_sys_regs' structure where - * the register context will be saved. + * to save/restore EL2 system register context. + * el2_sysregs_context_save/restore_common functions + * save and restore registers that are common to all + * configurations. The rest of the functions save and + * restore EL2 system registers that are present when a + * particular feature is enabled. All functions assume + * that 'x0' is pointing to a 'el2_sys_regs' structure + * where the register context will be saved/restored. * * The following registers are not added. * AMEVCNTVOFF0<n>_EL2 @@ -43,7 +92,7 @@ * ICH_LR<n>_EL2 * ----------------------------------------------------- */ -func el2_sysregs_context_save +func el2_sysregs_context_save_common mrs x9, actlr_el2 mrs x10, afsr0_el2 stp x9, x10, [x0, #CTX_ACTLR_EL2] @@ -88,11 +137,6 @@ func el2_sysregs_context_save mrs x12, mdcr_el2 stp x11, x12, [x0, #CTX_MAIR_EL2] -#if ENABLE_SPE_FOR_LOWER_ELS - mrs x13, PMSCR_EL2 - str x13, [x0, #CTX_PMSCR_EL2] -#endif /* ENABLE_SPE_FOR_LOWER_ELS */ - mrs x14, sctlr_el2 str x14, [x0, #CTX_SCTLR_EL2] @@ -115,128 +159,10 @@ func el2_sysregs_context_save mrs x15, vtcr_el2 mrs x16, vttbr_el2 stp x15, x16, [x0, #CTX_VTCR_EL2] - -#if CTX_INCLUDE_MTE_REGS - mrs x9, TFSR_EL2 - str x9, [x0, #CTX_TFSR_EL2] -#endif /* CTX_INCLUDE_MTE_REGS */ - -#if ENABLE_MPAM_FOR_LOWER_ELS - mrs x10, MPAM2_EL2 - str x10, [x0, #CTX_MPAM2_EL2] - - mrs x11, MPAMHCR_EL2 - mrs x12, MPAMVPM0_EL2 - stp x11, x12, [x0, #CTX_MPAMHCR_EL2] - - mrs x13, MPAMVPM1_EL2 - mrs x14, MPAMVPM2_EL2 - stp x13, x14, [x0, #CTX_MPAMVPM1_EL2] - - mrs x15, MPAMVPM3_EL2 - mrs x16, MPAMVPM4_EL2 - stp x15, x16, [x0, #CTX_MPAMVPM3_EL2] - - mrs x9, MPAMVPM5_EL2 - mrs x10, MPAMVPM6_EL2 - stp x9, x10, [x0, #CTX_MPAMVPM5_EL2] - - mrs x11, MPAMVPM7_EL2 - mrs x12, MPAMVPMV_EL2 - stp x11, x12, [x0, #CTX_MPAMVPM7_EL2] -#endif /* ENABLE_MPAM_FOR_LOWER_ELS */ - -#if ENABLE_FEAT_FGT - mrs x13, HDFGRTR_EL2 -#if ENABLE_FEAT_AMUv1 - mrs x14, HAFGRTR_EL2 - stp x13, x14, [x0, #CTX_HDFGRTR_EL2] -#else - str x13, [x0, #CTX_HDFGRTR_EL2] -#endif /* ENABLE_FEAT_AMUv1 */ - mrs x15, HDFGWTR_EL2 - mrs x16, HFGITR_EL2 - stp x15, x16, [x0, #CTX_HDFGWTR_EL2] - - mrs x9, HFGRTR_EL2 - mrs x10, HFGWTR_EL2 - stp x9, x10, [x0, #CTX_HFGRTR_EL2] -#endif /* ENABLE_FEAT_FGT */ - -#if ENABLE_FEAT_ECV - mrs x11, CNTPOFF_EL2 - str x11, [x0, #CTX_CNTPOFF_EL2] -#endif /* ENABLE_FEAT_ECV */ - -#if ENABLE_FEAT_VHE - /* - * CONTEXTIDR_EL2 register is saved only when FEAT_VHE or - * FEAT_Debugv8p2 (currently not in TF-A) is supported. - */ - mrs x9, contextidr_el2 - mrs x10, ttbr1_el2 - stp x9, x10, [x0, #CTX_CONTEXTIDR_EL2] -#endif /* ENABLE_FEAT_VHE */ - -#if RAS_EXTENSION - /* - * VDISR_EL2 and VSESR_EL2 registers are saved only when - * FEAT_RAS is supported. - */ - mrs x11, vdisr_el2 - mrs x12, vsesr_el2 - stp x11, x12, [x0, #CTX_VDISR_EL2] -#endif /* RAS_EXTENSION */ - -#if CTX_INCLUDE_NEVE_REGS - /* - * VNCR_EL2 register is saved only when FEAT_NV2 is supported. - */ - mrs x16, vncr_el2 - str x16, [x0, #CTX_VNCR_EL2] -#endif /* CTX_INCLUDE_NEVE_REGS */ - -#if ENABLE_TRF_FOR_NS - /* - * TRFCR_EL2 register is saved only when FEAT_TRF is supported. - */ - mrs x12, TRFCR_EL2 - str x12, [x0, #CTX_TRFCR_EL2] -#endif /* ENABLE_TRF_FOR_NS */ - -#if ENABLE_FEAT_CSV2_2 - /* - * SCXTNUM_EL2 register is saved only when FEAT_CSV2_2 is supported. - */ - mrs x13, scxtnum_el2 - str x13, [x0, #CTX_SCXTNUM_EL2] -#endif /* ENABLE_FEAT_CSV2_2 */ - -#if ENABLE_FEAT_HCX - mrs x14, hcrx_el2 - str x14, [x0, #CTX_HCRX_EL2] -#endif /* ENABLE_FEAT_HCX */ - ret -endfunc el2_sysregs_context_save +endfunc el2_sysregs_context_save_common - -/* ----------------------------------------------------- - * The following function strictly follows the AArch64 - * PCS to use x9-x16 (temporary caller-saved registers) - * to restore EL2 system register context. It assumes - * that 'x0' is pointing to a 'el2_sys_regs' structure - * from where the register context will be restored - - * The following registers are not restored - * AMEVCNTVOFF0<n>_EL2 - * AMEVCNTVOFF1<n>_EL2 - * ICH_AP0R<n>_EL2 - * ICH_AP1R<n>_EL2 - * ICH_LR<n>_EL2 - * ----------------------------------------------------- - */ -func el2_sysregs_context_restore +func el2_sysregs_context_restore_common ldp x9, x10, [x0, #CTX_ACTLR_EL2] msr actlr_el2, x9 msr afsr0_el2, x10 @@ -281,11 +207,6 @@ func el2_sysregs_context_restore msr mair_el2, x11 msr mdcr_el2, x12 -#if ENABLE_SPE_FOR_LOWER_ELS - ldr x13, [x0, #CTX_PMSCR_EL2] - msr PMSCR_EL2, x13 -#endif /* ENABLE_SPE_FOR_LOWER_ELS */ - ldr x14, [x0, #CTX_SCTLR_EL2] msr sctlr_el2, x14 @@ -308,13 +229,65 @@ func el2_sysregs_context_restore ldp x15, x16, [x0, #CTX_VTCR_EL2] msr vtcr_el2, x15 msr vttbr_el2, x16 + ret +endfunc el2_sysregs_context_restore_common + +#if ENABLE_SPE_FOR_LOWER_ELS +func el2_sysregs_context_save_spe + mrs x13, PMSCR_EL2 + str x13, [x0, #CTX_PMSCR_EL2] + ret +endfunc el2_sysregs_context_save_spe + +func el2_sysregs_context_restore_spe + ldr x13, [x0, #CTX_PMSCR_EL2] + msr PMSCR_EL2, x13 + ret +endfunc el2_sysregs_context_restore_spe +#endif /* ENABLE_SPE_FOR_LOWER_ELS */ #if CTX_INCLUDE_MTE_REGS +func el2_sysregs_context_save_mte + mrs x9, TFSR_EL2 + str x9, [x0, #CTX_TFSR_EL2] + ret +endfunc el2_sysregs_context_save_mte + +func el2_sysregs_context_restore_mte ldr x9, [x0, #CTX_TFSR_EL2] msr TFSR_EL2, x9 + ret +endfunc el2_sysregs_context_restore_mte #endif /* CTX_INCLUDE_MTE_REGS */ #if ENABLE_MPAM_FOR_LOWER_ELS +func el2_sysregs_context_save_mpam + mrs x10, MPAM2_EL2 + str x10, [x0, #CTX_MPAM2_EL2] + + mrs x11, MPAMHCR_EL2 + mrs x12, MPAMVPM0_EL2 + stp x11, x12, [x0, #CTX_MPAMHCR_EL2] + + mrs x13, MPAMVPM1_EL2 + mrs x14, MPAMVPM2_EL2 + stp x13, x14, [x0, #CTX_MPAMVPM1_EL2] + + mrs x15, MPAMVPM3_EL2 + mrs x16, MPAMVPM4_EL2 + stp x15, x16, [x0, #CTX_MPAMVPM3_EL2] + + mrs x9, MPAMVPM5_EL2 + mrs x10, MPAMVPM6_EL2 + stp x9, x10, [x0, #CTX_MPAMVPM5_EL2] + + mrs x11, MPAMVPM7_EL2 + mrs x12, MPAMVPMV_EL2 + stp x11, x12, [x0, #CTX_MPAMVPM7_EL2] + ret +endfunc func el2_sysregs_context_save_mpam + +func el2_sysregs_context_restore_mpam ldr x10, [x0, #CTX_MPAM2_EL2] msr MPAM2_EL2, x10 @@ -337,10 +310,31 @@ func el2_sysregs_context_restore ldp x11, x12, [x0, #CTX_MPAMVPM7_EL2] msr MPAMVPM7_EL2, x11 msr MPAMVPMV_EL2, x12 + ret +endfunc el2_sysregs_context_restore_mpam #endif /* ENABLE_MPAM_FOR_LOWER_ELS */ #if ENABLE_FEAT_FGT +func el2_sysregs_context_save_fgt + mrs x13, HDFGRTR_EL2 #if ENABLE_FEAT_AMUv1 + mrs x14, HAFGRTR_EL2 + stp x13, x14, [x0, #CTX_HDFGRTR_EL2] +#else + str x13, [x0, #CTX_HDFGRTR_EL2] +#endif /* ENABLE_FEAT_AMUv1 */ + mrs x15, HDFGWTR_EL2 + mrs x16, HFGITR_EL2 + stp x15, x16, [x0, #CTX_HDFGWTR_EL2] + + mrs x9, HFGRTR_EL2 + mrs x10, HFGWTR_EL2 + stp x9, x10, [x0, #CTX_HFGRTR_EL2] + ret +endfunc el2_sysregs_context_save_fgt + +func el2_sysregs_context_restore_fgt + #if ENABLE_FEAT_AMUv1 ldp x13, x14, [x0, #CTX_HDFGRTR_EL2] msr HAFGRTR_EL2, x14 #else @@ -355,14 +349,37 @@ func el2_sysregs_context_restore ldp x9, x10, [x0, #CTX_HFGRTR_EL2] msr HFGRTR_EL2, x9 msr HFGWTR_EL2, x10 + ret +endfunc el2_sysregs_context_restore_fgt #endif /* ENABLE_FEAT_FGT */ #if ENABLE_FEAT_ECV +func el2_sysregs_context_save_ecv + mrs x11, CNTPOFF_EL2 + str x11, [x0, #CTX_CNTPOFF_EL2] + ret +endfunc el2_sysregs_context_save_ecv + +func el2_sysregs_context_restore_ecv ldr x11, [x0, #CTX_CNTPOFF_EL2] msr CNTPOFF_EL2, x11 + ret +endfunc el2_sysregs_context_restore_ecv #endif /* ENABLE_FEAT_ECV */ #if ENABLE_FEAT_VHE +func el2_sysregs_context_save_vhe + /* + * CONTEXTIDR_EL2 register is saved only when FEAT_VHE or + * FEAT_Debugv8p2 (currently not in TF-A) is supported. + */ + mrs x9, contextidr_el2 + mrs x10, ttbr1_el2 + stp x9, x10, [x0, #CTX_CONTEXTIDR_EL2] + ret +endfunc el2_sysregs_context_save_vhe + +func el2_sysregs_context_restore_vhe /* * CONTEXTIDR_EL2 register is restored only when FEAT_VHE or * FEAT_Debugv8p2 (currently not in TF-A) is supported. @@ -370,9 +387,23 @@ func el2_sysregs_context_restore ldp x9, x10, [x0, #CTX_CONTEXTIDR_EL2] msr contextidr_el2, x9 msr ttbr1_el2, x10 + ret +endfunc el2_sysregs_context_restore_vhe #endif /* ENABLE_FEAT_VHE */ #if RAS_EXTENSION +func el2_sysregs_context_save_ras + /* + * VDISR_EL2 and VSESR_EL2 registers are saved only when + * FEAT_RAS is supported. + */ + mrs x11, vdisr_el2 + mrs x12, vsesr_el2 + stp x11, x12, [x0, #CTX_VDISR_EL2] + ret +endfunc el2_sysregs_context_save_ras + +func el2_sysregs_context_restore_ras /* * VDISR_EL2 and VSESR_EL2 registers are restored only when FEAT_RAS * is supported. @@ -380,40 +411,83 @@ func el2_sysregs_context_restore ldp x11, x12, [x0, #CTX_VDISR_EL2] msr vdisr_el2, x11 msr vsesr_el2, x12 + ret +endfunc el2_sysregs_context_restore_ras #endif /* RAS_EXTENSION */ #if CTX_INCLUDE_NEVE_REGS +func el2_sysregs_context_save_nv2 + /* + * VNCR_EL2 register is saved only when FEAT_NV2 is supported. + */ + mrs x16, vncr_el2 + str x16, [x0, #CTX_VNCR_EL2] + ret +endfunc el2_sysregs_context_save_nv2 + +func el2_sysregs_context_restore_nv2 /* * VNCR_EL2 register is restored only when FEAT_NV2 is supported. */ ldr x16, [x0, #CTX_VNCR_EL2] msr vncr_el2, x16 + ret +endfunc el2_sysregs_context_restore_nv2 #endif /* CTX_INCLUDE_NEVE_REGS */ #if ENABLE_TRF_FOR_NS +func el2_sysregs_context_save_trf + /* + * TRFCR_EL2 register is saved only when FEAT_TRF is supported. + */ + mrs x12, TRFCR_EL2 + str x12, [x0, #CTX_TRFCR_EL2] + ret +endfunc el2_sysregs_context_save_trf + +func el2_sysregs_context_restore_trf /* * TRFCR_EL2 register is restored only when FEAT_TRF is supported. */ ldr x12, [x0, #CTX_TRFCR_EL2] msr TRFCR_EL2, x12 + ret +endfunc el2_sysregs_context_restore_trf #endif /* ENABLE_TRF_FOR_NS */ #if ENABLE_FEAT_CSV2_2 +func el2_sysregs_context_save_csv2 + /* + * SCXTNUM_EL2 register is saved only when FEAT_CSV2_2 is supported. + */ + mrs x13, scxtnum_el2 + str x13, [x0, #CTX_SCXTNUM_EL2] + ret +endfunc el2_sysregs_context_save_csv2 + +func el2_sysregs_context_restore_csv2 /* * SCXTNUM_EL2 register is restored only when FEAT_CSV2_2 is supported. */ ldr x13, [x0, #CTX_SCXTNUM_EL2] msr scxtnum_el2, x13 + ret +endfunc el2_sysregs_context_restore_csv2 #endif /* ENABLE_FEAT_CSV2_2 */ #if ENABLE_FEAT_HCX +func el2_sysregs_context_save_hcx + mrs x14, hcrx_el2 + str x14, [x0, #CTX_HCRX_EL2] + ret +endfunc el2_sysregs_context_save_hcx + +func el2_sysregs_context_restore_hcx ldr x14, [x0, #CTX_HCRX_EL2] msr hcrx_el2, x14 -#endif /* ENABLE_FEAT_HCX */ - ret -endfunc el2_sysregs_context_restore - +endfunc el2_sysregs_context_restore_hcx +#endif /* ENABLE_FEAT_HCX */ #endif /* CTX_INCLUDE_EL2_REGS */ /* ------------------------------------------------------------------ @@ -732,9 +806,9 @@ endfunc fpregs_context_restore /* ------------------------------------------------------------------ * The following macro is used to save and restore all the general * purpose and ARMv8.3-PAuth (if enabled) registers. - * It also checks if Secure Cycle Counter is not disabled in MDCR_EL3 - * when ARMv8.5-PMU is implemented, and if called from Non-secure - * state saves PMCR_EL0 and disables Cycle Counter. + * It also checks if the Secure Cycle Counter (PMCCNTR_EL0) + * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0 + * needs not to be saved/restored during world switch. * * Ideally we would only save and restore the callee saved registers * when a world switch occurs but that type of implementation is more @@ -763,9 +837,17 @@ endfunc fpregs_context_restore str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] /* ---------------------------------------------------------- - * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1 - * failed, meaning that FEAT_PMUv3p5/7 is not implemented and - * PMCR_EL0 should be saved in non-secure context. + * Check if earlier initialization of MDCR_EL3.SCCD/MCCD to 1 + * has failed. + * + * MDCR_EL3: + * MCCD bit set, Prohibits the Cycle Counter PMCCNTR_EL0 from + * counting at EL3. + * SCCD bit set, Secure Cycle Counter Disable. Prohibits PMCCNTR_EL0 + * from counting in Secure state. + * If these bits are not set, meaning that FEAT_PMUv3p5/7 is + * not implemented and PMCR_EL0 should be saved in non-secure + * context. * ---------------------------------------------------------- */ mov_imm x10, (MDCR_SCCD_BIT | MDCR_MCCD_BIT) @@ -773,7 +855,13 @@ endfunc fpregs_context_restore tst x9, x10 bne 1f - /* Secure Cycle Counter is not disabled */ + /* ---------------------------------------------------------- + * If control reaches here, it ensures the Secure Cycle + * Counter (PMCCNTR_EL0) is not prohibited from counting at + * EL3 and in secure states. + * Henceforth, PMCR_EL0 to be saved before world switch. + * ---------------------------------------------------------- + */ mrs x9, pmcr_el0 /* Check caller's security state */ diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index e393493a2..866ac4154 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,6 +16,7 @@ #include <arch_features.h> #include <bl31/interrupt_mgmt.h> #include <common/bl_common.h> +#include <common/debug.h> #include <context.h> #include <drivers/arm/gicv3.h> #include <lib/el3_runtime/context_mgmt.h> @@ -204,6 +206,22 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info * /* Allow access to Allocation Tags when MTE is implemented. */ scr_el3 |= SCR_ATA_BIT; +#if HANDLE_EA_EL3_FIRST_NS + /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ + scr_el3 |= SCR_EA_BIT; +#endif + +#if RAS_TRAP_NS_ERR_REC_ACCESS + /* + * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR + * and RAS ERX registers from EL1 and EL2(from any security state) + * are trapped to EL3. + * Set here to trap only for NS EL1/EL2 + * + */ + scr_el3 |= SCR_TERR_BIT; +#endif + #ifdef IMAGE_BL31 /* * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as @@ -229,16 +247,23 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info * sctlr_el2); /* - * The GICv3 driver initializes the ICC_SRE_EL2 register during - * platform setup. Use the same setting for the corresponding - * context register to make sure the correct bits are set when - * restoring NS context. + * Program the ICC_SRE_EL2 to make sure the correct bits are set + * when restoring NS context. */ - u_register_t icc_sre_el2 = read_icc_sre_el2(); - icc_sre_el2 |= (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT); - icc_sre_el2 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); + u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | + ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, icc_sre_el2); + + /* + * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't + * throw anyone off who expects this to be sensible. + * TODO: A similar thing happens in cm_prepare_el3_exit. They should be + * unified with the proper PMU implementation + */ + u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & + PMCR_EL0_N_MASK); + write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); #endif /* CTX_INCLUDE_EL2_REGS */ } @@ -269,7 +294,7 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e * Security state and entrypoint attributes of the next EL. */ scr_el3 = read_scr(); - scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | + scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); /* @@ -299,21 +324,12 @@ static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *e scr_el3 |= SCR_HXEn_BIT; #endif -#if RAS_TRAP_LOWER_EL_ERR_ACCESS - /* - * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR - * and RAS ERX registers from EL1 and EL2 are trapped to EL3. - */ - scr_el3 |= SCR_TERR_BIT; -#endif - -#if !HANDLE_EA_EL3_FIRST /* - * SCR_EL3.EA: Do not route External Abort and SError Interrupt External - * to EL3 when executing at a lower EL. When executing at EL3, External - * Aborts are taken to EL3. + * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS + * registers are trapped to EL3. */ - scr_el3 &= ~SCR_EA_BIT; +#if ENABLE_FEAT_RNG_TRAP + scr_el3 |= SCR_TRNDR_BIT; #endif #if FAULT_INJECTION_SUPPORT @@ -790,11 +806,47 @@ void cm_el2_sysregs_context_save(uint32_t security_state) if ((security_state != SECURE) || ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { cpu_context_t *ctx; + el2_sysregs_t *el2_sysregs_ctx; ctx = cm_get_context(security_state); assert(ctx != NULL); - el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); + el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); + + el2_sysregs_context_save_common(el2_sysregs_ctx); +#if ENABLE_SPE_FOR_LOWER_ELS + el2_sysregs_context_save_spe(el2_sysregs_ctx); +#endif +#if CTX_INCLUDE_MTE_REGS + el2_sysregs_context_save_mte(el2_sysregs_ctx); +#endif +#if ENABLE_MPAM_FOR_LOWER_ELS + el2_sysregs_context_save_mpam(el2_sysregs_ctx); +#endif +#if ENABLE_FEAT_FGT + el2_sysregs_context_save_fgt(el2_sysregs_ctx); +#endif +#if ENABLE_FEAT_ECV + el2_sysregs_context_save_ecv(el2_sysregs_ctx); +#endif +#if ENABLE_FEAT_VHE + el2_sysregs_context_save_vhe(el2_sysregs_ctx); +#endif +#if RAS_EXTENSION + el2_sysregs_context_save_ras(el2_sysregs_ctx); +#endif +#if CTX_INCLUDE_NEVE_REGS + el2_sysregs_context_save_nv2(el2_sysregs_ctx); +#endif +#if ENABLE_TRF_FOR_NS + el2_sysregs_context_save_trf(el2_sysregs_ctx); +#endif +#if ENABLE_FEAT_CSV2_2 + el2_sysregs_context_save_csv2(el2_sysregs_ctx); +#endif +#if ENABLE_FEAT_HCX + el2_sysregs_context_save_hcx(el2_sysregs_ctx); +#endif } } @@ -812,11 +864,47 @@ void cm_el2_sysregs_context_restore(uint32_t security_state) if ((security_state != SECURE) || ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { cpu_context_t *ctx; + el2_sysregs_t *el2_sysregs_ctx; ctx = cm_get_context(security_state); assert(ctx != NULL); - el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); + el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); + + el2_sysregs_context_restore_common(el2_sysregs_ctx); +#if ENABLE_SPE_FOR_LOWER_ELS + el2_sysregs_context_restore_spe(el2_sysregs_ctx); +#endif +#if CTX_INCLUDE_MTE_REGS + el2_sysregs_context_restore_mte(el2_sysregs_ctx); +#endif +#if ENABLE_MPAM_FOR_LOWER_ELS + el2_sysregs_context_restore_mpam(el2_sysregs_ctx); +#endif +#if ENABLE_FEAT_FGT + el2_sysregs_context_restore_fgt(el2_sysregs_ctx); +#endif +#if ENABLE_FEAT_ECV + el2_sysregs_context_restore_ecv(el2_sysregs_ctx); +#endif +#if ENABLE_FEAT_VHE + el2_sysregs_context_restore_vhe(el2_sysregs_ctx); +#endif +#if RAS_EXTENSION + el2_sysregs_context_restore_ras(el2_sysregs_ctx); +#endif +#if CTX_INCLUDE_NEVE_REGS + el2_sysregs_context_restore_nv2(el2_sysregs_ctx); +#endif +#if ENABLE_TRF_FOR_NS + el2_sysregs_context_restore_trf(el2_sysregs_ctx); +#endif +#if ENABLE_FEAT_CSV2_2 + el2_sysregs_context_restore_csv2(el2_sysregs_ctx); +#endif +#if ENABLE_FEAT_HCX + el2_sysregs_context_restore_hcx(el2_sysregs_ctx); +#endif } } #endif /* CTX_INCLUDE_EL2_REGS */ diff --git a/lib/extensions/brbe/brbe.c b/lib/extensions/brbe/brbe.c index 6975b049c..1982619b7 100644 --- a/lib/extensions/brbe/brbe.c +++ b/lib/extensions/brbe/brbe.c @@ -5,22 +5,14 @@ */ #include <arch.h> +#include <arch_features.h> #include <arch_helpers.h> -static bool brbe_supported(void) -{ - uint64_t features; - - features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_BRBE_SHIFT; - return ((features & ID_AA64DFR0_BRBE_MASK) == - ID_AA64DFR0_BRBE_SUPPORTED); -} - void brbe_enable(void) { uint64_t val; - if (brbe_supported()) { + if (is_feat_brbe_present()) { /* * MDCR_EL3.SBRBE = 0b01 * diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c index 1c2b98448..ec8cca82b 100644 --- a/lib/extensions/sme/sme.c +++ b/lib/extensions/sme/sme.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,6 +37,8 @@ void sme_enable(cpu_context_t *context) /* Make sure SME is implemented in hardware before continuing. */ if (!feat_sme_supported()) { + /* Perhaps the hardware supports SVE only */ + sve_enable(context); return; } @@ -56,6 +58,7 @@ void sme_enable(cpu_context_t *context) /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */ cptr_el3 = read_cptr_el3(); write_cptr_el3(cptr_el3 | ESM_BIT); + isb(); /* * Set the max LEN value and FA64 bit. This register is set up globally @@ -71,6 +74,7 @@ void sme_enable(cpu_context_t *context) /* Reset CPTR_EL3 value. */ write_cptr_el3(cptr_el3); + isb(); /* Enable SVE/FPU in addition to SME. */ sve_enable(context); @@ -83,6 +87,8 @@ void sme_disable(cpu_context_t *context) /* Make sure SME is implemented in hardware before continuing. */ if (!feat_sme_supported()) { + /* Perhaps the hardware supports SVE only */ + sve_disable(context); return; } diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c index aa8904b9b..f7dcc767a 100644 --- a/lib/extensions/sve/sve.c +++ b/lib/extensions/sve/sve.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,9 +8,14 @@ #include <arch.h> #include <arch_helpers.h> +#include <lib/cassert.h> #include <lib/el3_runtime/pubsub.h> #include <lib/extensions/sve.h> +CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long); +CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short); +CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule); + /* * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation. * VECTOR_SIZE = (LEN+1) * 128 @@ -39,9 +44,9 @@ void sve_enable(cpu_context_t *context) cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); - /* Restrict maximum SVE vector length (SVE_VECTOR_LENGTH+1) * 128. */ + /* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */ write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, - (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(512))); + (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN))); } void sve_disable(cpu_context_t *context) diff --git a/lib/extensions/trbe/trbe.c b/lib/extensions/trbe/trbe.c index 9f754d521..b3463872b 100644 --- a/lib/extensions/trbe/trbe.c +++ b/lib/extensions/trbe/trbe.c @@ -1,10 +1,11 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch.h> +#include <arch_features.h> #include <arch_helpers.h> #include <lib/el3_runtime/pubsub.h> #include <lib/extensions/trbe.h> @@ -18,20 +19,11 @@ static void tsb_csync(void) __asm__ volatile("hint #18"); } -static bool trbe_supported(void) -{ - uint64_t features; - - features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEBUFFER_SHIFT; - return ((features & ID_AA64DFR0_TRACEBUFFER_MASK) == - ID_AA64DFR0_TRACEBUFFER_SUPPORTED); -} - void trbe_enable(void) { uint64_t val; - if (trbe_supported()) { + if (is_feat_trbe_present()) { /* * MDCR_EL3.NSTB = 0b11 * Allow access of trace buffer control registers from NS-EL1 @@ -46,7 +38,7 @@ void trbe_enable(void) static void *trbe_drain_trace_buffers_hook(const void *arg __unused) { - if (trbe_supported()) { + if (is_feat_trbe_present()) { /* * Before switching from normal world to secure world * the trace buffers need to be drained out to memory. This is diff --git a/lib/fconf/fconf_dyn_cfg_getter.c b/lib/fconf/fconf_dyn_cfg_getter.c index 3038c09e8..351772e11 100644 --- a/lib/fconf/fconf_dyn_cfg_getter.c +++ b/lib/fconf/fconf_dyn_cfg_getter.c @@ -12,6 +12,8 @@ #include <lib/object_pool.h> #include <libfdt.h> +#include <platform_def.h> + /* We currently use FW, TB_FW, SOC_FW, TOS_FW, NT_FW and HW configs */ #define MAX_DTB_INFO U(6) /* diff --git a/lib/fconf/fconf_tbbr_getter.c b/lib/fconf/fconf_tbbr_getter.c index 6f043e645..c3b4b7e0e 100644 --- a/lib/fconf/fconf_tbbr_getter.c +++ b/lib/fconf/fconf_tbbr_getter.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, Arm Limited. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,8 +44,8 @@ int fconf_populate_tbbr_dyn_config(uintptr_t config) /* Check if the value is boolean */ if ((tbbr_dyn_config.disable_auth != 0U) && (tbbr_dyn_config.disable_auth != 1U)) { - WARN("Invalid value for `%s` cell %d\n", - "disable_auth", tbbr_dyn_config.disable_auth); + WARN("Invalid value for `%s` cell %u\n", + "disable_auth", tbbr_dyn_config.disable_auth); return -1; } @@ -71,7 +71,7 @@ int fconf_populate_tbbr_dyn_config(uintptr_t config) } tbbr_dyn_config.mbedtls_heap_size = val32; - VERBOSE("%s%s%s %d\n", "FCONF: `tbbr.", "disable_auth", + VERBOSE("%s%s%s %u\n", "FCONF: `tbbr.", "disable_auth", "` cell found with value =", tbbr_dyn_config.disable_auth); VERBOSE("%s%s%s %p\n", "FCONF: `tbbr.", "mbedtls_heap_addr", "` cell found with value =", tbbr_dyn_config.mbedtls_heap_addr); diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c index d6fbc04b9..a6e17a34d 100644 --- a/lib/gpt_rme/gpt_rme.c +++ b/lib/gpt_rme/gpt_rme.c @@ -693,10 +693,6 @@ int gpt_enable(void) return -EPERM; } - /* Invalidate any stale TLB entries */ - tlbipaallos(); - dsb(); - /* Write the base address of the L0 tables into GPTBR */ write_gptbr_el3(((gpt_config.plat_gpt_l0_base >> GPTBR_BADDR_VAL_SHIFT) >> GPTBR_BADDR_SHIFT) & GPTBR_BADDR_MASK); @@ -718,6 +714,15 @@ int gpt_enable(void) gpccr_el3 |= SET_GPCCR_ORGN(GPCCR_ORGN_WB_RA_WA); gpccr_el3 |= SET_GPCCR_IRGN(GPCCR_IRGN_WB_RA_WA); + /* Prepopulate GPCCR_EL3 but don't enable GPC yet */ + write_gpccr_el3(gpccr_el3); + isb(); + + /* Invalidate any stale TLB entries and any cached register fields */ + tlbipaallos(); + dsb(); + isb(); + /* Enable GPT */ gpccr_el3 |= GPCCR_GPC_BIT; @@ -1076,7 +1081,7 @@ int gpt_delegate_pas(uint64_t base, size_t size, unsigned int src_sec_state) VERBOSE(" Caller: %u, Current GPI: %u\n", src_sec_state, gpi_info.gpi); spin_unlock(&gpt_lock); - return -EINVAL; + return -EPERM; } if (src_sec_state == SMC_FROM_SECURE) { @@ -1197,7 +1202,7 @@ int gpt_undelegate_pas(uint64_t base, size_t size, unsigned int src_sec_state) VERBOSE(" Caller: %u, Current GPI: %u\n", src_sec_state, gpi_info.gpi); spin_unlock(&gpt_lock); - return -EINVAL; + return -EPERM; } diff --git a/lib/libc/assert.c b/lib/libc/assert.c index c199de6f7..8973ed543 100644 --- a/lib/libc/assert.c +++ b/lib/libc/assert.c @@ -17,16 +17,7 @@ * LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1. */ -#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE -void __dead2 __assert(const char *file, unsigned int line, - const char *assertion) -{ - printf("ASSERT: %s:%u:%s\n", file, line, assertion); - backtrace("assert"); - console_flush(); - plat_panic_handler(); -} -#elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO +#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO void __dead2 __assert(const char *file, unsigned int line) { printf("ASSERT: %s:%u\n", file, line); diff --git a/lib/libc/printf.c b/lib/libc/printf.c index 45e153ec7..e52cbed73 100644 --- a/lib/libc/printf.c +++ b/lib/libc/printf.c @@ -7,9 +7,9 @@ #include <assert.h> #include <stdarg.h> #include <stdbool.h> +#include <stddef.h> #include <stdint.h> - -#include <common/debug.h> +#include <stdio.h> #define get_num_va_args(_args, _lcount) \ (((_lcount) > 1) ? va_arg(_args, long long int) : \ @@ -43,6 +43,12 @@ static int unsigned_num_print(unsigned long long int unum, unsigned int radix, int i = 0, count = 0; unsigned int rem; + /* num_buf is only large enough for radix >= 10 */ + if (radix < 10) { + assert(0); + return 0; + } + do { rem = unum % radix; if (rem < 0xa) diff --git a/lib/libc/putchar.c b/lib/libc/putchar.c index 037e28ac4..3472b2436 100644 --- a/lib/libc/putchar.c +++ b/lib/libc/putchar.c @@ -6,15 +6,9 @@ #include <stdio.h> -#include <drivers/console.h> - -int putchar(int c) +int __putchar(int c) { - int res; - if (console_putc((unsigned char)c) >= 0) - res = c; - else - res = EOF; - - return res; + return c; } + +int putchar(int c) __attribute__((weak,alias("__putchar"))); diff --git a/lib/libc/snprintf.c b/lib/libc/snprintf.c index 12f51c07f..6a2f0ba7f 100644 --- a/lib/libc/snprintf.c +++ b/lib/libc/snprintf.c @@ -6,11 +6,10 @@ #include <assert.h> #include <stdarg.h> +#include <stdbool.h> +#include <stddef.h> #include <stdint.h> -#include <common/debug.h> -#include <plat/common/platform.h> - #define get_num_va_args(_args, _lcount) \ (((_lcount) > 1) ? va_arg(_args, long long int) : \ (((_lcount) == 1) ? va_arg(_args, long int) : \ @@ -51,10 +50,10 @@ static void unsigned_num_print(char **s, size_t n, size_t *chars_printed, unsigned int rem; char ascii_a = capitalise ? 'A' : 'a'; + /* num_buf is only large enough for radix >= 10 */ if (radix < 10) { - ERROR("snprintf: unsupported radix '%u'.", radix); - plat_panic_handler(); - assert(0); /* Unreachable */ + assert(0); + return; } do { @@ -218,11 +217,8 @@ loop: break; default: - /* Panic on any other format specifier. */ - ERROR("snprintf: specifier with ASCII code '%d' not supported.", - *fmt); - plat_panic_handler(); - assert(0); /* Unreachable */ + CHECK_AND_PUT_CHAR(s, n, chars_printed, '%'); + CHECK_AND_PUT_CHAR(s, n, chars_printed, *fmt); } fmt++; continue; diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c index 6cf2fa03b..9fe7cf4b7 100644 --- a/lib/libfdt/fdt.c +++ b/lib/libfdt/fdt.c @@ -22,6 +22,10 @@ int32_t fdt_ro_probe_(const void *fdt) if (can_assume(VALID_DTB)) return totalsize; + /* The device tree must be at an 8-byte aligned address */ + if ((uintptr_t)fdt & 7) + return -FDT_ERR_ALIGNMENT; + if (fdt_magic(fdt) == FDT_MAGIC) { /* Complete tree */ if (!can_assume(LATEST)) { @@ -86,6 +90,10 @@ int fdt_check_header(const void *fdt) { size_t hdrsize; + /* The device tree must be at an 8-byte aligned address */ + if ((uintptr_t)fdt & 7) + return -FDT_ERR_ALIGNMENT; + if (fdt_magic(fdt) != FDT_MAGIC) return -FDT_ERR_BADMAGIC; if (!can_assume(LATEST)) { diff --git a/lib/libfdt/fdt_addresses.c b/lib/libfdt/fdt_addresses.c index 9a82cd0ba..c40ba094f 100644 --- a/lib/libfdt/fdt_addresses.c +++ b/lib/libfdt/fdt_addresses.c @@ -73,7 +73,7 @@ int fdt_appendprop_addrrange(void *fdt, int parent, int nodeoffset, /* check validity of address */ prop = data; if (addr_cells == 1) { - if ((addr > UINT32_MAX) || ((UINT32_MAX + 1 - addr) < size)) + if ((addr > UINT32_MAX) || (((uint64_t) UINT32_MAX + 1 - addr) < size)) return -FDT_ERR_BADVALUE; fdt32_st(prop, (uint32_t)addr); diff --git a/lib/libfdt/fdt_overlay.c b/lib/libfdt/fdt_overlay.c index d217e79b6..5c0c3981b 100644 --- a/lib/libfdt/fdt_overlay.c +++ b/lib/libfdt/fdt_overlay.c @@ -40,37 +40,22 @@ static uint32_t overlay_get_target_phandle(const void *fdto, int fragment) return fdt32_to_cpu(*val); } -/** - * overlay_get_target - retrieves the offset of a fragment's target - * @fdt: Base device tree blob - * @fdto: Device tree overlay blob - * @fragment: node offset of the fragment in the overlay - * @pathp: pointer which receives the path of the target (or NULL) - * - * overlay_get_target() retrieves the target offset in the base - * device tree of a fragment, no matter how the actual targeting is - * done (through a phandle or a path) - * - * returns: - * the targeted node offset in the base device tree - * Negative error code on error - */ -static int overlay_get_target(const void *fdt, const void *fdto, - int fragment, char const **pathp) +int fdt_overlay_target_offset(const void *fdt, const void *fdto, + int fragment_offset, char const **pathp) { uint32_t phandle; const char *path = NULL; int path_len = 0, ret; /* Try first to do a phandle based lookup */ - phandle = overlay_get_target_phandle(fdto, fragment); + phandle = overlay_get_target_phandle(fdto, fragment_offset); if (phandle == (uint32_t)-1) return -FDT_ERR_BADPHANDLE; /* no phandle, try path */ if (!phandle) { /* And then a path based lookup */ - path = fdt_getprop(fdto, fragment, "target-path", &path_len); + path = fdt_getprop(fdto, fragment_offset, "target-path", &path_len); if (path) ret = fdt_path_offset(fdt, path); else @@ -636,7 +621,7 @@ static int overlay_merge(void *fdt, void *fdto) if (overlay < 0) return overlay; - target = overlay_get_target(fdt, fdto, fragment, NULL); + target = fdt_overlay_target_offset(fdt, fdto, fragment, NULL); if (target < 0) return target; @@ -779,7 +764,7 @@ static int overlay_symbol_update(void *fdt, void *fdto) return -FDT_ERR_BADOVERLAY; /* get the target of the fragment */ - ret = overlay_get_target(fdt, fdto, fragment, &target_path); + ret = fdt_overlay_target_offset(fdt, fdto, fragment, &target_path); if (ret < 0) return ret; target = ret; @@ -801,7 +786,7 @@ static int overlay_symbol_update(void *fdt, void *fdto) if (!target_path) { /* again in case setprop_placeholder changed it */ - ret = overlay_get_target(fdt, fdto, fragment, &target_path); + ret = fdt_overlay_target_offset(fdt, fdto, fragment, &target_path); if (ret < 0) return ret; target = ret; diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c index 91cc6fefe..9f6c551a2 100644 --- a/lib/libfdt/fdt_ro.c +++ b/lib/libfdt/fdt_ro.c @@ -181,8 +181,8 @@ int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) if (!can_assume(VALID_INPUT) && !re) return -FDT_ERR_BADOFFSET; - *address = fdt64_ld(&re->address); - *size = fdt64_ld(&re->size); + *address = fdt64_ld_(&re->address); + *size = fdt64_ld_(&re->size); return 0; } @@ -192,7 +192,7 @@ int fdt_num_mem_rsv(const void *fdt) const struct fdt_reserve_entry *re; for (i = 0; (re = fdt_mem_rsv(fdt, i)) != NULL; i++) { - if (fdt64_ld(&re->size) == 0) + if (fdt64_ld_(&re->size) == 0) return i; } return -FDT_ERR_TRUNCATED; @@ -370,7 +370,7 @@ static const struct fdt_property *fdt_get_property_by_offset_(const void *fdt, prop = fdt_offset_ptr_(fdt, offset); if (lenp) - *lenp = fdt32_ld(&prop->len); + *lenp = fdt32_ld_(&prop->len); return prop; } @@ -408,7 +408,7 @@ static const struct fdt_property *fdt_get_property_namelen_(const void *fdt, offset = -FDT_ERR_INTERNAL; break; } - if (fdt_string_eq_(fdt, fdt32_ld(&prop->nameoff), + if (fdt_string_eq_(fdt, fdt32_ld_(&prop->nameoff), name, namelen)) { if (poffset) *poffset = offset; @@ -461,7 +461,7 @@ const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, /* Handle realignment */ if (!can_assume(LATEST) && fdt_version(fdt) < 0x10 && - (poffset + sizeof(*prop)) % 8 && fdt32_ld(&prop->len) >= 8) + (poffset + sizeof(*prop)) % 8 && fdt32_ld_(&prop->len) >= 8) return prop->data + 4; return prop->data; } @@ -479,22 +479,22 @@ const void *fdt_getprop_by_offset(const void *fdt, int offset, int namelen; if (!can_assume(VALID_INPUT)) { - name = fdt_get_string(fdt, fdt32_ld(&prop->nameoff), + name = fdt_get_string(fdt, fdt32_ld_(&prop->nameoff), &namelen); + *namep = name; if (!name) { if (lenp) *lenp = namelen; return NULL; } - *namep = name; } else { - *namep = fdt_string(fdt, fdt32_ld(&prop->nameoff)); + *namep = fdt_string(fdt, fdt32_ld_(&prop->nameoff)); } } /* Handle realignment */ if (!can_assume(LATEST) && fdt_version(fdt) < 0x10 && - (offset + sizeof(*prop)) % 8 && fdt32_ld(&prop->len) >= 8) + (offset + sizeof(*prop)) % 8 && fdt32_ld_(&prop->len) >= 8) return prop->data + 4; return prop->data; } @@ -519,7 +519,7 @@ uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) return 0; } - return fdt32_ld(php); + return fdt32_ld_(php); } const char *fdt_get_alias_namelen(const void *fdt, diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c index 68887b969..3621d3651 100644 --- a/lib/libfdt/fdt_rw.c +++ b/lib/libfdt/fdt_rw.c @@ -349,7 +349,10 @@ int fdt_add_subnode_namelen(void *fdt, int parentoffset, return offset; /* Try to place the new node after the parent's properties */ - fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */ + tag = fdt_next_tag(fdt, parentoffset, &nextoffset); + /* the fdt_subnode_offset_namelen() should ensure this never hits */ + if (!can_assume(LIBFDT_FLAWLESS) && (tag != FDT_BEGIN_NODE)) + return -FDT_ERR_INTERNAL; do { offset = nextoffset; tag = fdt_next_tag(fdt, offset, &nextoffset); @@ -391,7 +394,9 @@ int fdt_del_node(void *fdt, int nodeoffset) } static void fdt_packblocks_(const char *old, char *new, - int mem_rsv_size, int struct_size) + int mem_rsv_size, + int struct_size, + int strings_size) { int mem_rsv_off, struct_off, strings_off; @@ -406,8 +411,7 @@ static void fdt_packblocks_(const char *old, char *new, fdt_set_off_dt_struct(new, struct_off); fdt_set_size_dt_struct(new, struct_size); - memmove(new + strings_off, old + fdt_off_dt_strings(old), - fdt_size_dt_strings(old)); + memmove(new + strings_off, old + fdt_off_dt_strings(old), strings_size); fdt_set_off_dt_strings(new, strings_off); fdt_set_size_dt_strings(new, fdt_size_dt_strings(old)); } @@ -428,12 +432,14 @@ int fdt_open_into(const void *fdt, void *buf, int bufsize) if (can_assume(LATEST) || fdt_version(fdt) >= 17) { struct_size = fdt_size_dt_struct(fdt); - } else { + } else if (fdt_version(fdt) == 16) { struct_size = 0; while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END) ; if (struct_size < 0) return struct_size; + } else { + return -FDT_ERR_BADVERSION; } if (can_assume(LIBFDT_ORDER) || @@ -465,7 +471,8 @@ int fdt_open_into(const void *fdt, void *buf, int bufsize) return -FDT_ERR_NOSPACE; } - fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size); + fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size, + fdt_size_dt_strings(fdt)); memmove(buf, tmp, newsize); fdt_set_magic(buf, FDT_MAGIC); @@ -485,7 +492,8 @@ int fdt_pack(void *fdt) mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) * sizeof(struct fdt_reserve_entry); - fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt)); + fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt), + fdt_size_dt_strings(fdt)); fdt_set_totalsize(fdt, fdt_data_size_(fdt)); return 0; diff --git a/lib/libfdt/fdt_strerror.c b/lib/libfdt/fdt_strerror.c index b4356931b..d852b77e8 100644 --- a/lib/libfdt/fdt_strerror.c +++ b/lib/libfdt/fdt_strerror.c @@ -39,6 +39,7 @@ static struct fdt_errtabent fdt_errtable[] = { FDT_ERRTABENT(FDT_ERR_BADOVERLAY), FDT_ERRTABENT(FDT_ERR_NOPHANDLES), FDT_ERRTABENT(FDT_ERR_BADFLAGS), + FDT_ERRTABENT(FDT_ERR_ALIGNMENT), }; #define FDT_ERRTABSIZE ((int)(sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))) diff --git a/lib/libfdt/fdt_sw.c b/lib/libfdt/fdt_sw.c index 68b543c4d..4c569ee7e 100644 --- a/lib/libfdt/fdt_sw.c +++ b/lib/libfdt/fdt_sw.c @@ -377,7 +377,7 @@ int fdt_finish(void *fdt) fdt_set_totalsize(fdt, newstroffset + fdt_size_dt_strings(fdt)); /* And fix up fields that were keeping intermediate state. */ - fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION); + fdt_set_last_comp_version(fdt, FDT_LAST_COMPATIBLE_VERSION); fdt_set_magic(fdt, FDT_MAGIC); return 0; diff --git a/lib/libfdt/libfdt_internal.h b/lib/libfdt/libfdt_internal.h index d4e0bd49c..16bda1906 100644 --- a/lib/libfdt/libfdt_internal.h +++ b/lib/libfdt/libfdt_internal.h @@ -46,6 +46,25 @@ static inline struct fdt_reserve_entry *fdt_mem_rsv_w_(void *fdt, int n) return (void *)(uintptr_t)fdt_mem_rsv_(fdt, n); } +/* + * Internal helpers to access tructural elements of the device tree + * blob (rather than for exaple reading integers from within property + * values). We assume that we are either given a naturally aligned + * address for the platform or if we are not, we are on a platform + * where unaligned memory reads will be handled in a graceful manner. + * If not the external helpers fdtXX_ld() from libfdt.h can be used + * instead. + */ +static inline uint32_t fdt32_ld_(const fdt32_t *p) +{ + return fdt32_to_cpu(*p); +} + +static inline uint64_t fdt64_ld_(const fdt64_t *p) +{ + return fdt64_to_cpu(*p); +} + #define FDT_SW_MAGIC (~FDT_MAGIC) /**********************************************************************/ diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c index 72979cd9d..6c87b0d07 100644 --- a/lib/optee/optee_utils.c +++ b/lib/optee/optee_utils.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,8 @@ #include <common/debug.h> #include <lib/optee_utils.h> +#include <platform_def.h> + /* * load_addr_hi and load_addr_lo: image load address. * image_id: 0 - pager, 1 - paged @@ -192,8 +194,17 @@ int parse_optee_header(entry_point_info_t *header_ep, &header->optee_image_list[num]); } else if (header->optee_image_list[num].image_id == OPTEE_PAGED_IMAGE_ID) { - ret = parse_optee_image(paged_image_info, - &header->optee_image_list[num]); + if (paged_image_info == NULL) { + if (header->optee_image_list[num].size != 0U) { + ERROR("Paged image is not supported\n"); + return -1; + } + + continue; + } else { + ret = parse_optee_image(paged_image_info, + &header->optee_image_list[num]); + } } else { ERROR("Parse optee image failed.\n"); return -1; @@ -215,8 +226,10 @@ int parse_optee_header(entry_point_info_t *header_ep, * header image arguments so that can be read by the * BL32 SPD. */ - header_ep->args.arg1 = paged_image_info->image_base; - header_ep->args.arg2 = paged_image_info->image_size; + if (paged_image_info != NULL) { + header_ep->args.arg1 = paged_image_info->image_base; + header_ep->args.arg2 = paged_image_info->image_size; + } /* Set OPTEE runtime arch - aarch32/aarch64 */ if (header->arch == 0) { diff --git a/lib/psa/initial_attestation.c b/lib/psa/delegated_attestation.c index 44498a857..399a3f102 100644 --- a/lib/psa/initial_attestation.c +++ b/lib/psa/delegated_attestation.c @@ -1,34 +1,73 @@ /* - * Copyright (c) 2018-2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * */ -#include <initial_attestation.h> +#include <string.h> + +#include <delegated_attestation.h> #include <psa/client.h> #include <psa_manifest/sid.h> #if !PLAT_RSS_NOT_SUPPORTED psa_status_t -psa_initial_attest_get_token(const uint8_t *auth_challenge, - size_t challenge_size, - uint8_t *token_buf, - size_t token_buf_size, - size_t *token_size) +rss_delegated_attest_get_delegated_key(uint8_t ecc_curve, + uint32_t key_bits, + uint8_t *key_buf, + size_t key_buf_size, + size_t *key_size, + uint32_t hash_algo) { psa_status_t status; psa_invec in_vec[] = { - {auth_challenge, challenge_size} + {&ecc_curve, sizeof(ecc_curve)}, + {&key_bits, sizeof(key_bits)}, + {&hash_algo, sizeof(hash_algo)} }; psa_outvec out_vec[] = { - {token_buf, token_buf_size}, + {key_buf, key_buf_size} }; - status = psa_call(RSS_ATTESTATION_SERVICE_HANDLE, RSS_ATTEST_GET_TOKEN, - in_vec, IOVEC_LEN(in_vec), + if (key_size == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + status = psa_call(RSS_DELEGATED_SERVICE_HANDLE, + RSS_DELEGATED_ATTEST_GET_DELEGATED_KEY, + in_vec, IOVEC_LEN(in_vec), out_vec, IOVEC_LEN(out_vec)); + if (status == PSA_SUCCESS) { + *key_size = out_vec[0].len; + } + + return status; +} + +psa_status_t +rss_delegated_attest_get_token(const uint8_t *dak_pub_hash, + size_t dak_pub_hash_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size) +{ + psa_status_t status; + psa_invec in_vec[] = { + {dak_pub_hash, dak_pub_hash_size} + }; + psa_outvec out_vec[] = { + {token_buf, token_buf_size} + }; + + if (token_size == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + status = psa_call(RSS_DELEGATED_SERVICE_HANDLE, + RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN, + in_vec, IOVEC_LEN(in_vec), + out_vec, IOVEC_LEN(out_vec)); if (status == PSA_SUCCESS) { *token_size = out_vec[0].len; } @@ -36,9 +75,16 @@ psa_initial_attest_get_token(const uint8_t *auth_challenge, return status; } + #else /* !PLAT_RSS_NOT_SUPPORTED */ -#include <string.h> +static const uint8_t delegated_key[] = { + 0x20, 0x11, 0xC7, 0xF0, 0x3C, 0xEE, 0x43, 0x25, 0x17, 0x6E, + 0x52, 0x4F, 0x03, 0x3C, 0x0C, 0xE1, 0xE2, 0x1A, 0x76, 0xE6, + 0xC1, 0xA4, 0xF0, 0xB8, 0x39, 0xAA, 0x1D, 0xF6, 0x1E, 0x0E, + 0x8A, 0x5C, 0x8A, 0x05, 0x74, 0x0F, 0x9B, 0x69, 0xEF, 0xA7, + 0xEB, 0x1A, 0x41, 0x85, 0xBD, 0x11, 0x7F, 0x68 +}; static const uint8_t platform_token[] = { 0xD2, 0x84, 0x43, 0xA1, 0x01, 0x26, 0xA0, 0x59, @@ -142,14 +188,35 @@ static const uint8_t platform_token[] = { }; psa_status_t -psa_initial_attest_get_token(const uint8_t *auth_challenge, - size_t challenge_size, - uint8_t *token_buf, - size_t token_buf_size, - size_t *token_size) +rss_delegated_attest_get_delegated_key(uint8_t ecc_curve, + uint32_t key_bits, + uint8_t *key_buf, + size_t key_buf_size, + size_t *key_size, + uint32_t hash_algo) +{ + (void)ecc_curve; + (void)key_bits; + (void)hash_algo; + + if (key_buf_size < sizeof(delegated_key)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + (void)memcpy(key_buf, delegated_key, sizeof(delegated_key)); + *key_size = sizeof(delegated_key); + + return PSA_SUCCESS; +} +psa_status_t +rss_delegated_attest_get_token(const uint8_t *dak_pub_hash, + size_t dak_pub_hash_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size) { - (void)auth_challenge; - (void)challenge_size; + (void)dak_pub_hash; + (void)dak_pub_hash_size; if (token_buf_size < sizeof(platform_token)) { return PSA_ERROR_BUFFER_TOO_SMALL; diff --git a/lib/psa/measured_boot.c b/lib/psa/measured_boot.c index 5d3ca8ed2..6e9ff78f2 100644 --- a/lib/psa/measured_boot.c +++ b/lib/psa/measured_boot.c @@ -14,31 +14,35 @@ #include "measured_boot_private.h" -static void print_byte_array(const uint8_t *array, size_t len) +static void print_byte_array(const uint8_t *array __unused, size_t len __unused) { - unsigned int i; +#if LOG_LEVEL >= LOG_LEVEL_INFO + size_t i; if (array == NULL || len == 0U) { (void)printf("\n"); - } - - for (i = 0U; i < len; ++i) { - (void)printf(" %02x", array[i]); - if ((i & U(0xF)) == U(0xF)) { - (void)printf("\n"); - if (i < (len - 1U)) { - INFO("\t\t:"); + } else { + for (i = 0U; i < len; ++i) { + (void)printf(" %02x", array[i]); + if ((i & U(0xF)) == U(0xF)) { + (void)printf("\n"); + if (i < (len - 1U)) { + INFO("\t\t:"); + } } } } +#endif } static void log_measurement(uint8_t index, const uint8_t *signer_id, size_t signer_id_size, const uint8_t *version, /* string */ - uint32_t measurement_algo, + size_t version_size, const uint8_t *sw_type, /* string */ + size_t sw_type_size, + uint32_t measurement_algo, const uint8_t *measurement_value, size_t measurement_value_size, bool lock_measurement) @@ -47,9 +51,11 @@ static void log_measurement(uint8_t index, INFO(" - slot : %u\n", index); INFO(" - signer_id :"); print_byte_array(signer_id, signer_id_size); - INFO(" - version : %s\n", version); + INFO(" - version : %s\n", version); + INFO(" - version_size: %zu\n", version_size); + INFO(" - sw_type : %s\n", sw_type); + INFO(" - sw_type_size: %zu\n", sw_type_size); INFO(" - algorithm : %x\n", measurement_algo); - INFO(" - sw_type : %s\n", sw_type); INFO(" - measurement :"); print_byte_array(measurement_value, measurement_value_size); INFO(" - locking : %s\n", lock_measurement ? "true" : "false"); @@ -85,18 +91,17 @@ rss_measured_boot_extend_measurement(uint8_t index, {.base = measurement_value, .len = measurement_value_size} }; - uint32_t sw_type_size_limited; - if (sw_type != NULL) { - sw_type_size_limited = (sw_type_size < SW_TYPE_MAX_SIZE) ? - sw_type_size : SW_TYPE_MAX_SIZE; - memcpy(extend_iov.sw_type, sw_type, sw_type_size_limited); + if (sw_type_size > SW_TYPE_MAX_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(extend_iov.sw_type, sw_type, sw_type_size); } log_measurement(index, signer_id, signer_id_size, - version, measurement_algo, sw_type, - measurement_value, measurement_value_size, - lock_measurement); + version, version_size, sw_type, sw_type_size, + measurement_algo, measurement_value, + measurement_value_size, lock_measurement); return psa_call(RSS_MEASURED_BOOT_HANDLE, RSS_MEASURED_BOOT_EXTEND, @@ -120,9 +125,9 @@ rss_measured_boot_extend_measurement(uint8_t index, bool lock_measurement) { log_measurement(index, signer_id, signer_id_size, - version, measurement_algo, sw_type, - measurement_value, measurement_value_size, - lock_measurement); + version, version_size, sw_type, sw_type_size, + measurement_algo, measurement_value, + measurement_value_size, lock_measurement); return PSA_SUCCESS; } diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 170777f7a..8d736cc14 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -156,25 +156,26 @@ void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info) /******************************************************************************* * This function verifies that the all the other cores in the system have been * turned OFF and the current CPU is the last running CPU in the system. - * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false) - * otherwise. + * Returns true, if the current CPU is the last ON CPU or false otherwise. ******************************************************************************/ -unsigned int psci_is_last_on_cpu(void) +bool psci_is_last_on_cpu(void) { unsigned int cpu_idx, my_idx = plat_my_core_pos(); - for (cpu_idx = 0; cpu_idx < psci_plat_core_count; - cpu_idx++) { + for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { if (cpu_idx == my_idx) { assert(psci_get_aff_info_state() == AFF_STATE_ON); continue; } - if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF) - return 0; + if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF) { + VERBOSE("core=%u other than current core=%u %s\n", + cpu_idx, my_idx, "running in the system"); + return false; + } } - return 1; + return true; } /******************************************************************************* @@ -954,7 +955,7 @@ int psci_secondaries_brought_up(void) * Initiate power down sequence, by calling power down operations registered for * this CPU. ******************************************************************************/ -void psci_do_pwrdown_sequence(unsigned int power_level) +void psci_pwrdown_cpu(unsigned int power_level) { #if HW_ASSISTED_COHERENCY /* @@ -1009,11 +1010,11 @@ int psci_stop_other_cores(unsigned int wait_ms, /* Need to wait for other cores to shutdown */ if (wait_ms != 0U) { - while ((wait_ms-- != 0U) && (psci_is_last_on_cpu() != 0U)) { + while ((wait_ms-- != 0U) && (!psci_is_last_on_cpu())) { mdelay(1U); } - if (psci_is_last_on_cpu() != 0U) { + if (!psci_is_last_on_cpu()) { WARN("Failed to stop all cores!\n"); psci_print_power_domain_map(); return PSCI_E_DENIED; @@ -1022,3 +1023,30 @@ int psci_stop_other_cores(unsigned int wait_ms, return PSCI_E_SUCCESS; } + +/******************************************************************************* + * This function verifies that all the other cores in the system have been + * turned OFF and the current CPU is the last running CPU in the system. + * Returns true if the current CPU is the last ON CPU or false otherwise. + * + * This API has following differences with psci_is_last_on_cpu + * 1. PSCI states are locked + ******************************************************************************/ +bool psci_is_last_on_cpu_safe(void) +{ + unsigned int this_core = plat_my_core_pos(); + unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; + + psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes); + + psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); + + if (!psci_is_last_on_cpu()) { + psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); + return false; + } + + psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); + + return true; +} diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c index 52a8b8a18..a631f3ffb 100644 --- a/lib/psci/psci_main.c +++ b/lib/psci/psci_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -158,7 +158,7 @@ int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) entry_point_info_t ep; /* Check if the current CPU is the last ON CPU in the system */ - if (psci_is_last_on_cpu() == 0U) + if (!psci_is_last_on_cpu()) return PSCI_E_DENIED; /* Validate the entry point and get the entry_point_info */ diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c index 54470457a..637adb97e 100644 --- a/lib/psci/psci_off.c +++ b/lib/psci/psci_off.c @@ -109,7 +109,7 @@ int psci_do_cpu_off(unsigned int end_pwrlvl) /* * Arch. management. Initiate power down sequence. */ - psci_do_pwrdown_sequence(psci_find_max_off_lvl(&state_info)); + psci_pwrdown_cpu(psci_find_max_off_lvl(&state_info)); #if ENABLE_RUNTIME_INSTRUMENTATION PMF_CAPTURE_TIMESTAMP(rt_instr_svc, diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h index 72bd6bd11..1901c172f 100644 --- a/lib/psci/psci_private.h +++ b/lib/psci/psci_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,6 +47,9 @@ */ #define PSCI_MAX_CPUS_INDEX 0xFFFFU +/* Invalid parent */ +#define PSCI_PARENT_NODE_INVALID 0xFFFFFFFFU + /* * Helper functions to get/set the fields of PSCI per-cpu data. */ @@ -291,9 +294,8 @@ unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); void psci_print_power_domain_map(void); -unsigned int psci_is_last_on_cpu(void); +bool psci_is_last_on_cpu(void); int psci_spd_migrate_info(u_register_t *mpidr); -void psci_do_pwrdown_sequence(unsigned int power_level); /* * CPU power down is directly called only when HW_ASSISTED_COHERENCY is diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c index ffe3a911f..f71994d71 100644 --- a/lib/psci/psci_suspend.c +++ b/lib/psci/psci_suspend.c @@ -124,7 +124,7 @@ static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl, * TODO : Introduce a mechanism to query the cache level to flush * and the cpu-ops power down to perform from the platform. */ - psci_do_pwrdown_sequence(max_off_lvl); + psci_pwrdown_cpu(max_off_lvl); #if ENABLE_RUNTIME_INSTRUMENTATION PMF_CAPTURE_TIMESTAMP(rt_instr_svc, diff --git a/lib/semihosting/semihosting.c b/lib/semihosting/semihosting.c index e0845c1a5..163a82d84 100644 --- a/lib/semihosting/semihosting.c +++ b/lib/semihosting/semihosting.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,8 +64,10 @@ long semihosting_file_seek(long file_handle, ssize_t offset) result = semihosting_call(SEMIHOSTING_SYS_SEEK, (uintptr_t)&seek_block); - if (result != 0) { + if (result < 0) { result = semihosting_call(SEMIHOSTING_SYS_ERRNO, 0); + } else { + result = 0; } return result; diff --git a/lib/zlib/crc32.c b/lib/zlib/crc32.c index 9580440c0..f8357b083 100644 --- a/lib/zlib/crc32.c +++ b/lib/zlib/crc32.c @@ -1,12 +1,10 @@ /* crc32.c -- compute the CRC-32 of a data stream - * Copyright (C) 1995-2006, 2010, 2011, 2012, 2016 Mark Adler + * Copyright (C) 1995-2022 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h * - * Thanks to Rodney Brown <rbrown64@csc.com.au> for his contribution of faster - * CRC methods: exclusive-oring 32 bits of data at a time, and pre-computing - * tables for updating the shift register in one step with three exclusive-ors - * instead of four steps with four exclusive-ors. This results in about a - * factor of two increase in speed on a Power PC G4 (PPC7455) using gcc -O3. + * This interleaved implementation of a CRC makes use of pipelined multiple + * arithmetic-logic units, commonly found in modern CPU cores. It is due to + * Kadatch and Jenkins (2010). See doc/crc-doc.1.0.pdf in this distribution. */ /* @(#) $Id$ */ @@ -14,11 +12,12 @@ /* Note on the use of DYNAMIC_CRC_TABLE: there is no mutex or semaphore protection on the static variables used to control the first-use generation - of the crc tables. Therefore, if you #define DYNAMIC_CRC_TABLE, you should + of the crc tables. Therefore, if you #define DYNAMIC_CRC_TABLE, you should first call get_crc_table() to initialize the tables before allowing more than one thread to use crc32(). - DYNAMIC_CRC_TABLE and MAKECRCH can be #defined to write out crc32.h. + MAKECRCH can be #defined to write out crc32.h. A main() routine is also + produced, so that this one source file can be compiled to an executable. */ #ifdef MAKECRCH @@ -28,415 +27,1099 @@ # endif /* !DYNAMIC_CRC_TABLE */ #endif /* MAKECRCH */ -#include "zutil.h" /* for STDC and FAR definitions */ +#include "zutil.h" /* for Z_U4, Z_U8, z_crc_t, and FAR definitions */ -/* Definitions for doing the crc four data bytes at a time. */ -#if !defined(NOBYFOUR) && defined(Z_U4) -# define BYFOUR + /* + A CRC of a message is computed on N braids of words in the message, where + each word consists of W bytes (4 or 8). If N is 3, for example, then three + running sparse CRCs are calculated respectively on each braid, at these + indices in the array of words: 0, 3, 6, ..., 1, 4, 7, ..., and 2, 5, 8, ... + This is done starting at a word boundary, and continues until as many blocks + of N * W bytes as are available have been processed. The results are combined + into a single CRC at the end. For this code, N must be in the range 1..6 and + W must be 4 or 8. The upper limit on N can be increased if desired by adding + more #if blocks, extending the patterns apparent in the code. In addition, + crc32.h would need to be regenerated, if the maximum N value is increased. + + N and W are chosen empirically by benchmarking the execution time on a given + processor. The choices for N and W below were based on testing on Intel Kaby + Lake i7, AMD Ryzen 7, ARM Cortex-A57, Sparc64-VII, PowerPC POWER9, and MIPS64 + Octeon II processors. The Intel, AMD, and ARM processors were all fastest + with N=5, W=8. The Sparc, PowerPC, and MIPS64 were all fastest at N=5, W=4. + They were all tested with either gcc or clang, all using the -O3 optimization + level. Your mileage may vary. + */ + +/* Define N */ +#ifdef Z_TESTN +# define N Z_TESTN +#else +# define N 5 +#endif +#if N < 1 || N > 6 +# error N must be in 1..6 #endif -#ifdef BYFOUR - local unsigned long crc32_little OF((unsigned long, - const unsigned char FAR *, z_size_t)); - local unsigned long crc32_big OF((unsigned long, - const unsigned char FAR *, z_size_t)); -# define TBLS 8 + +/* + z_crc_t must be at least 32 bits. z_word_t must be at least as long as + z_crc_t. It is assumed here that z_word_t is either 32 bits or 64 bits, and + that bytes are eight bits. + */ + +/* + Define W and the associated z_word_t type. If W is not defined, then a + braided calculation is not used, and the associated tables and code are not + compiled. + */ +#ifdef Z_TESTW +# if Z_TESTW-1 != -1 +# define W Z_TESTW +# endif #else -# define TBLS 1 -#endif /* BYFOUR */ +# ifdef MAKECRCH +# define W 8 /* required for MAKECRCH */ +# else +# if defined(__x86_64__) || defined(__aarch64__) +# define W 8 +# else +# define W 4 +# endif +# endif +#endif +#ifdef W +# if W == 8 && defined(Z_U8) + typedef Z_U8 z_word_t; +# elif defined(Z_U4) +# undef W +# define W 4 + typedef Z_U4 z_word_t; +# else +# undef W +# endif +#endif + +/* If available, use the ARM processor CRC32 instruction. */ +#if defined(__aarch64__) && defined(__ARM_FEATURE_CRC32) && W == 8 +# define ARMCRC32 +#endif + +/* Local functions. */ +local z_crc_t multmodp OF((z_crc_t a, z_crc_t b)); +local z_crc_t x2nmodp OF((z_off64_t n, unsigned k)); + +#if defined(W) && (!defined(ARMCRC32) || defined(DYNAMIC_CRC_TABLE)) + local z_word_t byte_swap OF((z_word_t word)); +#endif + +#if defined(W) && !defined(ARMCRC32) + local z_crc_t crc_word OF((z_word_t data)); + local z_word_t crc_word_big OF((z_word_t data)); +#endif -/* Local functions for crc concatenation */ -local unsigned long gf2_matrix_times OF((unsigned long *mat, - unsigned long vec)); -local void gf2_matrix_square OF((unsigned long *square, unsigned long *mat)); -local uLong crc32_combine_ OF((uLong crc1, uLong crc2, z_off64_t len2)); +#if defined(W) && (!defined(ARMCRC32) || defined(DYNAMIC_CRC_TABLE)) +/* + Swap the bytes in a z_word_t to convert between little and big endian. Any + self-respecting compiler will optimize this to a single machine byte-swap + instruction, if one is available. This assumes that word_t is either 32 bits + or 64 bits. + */ +local z_word_t byte_swap(word) + z_word_t word; +{ +# if W == 8 + return + (word & 0xff00000000000000) >> 56 | + (word & 0xff000000000000) >> 40 | + (word & 0xff0000000000) >> 24 | + (word & 0xff00000000) >> 8 | + (word & 0xff000000) << 8 | + (word & 0xff0000) << 24 | + (word & 0xff00) << 40 | + (word & 0xff) << 56; +# else /* W == 4 */ + return + (word & 0xff000000) >> 24 | + (word & 0xff0000) >> 8 | + (word & 0xff00) << 8 | + (word & 0xff) << 24; +# endif +} +#endif +/* CRC polynomial. */ +#define POLY 0xedb88320 /* p(x) reflected, with x^32 implied */ #ifdef DYNAMIC_CRC_TABLE -local volatile int crc_table_empty = 1; -local z_crc_t FAR crc_table[TBLS][256]; +local z_crc_t FAR crc_table[256]; +local z_crc_t FAR x2n_table[32]; local void make_crc_table OF((void)); +#ifdef W + local z_word_t FAR crc_big_table[256]; + local z_crc_t FAR crc_braid_table[W][256]; + local z_word_t FAR crc_braid_big_table[W][256]; + local void braid OF((z_crc_t [][256], z_word_t [][256], int, int)); +#endif #ifdef MAKECRCH - local void write_table OF((FILE *, const z_crc_t FAR *)); + local void write_table OF((FILE *, const z_crc_t FAR *, int)); + local void write_table32hi OF((FILE *, const z_word_t FAR *, int)); + local void write_table64 OF((FILE *, const z_word_t FAR *, int)); #endif /* MAKECRCH */ + +/* + Define a once() function depending on the availability of atomics. If this is + compiled with DYNAMIC_CRC_TABLE defined, and if CRCs will be computed in + multiple threads, and if atomics are not available, then get_crc_table() must + be called to initialize the tables and must return before any threads are + allowed to compute or combine CRCs. + */ + +/* Definition of once functionality. */ +typedef struct once_s once_t; +local void once OF((once_t *, void (*)(void))); + +/* Check for the availability of atomics. */ +#if defined(__STDC__) && __STDC_VERSION__ >= 201112L && \ + !defined(__STDC_NO_ATOMICS__) + +#include <stdatomic.h> + +/* Structure for once(), which must be initialized with ONCE_INIT. */ +struct once_s { + atomic_flag begun; + atomic_int done; +}; +#define ONCE_INIT {ATOMIC_FLAG_INIT, 0} + +/* + Run the provided init() function exactly once, even if multiple threads + invoke once() at the same time. The state must be a once_t initialized with + ONCE_INIT. + */ +local void once(state, init) + once_t *state; + void (*init)(void); +{ + if (!atomic_load(&state->done)) { + if (atomic_flag_test_and_set(&state->begun)) + while (!atomic_load(&state->done)) + ; + else { + init(); + atomic_store(&state->done, 1); + } + } +} + +#else /* no atomics */ + +/* Structure for once(), which must be initialized with ONCE_INIT. */ +struct once_s { + volatile int begun; + volatile int done; +}; +#define ONCE_INIT {0, 0} + +/* Test and set. Alas, not atomic, but tries to minimize the period of + vulnerability. */ +local int test_and_set OF((int volatile *)); +local int test_and_set(flag) + int volatile *flag; +{ + int was; + + was = *flag; + *flag = 1; + return was; +} + +/* Run the provided init() function once. This is not thread-safe. */ +local void once(state, init) + once_t *state; + void (*init)(void); +{ + if (!state->done) { + if (test_and_set(&state->begun)) + while (!state->done) + ; + else { + init(); + state->done = 1; + } + } +} + +#endif + +/* State for once(). */ +local once_t made = ONCE_INIT; + /* Generate tables for a byte-wise 32-bit CRC calculation on the polynomial: x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1. Polynomials over GF(2) are represented in binary, one bit per coefficient, - with the lowest powers in the most significant bit. Then adding polynomials + with the lowest powers in the most significant bit. Then adding polynomials is just exclusive-or, and multiplying a polynomial by x is a right shift by - one. If we call the above polynomial p, and represent a byte as the + one. If we call the above polynomial p, and represent a byte as the polynomial q, also with the lowest power in the most significant bit (so the - byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p, + byte 0xb1 is the polynomial x^7+x^3+x^2+1), then the CRC is (q*x^32) mod p, where a mod b means the remainder after dividing a by b. This calculation is done using the shift-register method of multiplying and - taking the remainder. The register is initialized to zero, and for each + taking the remainder. The register is initialized to zero, and for each incoming bit, x^32 is added mod p to the register if the bit is a one (where - x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by - x (which is shifting right by one and adding x^32 mod p if the bit shifted - out is a one). We start with the highest power (least significant bit) of - q and repeat for all eight bits of q. - - The first table is simply the CRC of all possible eight bit values. This is - all the information needed to generate CRCs on data a byte at a time for all - combinations of CRC register values and incoming bytes. The remaining tables - allow for word-at-a-time CRC calculation for both big-endian and little- - endian machines, where a word is four bytes. -*/ + x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by x + (which is shifting right by one and adding x^32 mod p if the bit shifted out + is a one). We start with the highest power (least significant bit) of q and + repeat for all eight bits of q. + + The table is simply the CRC of all possible eight bit values. This is all the + information needed to generate CRCs on data a byte at a time for all + combinations of CRC register values and incoming bytes. + */ + local void make_crc_table() { - z_crc_t c; - int n, k; - z_crc_t poly; /* polynomial exclusive-or pattern */ - /* terms of polynomial defining this crc (except x^32): */ - static volatile int first = 1; /* flag to limit concurrent making */ - static const unsigned char p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26}; - - /* See if another task is already doing this (not thread-safe, but better - than nothing -- significantly reduces duration of vulnerability in - case the advice about DYNAMIC_CRC_TABLE is ignored) */ - if (first) { - first = 0; - - /* make exclusive-or pattern from polynomial (0xedb88320UL) */ - poly = 0; - for (n = 0; n < (int)(sizeof(p)/sizeof(unsigned char)); n++) - poly |= (z_crc_t)1 << (31 - p[n]); - - /* generate a crc for every 8-bit value */ - for (n = 0; n < 256; n++) { - c = (z_crc_t)n; - for (k = 0; k < 8; k++) - c = c & 1 ? poly ^ (c >> 1) : c >> 1; - crc_table[0][n] = c; - } - -#ifdef BYFOUR - /* generate crc for each value followed by one, two, and three zeros, - and then the byte reversal of those as well as the first table */ - for (n = 0; n < 256; n++) { - c = crc_table[0][n]; - crc_table[4][n] = ZSWAP32(c); - for (k = 1; k < 4; k++) { - c = crc_table[0][c & 0xff] ^ (c >> 8); - crc_table[k][n] = c; - crc_table[k + 4][n] = ZSWAP32(c); - } - } -#endif /* BYFOUR */ + unsigned i, j, n; + z_crc_t p; - crc_table_empty = 0; - } - else { /* not first */ - /* wait for the other guy to finish (not efficient, but rare) */ - while (crc_table_empty) - ; + /* initialize the CRC of bytes tables */ + for (i = 0; i < 256; i++) { + p = i; + for (j = 0; j < 8; j++) + p = p & 1 ? (p >> 1) ^ POLY : p >> 1; + crc_table[i] = p; +#ifdef W + crc_big_table[i] = byte_swap(p); +#endif } + /* initialize the x^2^n mod p(x) table */ + p = (z_crc_t)1 << 30; /* x^1 */ + x2n_table[0] = p; + for (n = 1; n < 32; n++) + x2n_table[n] = p = multmodp(p, p); + +#ifdef W + /* initialize the braiding tables -- needs x2n_table[] */ + braid(crc_braid_table, crc_braid_big_table, N, W); +#endif + #ifdef MAKECRCH - /* write out CRC tables to crc32.h */ { + /* + The crc32.h header file contains tables for both 32-bit and 64-bit + z_word_t's, and so requires a 64-bit type be available. In that case, + z_word_t must be defined to be 64-bits. This code then also generates + and writes out the tables for the case that z_word_t is 32 bits. + */ +#if !defined(W) || W != 8 +# error Need a 64-bit integer type in order to generate crc32.h. +#endif FILE *out; + int k, n; + z_crc_t ltl[8][256]; + z_word_t big[8][256]; out = fopen("crc32.h", "w"); if (out == NULL) return; - fprintf(out, "/* crc32.h -- tables for rapid CRC calculation\n"); - fprintf(out, " * Generated automatically by crc32.c\n */\n\n"); - fprintf(out, "local const z_crc_t FAR "); - fprintf(out, "crc_table[TBLS][256] =\n{\n {\n"); - write_table(out, crc_table[0]); -# ifdef BYFOUR - fprintf(out, "#ifdef BYFOUR\n"); - for (k = 1; k < 8; k++) { - fprintf(out, " },\n {\n"); - write_table(out, crc_table[k]); + + /* write out little-endian CRC table to crc32.h */ + fprintf(out, + "/* crc32.h -- tables for rapid CRC calculation\n" + " * Generated automatically by crc32.c\n */\n" + "\n" + "local const z_crc_t FAR crc_table[] = {\n" + " "); + write_table(out, crc_table, 256); + fprintf(out, + "};\n"); + + /* write out big-endian CRC table for 64-bit z_word_t to crc32.h */ + fprintf(out, + "\n" + "#ifdef W\n" + "\n" + "#if W == 8\n" + "\n" + "local const z_word_t FAR crc_big_table[] = {\n" + " "); + write_table64(out, crc_big_table, 256); + fprintf(out, + "};\n"); + + /* write out big-endian CRC table for 32-bit z_word_t to crc32.h */ + fprintf(out, + "\n" + "#else /* W == 4 */\n" + "\n" + "local const z_word_t FAR crc_big_table[] = {\n" + " "); + write_table32hi(out, crc_big_table, 256); + fprintf(out, + "};\n" + "\n" + "#endif\n"); + + /* write out braid tables for each value of N */ + for (n = 1; n <= 6; n++) { + fprintf(out, + "\n" + "#if N == %d\n", n); + + /* compute braid tables for this N and 64-bit word_t */ + braid(ltl, big, n, 8); + + /* write out braid tables for 64-bit z_word_t to crc32.h */ + fprintf(out, + "\n" + "#if W == 8\n" + "\n" + "local const z_crc_t FAR crc_braid_table[][256] = {\n"); + for (k = 0; k < 8; k++) { + fprintf(out, " {"); + write_table(out, ltl[k], 256); + fprintf(out, "}%s", k < 7 ? ",\n" : ""); + } + fprintf(out, + "};\n" + "\n" + "local const z_word_t FAR crc_braid_big_table[][256] = {\n"); + for (k = 0; k < 8; k++) { + fprintf(out, " {"); + write_table64(out, big[k], 256); + fprintf(out, "}%s", k < 7 ? ",\n" : ""); + } + fprintf(out, + "};\n"); + + /* compute braid tables for this N and 32-bit word_t */ + braid(ltl, big, n, 4); + + /* write out braid tables for 32-bit z_word_t to crc32.h */ + fprintf(out, + "\n" + "#else /* W == 4 */\n" + "\n" + "local const z_crc_t FAR crc_braid_table[][256] = {\n"); + for (k = 0; k < 4; k++) { + fprintf(out, " {"); + write_table(out, ltl[k], 256); + fprintf(out, "}%s", k < 3 ? ",\n" : ""); + } + fprintf(out, + "};\n" + "\n" + "local const z_word_t FAR crc_braid_big_table[][256] = {\n"); + for (k = 0; k < 4; k++) { + fprintf(out, " {"); + write_table32hi(out, big[k], 256); + fprintf(out, "}%s", k < 3 ? ",\n" : ""); + } + fprintf(out, + "};\n" + "\n" + "#endif\n" + "\n" + "#endif\n"); } - fprintf(out, "#endif\n"); -# endif /* BYFOUR */ - fprintf(out, " }\n};\n"); + fprintf(out, + "\n" + "#endif\n"); + + /* write out zeros operator table to crc32.h */ + fprintf(out, + "\n" + "local const z_crc_t FAR x2n_table[] = {\n" + " "); + write_table(out, x2n_table, 32); + fprintf(out, + "};\n"); fclose(out); } #endif /* MAKECRCH */ } #ifdef MAKECRCH -local void write_table(out, table) + +/* + Write the 32-bit values in table[0..k-1] to out, five per line in + hexadecimal separated by commas. + */ +local void write_table(out, table, k) FILE *out; const z_crc_t FAR *table; + int k; { int n; - for (n = 0; n < 256; n++) - fprintf(out, "%s0x%08lxUL%s", n % 5 ? "" : " ", + for (n = 0; n < k; n++) + fprintf(out, "%s0x%08lx%s", n == 0 || n % 5 ? "" : " ", (unsigned long)(table[n]), - n == 255 ? "\n" : (n % 5 == 4 ? ",\n" : ", ")); + n == k - 1 ? "" : (n % 5 == 4 ? ",\n" : ", ")); +} + +/* + Write the high 32-bits of each value in table[0..k-1] to out, five per line + in hexadecimal separated by commas. + */ +local void write_table32hi(out, table, k) +FILE *out; +const z_word_t FAR *table; +int k; +{ + int n; + + for (n = 0; n < k; n++) + fprintf(out, "%s0x%08lx%s", n == 0 || n % 5 ? "" : " ", + (unsigned long)(table[n] >> 32), + n == k - 1 ? "" : (n % 5 == 4 ? ",\n" : ", ")); +} + +/* + Write the 64-bit values in table[0..k-1] to out, three per line in + hexadecimal separated by commas. This assumes that if there is a 64-bit + type, then there is also a long long integer type, and it is at least 64 + bits. If not, then the type cast and format string can be adjusted + accordingly. + */ +local void write_table64(out, table, k) + FILE *out; + const z_word_t FAR *table; + int k; +{ + int n; + + for (n = 0; n < k; n++) + fprintf(out, "%s0x%016llx%s", n == 0 || n % 3 ? "" : " ", + (unsigned long long)(table[n]), + n == k - 1 ? "" : (n % 3 == 2 ? ",\n" : ", ")); } + +/* Actually do the deed. */ +int main() +{ + make_crc_table(); + return 0; +} + #endif /* MAKECRCH */ +#ifdef W +/* + Generate the little and big-endian braid tables for the given n and z_word_t + size w. Each array must have room for w blocks of 256 elements. + */ +local void braid(ltl, big, n, w) + z_crc_t ltl[][256]; + z_word_t big[][256]; + int n; + int w; +{ + int k; + z_crc_t i, p, q; + for (k = 0; k < w; k++) { + p = x2nmodp((n * w + 3 - k) << 3, 0); + ltl[k][0] = 0; + big[w - 1 - k][0] = 0; + for (i = 1; i < 256; i++) { + ltl[k][i] = q = multmodp(i << 24, p); + big[w - 1 - k][i] = byte_swap(q); + } + } +} +#endif + #else /* !DYNAMIC_CRC_TABLE */ /* ======================================================================== - * Tables of CRC-32s of all single-byte values, made by make_crc_table(). + * Tables for byte-wise and braided CRC-32 calculations, and a table of powers + * of x for combining CRC-32s, all made by make_crc_table(). */ #include "crc32.h" #endif /* DYNAMIC_CRC_TABLE */ +/* ======================================================================== + * Routines used for CRC calculation. Some are also required for the table + * generation above. + */ + +/* + Return a(x) multiplied by b(x) modulo p(x), where p(x) is the CRC polynomial, + reflected. For speed, this requires that a not be zero. + */ +local z_crc_t multmodp(a, b) + z_crc_t a; + z_crc_t b; +{ + z_crc_t m, p; + + m = (z_crc_t)1 << 31; + p = 0; + for (;;) { + if (a & m) { + p ^= b; + if ((a & (m - 1)) == 0) + break; + } + m >>= 1; + b = b & 1 ? (b >> 1) ^ POLY : b >> 1; + } + return p; +} + +/* + Return x^(n * 2^k) modulo p(x). Requires that x2n_table[] has been + initialized. + */ +local z_crc_t x2nmodp(n, k) + z_off64_t n; + unsigned k; +{ + z_crc_t p; + + p = (z_crc_t)1 << 31; /* x^0 == 1 */ + while (n) { + if (n & 1) + p = multmodp(x2n_table[k & 31], p); + n >>= 1; + k++; + } + return p; +} + /* ========================================================================= - * This function can be used by asm versions of crc32() + * This function can be used by asm versions of crc32(), and to force the + * generation of the CRC tables in a threaded application. */ const z_crc_t FAR * ZEXPORT get_crc_table() { #ifdef DYNAMIC_CRC_TABLE - if (crc_table_empty) - make_crc_table(); + once(&made, make_crc_table); #endif /* DYNAMIC_CRC_TABLE */ return (const z_crc_t FAR *)crc_table; } -/* ========================================================================= */ -#define DO1 crc = crc_table[0][((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8) -#define DO8 DO1; DO1; DO1; DO1; DO1; DO1; DO1; DO1 +/* ========================================================================= + * Use ARM machine instructions if available. This will compute the CRC about + * ten times faster than the braided calculation. This code does not check for + * the presence of the CRC instruction at run time. __ARM_FEATURE_CRC32 will + * only be defined if the compilation specifies an ARM processor architecture + * that has the instructions. For example, compiling with -march=armv8.1-a or + * -march=armv8-a+crc, or -march=native if the compile machine has the crc32 + * instructions. + */ +#ifdef ARMCRC32 + +/* + Constants empirically determined to maximize speed. These values are from + measurements on a Cortex-A57. Your mileage may vary. + */ +#define Z_BATCH 3990 /* number of words in a batch */ +#define Z_BATCH_ZEROS 0xa10d3d0c /* computed from Z_BATCH = 3990 */ +#define Z_BATCH_MIN 800 /* fewest words in a final batch */ -/* ========================================================================= */ unsigned long ZEXPORT crc32_z(crc, buf, len) unsigned long crc; const unsigned char FAR *buf; z_size_t len; { - if (buf == Z_NULL) return 0UL; + z_crc_t val; + z_word_t crc1, crc2; + const z_word_t *word; + z_word_t val0, val1, val2; + z_size_t last, last2, i; + z_size_t num; + + /* Return initial CRC, if requested. */ + if (buf == Z_NULL) return 0; #ifdef DYNAMIC_CRC_TABLE - if (crc_table_empty) - make_crc_table(); + once(&made, make_crc_table); #endif /* DYNAMIC_CRC_TABLE */ -#ifdef BYFOUR - if (sizeof(void *) == sizeof(ptrdiff_t)) { - z_crc_t endian; + /* Pre-condition the CRC */ + crc = (~crc) & 0xffffffff; - endian = 1; - if (*((unsigned char *)(&endian))) - return crc32_little(crc, buf, len); - else - return crc32_big(crc, buf, len); + /* Compute the CRC up to a word boundary. */ + while (len && ((z_size_t)buf & 7) != 0) { + len--; + val = *buf++; + __asm__ volatile("crc32b %w0, %w0, %w1" : "+r"(crc) : "r"(val)); } -#endif /* BYFOUR */ - crc = crc ^ 0xffffffffUL; - while (len >= 8) { - DO8; - len -= 8; + + /* Prepare to compute the CRC on full 64-bit words word[0..num-1]. */ + word = (z_word_t const *)buf; + num = len >> 3; + len &= 7; + + /* Do three interleaved CRCs to realize the throughput of one crc32x + instruction per cycle. Each CRC is calculated on Z_BATCH words. The + three CRCs are combined into a single CRC after each set of batches. */ + while (num >= 3 * Z_BATCH) { + crc1 = 0; + crc2 = 0; + for (i = 0; i < Z_BATCH; i++) { + val0 = word[i]; + val1 = word[i + Z_BATCH]; + val2 = word[i + 2 * Z_BATCH]; + __asm__ volatile("crc32x %w0, %w0, %x1" : "+r"(crc) : "r"(val0)); + __asm__ volatile("crc32x %w0, %w0, %x1" : "+r"(crc1) : "r"(val1)); + __asm__ volatile("crc32x %w0, %w0, %x1" : "+r"(crc2) : "r"(val2)); + } + word += 3 * Z_BATCH; + num -= 3 * Z_BATCH; + crc = multmodp(Z_BATCH_ZEROS, crc) ^ crc1; + crc = multmodp(Z_BATCH_ZEROS, crc) ^ crc2; } - if (len) do { - DO1; - } while (--len); - return crc ^ 0xffffffffUL; -} -/* ========================================================================= */ -unsigned long ZEXPORT crc32(crc, buf, len) - unsigned long crc; - const unsigned char FAR *buf; - uInt len; -{ - return crc32_z(crc, buf, len); + /* Do one last smaller batch with the remaining words, if there are enough + to pay for the combination of CRCs. */ + last = num / 3; + if (last >= Z_BATCH_MIN) { + last2 = last << 1; + crc1 = 0; + crc2 = 0; + for (i = 0; i < last; i++) { + val0 = word[i]; + val1 = word[i + last]; + val2 = word[i + last2]; + __asm__ volatile("crc32x %w0, %w0, %x1" : "+r"(crc) : "r"(val0)); + __asm__ volatile("crc32x %w0, %w0, %x1" : "+r"(crc1) : "r"(val1)); + __asm__ volatile("crc32x %w0, %w0, %x1" : "+r"(crc2) : "r"(val2)); + } + word += 3 * last; + num -= 3 * last; + val = x2nmodp(last, 6); + crc = multmodp(val, crc) ^ crc1; + crc = multmodp(val, crc) ^ crc2; + } + + /* Compute the CRC on any remaining words. */ + for (i = 0; i < num; i++) { + val0 = word[i]; + __asm__ volatile("crc32x %w0, %w0, %x1" : "+r"(crc) : "r"(val0)); + } + word += num; + + /* Complete the CRC on any remaining bytes. */ + buf = (const unsigned char FAR *)word; + while (len) { + len--; + val = *buf++; + __asm__ volatile("crc32b %w0, %w0, %w1" : "+r"(crc) : "r"(val)); + } + + /* Return the CRC, post-conditioned. */ + return crc ^ 0xffffffff; } -#ifdef BYFOUR +#else + +#ifdef W /* - This BYFOUR code accesses the passed unsigned char * buffer with a 32-bit - integer pointer type. This violates the strict aliasing rule, where a - compiler can assume, for optimization purposes, that two pointers to - fundamentally different types won't ever point to the same memory. This can - manifest as a problem only if one of the pointers is written to. This code - only reads from those pointers. So long as this code remains isolated in - this compilation unit, there won't be a problem. For this reason, this code - should not be copied and pasted into a compilation unit in which other code - writes to the buffer that is passed to these routines. + Return the CRC of the W bytes in the word_t data, taking the + least-significant byte of the word as the first byte of data, without any pre + or post conditioning. This is used to combine the CRCs of each braid. */ +local z_crc_t crc_word(data) + z_word_t data; +{ + int k; + for (k = 0; k < W; k++) + data = (data >> 8) ^ crc_table[data & 0xff]; + return (z_crc_t)data; +} -/* ========================================================================= */ -#define DOLIT4 c ^= *buf4++; \ - c = crc_table[3][c & 0xff] ^ crc_table[2][(c >> 8) & 0xff] ^ \ - crc_table[1][(c >> 16) & 0xff] ^ crc_table[0][c >> 24] -#define DOLIT32 DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4 +local z_word_t crc_word_big(data) + z_word_t data; +{ + int k; + for (k = 0; k < W; k++) + data = (data << 8) ^ + crc_big_table[(data >> ((W - 1) << 3)) & 0xff]; + return data; +} + +#endif /* ========================================================================= */ -local unsigned long crc32_little(crc, buf, len) +unsigned long ZEXPORT crc32_z(crc, buf, len) unsigned long crc; const unsigned char FAR *buf; z_size_t len; { - register z_crc_t c; - register const z_crc_t FAR *buf4; + /* Return initial CRC, if requested. */ + if (buf == Z_NULL) return 0; - c = (z_crc_t)crc; - c = ~c; - while (len && ((ptrdiff_t)buf & 3)) { - c = crc_table[0][(c ^ *buf++) & 0xff] ^ (c >> 8); - len--; - } +#ifdef DYNAMIC_CRC_TABLE + once(&made, make_crc_table); +#endif /* DYNAMIC_CRC_TABLE */ - buf4 = (const z_crc_t FAR *)(const void FAR *)buf; - while (len >= 32) { - DOLIT32; - len -= 32; - } - while (len >= 4) { - DOLIT4; - len -= 4; - } - buf = (const unsigned char FAR *)buf4; + /* Pre-condition the CRC */ + crc = (~crc) & 0xffffffff; - if (len) do { - c = crc_table[0][(c ^ *buf++) & 0xff] ^ (c >> 8); - } while (--len); - c = ~c; - return (unsigned long)c; -} +#ifdef W -/* ========================================================================= */ -#define DOBIG4 c ^= *buf4++; \ - c = crc_table[4][c & 0xff] ^ crc_table[5][(c >> 8) & 0xff] ^ \ - crc_table[6][(c >> 16) & 0xff] ^ crc_table[7][c >> 24] -#define DOBIG32 DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4 + /* If provided enough bytes, do a braided CRC calculation. */ + if (len >= N * W + W - 1) { + z_size_t blks; + z_word_t const *words; + unsigned endian; + int k; -/* ========================================================================= */ -local unsigned long crc32_big(crc, buf, len) - unsigned long crc; - const unsigned char FAR *buf; - z_size_t len; -{ - register z_crc_t c; - register const z_crc_t FAR *buf4; + /* Compute the CRC up to a z_word_t boundary. */ + while (len && ((z_size_t)buf & (W - 1)) != 0) { + len--; + crc = (crc >> 8) ^ crc_table[(crc ^ *buf++) & 0xff]; + } - c = ZSWAP32((z_crc_t)crc); - c = ~c; - while (len && ((ptrdiff_t)buf & 3)) { - c = crc_table[4][(c >> 24) ^ *buf++] ^ (c << 8); - len--; + /* Compute the CRC on as many N z_word_t blocks as are available. */ + blks = len / (N * W); + len -= blks * N * W; + words = (z_word_t const *)buf; + + /* Do endian check at execution time instead of compile time, since ARM + processors can change the endianess at execution time. If the + compiler knows what the endianess will be, it can optimize out the + check and the unused branch. */ + endian = 1; + if (*(unsigned char *)&endian) { + /* Little endian. */ + + z_crc_t crc0; + z_word_t word0; +#if N > 1 + z_crc_t crc1; + z_word_t word1; +#if N > 2 + z_crc_t crc2; + z_word_t word2; +#if N > 3 + z_crc_t crc3; + z_word_t word3; +#if N > 4 + z_crc_t crc4; + z_word_t word4; +#if N > 5 + z_crc_t crc5; + z_word_t word5; +#endif +#endif +#endif +#endif +#endif + + /* Initialize the CRC for each braid. */ + crc0 = crc; +#if N > 1 + crc1 = 0; +#if N > 2 + crc2 = 0; +#if N > 3 + crc3 = 0; +#if N > 4 + crc4 = 0; +#if N > 5 + crc5 = 0; +#endif +#endif +#endif +#endif +#endif + + /* + Process the first blks-1 blocks, computing the CRCs on each braid + independently. + */ + while (--blks) { + /* Load the word for each braid into registers. */ + word0 = crc0 ^ words[0]; +#if N > 1 + word1 = crc1 ^ words[1]; +#if N > 2 + word2 = crc2 ^ words[2]; +#if N > 3 + word3 = crc3 ^ words[3]; +#if N > 4 + word4 = crc4 ^ words[4]; +#if N > 5 + word5 = crc5 ^ words[5]; +#endif +#endif +#endif +#endif +#endif + words += N; + + /* Compute and update the CRC for each word. The loop should + get unrolled. */ + crc0 = crc_braid_table[0][word0 & 0xff]; +#if N > 1 + crc1 = crc_braid_table[0][word1 & 0xff]; +#if N > 2 + crc2 = crc_braid_table[0][word2 & 0xff]; +#if N > 3 + crc3 = crc_braid_table[0][word3 & 0xff]; +#if N > 4 + crc4 = crc_braid_table[0][word4 & 0xff]; +#if N > 5 + crc5 = crc_braid_table[0][word5 & 0xff]; +#endif +#endif +#endif +#endif +#endif + for (k = 1; k < W; k++) { + crc0 ^= crc_braid_table[k][(word0 >> (k << 3)) & 0xff]; +#if N > 1 + crc1 ^= crc_braid_table[k][(word1 >> (k << 3)) & 0xff]; +#if N > 2 + crc2 ^= crc_braid_table[k][(word2 >> (k << 3)) & 0xff]; +#if N > 3 + crc3 ^= crc_braid_table[k][(word3 >> (k << 3)) & 0xff]; +#if N > 4 + crc4 ^= crc_braid_table[k][(word4 >> (k << 3)) & 0xff]; +#if N > 5 + crc5 ^= crc_braid_table[k][(word5 >> (k << 3)) & 0xff]; +#endif +#endif +#endif +#endif +#endif + } + } + + /* + Process the last block, combining the CRCs of the N braids at the + same time. + */ + crc = crc_word(crc0 ^ words[0]); +#if N > 1 + crc = crc_word(crc1 ^ words[1] ^ crc); +#if N > 2 + crc = crc_word(crc2 ^ words[2] ^ crc); +#if N > 3 + crc = crc_word(crc3 ^ words[3] ^ crc); +#if N > 4 + crc = crc_word(crc4 ^ words[4] ^ crc); +#if N > 5 + crc = crc_word(crc5 ^ words[5] ^ crc); +#endif +#endif +#endif +#endif +#endif + words += N; + } + else { + /* Big endian. */ + + z_word_t crc0, word0, comb; +#if N > 1 + z_word_t crc1, word1; +#if N > 2 + z_word_t crc2, word2; +#if N > 3 + z_word_t crc3, word3; +#if N > 4 + z_word_t crc4, word4; +#if N > 5 + z_word_t crc5, word5; +#endif +#endif +#endif +#endif +#endif + + /* Initialize the CRC for each braid. */ + crc0 = byte_swap(crc); +#if N > 1 + crc1 = 0; +#if N > 2 + crc2 = 0; +#if N > 3 + crc3 = 0; +#if N > 4 + crc4 = 0; +#if N > 5 + crc5 = 0; +#endif +#endif +#endif +#endif +#endif + + /* + Process the first blks-1 blocks, computing the CRCs on each braid + independently. + */ + while (--blks) { + /* Load the word for each braid into registers. */ + word0 = crc0 ^ words[0]; +#if N > 1 + word1 = crc1 ^ words[1]; +#if N > 2 + word2 = crc2 ^ words[2]; +#if N > 3 + word3 = crc3 ^ words[3]; +#if N > 4 + word4 = crc4 ^ words[4]; +#if N > 5 + word5 = crc5 ^ words[5]; +#endif +#endif +#endif +#endif +#endif + words += N; + + /* Compute and update the CRC for each word. The loop should + get unrolled. */ + crc0 = crc_braid_big_table[0][word0 & 0xff]; +#if N > 1 + crc1 = crc_braid_big_table[0][word1 & 0xff]; +#if N > 2 + crc2 = crc_braid_big_table[0][word2 & 0xff]; +#if N > 3 + crc3 = crc_braid_big_table[0][word3 & 0xff]; +#if N > 4 + crc4 = crc_braid_big_table[0][word4 & 0xff]; +#if N > 5 + crc5 = crc_braid_big_table[0][word5 & 0xff]; +#endif +#endif +#endif +#endif +#endif + for (k = 1; k < W; k++) { + crc0 ^= crc_braid_big_table[k][(word0 >> (k << 3)) & 0xff]; +#if N > 1 + crc1 ^= crc_braid_big_table[k][(word1 >> (k << 3)) & 0xff]; +#if N > 2 + crc2 ^= crc_braid_big_table[k][(word2 >> (k << 3)) & 0xff]; +#if N > 3 + crc3 ^= crc_braid_big_table[k][(word3 >> (k << 3)) & 0xff]; +#if N > 4 + crc4 ^= crc_braid_big_table[k][(word4 >> (k << 3)) & 0xff]; +#if N > 5 + crc5 ^= crc_braid_big_table[k][(word5 >> (k << 3)) & 0xff]; +#endif +#endif +#endif +#endif +#endif + } + } + + /* + Process the last block, combining the CRCs of the N braids at the + same time. + */ + comb = crc_word_big(crc0 ^ words[0]); +#if N > 1 + comb = crc_word_big(crc1 ^ words[1] ^ comb); +#if N > 2 + comb = crc_word_big(crc2 ^ words[2] ^ comb); +#if N > 3 + comb = crc_word_big(crc3 ^ words[3] ^ comb); +#if N > 4 + comb = crc_word_big(crc4 ^ words[4] ^ comb); +#if N > 5 + comb = crc_word_big(crc5 ^ words[5] ^ comb); +#endif +#endif +#endif +#endif +#endif + words += N; + crc = byte_swap(comb); + } + + /* + Update the pointer to the remaining bytes to process. + */ + buf = (unsigned char const *)words; } - buf4 = (const z_crc_t FAR *)(const void FAR *)buf; - while (len >= 32) { - DOBIG32; - len -= 32; +#endif /* W */ + + /* Complete the computation of the CRC on any remaining bytes. */ + while (len >= 8) { + len -= 8; + crc = (crc >> 8) ^ crc_table[(crc ^ *buf++) & 0xff]; + crc = (crc >> 8) ^ crc_table[(crc ^ *buf++) & 0xff]; + crc = (crc >> 8) ^ crc_table[(crc ^ *buf++) & 0xff]; + crc = (crc >> 8) ^ crc_table[(crc ^ *buf++) & 0xff]; + crc = (crc >> 8) ^ crc_table[(crc ^ *buf++) & 0xff]; + crc = (crc >> 8) ^ crc_table[(crc ^ *buf++) & 0xff]; + crc = (crc >> 8) ^ crc_table[(crc ^ *buf++) & 0xff]; + crc = (crc >> 8) ^ crc_table[(crc ^ *buf++) & 0xff]; } - while (len >= 4) { - DOBIG4; - len -= 4; + while (len) { + len--; + crc = (crc >> 8) ^ crc_table[(crc ^ *buf++) & 0xff]; } - buf = (const unsigned char FAR *)buf4; - if (len) do { - c = crc_table[4][(c >> 24) ^ *buf++] ^ (c << 8); - } while (--len); - c = ~c; - return (unsigned long)(ZSWAP32(c)); + /* Return the CRC, post-conditioned. */ + return crc ^ 0xffffffff; } -#endif /* BYFOUR */ - -#define GF2_DIM 32 /* dimension of GF(2) vectors (length of CRC) */ +#endif /* ========================================================================= */ -local unsigned long gf2_matrix_times(mat, vec) - unsigned long *mat; - unsigned long vec; +unsigned long ZEXPORT crc32(crc, buf, len) + unsigned long crc; + const unsigned char FAR *buf; + uInt len; { - unsigned long sum; - - sum = 0; - while (vec) { - if (vec & 1) - sum ^= *mat; - vec >>= 1; - mat++; - } - return sum; + return crc32_z(crc, buf, len); } /* ========================================================================= */ -local void gf2_matrix_square(square, mat) - unsigned long *square; - unsigned long *mat; +uLong ZEXPORT crc32_combine64(crc1, crc2, len2) + uLong crc1; + uLong crc2; + z_off64_t len2; { - int n; - - for (n = 0; n < GF2_DIM; n++) - square[n] = gf2_matrix_times(mat, mat[n]); +#ifdef DYNAMIC_CRC_TABLE + once(&made, make_crc_table); +#endif /* DYNAMIC_CRC_TABLE */ + return multmodp(x2nmodp(len2, 3), crc1) ^ (crc2 & 0xffffffff); } /* ========================================================================= */ -local uLong crc32_combine_(crc1, crc2, len2) +uLong ZEXPORT crc32_combine(crc1, crc2, len2) uLong crc1; uLong crc2; - z_off64_t len2; + z_off_t len2; { - int n; - unsigned long row; - unsigned long even[GF2_DIM]; /* even-power-of-two zeros operator */ - unsigned long odd[GF2_DIM]; /* odd-power-of-two zeros operator */ - - /* degenerate case (also disallow negative lengths) */ - if (len2 <= 0) - return crc1; - - /* put operator for one zero bit in odd */ - odd[0] = 0xedb88320UL; /* CRC-32 polynomial */ - row = 1; - for (n = 1; n < GF2_DIM; n++) { - odd[n] = row; - row <<= 1; - } + return crc32_combine64(crc1, crc2, (z_off64_t)len2); +} - /* put operator for two zero bits in even */ - gf2_matrix_square(even, odd); - - /* put operator for four zero bits in odd */ - gf2_matrix_square(odd, even); - - /* apply len2 zeros to crc1 (first square will put the operator for one - zero byte, eight zero bits, in even) */ - do { - /* apply zeros operator for this bit of len2 */ - gf2_matrix_square(even, odd); - if (len2 & 1) - crc1 = gf2_matrix_times(even, crc1); - len2 >>= 1; - - /* if no more bits set, then done */ - if (len2 == 0) - break; - - /* another iteration of the loop with odd and even swapped */ - gf2_matrix_square(odd, even); - if (len2 & 1) - crc1 = gf2_matrix_times(odd, crc1); - len2 >>= 1; - - /* if no more bits set, then done */ - } while (len2 != 0); - - /* return combined crc */ - crc1 ^= crc2; - return crc1; +/* ========================================================================= */ +uLong ZEXPORT crc32_combine_gen64(len2) + z_off64_t len2; +{ +#ifdef DYNAMIC_CRC_TABLE + once(&made, make_crc_table); +#endif /* DYNAMIC_CRC_TABLE */ + return x2nmodp(len2, 3); } /* ========================================================================= */ -uLong ZEXPORT crc32_combine(crc1, crc2, len2) - uLong crc1; - uLong crc2; +uLong ZEXPORT crc32_combine_gen(len2) z_off_t len2; { - return crc32_combine_(crc1, crc2, len2); + return crc32_combine_gen64((z_off64_t)len2); } -uLong ZEXPORT crc32_combine64(crc1, crc2, len2) +/* ========================================================================= */ +uLong ZEXPORT crc32_combine_op(crc1, crc2, op) uLong crc1; uLong crc2; - z_off64_t len2; + uLong op; { - return crc32_combine_(crc1, crc2, len2); + return multmodp(op, crc1) ^ (crc2 & 0xffffffff); } diff --git a/lib/zlib/crc32.h b/lib/zlib/crc32.h index 9e0c77810..137df68d6 100644 --- a/lib/zlib/crc32.h +++ b/lib/zlib/crc32.h @@ -2,440 +2,9445 @@ * Generated automatically by crc32.c */ -local const z_crc_t FAR crc_table[TBLS][256] = -{ - { - 0x00000000UL, 0x77073096UL, 0xee0e612cUL, 0x990951baUL, 0x076dc419UL, - 0x706af48fUL, 0xe963a535UL, 0x9e6495a3UL, 0x0edb8832UL, 0x79dcb8a4UL, - 0xe0d5e91eUL, 0x97d2d988UL, 0x09b64c2bUL, 0x7eb17cbdUL, 0xe7b82d07UL, - 0x90bf1d91UL, 0x1db71064UL, 0x6ab020f2UL, 0xf3b97148UL, 0x84be41deUL, - 0x1adad47dUL, 0x6ddde4ebUL, 0xf4d4b551UL, 0x83d385c7UL, 0x136c9856UL, - 0x646ba8c0UL, 0xfd62f97aUL, 0x8a65c9ecUL, 0x14015c4fUL, 0x63066cd9UL, - 0xfa0f3d63UL, 0x8d080df5UL, 0x3b6e20c8UL, 0x4c69105eUL, 0xd56041e4UL, - 0xa2677172UL, 0x3c03e4d1UL, 0x4b04d447UL, 0xd20d85fdUL, 0xa50ab56bUL, - 0x35b5a8faUL, 0x42b2986cUL, 0xdbbbc9d6UL, 0xacbcf940UL, 0x32d86ce3UL, - 0x45df5c75UL, 0xdcd60dcfUL, 0xabd13d59UL, 0x26d930acUL, 0x51de003aUL, - 0xc8d75180UL, 0xbfd06116UL, 0x21b4f4b5UL, 0x56b3c423UL, 0xcfba9599UL, - 0xb8bda50fUL, 0x2802b89eUL, 0x5f058808UL, 0xc60cd9b2UL, 0xb10be924UL, - 0x2f6f7c87UL, 0x58684c11UL, 0xc1611dabUL, 0xb6662d3dUL, 0x76dc4190UL, - 0x01db7106UL, 0x98d220bcUL, 0xefd5102aUL, 0x71b18589UL, 0x06b6b51fUL, - 0x9fbfe4a5UL, 0xe8b8d433UL, 0x7807c9a2UL, 0x0f00f934UL, 0x9609a88eUL, - 0xe10e9818UL, 0x7f6a0dbbUL, 0x086d3d2dUL, 0x91646c97UL, 0xe6635c01UL, - 0x6b6b51f4UL, 0x1c6c6162UL, 0x856530d8UL, 0xf262004eUL, 0x6c0695edUL, - 0x1b01a57bUL, 0x8208f4c1UL, 0xf50fc457UL, 0x65b0d9c6UL, 0x12b7e950UL, - 0x8bbeb8eaUL, 0xfcb9887cUL, 0x62dd1ddfUL, 0x15da2d49UL, 0x8cd37cf3UL, - 0xfbd44c65UL, 0x4db26158UL, 0x3ab551ceUL, 0xa3bc0074UL, 0xd4bb30e2UL, - 0x4adfa541UL, 0x3dd895d7UL, 0xa4d1c46dUL, 0xd3d6f4fbUL, 0x4369e96aUL, - 0x346ed9fcUL, 0xad678846UL, 0xda60b8d0UL, 0x44042d73UL, 0x33031de5UL, - 0xaa0a4c5fUL, 0xdd0d7cc9UL, 0x5005713cUL, 0x270241aaUL, 0xbe0b1010UL, - 0xc90c2086UL, 0x5768b525UL, 0x206f85b3UL, 0xb966d409UL, 0xce61e49fUL, - 0x5edef90eUL, 0x29d9c998UL, 0xb0d09822UL, 0xc7d7a8b4UL, 0x59b33d17UL, - 0x2eb40d81UL, 0xb7bd5c3bUL, 0xc0ba6cadUL, 0xedb88320UL, 0x9abfb3b6UL, - 0x03b6e20cUL, 0x74b1d29aUL, 0xead54739UL, 0x9dd277afUL, 0x04db2615UL, - 0x73dc1683UL, 0xe3630b12UL, 0x94643b84UL, 0x0d6d6a3eUL, 0x7a6a5aa8UL, - 0xe40ecf0bUL, 0x9309ff9dUL, 0x0a00ae27UL, 0x7d079eb1UL, 0xf00f9344UL, - 0x8708a3d2UL, 0x1e01f268UL, 0x6906c2feUL, 0xf762575dUL, 0x806567cbUL, - 0x196c3671UL, 0x6e6b06e7UL, 0xfed41b76UL, 0x89d32be0UL, 0x10da7a5aUL, - 0x67dd4accUL, 0xf9b9df6fUL, 0x8ebeeff9UL, 0x17b7be43UL, 0x60b08ed5UL, - 0xd6d6a3e8UL, 0xa1d1937eUL, 0x38d8c2c4UL, 0x4fdff252UL, 0xd1bb67f1UL, - 0xa6bc5767UL, 0x3fb506ddUL, 0x48b2364bUL, 0xd80d2bdaUL, 0xaf0a1b4cUL, - 0x36034af6UL, 0x41047a60UL, 0xdf60efc3UL, 0xa867df55UL, 0x316e8eefUL, - 0x4669be79UL, 0xcb61b38cUL, 0xbc66831aUL, 0x256fd2a0UL, 0x5268e236UL, - 0xcc0c7795UL, 0xbb0b4703UL, 0x220216b9UL, 0x5505262fUL, 0xc5ba3bbeUL, - 0xb2bd0b28UL, 0x2bb45a92UL, 0x5cb36a04UL, 0xc2d7ffa7UL, 0xb5d0cf31UL, - 0x2cd99e8bUL, 0x5bdeae1dUL, 0x9b64c2b0UL, 0xec63f226UL, 0x756aa39cUL, - 0x026d930aUL, 0x9c0906a9UL, 0xeb0e363fUL, 0x72076785UL, 0x05005713UL, - 0x95bf4a82UL, 0xe2b87a14UL, 0x7bb12baeUL, 0x0cb61b38UL, 0x92d28e9bUL, - 0xe5d5be0dUL, 0x7cdcefb7UL, 0x0bdbdf21UL, 0x86d3d2d4UL, 0xf1d4e242UL, - 0x68ddb3f8UL, 0x1fda836eUL, 0x81be16cdUL, 0xf6b9265bUL, 0x6fb077e1UL, - 0x18b74777UL, 0x88085ae6UL, 0xff0f6a70UL, 0x66063bcaUL, 0x11010b5cUL, - 0x8f659effUL, 0xf862ae69UL, 0x616bffd3UL, 0x166ccf45UL, 0xa00ae278UL, - 0xd70dd2eeUL, 0x4e048354UL, 0x3903b3c2UL, 0xa7672661UL, 0xd06016f7UL, - 0x4969474dUL, 0x3e6e77dbUL, 0xaed16a4aUL, 0xd9d65adcUL, 0x40df0b66UL, - 0x37d83bf0UL, 0xa9bcae53UL, 0xdebb9ec5UL, 0x47b2cf7fUL, 0x30b5ffe9UL, - 0xbdbdf21cUL, 0xcabac28aUL, 0x53b39330UL, 0x24b4a3a6UL, 0xbad03605UL, - 0xcdd70693UL, 0x54de5729UL, 0x23d967bfUL, 0xb3667a2eUL, 0xc4614ab8UL, - 0x5d681b02UL, 0x2a6f2b94UL, 0xb40bbe37UL, 0xc30c8ea1UL, 0x5a05df1bUL, - 0x2d02ef8dUL -#ifdef BYFOUR - }, - { - 0x00000000UL, 0x191b3141UL, 0x32366282UL, 0x2b2d53c3UL, 0x646cc504UL, - 0x7d77f445UL, 0x565aa786UL, 0x4f4196c7UL, 0xc8d98a08UL, 0xd1c2bb49UL, - 0xfaefe88aUL, 0xe3f4d9cbUL, 0xacb54f0cUL, 0xb5ae7e4dUL, 0x9e832d8eUL, - 0x87981ccfUL, 0x4ac21251UL, 0x53d92310UL, 0x78f470d3UL, 0x61ef4192UL, - 0x2eaed755UL, 0x37b5e614UL, 0x1c98b5d7UL, 0x05838496UL, 0x821b9859UL, - 0x9b00a918UL, 0xb02dfadbUL, 0xa936cb9aUL, 0xe6775d5dUL, 0xff6c6c1cUL, - 0xd4413fdfUL, 0xcd5a0e9eUL, 0x958424a2UL, 0x8c9f15e3UL, 0xa7b24620UL, - 0xbea97761UL, 0xf1e8e1a6UL, 0xe8f3d0e7UL, 0xc3de8324UL, 0xdac5b265UL, - 0x5d5daeaaUL, 0x44469febUL, 0x6f6bcc28UL, 0x7670fd69UL, 0x39316baeUL, - 0x202a5aefUL, 0x0b07092cUL, 0x121c386dUL, 0xdf4636f3UL, 0xc65d07b2UL, - 0xed705471UL, 0xf46b6530UL, 0xbb2af3f7UL, 0xa231c2b6UL, 0x891c9175UL, - 0x9007a034UL, 0x179fbcfbUL, 0x0e848dbaUL, 0x25a9de79UL, 0x3cb2ef38UL, - 0x73f379ffUL, 0x6ae848beUL, 0x41c51b7dUL, 0x58de2a3cUL, 0xf0794f05UL, - 0xe9627e44UL, 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0x12ac6fadUL, 0x25c6adacUL, 0x1881f1a7UL, 0x2feb33a6UL, 0x765575a4UL, - 0x413fb7a5UL, 0xc429f8a0UL, 0xf3433aa1UL, 0xaafd7ca3UL, 0x9d97bea2UL, - 0xd073c4b5UL, 0xe71906b4UL, 0xbea740b6UL, 0x89cd82b7UL, 0x0cdbcdb2UL, - 0x3bb10fb3UL, 0x620f49b1UL, 0x55658bb0UL, 0x6822d7bbUL, 0x5f4815baUL, - 0x06f653b8UL, 0x319c91b9UL, 0xb48adebcUL, 0x83e01cbdUL, 0xda5e5abfUL, - 0xed3498beUL - }, - { - 0x00000000UL, 0x6567bcb8UL, 0x8bc809aaUL, 0xeeafb512UL, 0x5797628fUL, - 0x32f0de37UL, 0xdc5f6b25UL, 0xb938d79dUL, 0xef28b4c5UL, 0x8a4f087dUL, - 0x64e0bd6fUL, 0x018701d7UL, 0xb8bfd64aUL, 0xddd86af2UL, 0x3377dfe0UL, - 0x56106358UL, 0x9f571950UL, 0xfa30a5e8UL, 0x149f10faUL, 0x71f8ac42UL, - 0xc8c07bdfUL, 0xada7c767UL, 0x43087275UL, 0x266fcecdUL, 0x707fad95UL, - 0x1518112dUL, 0xfbb7a43fUL, 0x9ed01887UL, 0x27e8cf1aUL, 0x428f73a2UL, - 0xac20c6b0UL, 0xc9477a08UL, 0x3eaf32a0UL, 0x5bc88e18UL, 0xb5673b0aUL, - 0xd00087b2UL, 0x6938502fUL, 0x0c5fec97UL, 0xe2f05985UL, 0x8797e53dUL, - 0xd1878665UL, 0xb4e03addUL, 0x5a4f8fcfUL, 0x3f283377UL, 0x8610e4eaUL, - 0xe3775852UL, 0x0dd8ed40UL, 0x68bf51f8UL, 0xa1f82bf0UL, 0xc49f9748UL, - 0x2a30225aUL, 0x4f579ee2UL, 0xf66f497fUL, 0x9308f5c7UL, 0x7da740d5UL, - 0x18c0fc6dUL, 0x4ed09f35UL, 0x2bb7238dUL, 0xc518969fUL, 0xa07f2a27UL, - 0x1947fdbaUL, 0x7c204102UL, 0x928ff410UL, 0xf7e848a8UL, 0x3d58149bUL, - 0x583fa823UL, 0xb6901d31UL, 0xd3f7a189UL, 0x6acf7614UL, 0x0fa8caacUL, - 0xe1077fbeUL, 0x8460c306UL, 0xd270a05eUL, 0xb7171ce6UL, 0x59b8a9f4UL, - 0x3cdf154cUL, 0x85e7c2d1UL, 0xe0807e69UL, 0x0e2fcb7bUL, 0x6b4877c3UL, - 0xa20f0dcbUL, 0xc768b173UL, 0x29c70461UL, 0x4ca0b8d9UL, 0xf5986f44UL, - 0x90ffd3fcUL, 0x7e5066eeUL, 0x1b37da56UL, 0x4d27b90eUL, 0x284005b6UL, - 0xc6efb0a4UL, 0xa3880c1cUL, 0x1ab0db81UL, 0x7fd76739UL, 0x9178d22bUL, - 0xf41f6e93UL, 0x03f7263bUL, 0x66909a83UL, 0x883f2f91UL, 0xed589329UL, - 0x546044b4UL, 0x3107f80cUL, 0xdfa84d1eUL, 0xbacff1a6UL, 0xecdf92feUL, - 0x89b82e46UL, 0x67179b54UL, 0x027027ecUL, 0xbb48f071UL, 0xde2f4cc9UL, - 0x3080f9dbUL, 0x55e74563UL, 0x9ca03f6bUL, 0xf9c783d3UL, 0x176836c1UL, - 0x720f8a79UL, 0xcb375de4UL, 0xae50e15cUL, 0x40ff544eUL, 0x2598e8f6UL, - 0x73888baeUL, 0x16ef3716UL, 0xf8408204UL, 0x9d273ebcUL, 0x241fe921UL, - 0x41785599UL, 0xafd7e08bUL, 0xcab05c33UL, 0x3bb659edUL, 0x5ed1e555UL, - 0xb07e5047UL, 0xd519ecffUL, 0x6c213b62UL, 0x094687daUL, 0xe7e932c8UL, - 0x828e8e70UL, 0xd49eed28UL, 0xb1f95190UL, 0x5f56e482UL, 0x3a31583aUL, - 0x83098fa7UL, 0xe66e331fUL, 0x08c1860dUL, 0x6da63ab5UL, 0xa4e140bdUL, - 0xc186fc05UL, 0x2f294917UL, 0x4a4ef5afUL, 0xf3762232UL, 0x96119e8aUL, - 0x78be2b98UL, 0x1dd99720UL, 0x4bc9f478UL, 0x2eae48c0UL, 0xc001fdd2UL, - 0xa566416aUL, 0x1c5e96f7UL, 0x79392a4fUL, 0x97969f5dUL, 0xf2f123e5UL, - 0x05196b4dUL, 0x607ed7f5UL, 0x8ed162e7UL, 0xebb6de5fUL, 0x528e09c2UL, - 0x37e9b57aUL, 0xd9460068UL, 0xbc21bcd0UL, 0xea31df88UL, 0x8f566330UL, - 0x61f9d622UL, 0x049e6a9aUL, 0xbda6bd07UL, 0xd8c101bfUL, 0x366eb4adUL, - 0x53090815UL, 0x9a4e721dUL, 0xff29cea5UL, 0x11867bb7UL, 0x74e1c70fUL, - 0xcdd91092UL, 0xa8beac2aUL, 0x46111938UL, 0x2376a580UL, 0x7566c6d8UL, - 0x10017a60UL, 0xfeaecf72UL, 0x9bc973caUL, 0x22f1a457UL, 0x479618efUL, - 0xa939adfdUL, 0xcc5e1145UL, 0x06ee4d76UL, 0x6389f1ceUL, 0x8d2644dcUL, - 0xe841f864UL, 0x51792ff9UL, 0x341e9341UL, 0xdab12653UL, 0xbfd69aebUL, - 0xe9c6f9b3UL, 0x8ca1450bUL, 0x620ef019UL, 0x07694ca1UL, 0xbe519b3cUL, - 0xdb362784UL, 0x35999296UL, 0x50fe2e2eUL, 0x99b95426UL, 0xfcdee89eUL, - 0x12715d8cUL, 0x7716e134UL, 0xce2e36a9UL, 0xab498a11UL, 0x45e63f03UL, - 0x208183bbUL, 0x7691e0e3UL, 0x13f65c5bUL, 0xfd59e949UL, 0x983e55f1UL, - 0x2106826cUL, 0x44613ed4UL, 0xaace8bc6UL, 0xcfa9377eUL, 0x38417fd6UL, - 0x5d26c36eUL, 0xb389767cUL, 0xd6eecac4UL, 0x6fd61d59UL, 0x0ab1a1e1UL, - 0xe41e14f3UL, 0x8179a84bUL, 0xd769cb13UL, 0xb20e77abUL, 0x5ca1c2b9UL, - 0x39c67e01UL, 0x80fea99cUL, 0xe5991524UL, 0x0b36a036UL, 0x6e511c8eUL, - 0xa7166686UL, 0xc271da3eUL, 0x2cde6f2cUL, 0x49b9d394UL, 0xf0810409UL, - 0x95e6b8b1UL, 0x7b490da3UL, 0x1e2eb11bUL, 0x483ed243UL, 0x2d596efbUL, - 0xc3f6dbe9UL, 0xa6916751UL, 0x1fa9b0ccUL, 0x7ace0c74UL, 0x9461b966UL, - 0xf10605deUL +local const z_crc_t FAR crc_table[] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, + 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, + 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, + 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, + 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856, + 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, + 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, + 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a, + 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, + 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, + 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, + 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e, + 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, + 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, + 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, + 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, + 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, + 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010, + 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, + 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, + 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, + 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, + 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344, + 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, + 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, + 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c, + 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, + 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, + 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, + 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c, + 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, + 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, + 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, + 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278, + 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, + 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66, + 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, + 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, + 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, + 0x2d02ef8d}; + +#ifdef W + +#if W == 8 + +local const z_word_t FAR crc_big_table[] = { + 0x0000000000000000, 0x9630077700000000, 0x2c610eee00000000, + 0xba51099900000000, 0x19c46d0700000000, 0x8ff46a7000000000, + 0x35a563e900000000, 0xa395649e00000000, 0x3288db0e00000000, + 0xa4b8dc7900000000, 0x1ee9d5e000000000, 0x88d9d29700000000, + 0x2b4cb60900000000, 0xbd7cb17e00000000, 0x072db8e700000000, + 0x911dbf9000000000, 0x6410b71d00000000, 0xf220b06a00000000, + 0x4871b9f300000000, 0xde41be8400000000, 0x7dd4da1a00000000, + 0xebe4dd6d00000000, 0x51b5d4f400000000, 0xc785d38300000000, + 0x56986c1300000000, 0xc0a86b6400000000, 0x7af962fd00000000, + 0xecc9658a00000000, 0x4f5c011400000000, 0xd96c066300000000, + 0x633d0ffa00000000, 0xf50d088d00000000, 0xc8206e3b00000000, + 0x5e10694c00000000, 0xe44160d500000000, 0x727167a200000000, + 0xd1e4033c00000000, 0x47d4044b00000000, 0xfd850dd200000000, + 0x6bb50aa500000000, 0xfaa8b53500000000, 0x6c98b24200000000, + 0xd6c9bbdb00000000, 0x40f9bcac00000000, 0xe36cd83200000000, + 0x755cdf4500000000, 0xcf0dd6dc00000000, 0x593dd1ab00000000, + 0xac30d92600000000, 0x3a00de5100000000, 0x8051d7c800000000, + 0x1661d0bf00000000, 0xb5f4b42100000000, 0x23c4b35600000000, + 0x9995bacf00000000, 0x0fa5bdb800000000, 0x9eb8022800000000, + 0x0888055f00000000, 0xb2d90cc600000000, 0x24e90bb100000000, + 0x877c6f2f00000000, 0x114c685800000000, 0xab1d61c100000000, + 0x3d2d66b600000000, 0x9041dc7600000000, 0x0671db0100000000, + 0xbc20d29800000000, 0x2a10d5ef00000000, 0x8985b17100000000, + 0x1fb5b60600000000, 0xa5e4bf9f00000000, 0x33d4b8e800000000, + 0xa2c9077800000000, 0x34f9000f00000000, 0x8ea8099600000000, + 0x18980ee100000000, 0xbb0d6a7f00000000, 0x2d3d6d0800000000, + 0x976c649100000000, 0x015c63e600000000, 0xf4516b6b00000000, + 0x62616c1c00000000, 0xd830658500000000, 0x4e0062f200000000, + 0xed95066c00000000, 0x7ba5011b00000000, 0xc1f4088200000000, + 0x57c40ff500000000, 0xc6d9b06500000000, 0x50e9b71200000000, + 0xeab8be8b00000000, 0x7c88b9fc00000000, 0xdf1ddd6200000000, + 0x492dda1500000000, 0xf37cd38c00000000, 0x654cd4fb00000000, + 0x5861b24d00000000, 0xce51b53a00000000, 0x7400bca300000000, + 0xe230bbd400000000, 0x41a5df4a00000000, 0xd795d83d00000000, + 0x6dc4d1a400000000, 0xfbf4d6d300000000, 0x6ae9694300000000, + 0xfcd96e3400000000, 0x468867ad00000000, 0xd0b860da00000000, + 0x732d044400000000, 0xe51d033300000000, 0x5f4c0aaa00000000, + 0xc97c0ddd00000000, 0x3c71055000000000, 0xaa41022700000000, + 0x10100bbe00000000, 0x86200cc900000000, 0x25b5685700000000, + 0xb3856f2000000000, 0x09d466b900000000, 0x9fe461ce00000000, + 0x0ef9de5e00000000, 0x98c9d92900000000, 0x2298d0b000000000, + 0xb4a8d7c700000000, 0x173db35900000000, 0x810db42e00000000, + 0x3b5cbdb700000000, 0xad6cbac000000000, 0x2083b8ed00000000, + 0xb6b3bf9a00000000, 0x0ce2b60300000000, 0x9ad2b17400000000, + 0x3947d5ea00000000, 0xaf77d29d00000000, 0x1526db0400000000, + 0x8316dc7300000000, 0x120b63e300000000, 0x843b649400000000, + 0x3e6a6d0d00000000, 0xa85a6a7a00000000, 0x0bcf0ee400000000, + 0x9dff099300000000, 0x27ae000a00000000, 0xb19e077d00000000, + 0x44930ff000000000, 0xd2a3088700000000, 0x68f2011e00000000, + 0xfec2066900000000, 0x5d5762f700000000, 0xcb67658000000000, + 0x71366c1900000000, 0xe7066b6e00000000, 0x761bd4fe00000000, + 0xe02bd38900000000, 0x5a7ada1000000000, 0xcc4add6700000000, + 0x6fdfb9f900000000, 0xf9efbe8e00000000, 0x43beb71700000000, + 0xd58eb06000000000, 0xe8a3d6d600000000, 0x7e93d1a100000000, + 0xc4c2d83800000000, 0x52f2df4f00000000, 0xf167bbd100000000, + 0x6757bca600000000, 0xdd06b53f00000000, 0x4b36b24800000000, + 0xda2b0dd800000000, 0x4c1b0aaf00000000, 0xf64a033600000000, + 0x607a044100000000, 0xc3ef60df00000000, 0x55df67a800000000, + 0xef8e6e3100000000, 0x79be694600000000, 0x8cb361cb00000000, + 0x1a8366bc00000000, 0xa0d26f2500000000, 0x36e2685200000000, + 0x95770ccc00000000, 0x03470bbb00000000, 0xb916022200000000, + 0x2f26055500000000, 0xbe3bbac500000000, 0x280bbdb200000000, + 0x925ab42b00000000, 0x046ab35c00000000, 0xa7ffd7c200000000, + 0x31cfd0b500000000, 0x8b9ed92c00000000, 0x1daede5b00000000, + 0xb0c2649b00000000, 0x26f263ec00000000, 0x9ca36a7500000000, + 0x0a936d0200000000, 0xa906099c00000000, 0x3f360eeb00000000, + 0x8567077200000000, 0x1357000500000000, 0x824abf9500000000, + 0x147ab8e200000000, 0xae2bb17b00000000, 0x381bb60c00000000, + 0x9b8ed29200000000, 0x0dbed5e500000000, 0xb7efdc7c00000000, + 0x21dfdb0b00000000, 0xd4d2d38600000000, 0x42e2d4f100000000, + 0xf8b3dd6800000000, 0x6e83da1f00000000, 0xcd16be8100000000, + 0x5b26b9f600000000, 0xe177b06f00000000, 0x7747b71800000000, + 0xe65a088800000000, 0x706a0fff00000000, 0xca3b066600000000, + 0x5c0b011100000000, 0xff9e658f00000000, 0x69ae62f800000000, + 0xd3ff6b6100000000, 0x45cf6c1600000000, 0x78e20aa000000000, + 0xeed20dd700000000, 0x5483044e00000000, 0xc2b3033900000000, + 0x612667a700000000, 0xf71660d000000000, 0x4d47694900000000, + 0xdb776e3e00000000, 0x4a6ad1ae00000000, 0xdc5ad6d900000000, + 0x660bdf4000000000, 0xf03bd83700000000, 0x53aebca900000000, + 0xc59ebbde00000000, 0x7fcfb24700000000, 0xe9ffb53000000000, + 0x1cf2bdbd00000000, 0x8ac2baca00000000, 0x3093b35300000000, + 0xa6a3b42400000000, 0x0536d0ba00000000, 0x9306d7cd00000000, + 0x2957de5400000000, 0xbf67d92300000000, 0x2e7a66b300000000, + 0xb84a61c400000000, 0x021b685d00000000, 0x942b6f2a00000000, + 0x37be0bb400000000, 0xa18e0cc300000000, 0x1bdf055a00000000, + 0x8def022d00000000}; + +#else /* W == 4 */ + +local const z_word_t FAR crc_big_table[] = { + 0x00000000, 0x96300777, 0x2c610eee, 0xba510999, 0x19c46d07, + 0x8ff46a70, 0x35a563e9, 0xa395649e, 0x3288db0e, 0xa4b8dc79, + 0x1ee9d5e0, 0x88d9d297, 0x2b4cb609, 0xbd7cb17e, 0x072db8e7, + 0x911dbf90, 0x6410b71d, 0xf220b06a, 0x4871b9f3, 0xde41be84, + 0x7dd4da1a, 0xebe4dd6d, 0x51b5d4f4, 0xc785d383, 0x56986c13, + 0xc0a86b64, 0x7af962fd, 0xecc9658a, 0x4f5c0114, 0xd96c0663, + 0x633d0ffa, 0xf50d088d, 0xc8206e3b, 0x5e10694c, 0xe44160d5, + 0x727167a2, 0xd1e4033c, 0x47d4044b, 0xfd850dd2, 0x6bb50aa5, + 0xfaa8b535, 0x6c98b242, 0xd6c9bbdb, 0x40f9bcac, 0xe36cd832, + 0x755cdf45, 0xcf0dd6dc, 0x593dd1ab, 0xac30d926, 0x3a00de51, + 0x8051d7c8, 0x1661d0bf, 0xb5f4b421, 0x23c4b356, 0x9995bacf, + 0x0fa5bdb8, 0x9eb80228, 0x0888055f, 0xb2d90cc6, 0x24e90bb1, + 0x877c6f2f, 0x114c6858, 0xab1d61c1, 0x3d2d66b6, 0x9041dc76, + 0x0671db01, 0xbc20d298, 0x2a10d5ef, 0x8985b171, 0x1fb5b606, + 0xa5e4bf9f, 0x33d4b8e8, 0xa2c90778, 0x34f9000f, 0x8ea80996, + 0x18980ee1, 0xbb0d6a7f, 0x2d3d6d08, 0x976c6491, 0x015c63e6, + 0xf4516b6b, 0x62616c1c, 0xd8306585, 0x4e0062f2, 0xed95066c, + 0x7ba5011b, 0xc1f40882, 0x57c40ff5, 0xc6d9b065, 0x50e9b712, + 0xeab8be8b, 0x7c88b9fc, 0xdf1ddd62, 0x492dda15, 0xf37cd38c, + 0x654cd4fb, 0x5861b24d, 0xce51b53a, 0x7400bca3, 0xe230bbd4, + 0x41a5df4a, 0xd795d83d, 0x6dc4d1a4, 0xfbf4d6d3, 0x6ae96943, + 0xfcd96e34, 0x468867ad, 0xd0b860da, 0x732d0444, 0xe51d0333, + 0x5f4c0aaa, 0xc97c0ddd, 0x3c710550, 0xaa410227, 0x10100bbe, + 0x86200cc9, 0x25b56857, 0xb3856f20, 0x09d466b9, 0x9fe461ce, + 0x0ef9de5e, 0x98c9d929, 0x2298d0b0, 0xb4a8d7c7, 0x173db359, + 0x810db42e, 0x3b5cbdb7, 0xad6cbac0, 0x2083b8ed, 0xb6b3bf9a, + 0x0ce2b603, 0x9ad2b174, 0x3947d5ea, 0xaf77d29d, 0x1526db04, + 0x8316dc73, 0x120b63e3, 0x843b6494, 0x3e6a6d0d, 0xa85a6a7a, + 0x0bcf0ee4, 0x9dff0993, 0x27ae000a, 0xb19e077d, 0x44930ff0, + 0xd2a30887, 0x68f2011e, 0xfec20669, 0x5d5762f7, 0xcb676580, + 0x71366c19, 0xe7066b6e, 0x761bd4fe, 0xe02bd389, 0x5a7ada10, + 0xcc4add67, 0x6fdfb9f9, 0xf9efbe8e, 0x43beb717, 0xd58eb060, + 0xe8a3d6d6, 0x7e93d1a1, 0xc4c2d838, 0x52f2df4f, 0xf167bbd1, + 0x6757bca6, 0xdd06b53f, 0x4b36b248, 0xda2b0dd8, 0x4c1b0aaf, + 0xf64a0336, 0x607a0441, 0xc3ef60df, 0x55df67a8, 0xef8e6e31, + 0x79be6946, 0x8cb361cb, 0x1a8366bc, 0xa0d26f25, 0x36e26852, + 0x95770ccc, 0x03470bbb, 0xb9160222, 0x2f260555, 0xbe3bbac5, + 0x280bbdb2, 0x925ab42b, 0x046ab35c, 0xa7ffd7c2, 0x31cfd0b5, + 0x8b9ed92c, 0x1daede5b, 0xb0c2649b, 0x26f263ec, 0x9ca36a75, + 0x0a936d02, 0xa906099c, 0x3f360eeb, 0x85670772, 0x13570005, + 0x824abf95, 0x147ab8e2, 0xae2bb17b, 0x381bb60c, 0x9b8ed292, + 0x0dbed5e5, 0xb7efdc7c, 0x21dfdb0b, 0xd4d2d386, 0x42e2d4f1, + 0xf8b3dd68, 0x6e83da1f, 0xcd16be81, 0x5b26b9f6, 0xe177b06f, + 0x7747b718, 0xe65a0888, 0x706a0fff, 0xca3b0666, 0x5c0b0111, + 0xff9e658f, 0x69ae62f8, 0xd3ff6b61, 0x45cf6c16, 0x78e20aa0, + 0xeed20dd7, 0x5483044e, 0xc2b30339, 0x612667a7, 0xf71660d0, + 0x4d476949, 0xdb776e3e, 0x4a6ad1ae, 0xdc5ad6d9, 0x660bdf40, + 0xf03bd837, 0x53aebca9, 0xc59ebbde, 0x7fcfb247, 0xe9ffb530, + 0x1cf2bdbd, 0x8ac2baca, 0x3093b353, 0xa6a3b424, 0x0536d0ba, + 0x9306d7cd, 0x2957de54, 0xbf67d923, 0x2e7a66b3, 0xb84a61c4, + 0x021b685d, 0x942b6f2a, 0x37be0bb4, 0xa18e0cc3, 0x1bdf055a, + 0x8def022d}; + +#endif + +#if N == 1 + +#if W == 8 + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0xccaa009e, 0x4225077d, 0x8e8f07e3, 0x844a0efa, + 0x48e00e64, 0xc66f0987, 0x0ac50919, 0xd3e51bb5, 0x1f4f1b2b, + 0x91c01cc8, 0x5d6a1c56, 0x57af154f, 0x9b0515d1, 0x158a1232, + 0xd92012ac, 0x7cbb312b, 0xb01131b5, 0x3e9e3656, 0xf23436c8, + 0xf8f13fd1, 0x345b3f4f, 0xbad438ac, 0x767e3832, 0xaf5e2a9e, + 0x63f42a00, 0xed7b2de3, 0x21d12d7d, 0x2b142464, 0xe7be24fa, + 0x69312319, 0xa59b2387, 0xf9766256, 0x35dc62c8, 0xbb53652b, + 0x77f965b5, 0x7d3c6cac, 0xb1966c32, 0x3f196bd1, 0xf3b36b4f, + 0x2a9379e3, 0xe639797d, 0x68b67e9e, 0xa41c7e00, 0xaed97719, + 0x62737787, 0xecfc7064, 0x205670fa, 0x85cd537d, 0x496753e3, + 0xc7e85400, 0x0b42549e, 0x01875d87, 0xcd2d5d19, 0x43a25afa, + 0x8f085a64, 0x562848c8, 0x9a824856, 0x140d4fb5, 0xd8a74f2b, + 0xd2624632, 0x1ec846ac, 0x9047414f, 0x5ced41d1, 0x299dc2ed, + 0xe537c273, 0x6bb8c590, 0xa712c50e, 0xadd7cc17, 0x617dcc89, + 0xeff2cb6a, 0x2358cbf4, 0xfa78d958, 0x36d2d9c6, 0xb85dde25, + 0x74f7debb, 0x7e32d7a2, 0xb298d73c, 0x3c17d0df, 0xf0bdd041, + 0x5526f3c6, 0x998cf358, 0x1703f4bb, 0xdba9f425, 0xd16cfd3c, + 0x1dc6fda2, 0x9349fa41, 0x5fe3fadf, 0x86c3e873, 0x4a69e8ed, + 0xc4e6ef0e, 0x084cef90, 0x0289e689, 0xce23e617, 0x40ace1f4, + 0x8c06e16a, 0xd0eba0bb, 0x1c41a025, 0x92cea7c6, 0x5e64a758, + 0x54a1ae41, 0x980baedf, 0x1684a93c, 0xda2ea9a2, 0x030ebb0e, + 0xcfa4bb90, 0x412bbc73, 0x8d81bced, 0x8744b5f4, 0x4beeb56a, + 0xc561b289, 0x09cbb217, 0xac509190, 0x60fa910e, 0xee7596ed, + 0x22df9673, 0x281a9f6a, 0xe4b09ff4, 0x6a3f9817, 0xa6959889, + 0x7fb58a25, 0xb31f8abb, 0x3d908d58, 0xf13a8dc6, 0xfbff84df, + 0x37558441, 0xb9da83a2, 0x7570833c, 0x533b85da, 0x9f918544, + 0x111e82a7, 0xddb48239, 0xd7718b20, 0x1bdb8bbe, 0x95548c5d, + 0x59fe8cc3, 0x80de9e6f, 0x4c749ef1, 0xc2fb9912, 0x0e51998c, + 0x04949095, 0xc83e900b, 0x46b197e8, 0x8a1b9776, 0x2f80b4f1, + 0xe32ab46f, 0x6da5b38c, 0xa10fb312, 0xabcaba0b, 0x6760ba95, + 0xe9efbd76, 0x2545bde8, 0xfc65af44, 0x30cfafda, 0xbe40a839, + 0x72eaa8a7, 0x782fa1be, 0xb485a120, 0x3a0aa6c3, 0xf6a0a65d, + 0xaa4de78c, 0x66e7e712, 0xe868e0f1, 0x24c2e06f, 0x2e07e976, + 0xe2ade9e8, 0x6c22ee0b, 0xa088ee95, 0x79a8fc39, 0xb502fca7, + 0x3b8dfb44, 0xf727fbda, 0xfde2f2c3, 0x3148f25d, 0xbfc7f5be, + 0x736df520, 0xd6f6d6a7, 0x1a5cd639, 0x94d3d1da, 0x5879d144, + 0x52bcd85d, 0x9e16d8c3, 0x1099df20, 0xdc33dfbe, 0x0513cd12, + 0xc9b9cd8c, 0x4736ca6f, 0x8b9ccaf1, 0x8159c3e8, 0x4df3c376, + 0xc37cc495, 0x0fd6c40b, 0x7aa64737, 0xb60c47a9, 0x3883404a, + 0xf42940d4, 0xfeec49cd, 0x32464953, 0xbcc94eb0, 0x70634e2e, + 0xa9435c82, 0x65e95c1c, 0xeb665bff, 0x27cc5b61, 0x2d095278, + 0xe1a352e6, 0x6f2c5505, 0xa386559b, 0x061d761c, 0xcab77682, + 0x44387161, 0x889271ff, 0x825778e6, 0x4efd7878, 0xc0727f9b, + 0x0cd87f05, 0xd5f86da9, 0x19526d37, 0x97dd6ad4, 0x5b776a4a, + 0x51b26353, 0x9d1863cd, 0x1397642e, 0xdf3d64b0, 0x83d02561, + 0x4f7a25ff, 0xc1f5221c, 0x0d5f2282, 0x079a2b9b, 0xcb302b05, + 0x45bf2ce6, 0x89152c78, 0x50353ed4, 0x9c9f3e4a, 0x121039a9, + 0xdeba3937, 0xd47f302e, 0x18d530b0, 0x965a3753, 0x5af037cd, + 0xff6b144a, 0x33c114d4, 0xbd4e1337, 0x71e413a9, 0x7b211ab0, + 0xb78b1a2e, 0x39041dcd, 0xf5ae1d53, 0x2c8e0fff, 0xe0240f61, + 0x6eab0882, 0xa201081c, 0xa8c40105, 0x646e019b, 0xeae10678, + 0x264b06e6}, + {0x00000000, 0xa6770bb4, 0x979f1129, 0x31e81a9d, 0xf44f2413, + 0x52382fa7, 0x63d0353a, 0xc5a73e8e, 0x33ef4e67, 0x959845d3, + 0xa4705f4e, 0x020754fa, 0xc7a06a74, 0x61d761c0, 0x503f7b5d, + 0xf64870e9, 0x67de9cce, 0xc1a9977a, 0xf0418de7, 0x56368653, + 0x9391b8dd, 0x35e6b369, 0x040ea9f4, 0xa279a240, 0x5431d2a9, + 0xf246d91d, 0xc3aec380, 0x65d9c834, 0xa07ef6ba, 0x0609fd0e, + 0x37e1e793, 0x9196ec27, 0xcfbd399c, 0x69ca3228, 0x582228b5, + 0xfe552301, 0x3bf21d8f, 0x9d85163b, 0xac6d0ca6, 0x0a1a0712, + 0xfc5277fb, 0x5a257c4f, 0x6bcd66d2, 0xcdba6d66, 0x081d53e8, + 0xae6a585c, 0x9f8242c1, 0x39f54975, 0xa863a552, 0x0e14aee6, + 0x3ffcb47b, 0x998bbfcf, 0x5c2c8141, 0xfa5b8af5, 0xcbb39068, + 0x6dc49bdc, 0x9b8ceb35, 0x3dfbe081, 0x0c13fa1c, 0xaa64f1a8, + 0x6fc3cf26, 0xc9b4c492, 0xf85cde0f, 0x5e2bd5bb, 0x440b7579, + 0xe27c7ecd, 0xd3946450, 0x75e36fe4, 0xb044516a, 0x16335ade, + 0x27db4043, 0x81ac4bf7, 0x77e43b1e, 0xd19330aa, 0xe07b2a37, + 0x460c2183, 0x83ab1f0d, 0x25dc14b9, 0x14340e24, 0xb2430590, + 0x23d5e9b7, 0x85a2e203, 0xb44af89e, 0x123df32a, 0xd79acda4, + 0x71edc610, 0x4005dc8d, 0xe672d739, 0x103aa7d0, 0xb64dac64, + 0x87a5b6f9, 0x21d2bd4d, 0xe47583c3, 0x42028877, 0x73ea92ea, + 0xd59d995e, 0x8bb64ce5, 0x2dc14751, 0x1c295dcc, 0xba5e5678, + 0x7ff968f6, 0xd98e6342, 0xe86679df, 0x4e11726b, 0xb8590282, + 0x1e2e0936, 0x2fc613ab, 0x89b1181f, 0x4c162691, 0xea612d25, + 0xdb8937b8, 0x7dfe3c0c, 0xec68d02b, 0x4a1fdb9f, 0x7bf7c102, + 0xdd80cab6, 0x1827f438, 0xbe50ff8c, 0x8fb8e511, 0x29cfeea5, + 0xdf879e4c, 0x79f095f8, 0x48188f65, 0xee6f84d1, 0x2bc8ba5f, + 0x8dbfb1eb, 0xbc57ab76, 0x1a20a0c2, 0x8816eaf2, 0x2e61e146, + 0x1f89fbdb, 0xb9fef06f, 0x7c59cee1, 0xda2ec555, 0xebc6dfc8, + 0x4db1d47c, 0xbbf9a495, 0x1d8eaf21, 0x2c66b5bc, 0x8a11be08, + 0x4fb68086, 0xe9c18b32, 0xd82991af, 0x7e5e9a1b, 0xefc8763c, + 0x49bf7d88, 0x78576715, 0xde206ca1, 0x1b87522f, 0xbdf0599b, + 0x8c184306, 0x2a6f48b2, 0xdc27385b, 0x7a5033ef, 0x4bb82972, + 0xedcf22c6, 0x28681c48, 0x8e1f17fc, 0xbff70d61, 0x198006d5, + 0x47abd36e, 0xe1dcd8da, 0xd034c247, 0x7643c9f3, 0xb3e4f77d, + 0x1593fcc9, 0x247be654, 0x820cede0, 0x74449d09, 0xd23396bd, + 0xe3db8c20, 0x45ac8794, 0x800bb91a, 0x267cb2ae, 0x1794a833, + 0xb1e3a387, 0x20754fa0, 0x86024414, 0xb7ea5e89, 0x119d553d, + 0xd43a6bb3, 0x724d6007, 0x43a57a9a, 0xe5d2712e, 0x139a01c7, + 0xb5ed0a73, 0x840510ee, 0x22721b5a, 0xe7d525d4, 0x41a22e60, + 0x704a34fd, 0xd63d3f49, 0xcc1d9f8b, 0x6a6a943f, 0x5b828ea2, + 0xfdf58516, 0x3852bb98, 0x9e25b02c, 0xafcdaab1, 0x09baa105, + 0xfff2d1ec, 0x5985da58, 0x686dc0c5, 0xce1acb71, 0x0bbdf5ff, + 0xadcafe4b, 0x9c22e4d6, 0x3a55ef62, 0xabc30345, 0x0db408f1, + 0x3c5c126c, 0x9a2b19d8, 0x5f8c2756, 0xf9fb2ce2, 0xc813367f, + 0x6e643dcb, 0x982c4d22, 0x3e5b4696, 0x0fb35c0b, 0xa9c457bf, + 0x6c636931, 0xca146285, 0xfbfc7818, 0x5d8b73ac, 0x03a0a617, + 0xa5d7ada3, 0x943fb73e, 0x3248bc8a, 0xf7ef8204, 0x519889b0, + 0x6070932d, 0xc6079899, 0x304fe870, 0x9638e3c4, 0xa7d0f959, + 0x01a7f2ed, 0xc400cc63, 0x6277c7d7, 0x539fdd4a, 0xf5e8d6fe, + 0x647e3ad9, 0xc209316d, 0xf3e12bf0, 0x55962044, 0x90311eca, + 0x3646157e, 0x07ae0fe3, 0xa1d90457, 0x579174be, 0xf1e67f0a, + 0xc00e6597, 0x66796e23, 0xa3de50ad, 0x05a95b19, 0x34414184, + 0x92364a30}, + {0x00000000, 0xcb5cd3a5, 0x4dc8a10b, 0x869472ae, 0x9b914216, + 0x50cd91b3, 0xd659e31d, 0x1d0530b8, 0xec53826d, 0x270f51c8, + 0xa19b2366, 0x6ac7f0c3, 0x77c2c07b, 0xbc9e13de, 0x3a0a6170, + 0xf156b2d5, 0x03d6029b, 0xc88ad13e, 0x4e1ea390, 0x85427035, + 0x9847408d, 0x531b9328, 0xd58fe186, 0x1ed33223, 0xef8580f6, + 0x24d95353, 0xa24d21fd, 0x6911f258, 0x7414c2e0, 0xbf481145, + 0x39dc63eb, 0xf280b04e, 0x07ac0536, 0xccf0d693, 0x4a64a43d, + 0x81387798, 0x9c3d4720, 0x57619485, 0xd1f5e62b, 0x1aa9358e, + 0xebff875b, 0x20a354fe, 0xa6372650, 0x6d6bf5f5, 0x706ec54d, + 0xbb3216e8, 0x3da66446, 0xf6fab7e3, 0x047a07ad, 0xcf26d408, + 0x49b2a6a6, 0x82ee7503, 0x9feb45bb, 0x54b7961e, 0xd223e4b0, + 0x197f3715, 0xe82985c0, 0x23755665, 0xa5e124cb, 0x6ebdf76e, + 0x73b8c7d6, 0xb8e41473, 0x3e7066dd, 0xf52cb578, 0x0f580a6c, + 0xc404d9c9, 0x4290ab67, 0x89cc78c2, 0x94c9487a, 0x5f959bdf, + 0xd901e971, 0x125d3ad4, 0xe30b8801, 0x28575ba4, 0xaec3290a, + 0x659ffaaf, 0x789aca17, 0xb3c619b2, 0x35526b1c, 0xfe0eb8b9, + 0x0c8e08f7, 0xc7d2db52, 0x4146a9fc, 0x8a1a7a59, 0x971f4ae1, + 0x5c439944, 0xdad7ebea, 0x118b384f, 0xe0dd8a9a, 0x2b81593f, + 0xad152b91, 0x6649f834, 0x7b4cc88c, 0xb0101b29, 0x36846987, + 0xfdd8ba22, 0x08f40f5a, 0xc3a8dcff, 0x453cae51, 0x8e607df4, + 0x93654d4c, 0x58399ee9, 0xdeadec47, 0x15f13fe2, 0xe4a78d37, + 0x2ffb5e92, 0xa96f2c3c, 0x6233ff99, 0x7f36cf21, 0xb46a1c84, + 0x32fe6e2a, 0xf9a2bd8f, 0x0b220dc1, 0xc07ede64, 0x46eaacca, + 0x8db67f6f, 0x90b34fd7, 0x5bef9c72, 0xdd7beedc, 0x16273d79, + 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0x43d23e48, 0xfb6e592d, + 0xe9dbf6c3, 0x516791a6, 0xccb0a91f, 0x740cce7a, 0x66b96194, + 0xde0506f1}, + {0x00000000, 0x01c26a37, 0x0384d46e, 0x0246be59, 0x0709a8dc, + 0x06cbc2eb, 0x048d7cb2, 0x054f1685, 0x0e1351b8, 0x0fd13b8f, + 0x0d9785d6, 0x0c55efe1, 0x091af964, 0x08d89353, 0x0a9e2d0a, + 0x0b5c473d, 0x1c26a370, 0x1de4c947, 0x1fa2771e, 0x1e601d29, + 0x1b2f0bac, 0x1aed619b, 0x18abdfc2, 0x1969b5f5, 0x1235f2c8, + 0x13f798ff, 0x11b126a6, 0x10734c91, 0x153c5a14, 0x14fe3023, + 0x16b88e7a, 0x177ae44d, 0x384d46e0, 0x398f2cd7, 0x3bc9928e, + 0x3a0bf8b9, 0x3f44ee3c, 0x3e86840b, 0x3cc03a52, 0x3d025065, + 0x365e1758, 0x379c7d6f, 0x35dac336, 0x3418a901, 0x3157bf84, + 0x3095d5b3, 0x32d36bea, 0x331101dd, 0x246be590, 0x25a98fa7, + 0x27ef31fe, 0x262d5bc9, 0x23624d4c, 0x22a0277b, 0x20e69922, + 0x2124f315, 0x2a78b428, 0x2bbade1f, 0x29fc6046, 0x283e0a71, + 0x2d711cf4, 0x2cb376c3, 0x2ef5c89a, 0x2f37a2ad, 0x709a8dc0, + 0x7158e7f7, 0x731e59ae, 0x72dc3399, 0x7793251c, 0x76514f2b, + 0x7417f172, 0x75d59b45, 0x7e89dc78, 0x7f4bb64f, 0x7d0d0816, + 0x7ccf6221, 0x798074a4, 0x78421e93, 0x7a04a0ca, 0x7bc6cafd, + 0x6cbc2eb0, 0x6d7e4487, 0x6f38fade, 0x6efa90e9, 0x6bb5866c, + 0x6a77ec5b, 0x68315202, 0x69f33835, 0x62af7f08, 0x636d153f, + 0x612bab66, 0x60e9c151, 0x65a6d7d4, 0x6464bde3, 0x662203ba, + 0x67e0698d, 0x48d7cb20, 0x4915a117, 0x4b531f4e, 0x4a917579, + 0x4fde63fc, 0x4e1c09cb, 0x4c5ab792, 0x4d98dda5, 0x46c49a98, + 0x4706f0af, 0x45404ef6, 0x448224c1, 0x41cd3244, 0x400f5873, + 0x4249e62a, 0x438b8c1d, 0x54f16850, 0x55330267, 0x5775bc3e, + 0x56b7d609, 0x53f8c08c, 0x523aaabb, 0x507c14e2, 0x51be7ed5, + 0x5ae239e8, 0x5b2053df, 0x5966ed86, 0x58a487b1, 0x5deb9134, + 0x5c29fb03, 0x5e6f455a, 0x5fad2f6d, 0xe1351b80, 0xe0f771b7, + 0xe2b1cfee, 0xe373a5d9, 0xe63cb35c, 0xe7fed96b, 0xe5b86732, + 0xe47a0d05, 0xef264a38, 0xeee4200f, 0xeca29e56, 0xed60f461, + 0xe82fe2e4, 0xe9ed88d3, 0xebab368a, 0xea695cbd, 0xfd13b8f0, + 0xfcd1d2c7, 0xfe976c9e, 0xff5506a9, 0xfa1a102c, 0xfbd87a1b, + 0xf99ec442, 0xf85cae75, 0xf300e948, 0xf2c2837f, 0xf0843d26, + 0xf1465711, 0xf4094194, 0xf5cb2ba3, 0xf78d95fa, 0xf64fffcd, + 0xd9785d60, 0xd8ba3757, 0xdafc890e, 0xdb3ee339, 0xde71f5bc, + 0xdfb39f8b, 0xddf521d2, 0xdc374be5, 0xd76b0cd8, 0xd6a966ef, + 0xd4efd8b6, 0xd52db281, 0xd062a404, 0xd1a0ce33, 0xd3e6706a, + 0xd2241a5d, 0xc55efe10, 0xc49c9427, 0xc6da2a7e, 0xc7184049, + 0xc25756cc, 0xc3953cfb, 0xc1d382a2, 0xc011e895, 0xcb4dafa8, + 0xca8fc59f, 0xc8c97bc6, 0xc90b11f1, 0xcc440774, 0xcd866d43, + 0xcfc0d31a, 0xce02b92d, 0x91af9640, 0x906dfc77, 0x922b422e, + 0x93e92819, 0x96a63e9c, 0x976454ab, 0x9522eaf2, 0x94e080c5, + 0x9fbcc7f8, 0x9e7eadcf, 0x9c381396, 0x9dfa79a1, 0x98b56f24, + 0x99770513, 0x9b31bb4a, 0x9af3d17d, 0x8d893530, 0x8c4b5f07, + 0x8e0de15e, 0x8fcf8b69, 0x8a809dec, 0x8b42f7db, 0x89044982, + 0x88c623b5, 0x839a6488, 0x82580ebf, 0x801eb0e6, 0x81dcdad1, + 0x8493cc54, 0x8551a663, 0x8717183a, 0x86d5720d, 0xa9e2d0a0, + 0xa820ba97, 0xaa6604ce, 0xaba46ef9, 0xaeeb787c, 0xaf29124b, + 0xad6fac12, 0xacadc625, 0xa7f18118, 0xa633eb2f, 0xa4755576, + 0xa5b73f41, 0xa0f829c4, 0xa13a43f3, 0xa37cfdaa, 0xa2be979d, + 0xb5c473d0, 0xb40619e7, 0xb640a7be, 0xb782cd89, 0xb2cddb0c, + 0xb30fb13b, 0xb1490f62, 0xb08b6555, 0xbbd72268, 0xba15485f, + 0xb853f606, 0xb9919c31, 0xbcde8ab4, 0xbd1ce083, 0xbf5a5eda, + 0xbe9834ed}, + {0x00000000, 0x191b3141, 0x32366282, 0x2b2d53c3, 0x646cc504, + 0x7d77f445, 0x565aa786, 0x4f4196c7, 0xc8d98a08, 0xd1c2bb49, + 0xfaefe88a, 0xe3f4d9cb, 0xacb54f0c, 0xb5ae7e4d, 0x9e832d8e, + 0x87981ccf, 0x4ac21251, 0x53d92310, 0x78f470d3, 0x61ef4192, + 0x2eaed755, 0x37b5e614, 0x1c98b5d7, 0x05838496, 0x821b9859, + 0x9b00a918, 0xb02dfadb, 0xa936cb9a, 0xe6775d5d, 0xff6c6c1c, + 0xd4413fdf, 0xcd5a0e9e, 0x958424a2, 0x8c9f15e3, 0xa7b24620, + 0xbea97761, 0xf1e8e1a6, 0xe8f3d0e7, 0xc3de8324, 0xdac5b265, + 0x5d5daeaa, 0x44469feb, 0x6f6bcc28, 0x7670fd69, 0x39316bae, + 0x202a5aef, 0x0b07092c, 0x121c386d, 0xdf4636f3, 0xc65d07b2, + 0xed705471, 0xf46b6530, 0xbb2af3f7, 0xa231c2b6, 0x891c9175, + 0x9007a034, 0x179fbcfb, 0x0e848dba, 0x25a9de79, 0x3cb2ef38, + 0x73f379ff, 0x6ae848be, 0x41c51b7d, 0x58de2a3c, 0xf0794f05, + 0xe9627e44, 0xc24f2d87, 0xdb541cc6, 0x94158a01, 0x8d0ebb40, + 0xa623e883, 0xbf38d9c2, 0x38a0c50d, 0x21bbf44c, 0x0a96a78f, + 0x138d96ce, 0x5ccc0009, 0x45d73148, 0x6efa628b, 0x77e153ca, + 0xbabb5d54, 0xa3a06c15, 0x888d3fd6, 0x91960e97, 0xded79850, + 0xc7cca911, 0xece1fad2, 0xf5facb93, 0x7262d75c, 0x6b79e61d, + 0x4054b5de, 0x594f849f, 0x160e1258, 0x0f152319, 0x243870da, + 0x3d23419b, 0x65fd6ba7, 0x7ce65ae6, 0x57cb0925, 0x4ed03864, + 0x0191aea3, 0x188a9fe2, 0x33a7cc21, 0x2abcfd60, 0xad24e1af, + 0xb43fd0ee, 0x9f12832d, 0x8609b26c, 0xc94824ab, 0xd05315ea, + 0xfb7e4629, 0xe2657768, 0x2f3f79f6, 0x362448b7, 0x1d091b74, + 0x04122a35, 0x4b53bcf2, 0x52488db3, 0x7965de70, 0x607eef31, + 0xe7e6f3fe, 0xfefdc2bf, 0xd5d0917c, 0xcccba03d, 0x838a36fa, + 0x9a9107bb, 0xb1bc5478, 0xa8a76539, 0x3b83984b, 0x2298a90a, + 0x09b5fac9, 0x10aecb88, 0x5fef5d4f, 0x46f46c0e, 0x6dd93fcd, + 0x74c20e8c, 0xf35a1243, 0xea412302, 0xc16c70c1, 0xd8774180, + 0x9736d747, 0x8e2de606, 0xa500b5c5, 0xbc1b8484, 0x71418a1a, + 0x685abb5b, 0x4377e898, 0x5a6cd9d9, 0x152d4f1e, 0x0c367e5f, + 0x271b2d9c, 0x3e001cdd, 0xb9980012, 0xa0833153, 0x8bae6290, + 0x92b553d1, 0xddf4c516, 0xc4eff457, 0xefc2a794, 0xf6d996d5, + 0xae07bce9, 0xb71c8da8, 0x9c31de6b, 0x852aef2a, 0xca6b79ed, + 0xd37048ac, 0xf85d1b6f, 0xe1462a2e, 0x66de36e1, 0x7fc507a0, + 0x54e85463, 0x4df36522, 0x02b2f3e5, 0x1ba9c2a4, 0x30849167, + 0x299fa026, 0xe4c5aeb8, 0xfdde9ff9, 0xd6f3cc3a, 0xcfe8fd7b, + 0x80a96bbc, 0x99b25afd, 0xb29f093e, 0xab84387f, 0x2c1c24b0, + 0x350715f1, 0x1e2a4632, 0x07317773, 0x4870e1b4, 0x516bd0f5, + 0x7a468336, 0x635db277, 0xcbfad74e, 0xd2e1e60f, 0xf9ccb5cc, + 0xe0d7848d, 0xaf96124a, 0xb68d230b, 0x9da070c8, 0x84bb4189, + 0x03235d46, 0x1a386c07, 0x31153fc4, 0x280e0e85, 0x674f9842, + 0x7e54a903, 0x5579fac0, 0x4c62cb81, 0x8138c51f, 0x9823f45e, + 0xb30ea79d, 0xaa1596dc, 0xe554001b, 0xfc4f315a, 0xd7626299, + 0xce7953d8, 0x49e14f17, 0x50fa7e56, 0x7bd72d95, 0x62cc1cd4, + 0x2d8d8a13, 0x3496bb52, 0x1fbbe891, 0x06a0d9d0, 0x5e7ef3ec, + 0x4765c2ad, 0x6c48916e, 0x7553a02f, 0x3a1236e8, 0x230907a9, + 0x0824546a, 0x113f652b, 0x96a779e4, 0x8fbc48a5, 0xa4911b66, + 0xbd8a2a27, 0xf2cbbce0, 0xebd08da1, 0xc0fdde62, 0xd9e6ef23, + 0x14bce1bd, 0x0da7d0fc, 0x268a833f, 0x3f91b27e, 0x70d024b9, + 0x69cb15f8, 0x42e6463b, 0x5bfd777a, 0xdc656bb5, 0xc57e5af4, + 0xee530937, 0xf7483876, 0xb809aeb1, 0xa1129ff0, 0x8a3fcc33, + 0x9324fd72}, + {0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, + 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, + 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, + 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, + 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856, + 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, + 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, + 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a, + 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, + 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, + 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, + 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e, + 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, + 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, + 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, + 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, + 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, + 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010, + 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, + 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, + 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, + 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, + 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344, + 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, + 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, + 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c, + 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, + 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, + 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, + 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c, + 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, + 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, + 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, + 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278, + 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, + 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66, + 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, + 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, + 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, + 0x2d02ef8d}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x0000000000000000, 0x9630077700000000, 0x2c610eee00000000, + 0xba51099900000000, 0x19c46d0700000000, 0x8ff46a7000000000, + 0x35a563e900000000, 0xa395649e00000000, 0x3288db0e00000000, + 0xa4b8dc7900000000, 0x1ee9d5e000000000, 0x88d9d29700000000, + 0x2b4cb60900000000, 0xbd7cb17e00000000, 0x072db8e700000000, + 0x911dbf9000000000, 0x6410b71d00000000, 0xf220b06a00000000, + 0x4871b9f300000000, 0xde41be8400000000, 0x7dd4da1a00000000, + 0xebe4dd6d00000000, 0x51b5d4f400000000, 0xc785d38300000000, + 0x56986c1300000000, 0xc0a86b6400000000, 0x7af962fd00000000, + 0xecc9658a00000000, 0x4f5c011400000000, 0xd96c066300000000, + 0x633d0ffa00000000, 0xf50d088d00000000, 0xc8206e3b00000000, + 0x5e10694c00000000, 0xe44160d500000000, 0x727167a200000000, + 0xd1e4033c00000000, 0x47d4044b00000000, 0xfd850dd200000000, + 0x6bb50aa500000000, 0xfaa8b53500000000, 0x6c98b24200000000, + 0xd6c9bbdb00000000, 0x40f9bcac00000000, 0xe36cd83200000000, + 0x755cdf4500000000, 0xcf0dd6dc00000000, 0x593dd1ab00000000, + 0xac30d92600000000, 0x3a00de5100000000, 0x8051d7c800000000, + 0x1661d0bf00000000, 0xb5f4b42100000000, 0x23c4b35600000000, + 0x9995bacf00000000, 0x0fa5bdb800000000, 0x9eb8022800000000, + 0x0888055f00000000, 0xb2d90cc600000000, 0x24e90bb100000000, + 0x877c6f2f00000000, 0x114c685800000000, 0xab1d61c100000000, + 0x3d2d66b600000000, 0x9041dc7600000000, 0x0671db0100000000, + 0xbc20d29800000000, 0x2a10d5ef00000000, 0x8985b17100000000, + 0x1fb5b60600000000, 0xa5e4bf9f00000000, 0x33d4b8e800000000, + 0xa2c9077800000000, 0x34f9000f00000000, 0x8ea8099600000000, + 0x18980ee100000000, 0xbb0d6a7f00000000, 0x2d3d6d0800000000, + 0x976c649100000000, 0x015c63e600000000, 0xf4516b6b00000000, + 0x62616c1c00000000, 0xd830658500000000, 0x4e0062f200000000, + 0xed95066c00000000, 0x7ba5011b00000000, 0xc1f4088200000000, + 0x57c40ff500000000, 0xc6d9b06500000000, 0x50e9b71200000000, + 0xeab8be8b00000000, 0x7c88b9fc00000000, 0xdf1ddd6200000000, + 0x492dda1500000000, 0xf37cd38c00000000, 0x654cd4fb00000000, + 0x5861b24d00000000, 0xce51b53a00000000, 0x7400bca300000000, + 0xe230bbd400000000, 0x41a5df4a00000000, 0xd795d83d00000000, + 0x6dc4d1a400000000, 0xfbf4d6d300000000, 0x6ae9694300000000, + 0xfcd96e3400000000, 0x468867ad00000000, 0xd0b860da00000000, + 0x732d044400000000, 0xe51d033300000000, 0x5f4c0aaa00000000, + 0xc97c0ddd00000000, 0x3c71055000000000, 0xaa41022700000000, + 0x10100bbe00000000, 0x86200cc900000000, 0x25b5685700000000, + 0xb3856f2000000000, 0x09d466b900000000, 0x9fe461ce00000000, + 0x0ef9de5e00000000, 0x98c9d92900000000, 0x2298d0b000000000, + 0xb4a8d7c700000000, 0x173db35900000000, 0x810db42e00000000, + 0x3b5cbdb700000000, 0xad6cbac000000000, 0x2083b8ed00000000, + 0xb6b3bf9a00000000, 0x0ce2b60300000000, 0x9ad2b17400000000, + 0x3947d5ea00000000, 0xaf77d29d00000000, 0x1526db0400000000, + 0x8316dc7300000000, 0x120b63e300000000, 0x843b649400000000, + 0x3e6a6d0d00000000, 0xa85a6a7a00000000, 0x0bcf0ee400000000, + 0x9dff099300000000, 0x27ae000a00000000, 0xb19e077d00000000, + 0x44930ff000000000, 0xd2a3088700000000, 0x68f2011e00000000, + 0xfec2066900000000, 0x5d5762f700000000, 0xcb67658000000000, + 0x71366c1900000000, 0xe7066b6e00000000, 0x761bd4fe00000000, + 0xe02bd38900000000, 0x5a7ada1000000000, 0xcc4add6700000000, + 0x6fdfb9f900000000, 0xf9efbe8e00000000, 0x43beb71700000000, + 0xd58eb06000000000, 0xe8a3d6d600000000, 0x7e93d1a100000000, + 0xc4c2d83800000000, 0x52f2df4f00000000, 0xf167bbd100000000, + 0x6757bca600000000, 0xdd06b53f00000000, 0x4b36b24800000000, + 0xda2b0dd800000000, 0x4c1b0aaf00000000, 0xf64a033600000000, + 0x607a044100000000, 0xc3ef60df00000000, 0x55df67a800000000, + 0xef8e6e3100000000, 0x79be694600000000, 0x8cb361cb00000000, + 0x1a8366bc00000000, 0xa0d26f2500000000, 0x36e2685200000000, + 0x95770ccc00000000, 0x03470bbb00000000, 0xb916022200000000, + 0x2f26055500000000, 0xbe3bbac500000000, 0x280bbdb200000000, + 0x925ab42b00000000, 0x046ab35c00000000, 0xa7ffd7c200000000, + 0x31cfd0b500000000, 0x8b9ed92c00000000, 0x1daede5b00000000, + 0xb0c2649b00000000, 0x26f263ec00000000, 0x9ca36a7500000000, + 0x0a936d0200000000, 0xa906099c00000000, 0x3f360eeb00000000, + 0x8567077200000000, 0x1357000500000000, 0x824abf9500000000, + 0x147ab8e200000000, 0xae2bb17b00000000, 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0x1f18b18900000000, + 0x9126164c00000000, 0x252d61ea00000000, 0xb83789db00000000, + 0x0c3cfe7d00000000, 0x2bd068ec00000000, 0x9fdb1f4a00000000, + 0x02c1f77b00000000, 0xb6ca80dd00000000, 0x38f4271800000000, + 0x8cff50be00000000, 0x11e5b88f00000000, 0xa5eecf2900000000, + 0x4c9e87df00000000, 0xf895f07900000000, 0x658f184800000000, + 0xd1846fee00000000, 0x5fbac82b00000000, 0xebb1bf8d00000000, + 0x76ab57bc00000000, 0xc2a0201a00000000, 0xf2ea168800000000, + 0x46e1612e00000000, 0xdbfb891f00000000, 0x6ff0feb900000000, + 0xe1ce597c00000000, 0x55c52eda00000000, 0xc8dfc6eb00000000, + 0x7cd4b14d00000000, 0x95a4f9bb00000000, 0x21af8e1d00000000, + 0xbcb5662c00000000, 0x08be118a00000000, 0x8680b64f00000000, + 0x328bc1e900000000, 0xaf9129d800000000, 0x1b9a5e7e00000000, + 0x3c76c8ef00000000, 0x887dbf4900000000, 0x1567577800000000, + 0xa16c20de00000000, 0x2f52871b00000000, 0x9b59f0bd00000000, + 0x0643188c00000000, 0xb2486f2a00000000, 0x5b3827dc00000000, + 0xef33507a00000000, 0x7229b84b00000000, 0xc622cfed00000000, + 0x481c682800000000, 0xfc171f8e00000000, 0x610df7bf00000000, + 0xd506801900000000, 0x6ed3ab4700000000, 0xdad8dce100000000, + 0x47c234d000000000, 0xf3c9437600000000, 0x7df7e4b300000000, + 0xc9fc931500000000, 0x54e67b2400000000, 0xe0ed0c8200000000, + 0x099d447400000000, 0xbd9633d200000000, 0x208cdbe300000000, + 0x9487ac4500000000, 0x1ab90b8000000000, 0xaeb27c2600000000, + 0x33a8941700000000, 0x87a3e3b100000000, 0xa04f752000000000, + 0x1444028600000000, 0x895eeab700000000, 0x3d559d1100000000, + 0xb36b3ad400000000, 0x07604d7200000000, 0x9a7aa54300000000, + 0x2e71d2e500000000, 0xc7019a1300000000, 0x730aedb500000000, + 0xee10058400000000, 0x5a1b722200000000, 0xd425d5e700000000, + 0x602ea24100000000, 0xfd344a7000000000, 0x493f3dd600000000, + 0x8b9f1dcc00000000, 0x3f946a6a00000000, 0xa28e825b00000000, + 0x1685f5fd00000000, 0x98bb523800000000, 0x2cb0259e00000000, + 0xb1aacdaf00000000, 0x05a1ba0900000000, 0xecd1f2ff00000000, + 0x58da855900000000, 0xc5c06d6800000000, 0x71cb1ace00000000, + 0xfff5bd0b00000000, 0x4bfecaad00000000, 0xd6e4229c00000000, + 0x62ef553a00000000, 0x4503c3ab00000000, 0xf108b40d00000000, + 0x6c125c3c00000000, 0xd8192b9a00000000, 0x56278c5f00000000, + 0xe22cfbf900000000, 0x7f3613c800000000, 0xcb3d646e00000000, + 0x224d2c9800000000, 0x96465b3e00000000, 0x0b5cb30f00000000, + 0xbf57c4a900000000, 0x3169636c00000000, 0x856214ca00000000, + 0x1878fcfb00000000, 0xac738b5d00000000, 0x17a6a00300000000, + 0xa3add7a500000000, 0x3eb73f9400000000, 0x8abc483200000000, + 0x0482eff700000000, 0xb089985100000000, 0x2d93706000000000, + 0x999807c600000000, 0x70e84f3000000000, 0xc4e3389600000000, + 0x59f9d0a700000000, 0xedf2a70100000000, 0x63cc00c400000000, + 0xd7c7776200000000, 0x4add9f5300000000, 0xfed6e8f500000000, + 0xd93a7e6400000000, 0x6d3109c200000000, 0xf02be1f300000000, + 0x4420965500000000, 0xca1e319000000000, 0x7e15463600000000, + 0xe30fae0700000000, 0x5704d9a100000000, 0xbe74915700000000, + 0x0a7fe6f100000000, 0x97650ec000000000, 0x236e796600000000, + 0xad50dea300000000, 0x195ba90500000000, 0x8441413400000000, + 0x304a369200000000}, + {0x0000000000000000, 0x9e00aacc00000000, 0x7d07254200000000, + 0xe3078f8e00000000, 0xfa0e4a8400000000, 0x640ee04800000000, + 0x87096fc600000000, 0x1909c50a00000000, 0xb51be5d300000000, + 0x2b1b4f1f00000000, 0xc81cc09100000000, 0x561c6a5d00000000, + 0x4f15af5700000000, 0xd115059b00000000, 0x32128a1500000000, + 0xac1220d900000000, 0x2b31bb7c00000000, 0xb53111b000000000, + 0x56369e3e00000000, 0xc83634f200000000, 0xd13ff1f800000000, + 0x4f3f5b3400000000, 0xac38d4ba00000000, 0x32387e7600000000, + 0x9e2a5eaf00000000, 0x002af46300000000, 0xe32d7bed00000000, + 0x7d2dd12100000000, 0x6424142b00000000, 0xfa24bee700000000, + 0x1923316900000000, 0x87239ba500000000, 0x566276f900000000, + 0xc862dc3500000000, 0x2b6553bb00000000, 0xb565f97700000000, + 0xac6c3c7d00000000, 0x326c96b100000000, 0xd16b193f00000000, + 0x4f6bb3f300000000, 0xe379932a00000000, 0x7d7939e600000000, + 0x9e7eb66800000000, 0x007e1ca400000000, 0x1977d9ae00000000, + 0x8777736200000000, 0x6470fcec00000000, 0xfa70562000000000, + 0x7d53cd8500000000, 0xe353674900000000, 0x0054e8c700000000, + 0x9e54420b00000000, 0x875d870100000000, 0x195d2dcd00000000, + 0xfa5aa24300000000, 0x645a088f00000000, 0xc848285600000000, + 0x5648829a00000000, 0xb54f0d1400000000, 0x2b4fa7d800000000, + 0x324662d200000000, 0xac46c81e00000000, 0x4f41479000000000, + 0xd141ed5c00000000, 0xedc29d2900000000, 0x73c237e500000000, + 0x90c5b86b00000000, 0x0ec512a700000000, 0x17ccd7ad00000000, + 0x89cc7d6100000000, 0x6acbf2ef00000000, 0xf4cb582300000000, + 0x58d978fa00000000, 0xc6d9d23600000000, 0x25de5db800000000, + 0xbbdef77400000000, 0xa2d7327e00000000, 0x3cd798b200000000, + 0xdfd0173c00000000, 0x41d0bdf000000000, 0xc6f3265500000000, + 0x58f38c9900000000, 0xbbf4031700000000, 0x25f4a9db00000000, + 0x3cfd6cd100000000, 0xa2fdc61d00000000, 0x41fa499300000000, + 0xdffae35f00000000, 0x73e8c38600000000, 0xede8694a00000000, + 0x0eefe6c400000000, 0x90ef4c0800000000, 0x89e6890200000000, + 0x17e623ce00000000, 0xf4e1ac4000000000, 0x6ae1068c00000000, + 0xbba0ebd000000000, 0x25a0411c00000000, 0xc6a7ce9200000000, + 0x58a7645e00000000, 0x41aea15400000000, 0xdfae0b9800000000, + 0x3ca9841600000000, 0xa2a92eda00000000, 0x0ebb0e0300000000, + 0x90bba4cf00000000, 0x73bc2b4100000000, 0xedbc818d00000000, + 0xf4b5448700000000, 0x6ab5ee4b00000000, 0x89b261c500000000, + 0x17b2cb0900000000, 0x909150ac00000000, 0x0e91fa6000000000, + 0xed9675ee00000000, 0x7396df2200000000, 0x6a9f1a2800000000, + 0xf49fb0e400000000, 0x17983f6a00000000, 0x899895a600000000, + 0x258ab57f00000000, 0xbb8a1fb300000000, 0x588d903d00000000, + 0xc68d3af100000000, 0xdf84fffb00000000, 0x4184553700000000, + 0xa283dab900000000, 0x3c83707500000000, 0xda853b5300000000, + 0x4485919f00000000, 0xa7821e1100000000, 0x3982b4dd00000000, + 0x208b71d700000000, 0xbe8bdb1b00000000, 0x5d8c549500000000, + 0xc38cfe5900000000, 0x6f9ede8000000000, 0xf19e744c00000000, + 0x1299fbc200000000, 0x8c99510e00000000, 0x9590940400000000, + 0x0b903ec800000000, 0xe897b14600000000, 0x76971b8a00000000, + 0xf1b4802f00000000, 0x6fb42ae300000000, 0x8cb3a56d00000000, + 0x12b30fa100000000, 0x0bbacaab00000000, 0x95ba606700000000, + 0x76bdefe900000000, 0xe8bd452500000000, 0x44af65fc00000000, + 0xdaafcf3000000000, 0x39a840be00000000, 0xa7a8ea7200000000, + 0xbea12f7800000000, 0x20a185b400000000, 0xc3a60a3a00000000, + 0x5da6a0f600000000, 0x8ce74daa00000000, 0x12e7e76600000000, + 0xf1e068e800000000, 0x6fe0c22400000000, 0x76e9072e00000000, + 0xe8e9ade200000000, 0x0bee226c00000000, 0x95ee88a000000000, + 0x39fca87900000000, 0xa7fc02b500000000, 0x44fb8d3b00000000, + 0xdafb27f700000000, 0xc3f2e2fd00000000, 0x5df2483100000000, + 0xbef5c7bf00000000, 0x20f56d7300000000, 0xa7d6f6d600000000, + 0x39d65c1a00000000, 0xdad1d39400000000, 0x44d1795800000000, + 0x5dd8bc5200000000, 0xc3d8169e00000000, 0x20df991000000000, + 0xbedf33dc00000000, 0x12cd130500000000, 0x8ccdb9c900000000, + 0x6fca364700000000, 0xf1ca9c8b00000000, 0xe8c3598100000000, + 0x76c3f34d00000000, 0x95c47cc300000000, 0x0bc4d60f00000000, + 0x3747a67a00000000, 0xa9470cb600000000, 0x4a40833800000000, + 0xd44029f400000000, 0xcd49ecfe00000000, 0x5349463200000000, + 0xb04ec9bc00000000, 0x2e4e637000000000, 0x825c43a900000000, + 0x1c5ce96500000000, 0xff5b66eb00000000, 0x615bcc2700000000, + 0x7852092d00000000, 0xe652a3e100000000, 0x05552c6f00000000, + 0x9b5586a300000000, 0x1c761d0600000000, 0x8276b7ca00000000, + 0x6171384400000000, 0xff71928800000000, 0xe678578200000000, + 0x7878fd4e00000000, 0x9b7f72c000000000, 0x057fd80c00000000, + 0xa96df8d500000000, 0x376d521900000000, 0xd46add9700000000, + 0x4a6a775b00000000, 0x5363b25100000000, 0xcd63189d00000000, + 0x2e64971300000000, 0xb0643ddf00000000, 0x6125d08300000000, + 0xff257a4f00000000, 0x1c22f5c100000000, 0x82225f0d00000000, + 0x9b2b9a0700000000, 0x052b30cb00000000, 0xe62cbf4500000000, + 0x782c158900000000, 0xd43e355000000000, 0x4a3e9f9c00000000, + 0xa939101200000000, 0x3739bade00000000, 0x2e307fd400000000, + 0xb030d51800000000, 0x53375a9600000000, 0xcd37f05a00000000, + 0x4a146bff00000000, 0xd414c13300000000, 0x37134ebd00000000, + 0xa913e47100000000, 0xb01a217b00000000, 0x2e1a8bb700000000, + 0xcd1d043900000000, 0x531daef500000000, 0xff0f8e2c00000000, + 0x610f24e000000000, 0x8208ab6e00000000, 0x1c0801a200000000, + 0x0501c4a800000000, 0x9b016e6400000000, 0x7806e1ea00000000, + 0xe6064b2600000000}}; + +#else /* W == 4 */ + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0xb8bc6765, 0xaa09c88b, 0x12b5afee, 0x8f629757, + 0x37def032, 0x256b5fdc, 0x9dd738b9, 0xc5b428ef, 0x7d084f8a, + 0x6fbde064, 0xd7018701, 0x4ad6bfb8, 0xf26ad8dd, 0xe0df7733, + 0x58631056, 0x5019579f, 0xe8a530fa, 0xfa109f14, 0x42acf871, + 0xdf7bc0c8, 0x67c7a7ad, 0x75720843, 0xcdce6f26, 0x95ad7f70, + 0x2d111815, 0x3fa4b7fb, 0x8718d09e, 0x1acfe827, 0xa2738f42, + 0xb0c620ac, 0x087a47c9, 0xa032af3e, 0x188ec85b, 0x0a3b67b5, + 0xb28700d0, 0x2f503869, 0x97ec5f0c, 0x8559f0e2, 0x3de59787, + 0x658687d1, 0xdd3ae0b4, 0xcf8f4f5a, 0x7733283f, 0xeae41086, + 0x525877e3, 0x40edd80d, 0xf851bf68, 0xf02bf8a1, 0x48979fc4, + 0x5a22302a, 0xe29e574f, 0x7f496ff6, 0xc7f50893, 0xd540a77d, + 0x6dfcc018, 0x359fd04e, 0x8d23b72b, 0x9f9618c5, 0x272a7fa0, + 0xbafd4719, 0x0241207c, 0x10f48f92, 0xa848e8f7, 0x9b14583d, + 0x23a83f58, 0x311d90b6, 0x89a1f7d3, 0x1476cf6a, 0xaccaa80f, + 0xbe7f07e1, 0x06c36084, 0x5ea070d2, 0xe61c17b7, 0xf4a9b859, + 0x4c15df3c, 0xd1c2e785, 0x697e80e0, 0x7bcb2f0e, 0xc377486b, + 0xcb0d0fa2, 0x73b168c7, 0x6104c729, 0xd9b8a04c, 0x446f98f5, + 0xfcd3ff90, 0xee66507e, 0x56da371b, 0x0eb9274d, 0xb6054028, + 0xa4b0efc6, 0x1c0c88a3, 0x81dbb01a, 0x3967d77f, 0x2bd27891, + 0x936e1ff4, 0x3b26f703, 0x839a9066, 0x912f3f88, 0x299358ed, + 0xb4446054, 0x0cf80731, 0x1e4da8df, 0xa6f1cfba, 0xfe92dfec, + 0x462eb889, 0x549b1767, 0xec277002, 0x71f048bb, 0xc94c2fde, + 0xdbf98030, 0x6345e755, 0x6b3fa09c, 0xd383c7f9, 0xc1366817, + 0x798a0f72, 0xe45d37cb, 0x5ce150ae, 0x4e54ff40, 0xf6e89825, + 0xae8b8873, 0x1637ef16, 0x048240f8, 0xbc3e279d, 0x21e91f24, + 0x99557841, 0x8be0d7af, 0x335cb0ca, 0xed59b63b, 0x55e5d15e, + 0x47507eb0, 0xffec19d5, 0x623b216c, 0xda874609, 0xc832e9e7, + 0x708e8e82, 0x28ed9ed4, 0x9051f9b1, 0x82e4565f, 0x3a58313a, + 0xa78f0983, 0x1f336ee6, 0x0d86c108, 0xb53aa66d, 0xbd40e1a4, + 0x05fc86c1, 0x1749292f, 0xaff54e4a, 0x322276f3, 0x8a9e1196, + 0x982bbe78, 0x2097d91d, 0x78f4c94b, 0xc048ae2e, 0xd2fd01c0, + 0x6a4166a5, 0xf7965e1c, 0x4f2a3979, 0x5d9f9697, 0xe523f1f2, + 0x4d6b1905, 0xf5d77e60, 0xe762d18e, 0x5fdeb6eb, 0xc2098e52, + 0x7ab5e937, 0x680046d9, 0xd0bc21bc, 0x88df31ea, 0x3063568f, + 0x22d6f961, 0x9a6a9e04, 0x07bda6bd, 0xbf01c1d8, 0xadb46e36, + 0x15080953, 0x1d724e9a, 0xa5ce29ff, 0xb77b8611, 0x0fc7e174, + 0x9210d9cd, 0x2aacbea8, 0x38191146, 0x80a57623, 0xd8c66675, + 0x607a0110, 0x72cfaefe, 0xca73c99b, 0x57a4f122, 0xef189647, + 0xfdad39a9, 0x45115ecc, 0x764dee06, 0xcef18963, 0xdc44268d, + 0x64f841e8, 0xf92f7951, 0x41931e34, 0x5326b1da, 0xeb9ad6bf, + 0xb3f9c6e9, 0x0b45a18c, 0x19f00e62, 0xa14c6907, 0x3c9b51be, + 0x842736db, 0x96929935, 0x2e2efe50, 0x2654b999, 0x9ee8defc, + 0x8c5d7112, 0x34e11677, 0xa9362ece, 0x118a49ab, 0x033fe645, + 0xbb838120, 0xe3e09176, 0x5b5cf613, 0x49e959fd, 0xf1553e98, + 0x6c820621, 0xd43e6144, 0xc68bceaa, 0x7e37a9cf, 0xd67f4138, + 0x6ec3265d, 0x7c7689b3, 0xc4caeed6, 0x591dd66f, 0xe1a1b10a, + 0xf3141ee4, 0x4ba87981, 0x13cb69d7, 0xab770eb2, 0xb9c2a15c, + 0x017ec639, 0x9ca9fe80, 0x241599e5, 0x36a0360b, 0x8e1c516e, + 0x866616a7, 0x3eda71c2, 0x2c6fde2c, 0x94d3b949, 0x090481f0, + 0xb1b8e695, 0xa30d497b, 0x1bb12e1e, 0x43d23e48, 0xfb6e592d, + 0xe9dbf6c3, 0x516791a6, 0xccb0a91f, 0x740cce7a, 0x66b96194, + 0xde0506f1}, + {0x00000000, 0x01c26a37, 0x0384d46e, 0x0246be59, 0x0709a8dc, + 0x06cbc2eb, 0x048d7cb2, 0x054f1685, 0x0e1351b8, 0x0fd13b8f, + 0x0d9785d6, 0x0c55efe1, 0x091af964, 0x08d89353, 0x0a9e2d0a, + 0x0b5c473d, 0x1c26a370, 0x1de4c947, 0x1fa2771e, 0x1e601d29, + 0x1b2f0bac, 0x1aed619b, 0x18abdfc2, 0x1969b5f5, 0x1235f2c8, + 0x13f798ff, 0x11b126a6, 0x10734c91, 0x153c5a14, 0x14fe3023, + 0x16b88e7a, 0x177ae44d, 0x384d46e0, 0x398f2cd7, 0x3bc9928e, + 0x3a0bf8b9, 0x3f44ee3c, 0x3e86840b, 0x3cc03a52, 0x3d025065, + 0x365e1758, 0x379c7d6f, 0x35dac336, 0x3418a901, 0x3157bf84, + 0x3095d5b3, 0x32d36bea, 0x331101dd, 0x246be590, 0x25a98fa7, + 0x27ef31fe, 0x262d5bc9, 0x23624d4c, 0x22a0277b, 0x20e69922, + 0x2124f315, 0x2a78b428, 0x2bbade1f, 0x29fc6046, 0x283e0a71, + 0x2d711cf4, 0x2cb376c3, 0x2ef5c89a, 0x2f37a2ad, 0x709a8dc0, + 0x7158e7f7, 0x731e59ae, 0x72dc3399, 0x7793251c, 0x76514f2b, + 0x7417f172, 0x75d59b45, 0x7e89dc78, 0x7f4bb64f, 0x7d0d0816, + 0x7ccf6221, 0x798074a4, 0x78421e93, 0x7a04a0ca, 0x7bc6cafd, + 0x6cbc2eb0, 0x6d7e4487, 0x6f38fade, 0x6efa90e9, 0x6bb5866c, + 0x6a77ec5b, 0x68315202, 0x69f33835, 0x62af7f08, 0x636d153f, + 0x612bab66, 0x60e9c151, 0x65a6d7d4, 0x6464bde3, 0x662203ba, + 0x67e0698d, 0x48d7cb20, 0x4915a117, 0x4b531f4e, 0x4a917579, + 0x4fde63fc, 0x4e1c09cb, 0x4c5ab792, 0x4d98dda5, 0x46c49a98, + 0x4706f0af, 0x45404ef6, 0x448224c1, 0x41cd3244, 0x400f5873, + 0x4249e62a, 0x438b8c1d, 0x54f16850, 0x55330267, 0x5775bc3e, + 0x56b7d609, 0x53f8c08c, 0x523aaabb, 0x507c14e2, 0x51be7ed5, + 0x5ae239e8, 0x5b2053df, 0x5966ed86, 0x58a487b1, 0x5deb9134, + 0x5c29fb03, 0x5e6f455a, 0x5fad2f6d, 0xe1351b80, 0xe0f771b7, + 0xe2b1cfee, 0xe373a5d9, 0xe63cb35c, 0xe7fed96b, 0xe5b86732, + 0xe47a0d05, 0xef264a38, 0xeee4200f, 0xeca29e56, 0xed60f461, + 0xe82fe2e4, 0xe9ed88d3, 0xebab368a, 0xea695cbd, 0xfd13b8f0, + 0xfcd1d2c7, 0xfe976c9e, 0xff5506a9, 0xfa1a102c, 0xfbd87a1b, + 0xf99ec442, 0xf85cae75, 0xf300e948, 0xf2c2837f, 0xf0843d26, + 0xf1465711, 0xf4094194, 0xf5cb2ba3, 0xf78d95fa, 0xf64fffcd, + 0xd9785d60, 0xd8ba3757, 0xdafc890e, 0xdb3ee339, 0xde71f5bc, + 0xdfb39f8b, 0xddf521d2, 0xdc374be5, 0xd76b0cd8, 0xd6a966ef, + 0xd4efd8b6, 0xd52db281, 0xd062a404, 0xd1a0ce33, 0xd3e6706a, + 0xd2241a5d, 0xc55efe10, 0xc49c9427, 0xc6da2a7e, 0xc7184049, + 0xc25756cc, 0xc3953cfb, 0xc1d382a2, 0xc011e895, 0xcb4dafa8, + 0xca8fc59f, 0xc8c97bc6, 0xc90b11f1, 0xcc440774, 0xcd866d43, + 0xcfc0d31a, 0xce02b92d, 0x91af9640, 0x906dfc77, 0x922b422e, + 0x93e92819, 0x96a63e9c, 0x976454ab, 0x9522eaf2, 0x94e080c5, + 0x9fbcc7f8, 0x9e7eadcf, 0x9c381396, 0x9dfa79a1, 0x98b56f24, + 0x99770513, 0x9b31bb4a, 0x9af3d17d, 0x8d893530, 0x8c4b5f07, + 0x8e0de15e, 0x8fcf8b69, 0x8a809dec, 0x8b42f7db, 0x89044982, + 0x88c623b5, 0x839a6488, 0x82580ebf, 0x801eb0e6, 0x81dcdad1, + 0x8493cc54, 0x8551a663, 0x8717183a, 0x86d5720d, 0xa9e2d0a0, + 0xa820ba97, 0xaa6604ce, 0xaba46ef9, 0xaeeb787c, 0xaf29124b, + 0xad6fac12, 0xacadc625, 0xa7f18118, 0xa633eb2f, 0xa4755576, + 0xa5b73f41, 0xa0f829c4, 0xa13a43f3, 0xa37cfdaa, 0xa2be979d, + 0xb5c473d0, 0xb40619e7, 0xb640a7be, 0xb782cd89, 0xb2cddb0c, + 0xb30fb13b, 0xb1490f62, 0xb08b6555, 0xbbd72268, 0xba15485f, + 0xb853f606, 0xb9919c31, 0xbcde8ab4, 0xbd1ce083, 0xbf5a5eda, + 0xbe9834ed}, + {0x00000000, 0x191b3141, 0x32366282, 0x2b2d53c3, 0x646cc504, + 0x7d77f445, 0x565aa786, 0x4f4196c7, 0xc8d98a08, 0xd1c2bb49, + 0xfaefe88a, 0xe3f4d9cb, 0xacb54f0c, 0xb5ae7e4d, 0x9e832d8e, + 0x87981ccf, 0x4ac21251, 0x53d92310, 0x78f470d3, 0x61ef4192, + 0x2eaed755, 0x37b5e614, 0x1c98b5d7, 0x05838496, 0x821b9859, + 0x9b00a918, 0xb02dfadb, 0xa936cb9a, 0xe6775d5d, 0xff6c6c1c, + 0xd4413fdf, 0xcd5a0e9e, 0x958424a2, 0x8c9f15e3, 0xa7b24620, + 0xbea97761, 0xf1e8e1a6, 0xe8f3d0e7, 0xc3de8324, 0xdac5b265, + 0x5d5daeaa, 0x44469feb, 0x6f6bcc28, 0x7670fd69, 0x39316bae, + 0x202a5aef, 0x0b07092c, 0x121c386d, 0xdf4636f3, 0xc65d07b2, + 0xed705471, 0xf46b6530, 0xbb2af3f7, 0xa231c2b6, 0x891c9175, + 0x9007a034, 0x179fbcfb, 0x0e848dba, 0x25a9de79, 0x3cb2ef38, + 0x73f379ff, 0x6ae848be, 0x41c51b7d, 0x58de2a3c, 0xf0794f05, + 0xe9627e44, 0xc24f2d87, 0xdb541cc6, 0x94158a01, 0x8d0ebb40, + 0xa623e883, 0xbf38d9c2, 0x38a0c50d, 0x21bbf44c, 0x0a96a78f, + 0x138d96ce, 0x5ccc0009, 0x45d73148, 0x6efa628b, 0x77e153ca, + 0xbabb5d54, 0xa3a06c15, 0x888d3fd6, 0x91960e97, 0xded79850, + 0xc7cca911, 0xece1fad2, 0xf5facb93, 0x7262d75c, 0x6b79e61d, + 0x4054b5de, 0x594f849f, 0x160e1258, 0x0f152319, 0x243870da, + 0x3d23419b, 0x65fd6ba7, 0x7ce65ae6, 0x57cb0925, 0x4ed03864, + 0x0191aea3, 0x188a9fe2, 0x33a7cc21, 0x2abcfd60, 0xad24e1af, + 0xb43fd0ee, 0x9f12832d, 0x8609b26c, 0xc94824ab, 0xd05315ea, + 0xfb7e4629, 0xe2657768, 0x2f3f79f6, 0x362448b7, 0x1d091b74, + 0x04122a35, 0x4b53bcf2, 0x52488db3, 0x7965de70, 0x607eef31, + 0xe7e6f3fe, 0xfefdc2bf, 0xd5d0917c, 0xcccba03d, 0x838a36fa, + 0x9a9107bb, 0xb1bc5478, 0xa8a76539, 0x3b83984b, 0x2298a90a, + 0x09b5fac9, 0x10aecb88, 0x5fef5d4f, 0x46f46c0e, 0x6dd93fcd, + 0x74c20e8c, 0xf35a1243, 0xea412302, 0xc16c70c1, 0xd8774180, + 0x9736d747, 0x8e2de606, 0xa500b5c5, 0xbc1b8484, 0x71418a1a, + 0x685abb5b, 0x4377e898, 0x5a6cd9d9, 0x152d4f1e, 0x0c367e5f, + 0x271b2d9c, 0x3e001cdd, 0xb9980012, 0xa0833153, 0x8bae6290, + 0x92b553d1, 0xddf4c516, 0xc4eff457, 0xefc2a794, 0xf6d996d5, + 0xae07bce9, 0xb71c8da8, 0x9c31de6b, 0x852aef2a, 0xca6b79ed, + 0xd37048ac, 0xf85d1b6f, 0xe1462a2e, 0x66de36e1, 0x7fc507a0, + 0x54e85463, 0x4df36522, 0x02b2f3e5, 0x1ba9c2a4, 0x30849167, + 0x299fa026, 0xe4c5aeb8, 0xfdde9ff9, 0xd6f3cc3a, 0xcfe8fd7b, + 0x80a96bbc, 0x99b25afd, 0xb29f093e, 0xab84387f, 0x2c1c24b0, + 0x350715f1, 0x1e2a4632, 0x07317773, 0x4870e1b4, 0x516bd0f5, + 0x7a468336, 0x635db277, 0xcbfad74e, 0xd2e1e60f, 0xf9ccb5cc, + 0xe0d7848d, 0xaf96124a, 0xb68d230b, 0x9da070c8, 0x84bb4189, + 0x03235d46, 0x1a386c07, 0x31153fc4, 0x280e0e85, 0x674f9842, + 0x7e54a903, 0x5579fac0, 0x4c62cb81, 0x8138c51f, 0x9823f45e, + 0xb30ea79d, 0xaa1596dc, 0xe554001b, 0xfc4f315a, 0xd7626299, + 0xce7953d8, 0x49e14f17, 0x50fa7e56, 0x7bd72d95, 0x62cc1cd4, + 0x2d8d8a13, 0x3496bb52, 0x1fbbe891, 0x06a0d9d0, 0x5e7ef3ec, + 0x4765c2ad, 0x6c48916e, 0x7553a02f, 0x3a1236e8, 0x230907a9, + 0x0824546a, 0x113f652b, 0x96a779e4, 0x8fbc48a5, 0xa4911b66, + 0xbd8a2a27, 0xf2cbbce0, 0xebd08da1, 0xc0fdde62, 0xd9e6ef23, + 0x14bce1bd, 0x0da7d0fc, 0x268a833f, 0x3f91b27e, 0x70d024b9, + 0x69cb15f8, 0x42e6463b, 0x5bfd777a, 0xdc656bb5, 0xc57e5af4, + 0xee530937, 0xf7483876, 0xb809aeb1, 0xa1129ff0, 0x8a3fcc33, + 0x9324fd72}, + {0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, + 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, + 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, + 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, + 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856, + 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, + 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, + 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a, + 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, + 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, + 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, + 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e, + 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, + 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, + 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, + 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, + 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, + 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010, + 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, + 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, + 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, + 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, + 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344, + 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, + 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, + 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c, + 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, + 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, + 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, + 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c, + 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, + 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, + 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, + 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278, + 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, + 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66, + 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, + 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, + 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, + 0x2d02ef8d}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x00000000, 0x96300777, 0x2c610eee, 0xba510999, 0x19c46d07, + 0x8ff46a70, 0x35a563e9, 0xa395649e, 0x3288db0e, 0xa4b8dc79, + 0x1ee9d5e0, 0x88d9d297, 0x2b4cb609, 0xbd7cb17e, 0x072db8e7, + 0x911dbf90, 0x6410b71d, 0xf220b06a, 0x4871b9f3, 0xde41be84, + 0x7dd4da1a, 0xebe4dd6d, 0x51b5d4f4, 0xc785d383, 0x56986c13, + 0xc0a86b64, 0x7af962fd, 0xecc9658a, 0x4f5c0114, 0xd96c0663, + 0x633d0ffa, 0xf50d088d, 0xc8206e3b, 0x5e10694c, 0xe44160d5, + 0x727167a2, 0xd1e4033c, 0x47d4044b, 0xfd850dd2, 0x6bb50aa5, + 0xfaa8b535, 0x6c98b242, 0xd6c9bbdb, 0x40f9bcac, 0xe36cd832, + 0x755cdf45, 0xcf0dd6dc, 0x593dd1ab, 0xac30d926, 0x3a00de51, + 0x8051d7c8, 0x1661d0bf, 0xb5f4b421, 0x23c4b356, 0x9995bacf, + 0x0fa5bdb8, 0x9eb80228, 0x0888055f, 0xb2d90cc6, 0x24e90bb1, + 0x877c6f2f, 0x114c6858, 0xab1d61c1, 0x3d2d66b6, 0x9041dc76, + 0x0671db01, 0xbc20d298, 0x2a10d5ef, 0x8985b171, 0x1fb5b606, + 0xa5e4bf9f, 0x33d4b8e8, 0xa2c90778, 0x34f9000f, 0x8ea80996, + 0x18980ee1, 0xbb0d6a7f, 0x2d3d6d08, 0x976c6491, 0x015c63e6, + 0xf4516b6b, 0x62616c1c, 0xd8306585, 0x4e0062f2, 0xed95066c, + 0x7ba5011b, 0xc1f40882, 0x57c40ff5, 0xc6d9b065, 0x50e9b712, + 0xeab8be8b, 0x7c88b9fc, 0xdf1ddd62, 0x492dda15, 0xf37cd38c, + 0x654cd4fb, 0x5861b24d, 0xce51b53a, 0x7400bca3, 0xe230bbd4, + 0x41a5df4a, 0xd795d83d, 0x6dc4d1a4, 0xfbf4d6d3, 0x6ae96943, + 0xfcd96e34, 0x468867ad, 0xd0b860da, 0x732d0444, 0xe51d0333, + 0x5f4c0aaa, 0xc97c0ddd, 0x3c710550, 0xaa410227, 0x10100bbe, + 0x86200cc9, 0x25b56857, 0xb3856f20, 0x09d466b9, 0x9fe461ce, + 0x0ef9de5e, 0x98c9d929, 0x2298d0b0, 0xb4a8d7c7, 0x173db359, + 0x810db42e, 0x3b5cbdb7, 0xad6cbac0, 0x2083b8ed, 0xb6b3bf9a, + 0x0ce2b603, 0x9ad2b174, 0x3947d5ea, 0xaf77d29d, 0x1526db04, + 0x8316dc73, 0x120b63e3, 0x843b6494, 0x3e6a6d0d, 0xa85a6a7a, + 0x0bcf0ee4, 0x9dff0993, 0x27ae000a, 0xb19e077d, 0x44930ff0, + 0xd2a30887, 0x68f2011e, 0xfec20669, 0x5d5762f7, 0xcb676580, + 0x71366c19, 0xe7066b6e, 0x761bd4fe, 0xe02bd389, 0x5a7ada10, + 0xcc4add67, 0x6fdfb9f9, 0xf9efbe8e, 0x43beb717, 0xd58eb060, + 0xe8a3d6d6, 0x7e93d1a1, 0xc4c2d838, 0x52f2df4f, 0xf167bbd1, + 0x6757bca6, 0xdd06b53f, 0x4b36b248, 0xda2b0dd8, 0x4c1b0aaf, + 0xf64a0336, 0x607a0441, 0xc3ef60df, 0x55df67a8, 0xef8e6e31, + 0x79be6946, 0x8cb361cb, 0x1a8366bc, 0xa0d26f25, 0x36e26852, + 0x95770ccc, 0x03470bbb, 0xb9160222, 0x2f260555, 0xbe3bbac5, + 0x280bbdb2, 0x925ab42b, 0x046ab35c, 0xa7ffd7c2, 0x31cfd0b5, + 0x8b9ed92c, 0x1daede5b, 0xb0c2649b, 0x26f263ec, 0x9ca36a75, + 0x0a936d02, 0xa906099c, 0x3f360eeb, 0x85670772, 0x13570005, + 0x824abf95, 0x147ab8e2, 0xae2bb17b, 0x381bb60c, 0x9b8ed292, + 0x0dbed5e5, 0xb7efdc7c, 0x21dfdb0b, 0xd4d2d386, 0x42e2d4f1, + 0xf8b3dd68, 0x6e83da1f, 0xcd16be81, 0x5b26b9f6, 0xe177b06f, + 0x7747b718, 0xe65a0888, 0x706a0fff, 0xca3b0666, 0x5c0b0111, + 0xff9e658f, 0x69ae62f8, 0xd3ff6b61, 0x45cf6c16, 0x78e20aa0, + 0xeed20dd7, 0x5483044e, 0xc2b30339, 0x612667a7, 0xf71660d0, + 0x4d476949, 0xdb776e3e, 0x4a6ad1ae, 0xdc5ad6d9, 0x660bdf40, + 0xf03bd837, 0x53aebca9, 0xc59ebbde, 0x7fcfb247, 0xe9ffb530, + 0x1cf2bdbd, 0x8ac2baca, 0x3093b353, 0xa6a3b424, 0x0536d0ba, + 0x9306d7cd, 0x2957de54, 0xbf67d923, 0x2e7a66b3, 0xb84a61c4, + 0x021b685d, 0x942b6f2a, 0x37be0bb4, 0xa18e0cc3, 0x1bdf055a, + 0x8def022d}, + {0x00000000, 0x41311b19, 0x82623632, 0xc3532d2b, 0x04c56c64, + 0x45f4777d, 0x86a75a56, 0xc796414f, 0x088ad9c8, 0x49bbc2d1, + 0x8ae8effa, 0xcbd9f4e3, 0x0c4fb5ac, 0x4d7eaeb5, 0x8e2d839e, + 0xcf1c9887, 0x5112c24a, 0x1023d953, 0xd370f478, 0x9241ef61, + 0x55d7ae2e, 0x14e6b537, 0xd7b5981c, 0x96848305, 0x59981b82, + 0x18a9009b, 0xdbfa2db0, 0x9acb36a9, 0x5d5d77e6, 0x1c6c6cff, + 0xdf3f41d4, 0x9e0e5acd, 0xa2248495, 0xe3159f8c, 0x2046b2a7, + 0x6177a9be, 0xa6e1e8f1, 0xe7d0f3e8, 0x2483dec3, 0x65b2c5da, + 0xaaae5d5d, 0xeb9f4644, 0x28cc6b6f, 0x69fd7076, 0xae6b3139, + 0xef5a2a20, 0x2c09070b, 0x6d381c12, 0xf33646df, 0xb2075dc6, + 0x715470ed, 0x30656bf4, 0xf7f32abb, 0xb6c231a2, 0x75911c89, + 0x34a00790, 0xfbbc9f17, 0xba8d840e, 0x79dea925, 0x38efb23c, + 0xff79f373, 0xbe48e86a, 0x7d1bc541, 0x3c2ade58, 0x054f79f0, + 0x447e62e9, 0x872d4fc2, 0xc61c54db, 0x018a1594, 0x40bb0e8d, + 0x83e823a6, 0xc2d938bf, 0x0dc5a038, 0x4cf4bb21, 0x8fa7960a, + 0xce968d13, 0x0900cc5c, 0x4831d745, 0x8b62fa6e, 0xca53e177, + 0x545dbbba, 0x156ca0a3, 0xd63f8d88, 0x970e9691, 0x5098d7de, + 0x11a9ccc7, 0xd2fae1ec, 0x93cbfaf5, 0x5cd76272, 0x1de6796b, + 0xdeb55440, 0x9f844f59, 0x58120e16, 0x1923150f, 0xda703824, + 0x9b41233d, 0xa76bfd65, 0xe65ae67c, 0x2509cb57, 0x6438d04e, + 0xa3ae9101, 0xe29f8a18, 0x21cca733, 0x60fdbc2a, 0xafe124ad, + 0xeed03fb4, 0x2d83129f, 0x6cb20986, 0xab2448c9, 0xea1553d0, + 0x29467efb, 0x687765e2, 0xf6793f2f, 0xb7482436, 0x741b091d, + 0x352a1204, 0xf2bc534b, 0xb38d4852, 0x70de6579, 0x31ef7e60, + 0xfef3e6e7, 0xbfc2fdfe, 0x7c91d0d5, 0x3da0cbcc, 0xfa368a83, + 0xbb07919a, 0x7854bcb1, 0x3965a7a8, 0x4b98833b, 0x0aa99822, + 0xc9fab509, 0x88cbae10, 0x4f5def5f, 0x0e6cf446, 0xcd3fd96d, + 0x8c0ec274, 0x43125af3, 0x022341ea, 0xc1706cc1, 0x804177d8, + 0x47d73697, 0x06e62d8e, 0xc5b500a5, 0x84841bbc, 0x1a8a4171, + 0x5bbb5a68, 0x98e87743, 0xd9d96c5a, 0x1e4f2d15, 0x5f7e360c, + 0x9c2d1b27, 0xdd1c003e, 0x120098b9, 0x533183a0, 0x9062ae8b, + 0xd153b592, 0x16c5f4dd, 0x57f4efc4, 0x94a7c2ef, 0xd596d9f6, + 0xe9bc07ae, 0xa88d1cb7, 0x6bde319c, 0x2aef2a85, 0xed796bca, + 0xac4870d3, 0x6f1b5df8, 0x2e2a46e1, 0xe136de66, 0xa007c57f, + 0x6354e854, 0x2265f34d, 0xe5f3b202, 0xa4c2a91b, 0x67918430, + 0x26a09f29, 0xb8aec5e4, 0xf99fdefd, 0x3accf3d6, 0x7bfde8cf, + 0xbc6ba980, 0xfd5ab299, 0x3e099fb2, 0x7f3884ab, 0xb0241c2c, + 0xf1150735, 0x32462a1e, 0x73773107, 0xb4e17048, 0xf5d06b51, + 0x3683467a, 0x77b25d63, 0x4ed7facb, 0x0fe6e1d2, 0xccb5ccf9, + 0x8d84d7e0, 0x4a1296af, 0x0b238db6, 0xc870a09d, 0x8941bb84, + 0x465d2303, 0x076c381a, 0xc43f1531, 0x850e0e28, 0x42984f67, + 0x03a9547e, 0xc0fa7955, 0x81cb624c, 0x1fc53881, 0x5ef42398, + 0x9da70eb3, 0xdc9615aa, 0x1b0054e5, 0x5a314ffc, 0x996262d7, + 0xd85379ce, 0x174fe149, 0x567efa50, 0x952dd77b, 0xd41ccc62, + 0x138a8d2d, 0x52bb9634, 0x91e8bb1f, 0xd0d9a006, 0xecf37e5e, + 0xadc26547, 0x6e91486c, 0x2fa05375, 0xe836123a, 0xa9070923, + 0x6a542408, 0x2b653f11, 0xe479a796, 0xa548bc8f, 0x661b91a4, + 0x272a8abd, 0xe0bccbf2, 0xa18dd0eb, 0x62defdc0, 0x23efe6d9, + 0xbde1bc14, 0xfcd0a70d, 0x3f838a26, 0x7eb2913f, 0xb924d070, + 0xf815cb69, 0x3b46e642, 0x7a77fd5b, 0xb56b65dc, 0xf45a7ec5, + 0x370953ee, 0x763848f7, 0xb1ae09b8, 0xf09f12a1, 0x33cc3f8a, + 0x72fd2493}, + {0x00000000, 0x376ac201, 0x6ed48403, 0x59be4602, 0xdca80907, + 0xebc2cb06, 0xb27c8d04, 0x85164f05, 0xb851130e, 0x8f3bd10f, + 0xd685970d, 0xe1ef550c, 0x64f91a09, 0x5393d808, 0x0a2d9e0a, + 0x3d475c0b, 0x70a3261c, 0x47c9e41d, 0x1e77a21f, 0x291d601e, + 0xac0b2f1b, 0x9b61ed1a, 0xc2dfab18, 0xf5b56919, 0xc8f23512, + 0xff98f713, 0xa626b111, 0x914c7310, 0x145a3c15, 0x2330fe14, + 0x7a8eb816, 0x4de47a17, 0xe0464d38, 0xd72c8f39, 0x8e92c93b, + 0xb9f80b3a, 0x3cee443f, 0x0b84863e, 0x523ac03c, 0x6550023d, + 0x58175e36, 0x6f7d9c37, 0x36c3da35, 0x01a91834, 0x84bf5731, + 0xb3d59530, 0xea6bd332, 0xdd011133, 0x90e56b24, 0xa78fa925, + 0xfe31ef27, 0xc95b2d26, 0x4c4d6223, 0x7b27a022, 0x2299e620, + 0x15f32421, 0x28b4782a, 0x1fdeba2b, 0x4660fc29, 0x710a3e28, + 0xf41c712d, 0xc376b32c, 0x9ac8f52e, 0xada2372f, 0xc08d9a70, + 0xf7e75871, 0xae591e73, 0x9933dc72, 0x1c259377, 0x2b4f5176, + 0x72f11774, 0x459bd575, 0x78dc897e, 0x4fb64b7f, 0x16080d7d, + 0x2162cf7c, 0xa4748079, 0x931e4278, 0xcaa0047a, 0xfdcac67b, + 0xb02ebc6c, 0x87447e6d, 0xdefa386f, 0xe990fa6e, 0x6c86b56b, + 0x5bec776a, 0x02523168, 0x3538f369, 0x087faf62, 0x3f156d63, + 0x66ab2b61, 0x51c1e960, 0xd4d7a665, 0xe3bd6464, 0xba032266, + 0x8d69e067, 0x20cbd748, 0x17a11549, 0x4e1f534b, 0x7975914a, + 0xfc63de4f, 0xcb091c4e, 0x92b75a4c, 0xa5dd984d, 0x989ac446, + 0xaff00647, 0xf64e4045, 0xc1248244, 0x4432cd41, 0x73580f40, + 0x2ae64942, 0x1d8c8b43, 0x5068f154, 0x67023355, 0x3ebc7557, + 0x09d6b756, 0x8cc0f853, 0xbbaa3a52, 0xe2147c50, 0xd57ebe51, + 0xe839e25a, 0xdf53205b, 0x86ed6659, 0xb187a458, 0x3491eb5d, + 0x03fb295c, 0x5a456f5e, 0x6d2fad5f, 0x801b35e1, 0xb771f7e0, + 0xeecfb1e2, 0xd9a573e3, 0x5cb33ce6, 0x6bd9fee7, 0x3267b8e5, + 0x050d7ae4, 0x384a26ef, 0x0f20e4ee, 0x569ea2ec, 0x61f460ed, + 0xe4e22fe8, 0xd388ede9, 0x8a36abeb, 0xbd5c69ea, 0xf0b813fd, + 0xc7d2d1fc, 0x9e6c97fe, 0xa90655ff, 0x2c101afa, 0x1b7ad8fb, + 0x42c49ef9, 0x75ae5cf8, 0x48e900f3, 0x7f83c2f2, 0x263d84f0, + 0x115746f1, 0x944109f4, 0xa32bcbf5, 0xfa958df7, 0xcdff4ff6, + 0x605d78d9, 0x5737bad8, 0x0e89fcda, 0x39e33edb, 0xbcf571de, + 0x8b9fb3df, 0xd221f5dd, 0xe54b37dc, 0xd80c6bd7, 0xef66a9d6, + 0xb6d8efd4, 0x81b22dd5, 0x04a462d0, 0x33cea0d1, 0x6a70e6d3, + 0x5d1a24d2, 0x10fe5ec5, 0x27949cc4, 0x7e2adac6, 0x494018c7, + 0xcc5657c2, 0xfb3c95c3, 0xa282d3c1, 0x95e811c0, 0xa8af4dcb, + 0x9fc58fca, 0xc67bc9c8, 0xf1110bc9, 0x740744cc, 0x436d86cd, + 0x1ad3c0cf, 0x2db902ce, 0x4096af91, 0x77fc6d90, 0x2e422b92, + 0x1928e993, 0x9c3ea696, 0xab546497, 0xf2ea2295, 0xc580e094, + 0xf8c7bc9f, 0xcfad7e9e, 0x9613389c, 0xa179fa9d, 0x246fb598, + 0x13057799, 0x4abb319b, 0x7dd1f39a, 0x3035898d, 0x075f4b8c, + 0x5ee10d8e, 0x698bcf8f, 0xec9d808a, 0xdbf7428b, 0x82490489, + 0xb523c688, 0x88649a83, 0xbf0e5882, 0xe6b01e80, 0xd1dadc81, + 0x54cc9384, 0x63a65185, 0x3a181787, 0x0d72d586, 0xa0d0e2a9, + 0x97ba20a8, 0xce0466aa, 0xf96ea4ab, 0x7c78ebae, 0x4b1229af, + 0x12ac6fad, 0x25c6adac, 0x1881f1a7, 0x2feb33a6, 0x765575a4, + 0x413fb7a5, 0xc429f8a0, 0xf3433aa1, 0xaafd7ca3, 0x9d97bea2, + 0xd073c4b5, 0xe71906b4, 0xbea740b6, 0x89cd82b7, 0x0cdbcdb2, + 0x3bb10fb3, 0x620f49b1, 0x55658bb0, 0x6822d7bb, 0x5f4815ba, + 0x06f653b8, 0x319c91b9, 0xb48adebc, 0x83e01cbd, 0xda5e5abf, + 0xed3498be}, + {0x00000000, 0x6567bcb8, 0x8bc809aa, 0xeeafb512, 0x5797628f, + 0x32f0de37, 0xdc5f6b25, 0xb938d79d, 0xef28b4c5, 0x8a4f087d, + 0x64e0bd6f, 0x018701d7, 0xb8bfd64a, 0xddd86af2, 0x3377dfe0, + 0x56106358, 0x9f571950, 0xfa30a5e8, 0x149f10fa, 0x71f8ac42, + 0xc8c07bdf, 0xada7c767, 0x43087275, 0x266fcecd, 0x707fad95, + 0x1518112d, 0xfbb7a43f, 0x9ed01887, 0x27e8cf1a, 0x428f73a2, + 0xac20c6b0, 0xc9477a08, 0x3eaf32a0, 0x5bc88e18, 0xb5673b0a, + 0xd00087b2, 0x6938502f, 0x0c5fec97, 0xe2f05985, 0x8797e53d, + 0xd1878665, 0xb4e03add, 0x5a4f8fcf, 0x3f283377, 0x8610e4ea, + 0xe3775852, 0x0dd8ed40, 0x68bf51f8, 0xa1f82bf0, 0xc49f9748, + 0x2a30225a, 0x4f579ee2, 0xf66f497f, 0x9308f5c7, 0x7da740d5, + 0x18c0fc6d, 0x4ed09f35, 0x2bb7238d, 0xc518969f, 0xa07f2a27, + 0x1947fdba, 0x7c204102, 0x928ff410, 0xf7e848a8, 0x3d58149b, + 0x583fa823, 0xb6901d31, 0xd3f7a189, 0x6acf7614, 0x0fa8caac, + 0xe1077fbe, 0x8460c306, 0xd270a05e, 0xb7171ce6, 0x59b8a9f4, + 0x3cdf154c, 0x85e7c2d1, 0xe0807e69, 0x0e2fcb7b, 0x6b4877c3, + 0xa20f0dcb, 0xc768b173, 0x29c70461, 0x4ca0b8d9, 0xf5986f44, + 0x90ffd3fc, 0x7e5066ee, 0x1b37da56, 0x4d27b90e, 0x284005b6, + 0xc6efb0a4, 0xa3880c1c, 0x1ab0db81, 0x7fd76739, 0x9178d22b, + 0xf41f6e93, 0x03f7263b, 0x66909a83, 0x883f2f91, 0xed589329, + 0x546044b4, 0x3107f80c, 0xdfa84d1e, 0xbacff1a6, 0xecdf92fe, + 0x89b82e46, 0x67179b54, 0x027027ec, 0xbb48f071, 0xde2f4cc9, + 0x3080f9db, 0x55e74563, 0x9ca03f6b, 0xf9c783d3, 0x176836c1, + 0x720f8a79, 0xcb375de4, 0xae50e15c, 0x40ff544e, 0x2598e8f6, + 0x73888bae, 0x16ef3716, 0xf8408204, 0x9d273ebc, 0x241fe921, + 0x41785599, 0xafd7e08b, 0xcab05c33, 0x3bb659ed, 0x5ed1e555, + 0xb07e5047, 0xd519ecff, 0x6c213b62, 0x094687da, 0xe7e932c8, + 0x828e8e70, 0xd49eed28, 0xb1f95190, 0x5f56e482, 0x3a31583a, + 0x83098fa7, 0xe66e331f, 0x08c1860d, 0x6da63ab5, 0xa4e140bd, + 0xc186fc05, 0x2f294917, 0x4a4ef5af, 0xf3762232, 0x96119e8a, + 0x78be2b98, 0x1dd99720, 0x4bc9f478, 0x2eae48c0, 0xc001fdd2, + 0xa566416a, 0x1c5e96f7, 0x79392a4f, 0x97969f5d, 0xf2f123e5, + 0x05196b4d, 0x607ed7f5, 0x8ed162e7, 0xebb6de5f, 0x528e09c2, + 0x37e9b57a, 0xd9460068, 0xbc21bcd0, 0xea31df88, 0x8f566330, + 0x61f9d622, 0x049e6a9a, 0xbda6bd07, 0xd8c101bf, 0x366eb4ad, + 0x53090815, 0x9a4e721d, 0xff29cea5, 0x11867bb7, 0x74e1c70f, + 0xcdd91092, 0xa8beac2a, 0x46111938, 0x2376a580, 0x7566c6d8, + 0x10017a60, 0xfeaecf72, 0x9bc973ca, 0x22f1a457, 0x479618ef, + 0xa939adfd, 0xcc5e1145, 0x06ee4d76, 0x6389f1ce, 0x8d2644dc, + 0xe841f864, 0x51792ff9, 0x341e9341, 0xdab12653, 0xbfd69aeb, + 0xe9c6f9b3, 0x8ca1450b, 0x620ef019, 0x07694ca1, 0xbe519b3c, + 0xdb362784, 0x35999296, 0x50fe2e2e, 0x99b95426, 0xfcdee89e, + 0x12715d8c, 0x7716e134, 0xce2e36a9, 0xab498a11, 0x45e63f03, + 0x208183bb, 0x7691e0e3, 0x13f65c5b, 0xfd59e949, 0x983e55f1, + 0x2106826c, 0x44613ed4, 0xaace8bc6, 0xcfa9377e, 0x38417fd6, + 0x5d26c36e, 0xb389767c, 0xd6eecac4, 0x6fd61d59, 0x0ab1a1e1, + 0xe41e14f3, 0x8179a84b, 0xd769cb13, 0xb20e77ab, 0x5ca1c2b9, + 0x39c67e01, 0x80fea99c, 0xe5991524, 0x0b36a036, 0x6e511c8e, + 0xa7166686, 0xc271da3e, 0x2cde6f2c, 0x49b9d394, 0xf0810409, + 0x95e6b8b1, 0x7b490da3, 0x1e2eb11b, 0x483ed243, 0x2d596efb, + 0xc3f6dbe9, 0xa6916751, 0x1fa9b0cc, 0x7ace0c74, 0x9461b966, + 0xf10605de}}; + +#endif + +#endif + +#if N == 2 + +#if W == 8 + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0xae689191, 0x87a02563, 0x29c8b4f2, 0xd4314c87, + 0x7a59dd16, 0x539169e4, 0xfdf9f875, 0x73139f4f, 0xdd7b0ede, + 0xf4b3ba2c, 0x5adb2bbd, 0xa722d3c8, 0x094a4259, 0x2082f6ab, + 0x8eea673a, 0xe6273e9e, 0x484faf0f, 0x61871bfd, 0xcfef8a6c, + 0x32167219, 0x9c7ee388, 0xb5b6577a, 0x1bdec6eb, 0x9534a1d1, + 0x3b5c3040, 0x129484b2, 0xbcfc1523, 0x4105ed56, 0xef6d7cc7, + 0xc6a5c835, 0x68cd59a4, 0x173f7b7d, 0xb957eaec, 0x909f5e1e, + 0x3ef7cf8f, 0xc30e37fa, 0x6d66a66b, 0x44ae1299, 0xeac68308, + 0x642ce432, 0xca4475a3, 0xe38cc151, 0x4de450c0, 0xb01da8b5, + 0x1e753924, 0x37bd8dd6, 0x99d51c47, 0xf11845e3, 0x5f70d472, + 0x76b86080, 0xd8d0f111, 0x25290964, 0x8b4198f5, 0xa2892c07, + 0x0ce1bd96, 0x820bdaac, 0x2c634b3d, 0x05abffcf, 0xabc36e5e, + 0x563a962b, 0xf85207ba, 0xd19ab348, 0x7ff222d9, 0x2e7ef6fa, + 0x8016676b, 0xa9ded399, 0x07b64208, 0xfa4fba7d, 0x54272bec, + 0x7def9f1e, 0xd3870e8f, 0x5d6d69b5, 0xf305f824, 0xdacd4cd6, + 0x74a5dd47, 0x895c2532, 0x2734b4a3, 0x0efc0051, 0xa09491c0, + 0xc859c864, 0x663159f5, 0x4ff9ed07, 0xe1917c96, 0x1c6884e3, + 0xb2001572, 0x9bc8a180, 0x35a03011, 0xbb4a572b, 0x1522c6ba, + 0x3cea7248, 0x9282e3d9, 0x6f7b1bac, 0xc1138a3d, 0xe8db3ecf, + 0x46b3af5e, 0x39418d87, 0x97291c16, 0xbee1a8e4, 0x10893975, + 0xed70c100, 0x43185091, 0x6ad0e463, 0xc4b875f2, 0x4a5212c8, + 0xe43a8359, 0xcdf237ab, 0x639aa63a, 0x9e635e4f, 0x300bcfde, + 0x19c37b2c, 0xb7abeabd, 0xdf66b319, 0x710e2288, 0x58c6967a, + 0xf6ae07eb, 0x0b57ff9e, 0xa53f6e0f, 0x8cf7dafd, 0x229f4b6c, + 0xac752c56, 0x021dbdc7, 0x2bd50935, 0x85bd98a4, 0x784460d1, + 0xd62cf140, 0xffe445b2, 0x518cd423, 0x5cfdedf4, 0xf2957c65, + 0xdb5dc897, 0x75355906, 0x88cca173, 0x26a430e2, 0x0f6c8410, + 0xa1041581, 0x2fee72bb, 0x8186e32a, 0xa84e57d8, 0x0626c649, + 0xfbdf3e3c, 0x55b7afad, 0x7c7f1b5f, 0xd2178ace, 0xbadad36a, + 0x14b242fb, 0x3d7af609, 0x93126798, 0x6eeb9fed, 0xc0830e7c, + 0xe94bba8e, 0x47232b1f, 0xc9c94c25, 0x67a1ddb4, 0x4e696946, + 0xe001f8d7, 0x1df800a2, 0xb3909133, 0x9a5825c1, 0x3430b450, + 0x4bc29689, 0xe5aa0718, 0xcc62b3ea, 0x620a227b, 0x9ff3da0e, + 0x319b4b9f, 0x1853ff6d, 0xb63b6efc, 0x38d109c6, 0x96b99857, + 0xbf712ca5, 0x1119bd34, 0xece04541, 0x4288d4d0, 0x6b406022, + 0xc528f1b3, 0xade5a817, 0x038d3986, 0x2a458d74, 0x842d1ce5, + 0x79d4e490, 0xd7bc7501, 0xfe74c1f3, 0x501c5062, 0xdef63758, + 0x709ea6c9, 0x5956123b, 0xf73e83aa, 0x0ac77bdf, 0xa4afea4e, + 0x8d675ebc, 0x230fcf2d, 0x72831b0e, 0xdceb8a9f, 0xf5233e6d, + 0x5b4baffc, 0xa6b25789, 0x08dac618, 0x211272ea, 0x8f7ae37b, + 0x01908441, 0xaff815d0, 0x8630a122, 0x285830b3, 0xd5a1c8c6, + 0x7bc95957, 0x5201eda5, 0xfc697c34, 0x94a42590, 0x3accb401, + 0x130400f3, 0xbd6c9162, 0x40956917, 0xeefdf886, 0xc7354c74, + 0x695ddde5, 0xe7b7badf, 0x49df2b4e, 0x60179fbc, 0xce7f0e2d, + 0x3386f658, 0x9dee67c9, 0xb426d33b, 0x1a4e42aa, 0x65bc6073, + 0xcbd4f1e2, 0xe21c4510, 0x4c74d481, 0xb18d2cf4, 0x1fe5bd65, + 0x362d0997, 0x98459806, 0x16afff3c, 0xb8c76ead, 0x910fda5f, + 0x3f674bce, 0xc29eb3bb, 0x6cf6222a, 0x453e96d8, 0xeb560749, + 0x839b5eed, 0x2df3cf7c, 0x043b7b8e, 0xaa53ea1f, 0x57aa126a, + 0xf9c283fb, 0xd00a3709, 0x7e62a698, 0xf088c1a2, 0x5ee05033, + 0x7728e4c1, 0xd9407550, 0x24b98d25, 0x8ad11cb4, 0xa319a846, + 0x0d7139d7}, + {0x00000000, 0xb9fbdbe8, 0xa886b191, 0x117d6a79, 0x8a7c6563, + 0x3387be8b, 0x22fad4f2, 0x9b010f1a, 0xcf89cc87, 0x7672176f, + 0x670f7d16, 0xdef4a6fe, 0x45f5a9e4, 0xfc0e720c, 0xed731875, + 0x5488c39d, 0x44629f4f, 0xfd9944a7, 0xece42ede, 0x551ff536, + 0xce1efa2c, 0x77e521c4, 0x66984bbd, 0xdf639055, 0x8beb53c8, + 0x32108820, 0x236de259, 0x9a9639b1, 0x019736ab, 0xb86ced43, + 0xa911873a, 0x10ea5cd2, 0x88c53e9e, 0x313ee576, 0x20438f0f, + 0x99b854e7, 0x02b95bfd, 0xbb428015, 0xaa3fea6c, 0x13c43184, + 0x474cf219, 0xfeb729f1, 0xefca4388, 0x56319860, 0xcd30977a, + 0x74cb4c92, 0x65b626eb, 0xdc4dfd03, 0xcca7a1d1, 0x755c7a39, + 0x64211040, 0xdddacba8, 0x46dbc4b2, 0xff201f5a, 0xee5d7523, + 0x57a6aecb, 0x032e6d56, 0xbad5b6be, 0xaba8dcc7, 0x1253072f, + 0x89520835, 0x30a9d3dd, 0x21d4b9a4, 0x982f624c, 0xcafb7b7d, + 0x7300a095, 0x627dcaec, 0xdb861104, 0x40871e1e, 0xf97cc5f6, + 0xe801af8f, 0x51fa7467, 0x0572b7fa, 0xbc896c12, 0xadf4066b, + 0x140fdd83, 0x8f0ed299, 0x36f50971, 0x27886308, 0x9e73b8e0, + 0x8e99e432, 0x37623fda, 0x261f55a3, 0x9fe48e4b, 0x04e58151, + 0xbd1e5ab9, 0xac6330c0, 0x1598eb28, 0x411028b5, 0xf8ebf35d, + 0xe9969924, 0x506d42cc, 0xcb6c4dd6, 0x7297963e, 0x63eafc47, + 0xda1127af, 0x423e45e3, 0xfbc59e0b, 0xeab8f472, 0x53432f9a, + 0xc8422080, 0x71b9fb68, 0x60c49111, 0xd93f4af9, 0x8db78964, + 0x344c528c, 0x253138f5, 0x9ccae31d, 0x07cbec07, 0xbe3037ef, + 0xaf4d5d96, 0x16b6867e, 0x065cdaac, 0xbfa70144, 0xaeda6b3d, + 0x1721b0d5, 0x8c20bfcf, 0x35db6427, 0x24a60e5e, 0x9d5dd5b6, + 0xc9d5162b, 0x702ecdc3, 0x6153a7ba, 0xd8a87c52, 0x43a97348, + 0xfa52a8a0, 0xeb2fc2d9, 0x52d41931, 0x4e87f0bb, 0xf77c2b53, + 0xe601412a, 0x5ffa9ac2, 0xc4fb95d8, 0x7d004e30, 0x6c7d2449, + 0xd586ffa1, 0x810e3c3c, 0x38f5e7d4, 0x29888dad, 0x90735645, + 0x0b72595f, 0xb28982b7, 0xa3f4e8ce, 0x1a0f3326, 0x0ae56ff4, + 0xb31eb41c, 0xa263de65, 0x1b98058d, 0x80990a97, 0x3962d17f, + 0x281fbb06, 0x91e460ee, 0xc56ca373, 0x7c97789b, 0x6dea12e2, + 0xd411c90a, 0x4f10c610, 0xf6eb1df8, 0xe7967781, 0x5e6dac69, + 0xc642ce25, 0x7fb915cd, 0x6ec47fb4, 0xd73fa45c, 0x4c3eab46, + 0xf5c570ae, 0xe4b81ad7, 0x5d43c13f, 0x09cb02a2, 0xb030d94a, + 0xa14db333, 0x18b668db, 0x83b767c1, 0x3a4cbc29, 0x2b31d650, + 0x92ca0db8, 0x8220516a, 0x3bdb8a82, 0x2aa6e0fb, 0x935d3b13, + 0x085c3409, 0xb1a7efe1, 0xa0da8598, 0x19215e70, 0x4da99ded, + 0xf4524605, 0xe52f2c7c, 0x5cd4f794, 0xc7d5f88e, 0x7e2e2366, + 0x6f53491f, 0xd6a892f7, 0x847c8bc6, 0x3d87502e, 0x2cfa3a57, + 0x9501e1bf, 0x0e00eea5, 0xb7fb354d, 0xa6865f34, 0x1f7d84dc, + 0x4bf54741, 0xf20e9ca9, 0xe373f6d0, 0x5a882d38, 0xc1892222, + 0x7872f9ca, 0x690f93b3, 0xd0f4485b, 0xc01e1489, 0x79e5cf61, + 0x6898a518, 0xd1637ef0, 0x4a6271ea, 0xf399aa02, 0xe2e4c07b, + 0x5b1f1b93, 0x0f97d80e, 0xb66c03e6, 0xa711699f, 0x1eeab277, + 0x85ebbd6d, 0x3c106685, 0x2d6d0cfc, 0x9496d714, 0x0cb9b558, + 0xb5426eb0, 0xa43f04c9, 0x1dc4df21, 0x86c5d03b, 0x3f3e0bd3, + 0x2e4361aa, 0x97b8ba42, 0xc33079df, 0x7acba237, 0x6bb6c84e, + 0xd24d13a6, 0x494c1cbc, 0xf0b7c754, 0xe1caad2d, 0x583176c5, + 0x48db2a17, 0xf120f1ff, 0xe05d9b86, 0x59a6406e, 0xc2a74f74, + 0x7b5c949c, 0x6a21fee5, 0xd3da250d, 0x8752e690, 0x3ea93d78, + 0x2fd45701, 0x962f8ce9, 0x0d2e83f3, 0xb4d5581b, 0xa5a83262, + 0x1c53e98a}, + {0x00000000, 0x9d0fe176, 0xe16ec4ad, 0x7c6125db, 0x19ac8f1b, + 0x84a36e6d, 0xf8c24bb6, 0x65cdaac0, 0x33591e36, 0xae56ff40, + 0xd237da9b, 0x4f383bed, 0x2af5912d, 0xb7fa705b, 0xcb9b5580, + 0x5694b4f6, 0x66b23c6c, 0xfbbddd1a, 0x87dcf8c1, 0x1ad319b7, + 0x7f1eb377, 0xe2115201, 0x9e7077da, 0x037f96ac, 0x55eb225a, + 0xc8e4c32c, 0xb485e6f7, 0x298a0781, 0x4c47ad41, 0xd1484c37, + 0xad2969ec, 0x3026889a, 0xcd6478d8, 0x506b99ae, 0x2c0abc75, + 0xb1055d03, 0xd4c8f7c3, 0x49c716b5, 0x35a6336e, 0xa8a9d218, + 0xfe3d66ee, 0x63328798, 0x1f53a243, 0x825c4335, 0xe791e9f5, + 0x7a9e0883, 0x06ff2d58, 0x9bf0cc2e, 0xabd644b4, 0x36d9a5c2, + 0x4ab88019, 0xd7b7616f, 0xb27acbaf, 0x2f752ad9, 0x53140f02, + 0xce1bee74, 0x988f5a82, 0x0580bbf4, 0x79e19e2f, 0xe4ee7f59, + 0x8123d599, 0x1c2c34ef, 0x604d1134, 0xfd42f042, 0x41b9f7f1, + 0xdcb61687, 0xa0d7335c, 0x3dd8d22a, 0x581578ea, 0xc51a999c, + 0xb97bbc47, 0x24745d31, 0x72e0e9c7, 0xefef08b1, 0x938e2d6a, + 0x0e81cc1c, 0x6b4c66dc, 0xf64387aa, 0x8a22a271, 0x172d4307, + 0x270bcb9d, 0xba042aeb, 0xc6650f30, 0x5b6aee46, 0x3ea74486, + 0xa3a8a5f0, 0xdfc9802b, 0x42c6615d, 0x1452d5ab, 0x895d34dd, + 0xf53c1106, 0x6833f070, 0x0dfe5ab0, 0x90f1bbc6, 0xec909e1d, + 0x719f7f6b, 0x8cdd8f29, 0x11d26e5f, 0x6db34b84, 0xf0bcaaf2, + 0x95710032, 0x087ee144, 0x741fc49f, 0xe91025e9, 0xbf84911f, + 0x228b7069, 0x5eea55b2, 0xc3e5b4c4, 0xa6281e04, 0x3b27ff72, + 0x4746daa9, 0xda493bdf, 0xea6fb345, 0x77605233, 0x0b0177e8, + 0x960e969e, 0xf3c33c5e, 0x6eccdd28, 0x12adf8f3, 0x8fa21985, + 0xd936ad73, 0x44394c05, 0x385869de, 0xa55788a8, 0xc09a2268, + 0x5d95c31e, 0x21f4e6c5, 0xbcfb07b3, 0x8373efe2, 0x1e7c0e94, + 0x621d2b4f, 0xff12ca39, 0x9adf60f9, 0x07d0818f, 0x7bb1a454, + 0xe6be4522, 0xb02af1d4, 0x2d2510a2, 0x51443579, 0xcc4bd40f, + 0xa9867ecf, 0x34899fb9, 0x48e8ba62, 0xd5e75b14, 0xe5c1d38e, + 0x78ce32f8, 0x04af1723, 0x99a0f655, 0xfc6d5c95, 0x6162bde3, + 0x1d039838, 0x800c794e, 0xd698cdb8, 0x4b972cce, 0x37f60915, + 0xaaf9e863, 0xcf3442a3, 0x523ba3d5, 0x2e5a860e, 0xb3556778, + 0x4e17973a, 0xd318764c, 0xaf795397, 0x3276b2e1, 0x57bb1821, + 0xcab4f957, 0xb6d5dc8c, 0x2bda3dfa, 0x7d4e890c, 0xe041687a, + 0x9c204da1, 0x012facd7, 0x64e20617, 0xf9ede761, 0x858cc2ba, + 0x188323cc, 0x28a5ab56, 0xb5aa4a20, 0xc9cb6ffb, 0x54c48e8d, + 0x3109244d, 0xac06c53b, 0xd067e0e0, 0x4d680196, 0x1bfcb560, + 0x86f35416, 0xfa9271cd, 0x679d90bb, 0x02503a7b, 0x9f5fdb0d, + 0xe33efed6, 0x7e311fa0, 0xc2ca1813, 0x5fc5f965, 0x23a4dcbe, + 0xbeab3dc8, 0xdb669708, 0x4669767e, 0x3a0853a5, 0xa707b2d3, + 0xf1930625, 0x6c9ce753, 0x10fdc288, 0x8df223fe, 0xe83f893e, + 0x75306848, 0x09514d93, 0x945eace5, 0xa478247f, 0x3977c509, + 0x4516e0d2, 0xd81901a4, 0xbdd4ab64, 0x20db4a12, 0x5cba6fc9, + 0xc1b58ebf, 0x97213a49, 0x0a2edb3f, 0x764ffee4, 0xeb401f92, + 0x8e8db552, 0x13825424, 0x6fe371ff, 0xf2ec9089, 0x0fae60cb, + 0x92a181bd, 0xeec0a466, 0x73cf4510, 0x1602efd0, 0x8b0d0ea6, + 0xf76c2b7d, 0x6a63ca0b, 0x3cf77efd, 0xa1f89f8b, 0xdd99ba50, + 0x40965b26, 0x255bf1e6, 0xb8541090, 0xc435354b, 0x593ad43d, + 0x691c5ca7, 0xf413bdd1, 0x8872980a, 0x157d797c, 0x70b0d3bc, + 0xedbf32ca, 0x91de1711, 0x0cd1f667, 0x5a454291, 0xc74aa3e7, + 0xbb2b863c, 0x2624674a, 0x43e9cd8a, 0xdee62cfc, 0xa2870927, + 0x3f88e851}, + {0x00000000, 0xdd96d985, 0x605cb54b, 0xbdca6cce, 0xc0b96a96, + 0x1d2fb313, 0xa0e5dfdd, 0x7d730658, 0x5a03d36d, 0x87950ae8, + 0x3a5f6626, 0xe7c9bfa3, 0x9abab9fb, 0x472c607e, 0xfae60cb0, + 0x2770d535, 0xb407a6da, 0x69917f5f, 0xd45b1391, 0x09cdca14, + 0x74becc4c, 0xa92815c9, 0x14e27907, 0xc974a082, 0xee0475b7, + 0x3392ac32, 0x8e58c0fc, 0x53ce1979, 0x2ebd1f21, 0xf32bc6a4, + 0x4ee1aa6a, 0x937773ef, 0xb37e4bf5, 0x6ee89270, 0xd322febe, + 0x0eb4273b, 0x73c72163, 0xae51f8e6, 0x139b9428, 0xce0d4dad, + 0xe97d9898, 0x34eb411d, 0x89212dd3, 0x54b7f456, 0x29c4f20e, + 0xf4522b8b, 0x49984745, 0x940e9ec0, 0x0779ed2f, 0xdaef34aa, + 0x67255864, 0xbab381e1, 0xc7c087b9, 0x1a565e3c, 0xa79c32f2, + 0x7a0aeb77, 0x5d7a3e42, 0x80ece7c7, 0x3d268b09, 0xe0b0528c, + 0x9dc354d4, 0x40558d51, 0xfd9fe19f, 0x2009381a, 0xbd8d91ab, + 0x601b482e, 0xddd124e0, 0x0047fd65, 0x7d34fb3d, 0xa0a222b8, + 0x1d684e76, 0xc0fe97f3, 0xe78e42c6, 0x3a189b43, 0x87d2f78d, + 0x5a442e08, 0x27372850, 0xfaa1f1d5, 0x476b9d1b, 0x9afd449e, + 0x098a3771, 0xd41ceef4, 0x69d6823a, 0xb4405bbf, 0xc9335de7, + 0x14a58462, 0xa96fe8ac, 0x74f93129, 0x5389e41c, 0x8e1f3d99, + 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0xedf0b03f, 0x2c7e6fff, + 0x05457a7c, 0xc4cba5bc, 0x5d29c3bd, 0x9ca71c7d, 0x2735a3a7, + 0xe6bb7c67, 0x7f591a66, 0xbed7c5a6, 0x97ecd025, 0x56620fe5, + 0xcf8069e4, 0x0e0eb624, 0x9df642e2, 0x5c789d22, 0xc59afb23, + 0x041424e3, 0x2d2f3160, 0xeca1eea0, 0x754388a1, 0xb4cd5761, + 0x89c3676c, 0x484db8ac, 0xd1afdead, 0x1021016d, 0x391a14ee, + 0xf894cb2e, 0x6176ad2f, 0xa0f872ef, 0x33008629, 0xf28e59e9, + 0x6b6c3fe8, 0xaae2e028, 0x83d9f5ab, 0x42572a6b, 0xdbb54c6a, + 0x1a3b93aa}, + {0x00000000, 0xefc26b3e, 0x04f5d03d, 0xeb37bb03, 0x09eba07a, + 0xe629cb44, 0x0d1e7047, 0xe2dc1b79, 0x13d740f4, 0xfc152bca, + 0x172290c9, 0xf8e0fbf7, 0x1a3ce08e, 0xf5fe8bb0, 0x1ec930b3, + 0xf10b5b8d, 0x27ae81e8, 0xc86cead6, 0x235b51d5, 0xcc993aeb, + 0x2e452192, 0xc1874aac, 0x2ab0f1af, 0xc5729a91, 0x3479c11c, + 0xdbbbaa22, 0x308c1121, 0xdf4e7a1f, 0x3d926166, 0xd2500a58, + 0x3967b15b, 0xd6a5da65, 0x4f5d03d0, 0xa09f68ee, 0x4ba8d3ed, + 0xa46ab8d3, 0x46b6a3aa, 0xa974c894, 0x42437397, 0xad8118a9, + 0x5c8a4324, 0xb348281a, 0x587f9319, 0xb7bdf827, 0x5561e35e, + 0xbaa38860, 0x51943363, 0xbe56585d, 0x68f38238, 0x8731e906, + 0x6c065205, 0x83c4393b, 0x61182242, 0x8eda497c, 0x65edf27f, + 0x8a2f9941, 0x7b24c2cc, 0x94e6a9f2, 0x7fd112f1, 0x901379cf, + 0x72cf62b6, 0x9d0d0988, 0x763ab28b, 0x99f8d9b5, 0x9eba07a0, + 0x71786c9e, 0x9a4fd79d, 0x758dbca3, 0x9751a7da, 0x7893cce4, + 0x93a477e7, 0x7c661cd9, 0x8d6d4754, 0x62af2c6a, 0x89989769, + 0x665afc57, 0x8486e72e, 0x6b448c10, 0x80733713, 0x6fb15c2d, + 0xb9148648, 0x56d6ed76, 0xbde15675, 0x52233d4b, 0xb0ff2632, + 0x5f3d4d0c, 0xb40af60f, 0x5bc89d31, 0xaac3c6bc, 0x4501ad82, + 0xae361681, 0x41f47dbf, 0xa32866c6, 0x4cea0df8, 0xa7ddb6fb, + 0x481fddc5, 0xd1e70470, 0x3e256f4e, 0xd512d44d, 0x3ad0bf73, + 0xd80ca40a, 0x37cecf34, 0xdcf97437, 0x333b1f09, 0xc2304484, + 0x2df22fba, 0xc6c594b9, 0x2907ff87, 0xcbdbe4fe, 0x24198fc0, + 0xcf2e34c3, 0x20ec5ffd, 0xf6498598, 0x198beea6, 0xf2bc55a5, + 0x1d7e3e9b, 0xffa225e2, 0x10604edc, 0xfb57f5df, 0x14959ee1, + 0xe59ec56c, 0x0a5cae52, 0xe16b1551, 0x0ea97e6f, 0xec756516, + 0x03b70e28, 0xe880b52b, 0x0742de15, 0xe6050901, 0x09c7623f, + 0xe2f0d93c, 0x0d32b202, 0xefeea97b, 0x002cc245, 0xeb1b7946, + 0x04d91278, 0xf5d249f5, 0x1a1022cb, 0xf12799c8, 0x1ee5f2f6, + 0xfc39e98f, 0x13fb82b1, 0xf8cc39b2, 0x170e528c, 0xc1ab88e9, + 0x2e69e3d7, 0xc55e58d4, 0x2a9c33ea, 0xc8402893, 0x278243ad, + 0xccb5f8ae, 0x23779390, 0xd27cc81d, 0x3dbea323, 0xd6891820, + 0x394b731e, 0xdb976867, 0x34550359, 0xdf62b85a, 0x30a0d364, + 0xa9580ad1, 0x469a61ef, 0xadaddaec, 0x426fb1d2, 0xa0b3aaab, + 0x4f71c195, 0xa4467a96, 0x4b8411a8, 0xba8f4a25, 0x554d211b, + 0xbe7a9a18, 0x51b8f126, 0xb364ea5f, 0x5ca68161, 0xb7913a62, + 0x5853515c, 0x8ef68b39, 0x6134e007, 0x8a035b04, 0x65c1303a, + 0x871d2b43, 0x68df407d, 0x83e8fb7e, 0x6c2a9040, 0x9d21cbcd, + 0x72e3a0f3, 0x99d41bf0, 0x761670ce, 0x94ca6bb7, 0x7b080089, + 0x903fbb8a, 0x7ffdd0b4, 0x78bf0ea1, 0x977d659f, 0x7c4ade9c, + 0x9388b5a2, 0x7154aedb, 0x9e96c5e5, 0x75a17ee6, 0x9a6315d8, + 0x6b684e55, 0x84aa256b, 0x6f9d9e68, 0x805ff556, 0x6283ee2f, + 0x8d418511, 0x66763e12, 0x89b4552c, 0x5f118f49, 0xb0d3e477, + 0x5be45f74, 0xb426344a, 0x56fa2f33, 0xb938440d, 0x520fff0e, + 0xbdcd9430, 0x4cc6cfbd, 0xa304a483, 0x48331f80, 0xa7f174be, + 0x452d6fc7, 0xaaef04f9, 0x41d8bffa, 0xae1ad4c4, 0x37e20d71, + 0xd820664f, 0x3317dd4c, 0xdcd5b672, 0x3e09ad0b, 0xd1cbc635, + 0x3afc7d36, 0xd53e1608, 0x24354d85, 0xcbf726bb, 0x20c09db8, + 0xcf02f686, 0x2ddeedff, 0xc21c86c1, 0x292b3dc2, 0xc6e956fc, + 0x104c8c99, 0xff8ee7a7, 0x14b95ca4, 0xfb7b379a, 0x19a72ce3, + 0xf66547dd, 0x1d52fcde, 0xf29097e0, 0x039bcc6d, 0xec59a753, + 0x076e1c50, 0xe8ac776e, 0x0a706c17, 0xe5b20729, 0x0e85bc2a, + 0xe147d714}, + {0x00000000, 0x177b1443, 0x2ef62886, 0x398d3cc5, 0x5dec510c, + 0x4a97454f, 0x731a798a, 0x64616dc9, 0xbbd8a218, 0xaca3b65b, + 0x952e8a9e, 0x82559edd, 0xe634f314, 0xf14fe757, 0xc8c2db92, + 0xdfb9cfd1, 0xacc04271, 0xbbbb5632, 0x82366af7, 0x954d7eb4, + 0xf12c137d, 0xe657073e, 0xdfda3bfb, 0xc8a12fb8, 0x1718e069, + 0x0063f42a, 0x39eec8ef, 0x2e95dcac, 0x4af4b165, 0x5d8fa526, + 0x640299e3, 0x73798da0, 0x82f182a3, 0x958a96e0, 0xac07aa25, + 0xbb7cbe66, 0xdf1dd3af, 0xc866c7ec, 0xf1ebfb29, 0xe690ef6a, + 0x392920bb, 0x2e5234f8, 0x17df083d, 0x00a41c7e, 0x64c571b7, + 0x73be65f4, 0x4a335931, 0x5d484d72, 0x2e31c0d2, 0x394ad491, + 0x00c7e854, 0x17bcfc17, 0x73dd91de, 0x64a6859d, 0x5d2bb958, + 0x4a50ad1b, 0x95e962ca, 0x82927689, 0xbb1f4a4c, 0xac645e0f, + 0xc80533c6, 0xdf7e2785, 0xe6f31b40, 0xf1880f03, 0xde920307, + 0xc9e91744, 0xf0642b81, 0xe71f3fc2, 0x837e520b, 0x94054648, + 0xad887a8d, 0xbaf36ece, 0x654aa11f, 0x7231b55c, 0x4bbc8999, + 0x5cc79dda, 0x38a6f013, 0x2fdde450, 0x1650d895, 0x012bccd6, + 0x72524176, 0x65295535, 0x5ca469f0, 0x4bdf7db3, 0x2fbe107a, + 0x38c50439, 0x014838fc, 0x16332cbf, 0xc98ae36e, 0xdef1f72d, + 0xe77ccbe8, 0xf007dfab, 0x9466b262, 0x831da621, 0xba909ae4, + 0xadeb8ea7, 0x5c6381a4, 0x4b1895e7, 0x7295a922, 0x65eebd61, + 0x018fd0a8, 0x16f4c4eb, 0x2f79f82e, 0x3802ec6d, 0xe7bb23bc, + 0xf0c037ff, 0xc94d0b3a, 0xde361f79, 0xba5772b0, 0xad2c66f3, + 0x94a15a36, 0x83da4e75, 0xf0a3c3d5, 0xe7d8d796, 0xde55eb53, + 0xc92eff10, 0xad4f92d9, 0xba34869a, 0x83b9ba5f, 0x94c2ae1c, + 0x4b7b61cd, 0x5c00758e, 0x658d494b, 0x72f65d08, 0x169730c1, + 0x01ec2482, 0x38611847, 0x2f1a0c04, 0x6655004f, 0x712e140c, + 0x48a328c9, 0x5fd83c8a, 0x3bb95143, 0x2cc24500, 0x154f79c5, + 0x02346d86, 0xdd8da257, 0xcaf6b614, 0xf37b8ad1, 0xe4009e92, + 0x8061f35b, 0x971ae718, 0xae97dbdd, 0xb9eccf9e, 0xca95423e, + 0xddee567d, 0xe4636ab8, 0xf3187efb, 0x97791332, 0x80020771, + 0xb98f3bb4, 0xaef42ff7, 0x714de026, 0x6636f465, 0x5fbbc8a0, + 0x48c0dce3, 0x2ca1b12a, 0x3bdaa569, 0x025799ac, 0x152c8def, + 0xe4a482ec, 0xf3df96af, 0xca52aa6a, 0xdd29be29, 0xb948d3e0, + 0xae33c7a3, 0x97befb66, 0x80c5ef25, 0x5f7c20f4, 0x480734b7, + 0x718a0872, 0x66f11c31, 0x029071f8, 0x15eb65bb, 0x2c66597e, + 0x3b1d4d3d, 0x4864c09d, 0x5f1fd4de, 0x6692e81b, 0x71e9fc58, + 0x15889191, 0x02f385d2, 0x3b7eb917, 0x2c05ad54, 0xf3bc6285, + 0xe4c776c6, 0xdd4a4a03, 0xca315e40, 0xae503389, 0xb92b27ca, + 0x80a61b0f, 0x97dd0f4c, 0xb8c70348, 0xafbc170b, 0x96312bce, + 0x814a3f8d, 0xe52b5244, 0xf2504607, 0xcbdd7ac2, 0xdca66e81, + 0x031fa150, 0x1464b513, 0x2de989d6, 0x3a929d95, 0x5ef3f05c, + 0x4988e41f, 0x7005d8da, 0x677ecc99, 0x14074139, 0x037c557a, + 0x3af169bf, 0x2d8a7dfc, 0x49eb1035, 0x5e900476, 0x671d38b3, + 0x70662cf0, 0xafdfe321, 0xb8a4f762, 0x8129cba7, 0x9652dfe4, + 0xf233b22d, 0xe548a66e, 0xdcc59aab, 0xcbbe8ee8, 0x3a3681eb, + 0x2d4d95a8, 0x14c0a96d, 0x03bbbd2e, 0x67dad0e7, 0x70a1c4a4, + 0x492cf861, 0x5e57ec22, 0x81ee23f3, 0x969537b0, 0xaf180b75, + 0xb8631f36, 0xdc0272ff, 0xcb7966bc, 0xf2f45a79, 0xe58f4e3a, + 0x96f6c39a, 0x818dd7d9, 0xb800eb1c, 0xaf7bff5f, 0xcb1a9296, + 0xdc6186d5, 0xe5ecba10, 0xf297ae53, 0x2d2e6182, 0x3a5575c1, + 0x03d84904, 0x14a35d47, 0x70c2308e, 0x67b924cd, 0x5e341808, + 0x494f0c4b}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x0000000000000000, 0x43147b1700000000, 0x8628f62e00000000, + 0xc53c8d3900000000, 0x0c51ec5d00000000, 0x4f45974a00000000, + 0x8a791a7300000000, 0xc96d616400000000, 0x18a2d8bb00000000, + 0x5bb6a3ac00000000, 0x9e8a2e9500000000, 0xdd9e558200000000, + 0x14f334e600000000, 0x57e74ff100000000, 0x92dbc2c800000000, + 0xd1cfb9df00000000, 0x7142c0ac00000000, 0x3256bbbb00000000, + 0xf76a368200000000, 0xb47e4d9500000000, 0x7d132cf100000000, + 0x3e0757e600000000, 0xfb3bdadf00000000, 0xb82fa1c800000000, + 0x69e0181700000000, 0x2af4630000000000, 0xefc8ee3900000000, + 0xacdc952e00000000, 0x65b1f44a00000000, 0x26a58f5d00000000, + 0xe399026400000000, 0xa08d797300000000, 0xa382f18200000000, + 0xe0968a9500000000, 0x25aa07ac00000000, 0x66be7cbb00000000, + 0xafd31ddf00000000, 0xecc766c800000000, 0x29fbebf100000000, + 0x6aef90e600000000, 0xbb20293900000000, 0xf834522e00000000, + 0x3d08df1700000000, 0x7e1ca40000000000, 0xb771c56400000000, + 0xf465be7300000000, 0x3159334a00000000, 0x724d485d00000000, + 0xd2c0312e00000000, 0x91d44a3900000000, 0x54e8c70000000000, + 0x17fcbc1700000000, 0xde91dd7300000000, 0x9d85a66400000000, + 0x58b92b5d00000000, 0x1bad504a00000000, 0xca62e99500000000, + 0x8976928200000000, 0x4c4a1fbb00000000, 0x0f5e64ac00000000, + 0xc63305c800000000, 0x85277edf00000000, 0x401bf3e600000000, + 0x030f88f100000000, 0x070392de00000000, 0x4417e9c900000000, + 0x812b64f000000000, 0xc23f1fe700000000, 0x0b527e8300000000, + 0x4846059400000000, 0x8d7a88ad00000000, 0xce6ef3ba00000000, + 0x1fa14a6500000000, 0x5cb5317200000000, 0x9989bc4b00000000, + 0xda9dc75c00000000, 0x13f0a63800000000, 0x50e4dd2f00000000, + 0x95d8501600000000, 0xd6cc2b0100000000, 0x7641527200000000, + 0x3555296500000000, 0xf069a45c00000000, 0xb37ddf4b00000000, + 0x7a10be2f00000000, 0x3904c53800000000, 0xfc38480100000000, + 0xbf2c331600000000, 0x6ee38ac900000000, 0x2df7f1de00000000, + 0xe8cb7ce700000000, 0xabdf07f000000000, 0x62b2669400000000, + 0x21a61d8300000000, 0xe49a90ba00000000, 0xa78eebad00000000, + 0xa481635c00000000, 0xe795184b00000000, 0x22a9957200000000, + 0x61bdee6500000000, 0xa8d08f0100000000, 0xebc4f41600000000, + 0x2ef8792f00000000, 0x6dec023800000000, 0xbc23bbe700000000, + 0xff37c0f000000000, 0x3a0b4dc900000000, 0x791f36de00000000, + 0xb07257ba00000000, 0xf3662cad00000000, 0x365aa19400000000, + 0x754eda8300000000, 0xd5c3a3f000000000, 0x96d7d8e700000000, + 0x53eb55de00000000, 0x10ff2ec900000000, 0xd9924fad00000000, + 0x9a8634ba00000000, 0x5fbab98300000000, 0x1caec29400000000, + 0xcd617b4b00000000, 0x8e75005c00000000, 0x4b498d6500000000, + 0x085df67200000000, 0xc130971600000000, 0x8224ec0100000000, + 0x4718613800000000, 0x040c1a2f00000000, 0x4f00556600000000, + 0x0c142e7100000000, 0xc928a34800000000, 0x8a3cd85f00000000, + 0x4351b93b00000000, 0x0045c22c00000000, 0xc5794f1500000000, + 0x866d340200000000, 0x57a28ddd00000000, 0x14b6f6ca00000000, + 0xd18a7bf300000000, 0x929e00e400000000, 0x5bf3618000000000, + 0x18e71a9700000000, 0xdddb97ae00000000, 0x9ecfecb900000000, + 0x3e4295ca00000000, 0x7d56eedd00000000, 0xb86a63e400000000, + 0xfb7e18f300000000, 0x3213799700000000, 0x7107028000000000, + 0xb43b8fb900000000, 0xf72ff4ae00000000, 0x26e04d7100000000, + 0x65f4366600000000, 0xa0c8bb5f00000000, 0xe3dcc04800000000, + 0x2ab1a12c00000000, 0x69a5da3b00000000, 0xac99570200000000, + 0xef8d2c1500000000, 0xec82a4e400000000, 0xaf96dff300000000, + 0x6aaa52ca00000000, 0x29be29dd00000000, 0xe0d348b900000000, + 0xa3c733ae00000000, 0x66fbbe9700000000, 0x25efc58000000000, + 0xf4207c5f00000000, 0xb734074800000000, 0x72088a7100000000, + 0x311cf16600000000, 0xf871900200000000, 0xbb65eb1500000000, + 0x7e59662c00000000, 0x3d4d1d3b00000000, 0x9dc0644800000000, + 0xded41f5f00000000, 0x1be8926600000000, 0x58fce97100000000, + 0x9191881500000000, 0xd285f30200000000, 0x17b97e3b00000000, + 0x54ad052c00000000, 0x8562bcf300000000, 0xc676c7e400000000, + 0x034a4add00000000, 0x405e31ca00000000, 0x893350ae00000000, + 0xca272bb900000000, 0x0f1ba68000000000, 0x4c0fdd9700000000, + 0x4803c7b800000000, 0x0b17bcaf00000000, 0xce2b319600000000, + 0x8d3f4a8100000000, 0x44522be500000000, 0x074650f200000000, + 0xc27addcb00000000, 0x816ea6dc00000000, 0x50a11f0300000000, + 0x13b5641400000000, 0xd689e92d00000000, 0x959d923a00000000, + 0x5cf0f35e00000000, 0x1fe4884900000000, 0xdad8057000000000, + 0x99cc7e6700000000, 0x3941071400000000, 0x7a557c0300000000, + 0xbf69f13a00000000, 0xfc7d8a2d00000000, 0x3510eb4900000000, + 0x7604905e00000000, 0xb3381d6700000000, 0xf02c667000000000, + 0x21e3dfaf00000000, 0x62f7a4b800000000, 0xa7cb298100000000, + 0xe4df529600000000, 0x2db233f200000000, 0x6ea648e500000000, + 0xab9ac5dc00000000, 0xe88ebecb00000000, 0xeb81363a00000000, + 0xa8954d2d00000000, 0x6da9c01400000000, 0x2ebdbb0300000000, + 0xe7d0da6700000000, 0xa4c4a17000000000, 0x61f82c4900000000, + 0x22ec575e00000000, 0xf323ee8100000000, 0xb037959600000000, + 0x750b18af00000000, 0x361f63b800000000, 0xff7202dc00000000, + 0xbc6679cb00000000, 0x795af4f200000000, 0x3a4e8fe500000000, + 0x9ac3f69600000000, 0xd9d78d8100000000, 0x1ceb00b800000000, + 0x5fff7baf00000000, 0x96921acb00000000, 0xd58661dc00000000, + 0x10baece500000000, 0x53ae97f200000000, 0x82612e2d00000000, + 0xc175553a00000000, 0x0449d80300000000, 0x475da31400000000, + 0x8e30c27000000000, 0xcd24b96700000000, 0x0818345e00000000, + 0x4b0c4f4900000000}, + {0x0000000000000000, 0x3e6bc2ef00000000, 0x3dd0f50400000000, + 0x03bb37eb00000000, 0x7aa0eb0900000000, 0x44cb29e600000000, + 0x47701e0d00000000, 0x791bdce200000000, 0xf440d71300000000, + 0xca2b15fc00000000, 0xc990221700000000, 0xf7fbe0f800000000, + 0x8ee03c1a00000000, 0xb08bfef500000000, 0xb330c91e00000000, + 0x8d5b0bf100000000, 0xe881ae2700000000, 0xd6ea6cc800000000, + 0xd5515b2300000000, 0xeb3a99cc00000000, 0x9221452e00000000, + 0xac4a87c100000000, 0xaff1b02a00000000, 0x919a72c500000000, + 0x1cc1793400000000, 0x22aabbdb00000000, 0x21118c3000000000, + 0x1f7a4edf00000000, 0x6661923d00000000, 0x580a50d200000000, + 0x5bb1673900000000, 0x65daa5d600000000, 0xd0035d4f00000000, + 0xee689fa000000000, 0xedd3a84b00000000, 0xd3b86aa400000000, + 0xaaa3b64600000000, 0x94c874a900000000, 0x9773434200000000, + 0xa91881ad00000000, 0x24438a5c00000000, 0x1a2848b300000000, + 0x19937f5800000000, 0x27f8bdb700000000, 0x5ee3615500000000, + 0x6088a3ba00000000, 0x6333945100000000, 0x5d5856be00000000, + 0x3882f36800000000, 0x06e9318700000000, 0x0552066c00000000, + 0x3b39c48300000000, 0x4222186100000000, 0x7c49da8e00000000, + 0x7ff2ed6500000000, 0x41992f8a00000000, 0xccc2247b00000000, + 0xf2a9e69400000000, 0xf112d17f00000000, 0xcf79139000000000, + 0xb662cf7200000000, 0x88090d9d00000000, 0x8bb23a7600000000, + 0xb5d9f89900000000, 0xa007ba9e00000000, 0x9e6c787100000000, + 0x9dd74f9a00000000, 0xa3bc8d7500000000, 0xdaa7519700000000, + 0xe4cc937800000000, 0xe777a49300000000, 0xd91c667c00000000, + 0x54476d8d00000000, 0x6a2caf6200000000, 0x6997988900000000, + 0x57fc5a6600000000, 0x2ee7868400000000, 0x108c446b00000000, + 0x1337738000000000, 0x2d5cb16f00000000, 0x488614b900000000, + 0x76edd65600000000, 0x7556e1bd00000000, 0x4b3d235200000000, + 0x3226ffb000000000, 0x0c4d3d5f00000000, 0x0ff60ab400000000, + 0x319dc85b00000000, 0xbcc6c3aa00000000, 0x82ad014500000000, + 0x811636ae00000000, 0xbf7df44100000000, 0xc66628a300000000, + 0xf80dea4c00000000, 0xfbb6dda700000000, 0xc5dd1f4800000000, + 0x7004e7d100000000, 0x4e6f253e00000000, 0x4dd412d500000000, + 0x73bfd03a00000000, 0x0aa40cd800000000, 0x34cfce3700000000, + 0x3774f9dc00000000, 0x091f3b3300000000, 0x844430c200000000, + 0xba2ff22d00000000, 0xb994c5c600000000, 0x87ff072900000000, + 0xfee4dbcb00000000, 0xc08f192400000000, 0xc3342ecf00000000, + 0xfd5fec2000000000, 0x988549f600000000, 0xa6ee8b1900000000, + 0xa555bcf200000000, 0x9b3e7e1d00000000, 0xe225a2ff00000000, + 0xdc4e601000000000, 0xdff557fb00000000, 0xe19e951400000000, + 0x6cc59ee500000000, 0x52ae5c0a00000000, 0x51156be100000000, + 0x6f7ea90e00000000, 0x166575ec00000000, 0x280eb70300000000, + 0x2bb580e800000000, 0x15de420700000000, 0x010905e600000000, + 0x3f62c70900000000, 0x3cd9f0e200000000, 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0x8fcff73e00000000, + 0xfa370ec300000000, 0x6ba6666d00000000, 0x9912ae4400000000, + 0x0883c6ea00000000, 0x32e42c6400000000, 0xa37544ca00000000, + 0x51c18ce300000000, 0xc050e44d00000000, 0xb5a81db000000000, + 0x2439751e00000000, 0xd68dbd3700000000, 0x471cd59900000000, + 0xe34518f100000000, 0x72d4705f00000000, 0x8060b87600000000, + 0x11f1d0d800000000, 0x6409292500000000, 0xf598418b00000000, + 0x072c89a200000000, 0x96bde10c00000000, 0xacda0b8200000000, + 0x3d4b632c00000000, 0xcfffab0500000000, 0x5e6ec3ab00000000, + 0x2b963a5600000000, 0xba0752f800000000, 0x48b39ad100000000, + 0xd922f27f00000000, 0xfaf67e2e00000000, 0x6b67168000000000, + 0x99d3dea900000000, 0x0842b60700000000, 0x7dba4ffa00000000, + 0xec2b275400000000, 0x1e9fef7d00000000, 0x8f0e87d300000000, + 0xb5696d5d00000000, 0x24f805f300000000, 0xd64ccdda00000000, + 0x47dda57400000000, 0x32255c8900000000, 0xa3b4342700000000, + 0x5100fc0e00000000, 0xc09194a000000000, 0x64c859c800000000, + 0xf559316600000000, 0x07edf94f00000000, 0x967c91e100000000, + 0xe384681c00000000, 0x721500b200000000, 0x80a1c89b00000000, + 0x1130a03500000000, 0x2b574abb00000000, 0xbac6221500000000, + 0x4872ea3c00000000, 0xd9e3829200000000, 0xac1b7b6f00000000, + 0x3d8a13c100000000, 0xcf3edbe800000000, 0x5eafb34600000000, + 0x878d413900000000, 0x161c299700000000, 0xe4a8e1be00000000, + 0x7539891000000000, 0x00c170ed00000000, 0x9150184300000000, + 0x63e4d06a00000000, 0xf275b8c400000000, 0xc812524a00000000, + 0x59833ae400000000, 0xab37f2cd00000000, 0x3aa69a6300000000, + 0x4f5e639e00000000, 0xdecf0b3000000000, 0x2c7bc31900000000, + 0xbdeaabb700000000, 0x19b366df00000000, 0x88220e7100000000, + 0x7a96c65800000000, 0xeb07aef600000000, 0x9eff570b00000000, + 0x0f6e3fa500000000, 0xfddaf78c00000000, 0x6c4b9f2200000000, + 0x562c75ac00000000, 0xc7bd1d0200000000, 0x3509d52b00000000, + 0xa498bd8500000000, 0xd160447800000000, 0x40f12cd600000000, + 0xb245e4ff00000000, 0x23d48c5100000000, 0xf4edfd5c00000000, + 0x657c95f200000000, 0x97c85ddb00000000, 0x0659357500000000, + 0x73a1cc8800000000, 0xe230a42600000000, 0x10846c0f00000000, + 0x811504a100000000, 0xbb72ee2f00000000, 0x2ae3868100000000, + 0xd8574ea800000000, 0x49c6260600000000, 0x3c3edffb00000000, + 0xadafb75500000000, 0x5f1b7f7c00000000, 0xce8a17d200000000, + 0x6ad3daba00000000, 0xfb42b21400000000, 0x09f67a3d00000000, + 0x9867129300000000, 0xed9feb6e00000000, 0x7c0e83c000000000, + 0x8eba4be900000000, 0x1f2b234700000000, 0x254cc9c900000000, + 0xb4dda16700000000, 0x4669694e00000000, 0xd7f801e000000000, + 0xa200f81d00000000, 0x339190b300000000, 0xc125589a00000000, + 0x50b4303400000000, 0x8996c24b00000000, 0x1807aae500000000, + 0xeab362cc00000000, 0x7b220a6200000000, 0x0edaf39f00000000, + 0x9f4b9b3100000000, 0x6dff531800000000, 0xfc6e3bb600000000, + 0xc609d13800000000, 0x5798b99600000000, 0xa52c71bf00000000, + 0x34bd191100000000, 0x4145e0ec00000000, 0xd0d4884200000000, + 0x2260406b00000000, 0xb3f128c500000000, 0x17a8e5ad00000000, + 0x86398d0300000000, 0x748d452a00000000, 0xe51c2d8400000000, + 0x90e4d47900000000, 0x0175bcd700000000, 0xf3c174fe00000000, + 0x62501c5000000000, 0x5837f6de00000000, 0xc9a69e7000000000, + 0x3b12565900000000, 0xaa833ef700000000, 0xdf7bc70a00000000, + 0x4eeaafa400000000, 0xbc5e678d00000000, 0x2dcf0f2300000000, + 0x0e1b837200000000, 0x9f8aebdc00000000, 0x6d3e23f500000000, + 0xfcaf4b5b00000000, 0x8957b2a600000000, 0x18c6da0800000000, + 0xea72122100000000, 0x7be37a8f00000000, 0x4184900100000000, + 0xd015f8af00000000, 0x22a1308600000000, 0xb330582800000000, + 0xc6c8a1d500000000, 0x5759c97b00000000, 0xa5ed015200000000, + 0x347c69fc00000000, 0x9025a49400000000, 0x01b4cc3a00000000, + 0xf300041300000000, 0x62916cbd00000000, 0x1769954000000000, + 0x86f8fdee00000000, 0x744c35c700000000, 0xe5dd5d6900000000, + 0xdfbab7e700000000, 0x4e2bdf4900000000, 0xbc9f176000000000, + 0x2d0e7fce00000000, 0x58f6863300000000, 0xc967ee9d00000000, + 0x3bd326b400000000, 0xaa424e1a00000000, 0x7360bc6500000000, + 0xe2f1d4cb00000000, 0x10451ce200000000, 0x81d4744c00000000, + 0xf42c8db100000000, 0x65bde51f00000000, 0x97092d3600000000, + 0x0698459800000000, 0x3cffaf1600000000, 0xad6ec7b800000000, + 0x5fda0f9100000000, 0xce4b673f00000000, 0xbbb39ec200000000, + 0x2a22f66c00000000, 0xd8963e4500000000, 0x490756eb00000000, + 0xed5e9b8300000000, 0x7ccff32d00000000, 0x8e7b3b0400000000, + 0x1fea53aa00000000, 0x6a12aa5700000000, 0xfb83c2f900000000, + 0x09370ad000000000, 0x98a6627e00000000, 0xa2c188f000000000, + 0x3350e05e00000000, 0xc1e4287700000000, 0x507540d900000000, + 0x258db92400000000, 0xb41cd18a00000000, 0x46a819a300000000, + 0xd739710d00000000}}; + +#else /* W == 4 */ + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0xccaa009e, 0x4225077d, 0x8e8f07e3, 0x844a0efa, + 0x48e00e64, 0xc66f0987, 0x0ac50919, 0xd3e51bb5, 0x1f4f1b2b, + 0x91c01cc8, 0x5d6a1c56, 0x57af154f, 0x9b0515d1, 0x158a1232, + 0xd92012ac, 0x7cbb312b, 0xb01131b5, 0x3e9e3656, 0xf23436c8, + 0xf8f13fd1, 0x345b3f4f, 0xbad438ac, 0x767e3832, 0xaf5e2a9e, + 0x63f42a00, 0xed7b2de3, 0x21d12d7d, 0x2b142464, 0xe7be24fa, + 0x69312319, 0xa59b2387, 0xf9766256, 0x35dc62c8, 0xbb53652b, + 0x77f965b5, 0x7d3c6cac, 0xb1966c32, 0x3f196bd1, 0xf3b36b4f, + 0x2a9379e3, 0xe639797d, 0x68b67e9e, 0xa41c7e00, 0xaed97719, + 0x62737787, 0xecfc7064, 0x205670fa, 0x85cd537d, 0x496753e3, + 0xc7e85400, 0x0b42549e, 0x01875d87, 0xcd2d5d19, 0x43a25afa, + 0x8f085a64, 0x562848c8, 0x9a824856, 0x140d4fb5, 0xd8a74f2b, + 0xd2624632, 0x1ec846ac, 0x9047414f, 0x5ced41d1, 0x299dc2ed, + 0xe537c273, 0x6bb8c590, 0xa712c50e, 0xadd7cc17, 0x617dcc89, + 0xeff2cb6a, 0x2358cbf4, 0xfa78d958, 0x36d2d9c6, 0xb85dde25, + 0x74f7debb, 0x7e32d7a2, 0xb298d73c, 0x3c17d0df, 0xf0bdd041, + 0x5526f3c6, 0x998cf358, 0x1703f4bb, 0xdba9f425, 0xd16cfd3c, + 0x1dc6fda2, 0x9349fa41, 0x5fe3fadf, 0x86c3e873, 0x4a69e8ed, + 0xc4e6ef0e, 0x084cef90, 0x0289e689, 0xce23e617, 0x40ace1f4, + 0x8c06e16a, 0xd0eba0bb, 0x1c41a025, 0x92cea7c6, 0x5e64a758, + 0x54a1ae41, 0x980baedf, 0x1684a93c, 0xda2ea9a2, 0x030ebb0e, + 0xcfa4bb90, 0x412bbc73, 0x8d81bced, 0x8744b5f4, 0x4beeb56a, + 0xc561b289, 0x09cbb217, 0xac509190, 0x60fa910e, 0xee7596ed, + 0x22df9673, 0x281a9f6a, 0xe4b09ff4, 0x6a3f9817, 0xa6959889, + 0x7fb58a25, 0xb31f8abb, 0x3d908d58, 0xf13a8dc6, 0xfbff84df, + 0x37558441, 0xb9da83a2, 0x7570833c, 0x533b85da, 0x9f918544, + 0x111e82a7, 0xddb48239, 0xd7718b20, 0x1bdb8bbe, 0x95548c5d, + 0x59fe8cc3, 0x80de9e6f, 0x4c749ef1, 0xc2fb9912, 0x0e51998c, + 0x04949095, 0xc83e900b, 0x46b197e8, 0x8a1b9776, 0x2f80b4f1, + 0xe32ab46f, 0x6da5b38c, 0xa10fb312, 0xabcaba0b, 0x6760ba95, + 0xe9efbd76, 0x2545bde8, 0xfc65af44, 0x30cfafda, 0xbe40a839, + 0x72eaa8a7, 0x782fa1be, 0xb485a120, 0x3a0aa6c3, 0xf6a0a65d, + 0xaa4de78c, 0x66e7e712, 0xe868e0f1, 0x24c2e06f, 0x2e07e976, + 0xe2ade9e8, 0x6c22ee0b, 0xa088ee95, 0x79a8fc39, 0xb502fca7, + 0x3b8dfb44, 0xf727fbda, 0xfde2f2c3, 0x3148f25d, 0xbfc7f5be, + 0x736df520, 0xd6f6d6a7, 0x1a5cd639, 0x94d3d1da, 0x5879d144, + 0x52bcd85d, 0x9e16d8c3, 0x1099df20, 0xdc33dfbe, 0x0513cd12, + 0xc9b9cd8c, 0x4736ca6f, 0x8b9ccaf1, 0x8159c3e8, 0x4df3c376, + 0xc37cc495, 0x0fd6c40b, 0x7aa64737, 0xb60c47a9, 0x3883404a, + 0xf42940d4, 0xfeec49cd, 0x32464953, 0xbcc94eb0, 0x70634e2e, + 0xa9435c82, 0x65e95c1c, 0xeb665bff, 0x27cc5b61, 0x2d095278, + 0xe1a352e6, 0x6f2c5505, 0xa386559b, 0x061d761c, 0xcab77682, + 0x44387161, 0x889271ff, 0x825778e6, 0x4efd7878, 0xc0727f9b, + 0x0cd87f05, 0xd5f86da9, 0x19526d37, 0x97dd6ad4, 0x5b776a4a, + 0x51b26353, 0x9d1863cd, 0x1397642e, 0xdf3d64b0, 0x83d02561, + 0x4f7a25ff, 0xc1f5221c, 0x0d5f2282, 0x079a2b9b, 0xcb302b05, + 0x45bf2ce6, 0x89152c78, 0x50353ed4, 0x9c9f3e4a, 0x121039a9, + 0xdeba3937, 0xd47f302e, 0x18d530b0, 0x965a3753, 0x5af037cd, + 0xff6b144a, 0x33c114d4, 0xbd4e1337, 0x71e413a9, 0x7b211ab0, + 0xb78b1a2e, 0x39041dcd, 0xf5ae1d53, 0x2c8e0fff, 0xe0240f61, + 0x6eab0882, 0xa201081c, 0xa8c40105, 0x646e019b, 0xeae10678, + 0x264b06e6}, + {0x00000000, 0xa6770bb4, 0x979f1129, 0x31e81a9d, 0xf44f2413, + 0x52382fa7, 0x63d0353a, 0xc5a73e8e, 0x33ef4e67, 0x959845d3, + 0xa4705f4e, 0x020754fa, 0xc7a06a74, 0x61d761c0, 0x503f7b5d, + 0xf64870e9, 0x67de9cce, 0xc1a9977a, 0xf0418de7, 0x56368653, + 0x9391b8dd, 0x35e6b369, 0x040ea9f4, 0xa279a240, 0x5431d2a9, + 0xf246d91d, 0xc3aec380, 0x65d9c834, 0xa07ef6ba, 0x0609fd0e, + 0x37e1e793, 0x9196ec27, 0xcfbd399c, 0x69ca3228, 0x582228b5, + 0xfe552301, 0x3bf21d8f, 0x9d85163b, 0xac6d0ca6, 0x0a1a0712, + 0xfc5277fb, 0x5a257c4f, 0x6bcd66d2, 0xcdba6d66, 0x081d53e8, + 0xae6a585c, 0x9f8242c1, 0x39f54975, 0xa863a552, 0x0e14aee6, + 0x3ffcb47b, 0x998bbfcf, 0x5c2c8141, 0xfa5b8af5, 0xcbb39068, + 0x6dc49bdc, 0x9b8ceb35, 0x3dfbe081, 0x0c13fa1c, 0xaa64f1a8, + 0x6fc3cf26, 0xc9b4c492, 0xf85cde0f, 0x5e2bd5bb, 0x440b7579, + 0xe27c7ecd, 0xd3946450, 0x75e36fe4, 0xb044516a, 0x16335ade, + 0x27db4043, 0x81ac4bf7, 0x77e43b1e, 0xd19330aa, 0xe07b2a37, + 0x460c2183, 0x83ab1f0d, 0x25dc14b9, 0x14340e24, 0xb2430590, + 0x23d5e9b7, 0x85a2e203, 0xb44af89e, 0x123df32a, 0xd79acda4, + 0x71edc610, 0x4005dc8d, 0xe672d739, 0x103aa7d0, 0xb64dac64, + 0x87a5b6f9, 0x21d2bd4d, 0xe47583c3, 0x42028877, 0x73ea92ea, + 0xd59d995e, 0x8bb64ce5, 0x2dc14751, 0x1c295dcc, 0xba5e5678, + 0x7ff968f6, 0xd98e6342, 0xe86679df, 0x4e11726b, 0xb8590282, + 0x1e2e0936, 0x2fc613ab, 0x89b1181f, 0x4c162691, 0xea612d25, + 0xdb8937b8, 0x7dfe3c0c, 0xec68d02b, 0x4a1fdb9f, 0x7bf7c102, + 0xdd80cab6, 0x1827f438, 0xbe50ff8c, 0x8fb8e511, 0x29cfeea5, + 0xdf879e4c, 0x79f095f8, 0x48188f65, 0xee6f84d1, 0x2bc8ba5f, + 0x8dbfb1eb, 0xbc57ab76, 0x1a20a0c2, 0x8816eaf2, 0x2e61e146, + 0x1f89fbdb, 0xb9fef06f, 0x7c59cee1, 0xda2ec555, 0xebc6dfc8, + 0x4db1d47c, 0xbbf9a495, 0x1d8eaf21, 0x2c66b5bc, 0x8a11be08, + 0x4fb68086, 0xe9c18b32, 0xd82991af, 0x7e5e9a1b, 0xefc8763c, + 0x49bf7d88, 0x78576715, 0xde206ca1, 0x1b87522f, 0xbdf0599b, + 0x8c184306, 0x2a6f48b2, 0xdc27385b, 0x7a5033ef, 0x4bb82972, + 0xedcf22c6, 0x28681c48, 0x8e1f17fc, 0xbff70d61, 0x198006d5, + 0x47abd36e, 0xe1dcd8da, 0xd034c247, 0x7643c9f3, 0xb3e4f77d, + 0x1593fcc9, 0x247be654, 0x820cede0, 0x74449d09, 0xd23396bd, + 0xe3db8c20, 0x45ac8794, 0x800bb91a, 0x267cb2ae, 0x1794a833, + 0xb1e3a387, 0x20754fa0, 0x86024414, 0xb7ea5e89, 0x119d553d, + 0xd43a6bb3, 0x724d6007, 0x43a57a9a, 0xe5d2712e, 0x139a01c7, + 0xb5ed0a73, 0x840510ee, 0x22721b5a, 0xe7d525d4, 0x41a22e60, + 0x704a34fd, 0xd63d3f49, 0xcc1d9f8b, 0x6a6a943f, 0x5b828ea2, + 0xfdf58516, 0x3852bb98, 0x9e25b02c, 0xafcdaab1, 0x09baa105, + 0xfff2d1ec, 0x5985da58, 0x686dc0c5, 0xce1acb71, 0x0bbdf5ff, + 0xadcafe4b, 0x9c22e4d6, 0x3a55ef62, 0xabc30345, 0x0db408f1, + 0x3c5c126c, 0x9a2b19d8, 0x5f8c2756, 0xf9fb2ce2, 0xc813367f, + 0x6e643dcb, 0x982c4d22, 0x3e5b4696, 0x0fb35c0b, 0xa9c457bf, + 0x6c636931, 0xca146285, 0xfbfc7818, 0x5d8b73ac, 0x03a0a617, + 0xa5d7ada3, 0x943fb73e, 0x3248bc8a, 0xf7ef8204, 0x519889b0, + 0x6070932d, 0xc6079899, 0x304fe870, 0x9638e3c4, 0xa7d0f959, + 0x01a7f2ed, 0xc400cc63, 0x6277c7d7, 0x539fdd4a, 0xf5e8d6fe, + 0x647e3ad9, 0xc209316d, 0xf3e12bf0, 0x55962044, 0x90311eca, + 0x3646157e, 0x07ae0fe3, 0xa1d90457, 0x579174be, 0xf1e67f0a, + 0xc00e6597, 0x66796e23, 0xa3de50ad, 0x05a95b19, 0x34414184, + 0x92364a30}, + {0x00000000, 0xcb5cd3a5, 0x4dc8a10b, 0x869472ae, 0x9b914216, + 0x50cd91b3, 0xd659e31d, 0x1d0530b8, 0xec53826d, 0x270f51c8, + 0xa19b2366, 0x6ac7f0c3, 0x77c2c07b, 0xbc9e13de, 0x3a0a6170, + 0xf156b2d5, 0x03d6029b, 0xc88ad13e, 0x4e1ea390, 0x85427035, + 0x9847408d, 0x531b9328, 0xd58fe186, 0x1ed33223, 0xef8580f6, + 0x24d95353, 0xa24d21fd, 0x6911f258, 0x7414c2e0, 0xbf481145, + 0x39dc63eb, 0xf280b04e, 0x07ac0536, 0xccf0d693, 0x4a64a43d, + 0x81387798, 0x9c3d4720, 0x57619485, 0xd1f5e62b, 0x1aa9358e, + 0xebff875b, 0x20a354fe, 0xa6372650, 0x6d6bf5f5, 0x706ec54d, + 0xbb3216e8, 0x3da66446, 0xf6fab7e3, 0x047a07ad, 0xcf26d408, + 0x49b2a6a6, 0x82ee7503, 0x9feb45bb, 0x54b7961e, 0xd223e4b0, + 0x197f3715, 0xe82985c0, 0x23755665, 0xa5e124cb, 0x6ebdf76e, + 0x73b8c7d6, 0xb8e41473, 0x3e7066dd, 0xf52cb578, 0x0f580a6c, + 0xc404d9c9, 0x4290ab67, 0x89cc78c2, 0x94c9487a, 0x5f959bdf, + 0xd901e971, 0x125d3ad4, 0xe30b8801, 0x28575ba4, 0xaec3290a, + 0x659ffaaf, 0x789aca17, 0xb3c619b2, 0x35526b1c, 0xfe0eb8b9, + 0x0c8e08f7, 0xc7d2db52, 0x4146a9fc, 0x8a1a7a59, 0x971f4ae1, + 0x5c439944, 0xdad7ebea, 0x118b384f, 0xe0dd8a9a, 0x2b81593f, + 0xad152b91, 0x6649f834, 0x7b4cc88c, 0xb0101b29, 0x36846987, + 0xfdd8ba22, 0x08f40f5a, 0xc3a8dcff, 0x453cae51, 0x8e607df4, + 0x93654d4c, 0x58399ee9, 0xdeadec47, 0x15f13fe2, 0xe4a78d37, + 0x2ffb5e92, 0xa96f2c3c, 0x6233ff99, 0x7f36cf21, 0xb46a1c84, + 0x32fe6e2a, 0xf9a2bd8f, 0x0b220dc1, 0xc07ede64, 0x46eaacca, + 0x8db67f6f, 0x90b34fd7, 0x5bef9c72, 0xdd7beedc, 0x16273d79, + 0xe7718fac, 0x2c2d5c09, 0xaab92ea7, 0x61e5fd02, 0x7ce0cdba, + 0xb7bc1e1f, 0x31286cb1, 0xfa74bf14, 0x1eb014d8, 0xd5ecc77d, + 0x5378b5d3, 0x98246676, 0x852156ce, 0x4e7d856b, 0xc8e9f7c5, + 0x03b52460, 0xf2e396b5, 0x39bf4510, 0xbf2b37be, 0x7477e41b, + 0x6972d4a3, 0xa22e0706, 0x24ba75a8, 0xefe6a60d, 0x1d661643, + 0xd63ac5e6, 0x50aeb748, 0x9bf264ed, 0x86f75455, 0x4dab87f0, + 0xcb3ff55e, 0x006326fb, 0xf135942e, 0x3a69478b, 0xbcfd3525, + 0x77a1e680, 0x6aa4d638, 0xa1f8059d, 0x276c7733, 0xec30a496, + 0x191c11ee, 0xd240c24b, 0x54d4b0e5, 0x9f886340, 0x828d53f8, + 0x49d1805d, 0xcf45f2f3, 0x04192156, 0xf54f9383, 0x3e134026, + 0xb8873288, 0x73dbe12d, 0x6eded195, 0xa5820230, 0x2316709e, + 0xe84aa33b, 0x1aca1375, 0xd196c0d0, 0x5702b27e, 0x9c5e61db, + 0x815b5163, 0x4a0782c6, 0xcc93f068, 0x07cf23cd, 0xf6999118, + 0x3dc542bd, 0xbb513013, 0x700de3b6, 0x6d08d30e, 0xa65400ab, + 0x20c07205, 0xeb9ca1a0, 0x11e81eb4, 0xdab4cd11, 0x5c20bfbf, + 0x977c6c1a, 0x8a795ca2, 0x41258f07, 0xc7b1fda9, 0x0ced2e0c, + 0xfdbb9cd9, 0x36e74f7c, 0xb0733dd2, 0x7b2fee77, 0x662adecf, + 0xad760d6a, 0x2be27fc4, 0xe0beac61, 0x123e1c2f, 0xd962cf8a, + 0x5ff6bd24, 0x94aa6e81, 0x89af5e39, 0x42f38d9c, 0xc467ff32, + 0x0f3b2c97, 0xfe6d9e42, 0x35314de7, 0xb3a53f49, 0x78f9ecec, + 0x65fcdc54, 0xaea00ff1, 0x28347d5f, 0xe368aefa, 0x16441b82, + 0xdd18c827, 0x5b8cba89, 0x90d0692c, 0x8dd55994, 0x46898a31, + 0xc01df89f, 0x0b412b3a, 0xfa1799ef, 0x314b4a4a, 0xb7df38e4, + 0x7c83eb41, 0x6186dbf9, 0xaada085c, 0x2c4e7af2, 0xe712a957, + 0x15921919, 0xdececabc, 0x585ab812, 0x93066bb7, 0x8e035b0f, + 0x455f88aa, 0xc3cbfa04, 0x089729a1, 0xf9c19b74, 0x329d48d1, + 0xb4093a7f, 0x7f55e9da, 0x6250d962, 0xa90c0ac7, 0x2f987869, + 0xe4c4abcc}, + {0x00000000, 0x3d6029b0, 0x7ac05360, 0x47a07ad0, 0xf580a6c0, + 0xc8e08f70, 0x8f40f5a0, 0xb220dc10, 0x30704bc1, 0x0d106271, + 0x4ab018a1, 0x77d03111, 0xc5f0ed01, 0xf890c4b1, 0xbf30be61, + 0x825097d1, 0x60e09782, 0x5d80be32, 0x1a20c4e2, 0x2740ed52, + 0x95603142, 0xa80018f2, 0xefa06222, 0xd2c04b92, 0x5090dc43, + 0x6df0f5f3, 0x2a508f23, 0x1730a693, 0xa5107a83, 0x98705333, + 0xdfd029e3, 0xe2b00053, 0xc1c12f04, 0xfca106b4, 0xbb017c64, + 0x866155d4, 0x344189c4, 0x0921a074, 0x4e81daa4, 0x73e1f314, + 0xf1b164c5, 0xccd14d75, 0x8b7137a5, 0xb6111e15, 0x0431c205, + 0x3951ebb5, 0x7ef19165, 0x4391b8d5, 0xa121b886, 0x9c419136, + 0xdbe1ebe6, 0xe681c256, 0x54a11e46, 0x69c137f6, 0x2e614d26, + 0x13016496, 0x9151f347, 0xac31daf7, 0xeb91a027, 0xd6f18997, + 0x64d15587, 0x59b17c37, 0x1e1106e7, 0x23712f57, 0x58f35849, + 0x659371f9, 0x22330b29, 0x1f532299, 0xad73fe89, 0x9013d739, + 0xd7b3ade9, 0xead38459, 0x68831388, 0x55e33a38, 0x124340e8, + 0x2f236958, 0x9d03b548, 0xa0639cf8, 0xe7c3e628, 0xdaa3cf98, + 0x3813cfcb, 0x0573e67b, 0x42d39cab, 0x7fb3b51b, 0xcd93690b, + 0xf0f340bb, 0xb7533a6b, 0x8a3313db, 0x0863840a, 0x3503adba, + 0x72a3d76a, 0x4fc3feda, 0xfde322ca, 0xc0830b7a, 0x872371aa, + 0xba43581a, 0x9932774d, 0xa4525efd, 0xe3f2242d, 0xde920d9d, + 0x6cb2d18d, 0x51d2f83d, 0x167282ed, 0x2b12ab5d, 0xa9423c8c, + 0x9422153c, 0xd3826fec, 0xeee2465c, 0x5cc29a4c, 0x61a2b3fc, + 0x2602c92c, 0x1b62e09c, 0xf9d2e0cf, 0xc4b2c97f, 0x8312b3af, + 0xbe729a1f, 0x0c52460f, 0x31326fbf, 0x7692156f, 0x4bf23cdf, + 0xc9a2ab0e, 0xf4c282be, 0xb362f86e, 0x8e02d1de, 0x3c220dce, + 0x0142247e, 0x46e25eae, 0x7b82771e, 0xb1e6b092, 0x8c869922, + 0xcb26e3f2, 0xf646ca42, 0x44661652, 0x79063fe2, 0x3ea64532, + 0x03c66c82, 0x8196fb53, 0xbcf6d2e3, 0xfb56a833, 0xc6368183, + 0x74165d93, 0x49767423, 0x0ed60ef3, 0x33b62743, 0xd1062710, + 0xec660ea0, 0xabc67470, 0x96a65dc0, 0x248681d0, 0x19e6a860, + 0x5e46d2b0, 0x6326fb00, 0xe1766cd1, 0xdc164561, 0x9bb63fb1, + 0xa6d61601, 0x14f6ca11, 0x2996e3a1, 0x6e369971, 0x5356b0c1, + 0x70279f96, 0x4d47b626, 0x0ae7ccf6, 0x3787e546, 0x85a73956, + 0xb8c710e6, 0xff676a36, 0xc2074386, 0x4057d457, 0x7d37fde7, + 0x3a978737, 0x07f7ae87, 0xb5d77297, 0x88b75b27, 0xcf1721f7, + 0xf2770847, 0x10c70814, 0x2da721a4, 0x6a075b74, 0x576772c4, + 0xe547aed4, 0xd8278764, 0x9f87fdb4, 0xa2e7d404, 0x20b743d5, + 0x1dd76a65, 0x5a7710b5, 0x67173905, 0xd537e515, 0xe857cca5, + 0xaff7b675, 0x92979fc5, 0xe915e8db, 0xd475c16b, 0x93d5bbbb, + 0xaeb5920b, 0x1c954e1b, 0x21f567ab, 0x66551d7b, 0x5b3534cb, + 0xd965a31a, 0xe4058aaa, 0xa3a5f07a, 0x9ec5d9ca, 0x2ce505da, + 0x11852c6a, 0x562556ba, 0x6b457f0a, 0x89f57f59, 0xb49556e9, + 0xf3352c39, 0xce550589, 0x7c75d999, 0x4115f029, 0x06b58af9, + 0x3bd5a349, 0xb9853498, 0x84e51d28, 0xc34567f8, 0xfe254e48, + 0x4c059258, 0x7165bbe8, 0x36c5c138, 0x0ba5e888, 0x28d4c7df, + 0x15b4ee6f, 0x521494bf, 0x6f74bd0f, 0xdd54611f, 0xe03448af, + 0xa794327f, 0x9af41bcf, 0x18a48c1e, 0x25c4a5ae, 0x6264df7e, + 0x5f04f6ce, 0xed242ade, 0xd044036e, 0x97e479be, 0xaa84500e, + 0x4834505d, 0x755479ed, 0x32f4033d, 0x0f942a8d, 0xbdb4f69d, + 0x80d4df2d, 0xc774a5fd, 0xfa148c4d, 0x78441b9c, 0x4524322c, + 0x028448fc, 0x3fe4614c, 0x8dc4bd5c, 0xb0a494ec, 0xf704ee3c, + 0xca64c78c}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x00000000, 0xb029603d, 0x6053c07a, 0xd07aa047, 0xc0a680f5, + 0x708fe0c8, 0xa0f5408f, 0x10dc20b2, 0xc14b7030, 0x7162100d, + 0xa118b04a, 0x1131d077, 0x01edf0c5, 0xb1c490f8, 0x61be30bf, + 0xd1975082, 0x8297e060, 0x32be805d, 0xe2c4201a, 0x52ed4027, + 0x42316095, 0xf21800a8, 0x2262a0ef, 0x924bc0d2, 0x43dc9050, + 0xf3f5f06d, 0x238f502a, 0x93a63017, 0x837a10a5, 0x33537098, + 0xe329d0df, 0x5300b0e2, 0x042fc1c1, 0xb406a1fc, 0x647c01bb, + 0xd4556186, 0xc4894134, 0x74a02109, 0xa4da814e, 0x14f3e173, + 0xc564b1f1, 0x754dd1cc, 0xa537718b, 0x151e11b6, 0x05c23104, + 0xb5eb5139, 0x6591f17e, 0xd5b89143, 0x86b821a1, 0x3691419c, + 0xe6ebe1db, 0x56c281e6, 0x461ea154, 0xf637c169, 0x264d612e, + 0x96640113, 0x47f35191, 0xf7da31ac, 0x27a091eb, 0x9789f1d6, + 0x8755d164, 0x377cb159, 0xe706111e, 0x572f7123, 0x4958f358, + 0xf9719365, 0x290b3322, 0x9922531f, 0x89fe73ad, 0x39d71390, + 0xe9adb3d7, 0x5984d3ea, 0x88138368, 0x383ae355, 0xe8404312, + 0x5869232f, 0x48b5039d, 0xf89c63a0, 0x28e6c3e7, 0x98cfa3da, + 0xcbcf1338, 0x7be67305, 0xab9cd342, 0x1bb5b37f, 0x0b6993cd, + 0xbb40f3f0, 0x6b3a53b7, 0xdb13338a, 0x0a846308, 0xbaad0335, + 0x6ad7a372, 0xdafec34f, 0xca22e3fd, 0x7a0b83c0, 0xaa712387, + 0x1a5843ba, 0x4d773299, 0xfd5e52a4, 0x2d24f2e3, 0x9d0d92de, + 0x8dd1b26c, 0x3df8d251, 0xed827216, 0x5dab122b, 0x8c3c42a9, + 0x3c152294, 0xec6f82d3, 0x5c46e2ee, 0x4c9ac25c, 0xfcb3a261, + 0x2cc90226, 0x9ce0621b, 0xcfe0d2f9, 0x7fc9b2c4, 0xafb31283, + 0x1f9a72be, 0x0f46520c, 0xbf6f3231, 0x6f159276, 0xdf3cf24b, + 0x0eaba2c9, 0xbe82c2f4, 0x6ef862b3, 0xded1028e, 0xce0d223c, + 0x7e244201, 0xae5ee246, 0x1e77827b, 0x92b0e6b1, 0x2299868c, + 0xf2e326cb, 0x42ca46f6, 0x52166644, 0xe23f0679, 0x3245a63e, + 0x826cc603, 0x53fb9681, 0xe3d2f6bc, 0x33a856fb, 0x838136c6, + 0x935d1674, 0x23747649, 0xf30ed60e, 0x4327b633, 0x102706d1, + 0xa00e66ec, 0x7074c6ab, 0xc05da696, 0xd0818624, 0x60a8e619, + 0xb0d2465e, 0x00fb2663, 0xd16c76e1, 0x614516dc, 0xb13fb69b, + 0x0116d6a6, 0x11caf614, 0xa1e39629, 0x7199366e, 0xc1b05653, + 0x969f2770, 0x26b6474d, 0xf6cce70a, 0x46e58737, 0x5639a785, + 0xe610c7b8, 0x366a67ff, 0x864307c2, 0x57d45740, 0xe7fd377d, + 0x3787973a, 0x87aef707, 0x9772d7b5, 0x275bb788, 0xf72117cf, + 0x470877f2, 0x1408c710, 0xa421a72d, 0x745b076a, 0xc4726757, + 0xd4ae47e5, 0x648727d8, 0xb4fd879f, 0x04d4e7a2, 0xd543b720, + 0x656ad71d, 0xb510775a, 0x05391767, 0x15e537d5, 0xa5cc57e8, + 0x75b6f7af, 0xc59f9792, 0xdbe815e9, 0x6bc175d4, 0xbbbbd593, + 0x0b92b5ae, 0x1b4e951c, 0xab67f521, 0x7b1d5566, 0xcb34355b, + 0x1aa365d9, 0xaa8a05e4, 0x7af0a5a3, 0xcad9c59e, 0xda05e52c, + 0x6a2c8511, 0xba562556, 0x0a7f456b, 0x597ff589, 0xe95695b4, + 0x392c35f3, 0x890555ce, 0x99d9757c, 0x29f01541, 0xf98ab506, + 0x49a3d53b, 0x983485b9, 0x281de584, 0xf86745c3, 0x484e25fe, + 0x5892054c, 0xe8bb6571, 0x38c1c536, 0x88e8a50b, 0xdfc7d428, + 0x6feeb415, 0xbf941452, 0x0fbd746f, 0x1f6154dd, 0xaf4834e0, + 0x7f3294a7, 0xcf1bf49a, 0x1e8ca418, 0xaea5c425, 0x7edf6462, + 0xcef6045f, 0xde2a24ed, 0x6e0344d0, 0xbe79e497, 0x0e5084aa, + 0x5d503448, 0xed795475, 0x3d03f432, 0x8d2a940f, 0x9df6b4bd, + 0x2ddfd480, 0xfda574c7, 0x4d8c14fa, 0x9c1b4478, 0x2c322445, + 0xfc488402, 0x4c61e43f, 0x5cbdc48d, 0xec94a4b0, 0x3cee04f7, + 0x8cc764ca}, + {0x00000000, 0xa5d35ccb, 0x0ba1c84d, 0xae729486, 0x1642919b, + 0xb391cd50, 0x1de359d6, 0xb830051d, 0x6d8253ec, 0xc8510f27, + 0x66239ba1, 0xc3f0c76a, 0x7bc0c277, 0xde139ebc, 0x70610a3a, + 0xd5b256f1, 0x9b02d603, 0x3ed18ac8, 0x90a31e4e, 0x35704285, + 0x8d404798, 0x28931b53, 0x86e18fd5, 0x2332d31e, 0xf68085ef, + 0x5353d924, 0xfd214da2, 0x58f21169, 0xe0c21474, 0x451148bf, + 0xeb63dc39, 0x4eb080f2, 0x3605ac07, 0x93d6f0cc, 0x3da4644a, + 0x98773881, 0x20473d9c, 0x85946157, 0x2be6f5d1, 0x8e35a91a, + 0x5b87ffeb, 0xfe54a320, 0x502637a6, 0xf5f56b6d, 0x4dc56e70, + 0xe81632bb, 0x4664a63d, 0xe3b7faf6, 0xad077a04, 0x08d426cf, + 0xa6a6b249, 0x0375ee82, 0xbb45eb9f, 0x1e96b754, 0xb0e423d2, + 0x15377f19, 0xc08529e8, 0x65567523, 0xcb24e1a5, 0x6ef7bd6e, + 0xd6c7b873, 0x7314e4b8, 0xdd66703e, 0x78b52cf5, 0x6c0a580f, + 0xc9d904c4, 0x67ab9042, 0xc278cc89, 0x7a48c994, 0xdf9b955f, + 0x71e901d9, 0xd43a5d12, 0x01880be3, 0xa45b5728, 0x0a29c3ae, + 0xaffa9f65, 0x17ca9a78, 0xb219c6b3, 0x1c6b5235, 0xb9b80efe, + 0xf7088e0c, 0x52dbd2c7, 0xfca94641, 0x597a1a8a, 0xe14a1f97, + 0x4499435c, 0xeaebd7da, 0x4f388b11, 0x9a8adde0, 0x3f59812b, + 0x912b15ad, 0x34f84966, 0x8cc84c7b, 0x291b10b0, 0x87698436, + 0x22bad8fd, 0x5a0ff408, 0xffdca8c3, 0x51ae3c45, 0xf47d608e, + 0x4c4d6593, 0xe99e3958, 0x47ecadde, 0xe23ff115, 0x378da7e4, + 0x925efb2f, 0x3c2c6fa9, 0x99ff3362, 0x21cf367f, 0x841c6ab4, + 0x2a6efe32, 0x8fbda2f9, 0xc10d220b, 0x64de7ec0, 0xcaacea46, + 0x6f7fb68d, 0xd74fb390, 0x729cef5b, 0xdcee7bdd, 0x793d2716, + 0xac8f71e7, 0x095c2d2c, 0xa72eb9aa, 0x02fde561, 0xbacde07c, + 0x1f1ebcb7, 0xb16c2831, 0x14bf74fa, 0xd814b01e, 0x7dc7ecd5, + 0xd3b57853, 0x76662498, 0xce562185, 0x6b857d4e, 0xc5f7e9c8, + 0x6024b503, 0xb596e3f2, 0x1045bf39, 0xbe372bbf, 0x1be47774, + 0xa3d47269, 0x06072ea2, 0xa875ba24, 0x0da6e6ef, 0x4316661d, + 0xe6c53ad6, 0x48b7ae50, 0xed64f29b, 0x5554f786, 0xf087ab4d, + 0x5ef53fcb, 0xfb266300, 0x2e9435f1, 0x8b47693a, 0x2535fdbc, + 0x80e6a177, 0x38d6a46a, 0x9d05f8a1, 0x33776c27, 0x96a430ec, + 0xee111c19, 0x4bc240d2, 0xe5b0d454, 0x4063889f, 0xf8538d82, + 0x5d80d149, 0xf3f245cf, 0x56211904, 0x83934ff5, 0x2640133e, + 0x883287b8, 0x2de1db73, 0x95d1de6e, 0x300282a5, 0x9e701623, + 0x3ba34ae8, 0x7513ca1a, 0xd0c096d1, 0x7eb20257, 0xdb615e9c, + 0x63515b81, 0xc682074a, 0x68f093cc, 0xcd23cf07, 0x189199f6, + 0xbd42c53d, 0x133051bb, 0xb6e30d70, 0x0ed3086d, 0xab0054a6, + 0x0572c020, 0xa0a19ceb, 0xb41ee811, 0x11cdb4da, 0xbfbf205c, + 0x1a6c7c97, 0xa25c798a, 0x078f2541, 0xa9fdb1c7, 0x0c2eed0c, + 0xd99cbbfd, 0x7c4fe736, 0xd23d73b0, 0x77ee2f7b, 0xcfde2a66, + 0x6a0d76ad, 0xc47fe22b, 0x61acbee0, 0x2f1c3e12, 0x8acf62d9, + 0x24bdf65f, 0x816eaa94, 0x395eaf89, 0x9c8df342, 0x32ff67c4, + 0x972c3b0f, 0x429e6dfe, 0xe74d3135, 0x493fa5b3, 0xececf978, + 0x54dcfc65, 0xf10fa0ae, 0x5f7d3428, 0xfaae68e3, 0x821b4416, + 0x27c818dd, 0x89ba8c5b, 0x2c69d090, 0x9459d58d, 0x318a8946, + 0x9ff81dc0, 0x3a2b410b, 0xef9917fa, 0x4a4a4b31, 0xe438dfb7, + 0x41eb837c, 0xf9db8661, 0x5c08daaa, 0xf27a4e2c, 0x57a912e7, + 0x19199215, 0xbccacede, 0x12b85a58, 0xb76b0693, 0x0f5b038e, + 0xaa885f45, 0x04facbc3, 0xa1299708, 0x749bc1f9, 0xd1489d32, + 0x7f3a09b4, 0xdae9557f, 0x62d95062, 0xc70a0ca9, 0x6978982f, + 0xccabc4e4}, + {0x00000000, 0xb40b77a6, 0x29119f97, 0x9d1ae831, 0x13244ff4, + 0xa72f3852, 0x3a35d063, 0x8e3ea7c5, 0x674eef33, 0xd3459895, + 0x4e5f70a4, 0xfa540702, 0x746aa0c7, 0xc061d761, 0x5d7b3f50, + 0xe97048f6, 0xce9cde67, 0x7a97a9c1, 0xe78d41f0, 0x53863656, + 0xddb89193, 0x69b3e635, 0xf4a90e04, 0x40a279a2, 0xa9d23154, + 0x1dd946f2, 0x80c3aec3, 0x34c8d965, 0xbaf67ea0, 0x0efd0906, + 0x93e7e137, 0x27ec9691, 0x9c39bdcf, 0x2832ca69, 0xb5282258, + 0x012355fe, 0x8f1df23b, 0x3b16859d, 0xa60c6dac, 0x12071a0a, + 0xfb7752fc, 0x4f7c255a, 0xd266cd6b, 0x666dbacd, 0xe8531d08, + 0x5c586aae, 0xc142829f, 0x7549f539, 0x52a563a8, 0xe6ae140e, + 0x7bb4fc3f, 0xcfbf8b99, 0x41812c5c, 0xf58a5bfa, 0x6890b3cb, + 0xdc9bc46d, 0x35eb8c9b, 0x81e0fb3d, 0x1cfa130c, 0xa8f164aa, + 0x26cfc36f, 0x92c4b4c9, 0x0fde5cf8, 0xbbd52b5e, 0x79750b44, + 0xcd7e7ce2, 0x506494d3, 0xe46fe375, 0x6a5144b0, 0xde5a3316, + 0x4340db27, 0xf74bac81, 0x1e3be477, 0xaa3093d1, 0x372a7be0, + 0x83210c46, 0x0d1fab83, 0xb914dc25, 0x240e3414, 0x900543b2, + 0xb7e9d523, 0x03e2a285, 0x9ef84ab4, 0x2af33d12, 0xa4cd9ad7, + 0x10c6ed71, 0x8ddc0540, 0x39d772e6, 0xd0a73a10, 0x64ac4db6, + 0xf9b6a587, 0x4dbdd221, 0xc38375e4, 0x77880242, 0xea92ea73, + 0x5e999dd5, 0xe54cb68b, 0x5147c12d, 0xcc5d291c, 0x78565eba, + 0xf668f97f, 0x42638ed9, 0xdf7966e8, 0x6b72114e, 0x820259b8, + 0x36092e1e, 0xab13c62f, 0x1f18b189, 0x9126164c, 0x252d61ea, + 0xb83789db, 0x0c3cfe7d, 0x2bd068ec, 0x9fdb1f4a, 0x02c1f77b, + 0xb6ca80dd, 0x38f42718, 0x8cff50be, 0x11e5b88f, 0xa5eecf29, + 0x4c9e87df, 0xf895f079, 0x658f1848, 0xd1846fee, 0x5fbac82b, + 0xebb1bf8d, 0x76ab57bc, 0xc2a0201a, 0xf2ea1688, 0x46e1612e, + 0xdbfb891f, 0x6ff0feb9, 0xe1ce597c, 0x55c52eda, 0xc8dfc6eb, + 0x7cd4b14d, 0x95a4f9bb, 0x21af8e1d, 0xbcb5662c, 0x08be118a, + 0x8680b64f, 0x328bc1e9, 0xaf9129d8, 0x1b9a5e7e, 0x3c76c8ef, + 0x887dbf49, 0x15675778, 0xa16c20de, 0x2f52871b, 0x9b59f0bd, + 0x0643188c, 0xb2486f2a, 0x5b3827dc, 0xef33507a, 0x7229b84b, + 0xc622cfed, 0x481c6828, 0xfc171f8e, 0x610df7bf, 0xd5068019, + 0x6ed3ab47, 0xdad8dce1, 0x47c234d0, 0xf3c94376, 0x7df7e4b3, + 0xc9fc9315, 0x54e67b24, 0xe0ed0c82, 0x099d4474, 0xbd9633d2, + 0x208cdbe3, 0x9487ac45, 0x1ab90b80, 0xaeb27c26, 0x33a89417, + 0x87a3e3b1, 0xa04f7520, 0x14440286, 0x895eeab7, 0x3d559d11, + 0xb36b3ad4, 0x07604d72, 0x9a7aa543, 0x2e71d2e5, 0xc7019a13, + 0x730aedb5, 0xee100584, 0x5a1b7222, 0xd425d5e7, 0x602ea241, + 0xfd344a70, 0x493f3dd6, 0x8b9f1dcc, 0x3f946a6a, 0xa28e825b, + 0x1685f5fd, 0x98bb5238, 0x2cb0259e, 0xb1aacdaf, 0x05a1ba09, + 0xecd1f2ff, 0x58da8559, 0xc5c06d68, 0x71cb1ace, 0xfff5bd0b, + 0x4bfecaad, 0xd6e4229c, 0x62ef553a, 0x4503c3ab, 0xf108b40d, + 0x6c125c3c, 0xd8192b9a, 0x56278c5f, 0xe22cfbf9, 0x7f3613c8, + 0xcb3d646e, 0x224d2c98, 0x96465b3e, 0x0b5cb30f, 0xbf57c4a9, + 0x3169636c, 0x856214ca, 0x1878fcfb, 0xac738b5d, 0x17a6a003, + 0xa3add7a5, 0x3eb73f94, 0x8abc4832, 0x0482eff7, 0xb0899851, + 0x2d937060, 0x999807c6, 0x70e84f30, 0xc4e33896, 0x59f9d0a7, + 0xedf2a701, 0x63cc00c4, 0xd7c77762, 0x4add9f53, 0xfed6e8f5, + 0xd93a7e64, 0x6d3109c2, 0xf02be1f3, 0x44209655, 0xca1e3190, + 0x7e154636, 0xe30fae07, 0x5704d9a1, 0xbe749157, 0x0a7fe6f1, + 0x97650ec0, 0x236e7966, 0xad50dea3, 0x195ba905, 0x84414134, + 0x304a3692}, + {0x00000000, 0x9e00aacc, 0x7d072542, 0xe3078f8e, 0xfa0e4a84, + 0x640ee048, 0x87096fc6, 0x1909c50a, 0xb51be5d3, 0x2b1b4f1f, + 0xc81cc091, 0x561c6a5d, 0x4f15af57, 0xd115059b, 0x32128a15, + 0xac1220d9, 0x2b31bb7c, 0xb53111b0, 0x56369e3e, 0xc83634f2, + 0xd13ff1f8, 0x4f3f5b34, 0xac38d4ba, 0x32387e76, 0x9e2a5eaf, + 0x002af463, 0xe32d7bed, 0x7d2dd121, 0x6424142b, 0xfa24bee7, + 0x19233169, 0x87239ba5, 0x566276f9, 0xc862dc35, 0x2b6553bb, + 0xb565f977, 0xac6c3c7d, 0x326c96b1, 0xd16b193f, 0x4f6bb3f3, + 0xe379932a, 0x7d7939e6, 0x9e7eb668, 0x007e1ca4, 0x1977d9ae, + 0x87777362, 0x6470fcec, 0xfa705620, 0x7d53cd85, 0xe3536749, + 0x0054e8c7, 0x9e54420b, 0x875d8701, 0x195d2dcd, 0xfa5aa243, + 0x645a088f, 0xc8482856, 0x5648829a, 0xb54f0d14, 0x2b4fa7d8, + 0x324662d2, 0xac46c81e, 0x4f414790, 0xd141ed5c, 0xedc29d29, + 0x73c237e5, 0x90c5b86b, 0x0ec512a7, 0x17ccd7ad, 0x89cc7d61, + 0x6acbf2ef, 0xf4cb5823, 0x58d978fa, 0xc6d9d236, 0x25de5db8, + 0xbbdef774, 0xa2d7327e, 0x3cd798b2, 0xdfd0173c, 0x41d0bdf0, + 0xc6f32655, 0x58f38c99, 0xbbf40317, 0x25f4a9db, 0x3cfd6cd1, + 0xa2fdc61d, 0x41fa4993, 0xdffae35f, 0x73e8c386, 0xede8694a, + 0x0eefe6c4, 0x90ef4c08, 0x89e68902, 0x17e623ce, 0xf4e1ac40, + 0x6ae1068c, 0xbba0ebd0, 0x25a0411c, 0xc6a7ce92, 0x58a7645e, + 0x41aea154, 0xdfae0b98, 0x3ca98416, 0xa2a92eda, 0x0ebb0e03, + 0x90bba4cf, 0x73bc2b41, 0xedbc818d, 0xf4b54487, 0x6ab5ee4b, + 0x89b261c5, 0x17b2cb09, 0x909150ac, 0x0e91fa60, 0xed9675ee, + 0x7396df22, 0x6a9f1a28, 0xf49fb0e4, 0x17983f6a, 0x899895a6, + 0x258ab57f, 0xbb8a1fb3, 0x588d903d, 0xc68d3af1, 0xdf84fffb, + 0x41845537, 0xa283dab9, 0x3c837075, 0xda853b53, 0x4485919f, + 0xa7821e11, 0x3982b4dd, 0x208b71d7, 0xbe8bdb1b, 0x5d8c5495, + 0xc38cfe59, 0x6f9ede80, 0xf19e744c, 0x1299fbc2, 0x8c99510e, + 0x95909404, 0x0b903ec8, 0xe897b146, 0x76971b8a, 0xf1b4802f, + 0x6fb42ae3, 0x8cb3a56d, 0x12b30fa1, 0x0bbacaab, 0x95ba6067, + 0x76bdefe9, 0xe8bd4525, 0x44af65fc, 0xdaafcf30, 0x39a840be, + 0xa7a8ea72, 0xbea12f78, 0x20a185b4, 0xc3a60a3a, 0x5da6a0f6, + 0x8ce74daa, 0x12e7e766, 0xf1e068e8, 0x6fe0c224, 0x76e9072e, + 0xe8e9ade2, 0x0bee226c, 0x95ee88a0, 0x39fca879, 0xa7fc02b5, + 0x44fb8d3b, 0xdafb27f7, 0xc3f2e2fd, 0x5df24831, 0xbef5c7bf, + 0x20f56d73, 0xa7d6f6d6, 0x39d65c1a, 0xdad1d394, 0x44d17958, + 0x5dd8bc52, 0xc3d8169e, 0x20df9910, 0xbedf33dc, 0x12cd1305, + 0x8ccdb9c9, 0x6fca3647, 0xf1ca9c8b, 0xe8c35981, 0x76c3f34d, + 0x95c47cc3, 0x0bc4d60f, 0x3747a67a, 0xa9470cb6, 0x4a408338, + 0xd44029f4, 0xcd49ecfe, 0x53494632, 0xb04ec9bc, 0x2e4e6370, + 0x825c43a9, 0x1c5ce965, 0xff5b66eb, 0x615bcc27, 0x7852092d, + 0xe652a3e1, 0x05552c6f, 0x9b5586a3, 0x1c761d06, 0x8276b7ca, + 0x61713844, 0xff719288, 0xe6785782, 0x7878fd4e, 0x9b7f72c0, + 0x057fd80c, 0xa96df8d5, 0x376d5219, 0xd46add97, 0x4a6a775b, + 0x5363b251, 0xcd63189d, 0x2e649713, 0xb0643ddf, 0x6125d083, + 0xff257a4f, 0x1c22f5c1, 0x82225f0d, 0x9b2b9a07, 0x052b30cb, + 0xe62cbf45, 0x782c1589, 0xd43e3550, 0x4a3e9f9c, 0xa9391012, + 0x3739bade, 0x2e307fd4, 0xb030d518, 0x53375a96, 0xcd37f05a, + 0x4a146bff, 0xd414c133, 0x37134ebd, 0xa913e471, 0xb01a217b, + 0x2e1a8bb7, 0xcd1d0439, 0x531daef5, 0xff0f8e2c, 0x610f24e0, + 0x8208ab6e, 0x1c0801a2, 0x0501c4a8, 0x9b016e64, 0x7806e1ea, + 0xe6064b26}}; + #endif - } -}; + +#endif + +#if N == 3 + +#if W == 8 + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0x81256527, 0xd93bcc0f, 0x581ea928, 0x69069e5f, + 0xe823fb78, 0xb03d5250, 0x31183777, 0xd20d3cbe, 0x53285999, + 0x0b36f0b1, 0x8a139596, 0xbb0ba2e1, 0x3a2ec7c6, 0x62306eee, + 0xe3150bc9, 0x7f6b7f3d, 0xfe4e1a1a, 0xa650b332, 0x2775d615, + 0x166de162, 0x97488445, 0xcf562d6d, 0x4e73484a, 0xad664383, + 0x2c4326a4, 0x745d8f8c, 0xf578eaab, 0xc460dddc, 0x4545b8fb, + 0x1d5b11d3, 0x9c7e74f4, 0xfed6fe7a, 0x7ff39b5d, 0x27ed3275, + 0xa6c85752, 0x97d06025, 0x16f50502, 0x4eebac2a, 0xcfcec90d, + 0x2cdbc2c4, 0xadfea7e3, 0xf5e00ecb, 0x74c56bec, 0x45dd5c9b, + 0xc4f839bc, 0x9ce69094, 0x1dc3f5b3, 0x81bd8147, 0x0098e460, + 0x58864d48, 0xd9a3286f, 0xe8bb1f18, 0x699e7a3f, 0x3180d317, + 0xb0a5b630, 0x53b0bdf9, 0xd295d8de, 0x8a8b71f6, 0x0bae14d1, + 0x3ab623a6, 0xbb934681, 0xe38defa9, 0x62a88a8e, 0x26dcfab5, + 0xa7f99f92, 0xffe736ba, 0x7ec2539d, 0x4fda64ea, 0xceff01cd, + 0x96e1a8e5, 0x17c4cdc2, 0xf4d1c60b, 0x75f4a32c, 0x2dea0a04, + 0xaccf6f23, 0x9dd75854, 0x1cf23d73, 0x44ec945b, 0xc5c9f17c, + 0x59b78588, 0xd892e0af, 0x808c4987, 0x01a92ca0, 0x30b11bd7, + 0xb1947ef0, 0xe98ad7d8, 0x68afb2ff, 0x8bbab936, 0x0a9fdc11, + 0x52817539, 0xd3a4101e, 0xe2bc2769, 0x6399424e, 0x3b87eb66, + 0xbaa28e41, 0xd80a04cf, 0x592f61e8, 0x0131c8c0, 0x8014ade7, + 0xb10c9a90, 0x3029ffb7, 0x6837569f, 0xe91233b8, 0x0a073871, + 0x8b225d56, 0xd33cf47e, 0x52199159, 0x6301a62e, 0xe224c309, + 0xba3a6a21, 0x3b1f0f06, 0xa7617bf2, 0x26441ed5, 0x7e5ab7fd, + 0xff7fd2da, 0xce67e5ad, 0x4f42808a, 0x175c29a2, 0x96794c85, + 0x756c474c, 0xf449226b, 0xac578b43, 0x2d72ee64, 0x1c6ad913, + 0x9d4fbc34, 0xc551151c, 0x4474703b, 0x4db9f56a, 0xcc9c904d, + 0x94823965, 0x15a75c42, 0x24bf6b35, 0xa59a0e12, 0xfd84a73a, + 0x7ca1c21d, 0x9fb4c9d4, 0x1e91acf3, 0x468f05db, 0xc7aa60fc, + 0xf6b2578b, 0x779732ac, 0x2f899b84, 0xaeacfea3, 0x32d28a57, + 0xb3f7ef70, 0xebe94658, 0x6acc237f, 0x5bd41408, 0xdaf1712f, + 0x82efd807, 0x03cabd20, 0xe0dfb6e9, 0x61fad3ce, 0x39e47ae6, + 0xb8c11fc1, 0x89d928b6, 0x08fc4d91, 0x50e2e4b9, 0xd1c7819e, + 0xb36f0b10, 0x324a6e37, 0x6a54c71f, 0xeb71a238, 0xda69954f, + 0x5b4cf068, 0x03525940, 0x82773c67, 0x616237ae, 0xe0475289, + 0xb859fba1, 0x397c9e86, 0x0864a9f1, 0x8941ccd6, 0xd15f65fe, + 0x507a00d9, 0xcc04742d, 0x4d21110a, 0x153fb822, 0x941add05, + 0xa502ea72, 0x24278f55, 0x7c39267d, 0xfd1c435a, 0x1e094893, + 0x9f2c2db4, 0xc732849c, 0x4617e1bb, 0x770fd6cc, 0xf62ab3eb, + 0xae341ac3, 0x2f117fe4, 0x6b650fdf, 0xea406af8, 0xb25ec3d0, + 0x337ba6f7, 0x02639180, 0x8346f4a7, 0xdb585d8f, 0x5a7d38a8, + 0xb9683361, 0x384d5646, 0x6053ff6e, 0xe1769a49, 0xd06ead3e, + 0x514bc819, 0x09556131, 0x88700416, 0x140e70e2, 0x952b15c5, + 0xcd35bced, 0x4c10d9ca, 0x7d08eebd, 0xfc2d8b9a, 0xa43322b2, + 0x25164795, 0xc6034c5c, 0x4726297b, 0x1f388053, 0x9e1de574, + 0xaf05d203, 0x2e20b724, 0x763e1e0c, 0xf71b7b2b, 0x95b3f1a5, + 0x14969482, 0x4c883daa, 0xcdad588d, 0xfcb56ffa, 0x7d900add, + 0x258ea3f5, 0xa4abc6d2, 0x47becd1b, 0xc69ba83c, 0x9e850114, + 0x1fa06433, 0x2eb85344, 0xaf9d3663, 0xf7839f4b, 0x76a6fa6c, + 0xead88e98, 0x6bfdebbf, 0x33e34297, 0xb2c627b0, 0x83de10c7, + 0x02fb75e0, 0x5ae5dcc8, 0xdbc0b9ef, 0x38d5b226, 0xb9f0d701, + 0xe1ee7e29, 0x60cb1b0e, 0x51d32c79, 0xd0f6495e, 0x88e8e076, + 0x09cd8551}, + {0x00000000, 0x9b73ead4, 0xed96d3e9, 0x76e5393d, 0x005ca193, + 0x9b2f4b47, 0xedca727a, 0x76b998ae, 0x00b94326, 0x9bcaa9f2, + 0xed2f90cf, 0x765c7a1b, 0x00e5e2b5, 0x9b960861, 0xed73315c, + 0x7600db88, 0x0172864c, 0x9a016c98, 0xece455a5, 0x7797bf71, + 0x012e27df, 0x9a5dcd0b, 0xecb8f436, 0x77cb1ee2, 0x01cbc56a, + 0x9ab82fbe, 0xec5d1683, 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0x205971c7, 0xc1777ba3, 0x2e25cd42, + 0xc4a31020, 0x2bf1a6c1, 0x14e696e1, 0xfbb42000, 0x1132fd62, + 0xfe604b83, 0x1f4e41e7, 0xf01cf706, 0x1a9a2a64, 0xf5c89c85, + 0x03b738ed, 0xece58e0c, 0x0663536e, 0xe931e58f, 0x081fefeb, + 0xe74d590a, 0x0dcb8468, 0xe2993289, 0x3a45caf9, 0xd5177c18, + 0x3f91a17a, 0xd0c3179b, 0x31ed1dff, 0xdebfab1e, 0x3439767c, + 0xdb6bc09d, 0x2d1464f5, 0xc246d214, 0x28c00f76, 0xc792b997, + 0x26bcb3f3, 0xc9ee0512, 0x2368d870, 0xcc3a6e91, 0x49a02ed1, + 0xa6f29830, 0x4c744552, 0xa326f3b3, 0x4208f9d7, 0xad5a4f36, + 0x47dc9254, 0xa88e24b5, 0x5ef180dd, 0xb1a3363c, 0x5b25eb5e, + 0xb4775dbf, 0x555957db, 0xba0be13a, 0x508d3c58, 0xbfdf8ab9, + 0x670372c9, 0x8851c428, 0x62d7194a, 0x8d85afab, 0x6caba5cf, + 0x83f9132e, 0x697fce4c, 0x862d78ad, 0x7052dcc5, 0x9f006a24, + 0x7586b746, 0x9ad401a7, 0x7bfa0bc3, 0x94a8bd22, 0x7e2e6040, + 0x917cd6a1}, + {0x00000000, 0x87a6cb43, 0xd43c90c7, 0x539a5b84, 0x730827cf, + 0xf4aeec8c, 0xa734b708, 0x20927c4b, 0xe6104f9e, 0x61b684dd, + 0x322cdf59, 0xb58a141a, 0x95186851, 0x12bea312, 0x4124f896, + 0xc68233d5, 0x1751997d, 0x90f7523e, 0xc36d09ba, 0x44cbc2f9, + 0x6459beb2, 0xe3ff75f1, 0xb0652e75, 0x37c3e536, 0xf141d6e3, + 0x76e71da0, 0x257d4624, 0xa2db8d67, 0x8249f12c, 0x05ef3a6f, + 0x567561eb, 0xd1d3aaa8, 0x2ea332fa, 0xa905f9b9, 0xfa9fa23d, + 0x7d39697e, 0x5dab1535, 0xda0dde76, 0x899785f2, 0x0e314eb1, + 0xc8b37d64, 0x4f15b627, 0x1c8feda3, 0x9b2926e0, 0xbbbb5aab, + 0x3c1d91e8, 0x6f87ca6c, 0xe821012f, 0x39f2ab87, 0xbe5460c4, + 0xedce3b40, 0x6a68f003, 0x4afa8c48, 0xcd5c470b, 0x9ec61c8f, + 0x1960d7cc, 0xdfe2e419, 0x58442f5a, 0x0bde74de, 0x8c78bf9d, + 0xaceac3d6, 0x2b4c0895, 0x78d65311, 0xff709852, 0x5d4665f4, + 0xdae0aeb7, 0x897af533, 0x0edc3e70, 0x2e4e423b, 0xa9e88978, + 0xfa72d2fc, 0x7dd419bf, 0xbb562a6a, 0x3cf0e129, 0x6f6abaad, + 0xe8cc71ee, 0xc85e0da5, 0x4ff8c6e6, 0x1c629d62, 0x9bc45621, + 0x4a17fc89, 0xcdb137ca, 0x9e2b6c4e, 0x198da70d, 0x391fdb46, + 0xbeb91005, 0xed234b81, 0x6a8580c2, 0xac07b317, 0x2ba17854, + 0x783b23d0, 0xff9de893, 0xdf0f94d8, 0x58a95f9b, 0x0b33041f, + 0x8c95cf5c, 0x73e5570e, 0xf4439c4d, 0xa7d9c7c9, 0x207f0c8a, + 0x00ed70c1, 0x874bbb82, 0xd4d1e006, 0x53772b45, 0x95f51890, + 0x1253d3d3, 0x41c98857, 0xc66f4314, 0xe6fd3f5f, 0x615bf41c, + 0x32c1af98, 0xb56764db, 0x64b4ce73, 0xe3120530, 0xb0885eb4, + 0x372e95f7, 0x17bce9bc, 0x901a22ff, 0xc380797b, 0x4426b238, + 0x82a481ed, 0x05024aae, 0x5698112a, 0xd13eda69, 0xf1aca622, + 0x760a6d61, 0x259036e5, 0xa236fda6, 0xba8ccbe8, 0x3d2a00ab, + 0x6eb05b2f, 0xe916906c, 0xc984ec27, 0x4e222764, 0x1db87ce0, + 0x9a1eb7a3, 0x5c9c8476, 0xdb3a4f35, 0x88a014b1, 0x0f06dff2, + 0x2f94a3b9, 0xa83268fa, 0xfba8337e, 0x7c0ef83d, 0xaddd5295, + 0x2a7b99d6, 0x79e1c252, 0xfe470911, 0xded5755a, 0x5973be19, + 0x0ae9e59d, 0x8d4f2ede, 0x4bcd1d0b, 0xcc6bd648, 0x9ff18dcc, + 0x1857468f, 0x38c53ac4, 0xbf63f187, 0xecf9aa03, 0x6b5f6140, + 0x942ff912, 0x13893251, 0x401369d5, 0xc7b5a296, 0xe727dedd, + 0x6081159e, 0x331b4e1a, 0xb4bd8559, 0x723fb68c, 0xf5997dcf, + 0xa603264b, 0x21a5ed08, 0x01379143, 0x86915a00, 0xd50b0184, + 0x52adcac7, 0x837e606f, 0x04d8ab2c, 0x5742f0a8, 0xd0e43beb, + 0xf07647a0, 0x77d08ce3, 0x244ad767, 0xa3ec1c24, 0x656e2ff1, + 0xe2c8e4b2, 0xb152bf36, 0x36f47475, 0x1666083e, 0x91c0c37d, + 0xc25a98f9, 0x45fc53ba, 0xe7caae1c, 0x606c655f, 0x33f63edb, + 0xb450f598, 0x94c289d3, 0x13644290, 0x40fe1914, 0xc758d257, + 0x01dae182, 0x867c2ac1, 0xd5e67145, 0x5240ba06, 0x72d2c64d, + 0xf5740d0e, 0xa6ee568a, 0x21489dc9, 0xf09b3761, 0x773dfc22, + 0x24a7a7a6, 0xa3016ce5, 0x839310ae, 0x0435dbed, 0x57af8069, + 0xd0094b2a, 0x168b78ff, 0x912db3bc, 0xc2b7e838, 0x4511237b, + 0x65835f30, 0xe2259473, 0xb1bfcff7, 0x361904b4, 0xc9699ce6, + 0x4ecf57a5, 0x1d550c21, 0x9af3c762, 0xba61bb29, 0x3dc7706a, + 0x6e5d2bee, 0xe9fbe0ad, 0x2f79d378, 0xa8df183b, 0xfb4543bf, + 0x7ce388fc, 0x5c71f4b7, 0xdbd73ff4, 0x884d6470, 0x0febaf33, + 0xde38059b, 0x599eced8, 0x0a04955c, 0x8da25e1f, 0xad302254, + 0x2a96e917, 0x790cb293, 0xfeaa79d0, 0x38284a05, 0xbf8e8146, + 0xec14dac2, 0x6bb21181, 0x4b206dca, 0xcc86a689, 0x9f1cfd0d, + 0x18ba364e}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x0000000000000000, 0x43cba68700000000, 0xc7903cd400000000, + 0x845b9a5300000000, 0xcf27087300000000, 0x8cecaef400000000, + 0x08b734a700000000, 0x4b7c922000000000, 0x9e4f10e600000000, + 0xdd84b66100000000, 0x59df2c3200000000, 0x1a148ab500000000, + 0x5168189500000000, 0x12a3be1200000000, 0x96f8244100000000, + 0xd53382c600000000, 0x7d99511700000000, 0x3e52f79000000000, + 0xba096dc300000000, 0xf9c2cb4400000000, 0xb2be596400000000, + 0xf175ffe300000000, 0x752e65b000000000, 0x36e5c33700000000, + 0xe3d641f100000000, 0xa01de77600000000, 0x24467d2500000000, + 0x678ddba200000000, 0x2cf1498200000000, 0x6f3aef0500000000, + 0xeb61755600000000, 0xa8aad3d100000000, 0xfa32a32e00000000, + 0xb9f905a900000000, 0x3da29ffa00000000, 0x7e69397d00000000, + 0x3515ab5d00000000, 0x76de0dda00000000, 0xf285978900000000, + 0xb14e310e00000000, 0x647db3c800000000, 0x27b6154f00000000, + 0xa3ed8f1c00000000, 0xe026299b00000000, 0xab5abbbb00000000, + 0xe8911d3c00000000, 0x6cca876f00000000, 0x2f0121e800000000, + 0x87abf23900000000, 0xc46054be00000000, 0x403bceed00000000, + 0x03f0686a00000000, 0x488cfa4a00000000, 0x0b475ccd00000000, + 0x8f1cc69e00000000, 0xccd7601900000000, 0x19e4e2df00000000, + 0x5a2f445800000000, 0xde74de0b00000000, 0x9dbf788c00000000, + 0xd6c3eaac00000000, 0x95084c2b00000000, 0x1153d67800000000, + 0x529870ff00000000, 0xf465465d00000000, 0xb7aee0da00000000, + 0x33f57a8900000000, 0x703edc0e00000000, 0x3b424e2e00000000, + 0x7889e8a900000000, 0xfcd272fa00000000, 0xbf19d47d00000000, + 0x6a2a56bb00000000, 0x29e1f03c00000000, 0xadba6a6f00000000, + 0xee71cce800000000, 0xa50d5ec800000000, 0xe6c6f84f00000000, + 0x629d621c00000000, 0x2156c49b00000000, 0x89fc174a00000000, + 0xca37b1cd00000000, 0x4e6c2b9e00000000, 0x0da78d1900000000, + 0x46db1f3900000000, 0x0510b9be00000000, 0x814b23ed00000000, + 0xc280856a00000000, 0x17b307ac00000000, 0x5478a12b00000000, + 0xd0233b7800000000, 0x93e89dff00000000, 0xd8940fdf00000000, + 0x9b5fa95800000000, 0x1f04330b00000000, 0x5ccf958c00000000, + 0x0e57e57300000000, 0x4d9c43f400000000, 0xc9c7d9a700000000, + 0x8a0c7f2000000000, 0xc170ed0000000000, 0x82bb4b8700000000, + 0x06e0d1d400000000, 0x452b775300000000, 0x9018f59500000000, + 0xd3d3531200000000, 0x5788c94100000000, 0x14436fc600000000, + 0x5f3ffde600000000, 0x1cf45b6100000000, 0x98afc13200000000, + 0xdb6467b500000000, 0x73ceb46400000000, 0x300512e300000000, + 0xb45e88b000000000, 0xf7952e3700000000, 0xbce9bc1700000000, + 0xff221a9000000000, 0x7b7980c300000000, 0x38b2264400000000, + 0xed81a48200000000, 0xae4a020500000000, 0x2a11985600000000, + 0x69da3ed100000000, 0x22a6acf100000000, 0x616d0a7600000000, + 0xe536902500000000, 0xa6fd36a200000000, 0xe8cb8cba00000000, + 0xab002a3d00000000, 0x2f5bb06e00000000, 0x6c9016e900000000, + 0x27ec84c900000000, 0x6427224e00000000, 0xe07cb81d00000000, + 0xa3b71e9a00000000, 0x76849c5c00000000, 0x354f3adb00000000, + 0xb114a08800000000, 0xf2df060f00000000, 0xb9a3942f00000000, + 0xfa6832a800000000, 0x7e33a8fb00000000, 0x3df80e7c00000000, + 0x9552ddad00000000, 0xd6997b2a00000000, 0x52c2e17900000000, + 0x110947fe00000000, 0x5a75d5de00000000, 0x19be735900000000, + 0x9de5e90a00000000, 0xde2e4f8d00000000, 0x0b1dcd4b00000000, + 0x48d66bcc00000000, 0xcc8df19f00000000, 0x8f46571800000000, + 0xc43ac53800000000, 0x87f163bf00000000, 0x03aaf9ec00000000, + 0x40615f6b00000000, 0x12f92f9400000000, 0x5132891300000000, + 0xd569134000000000, 0x96a2b5c700000000, 0xddde27e700000000, + 0x9e15816000000000, 0x1a4e1b3300000000, 0x5985bdb400000000, + 0x8cb63f7200000000, 0xcf7d99f500000000, 0x4b2603a600000000, + 0x08eda52100000000, 0x4391370100000000, 0x005a918600000000, + 0x84010bd500000000, 0xc7caad5200000000, 0x6f607e8300000000, + 0x2cabd80400000000, 0xa8f0425700000000, 0xeb3be4d000000000, + 0xa04776f000000000, 0xe38cd07700000000, 0x67d74a2400000000, + 0x241ceca300000000, 0xf12f6e6500000000, 0xb2e4c8e200000000, + 0x36bf52b100000000, 0x7574f43600000000, 0x3e08661600000000, + 0x7dc3c09100000000, 0xf9985ac200000000, 0xba53fc4500000000, + 0x1caecae700000000, 0x5f656c6000000000, 0xdb3ef63300000000, + 0x98f550b400000000, 0xd389c29400000000, 0x9042641300000000, + 0x1419fe4000000000, 0x57d258c700000000, 0x82e1da0100000000, + 0xc12a7c8600000000, 0x4571e6d500000000, 0x06ba405200000000, + 0x4dc6d27200000000, 0x0e0d74f500000000, 0x8a56eea600000000, + 0xc99d482100000000, 0x61379bf000000000, 0x22fc3d7700000000, + 0xa6a7a72400000000, 0xe56c01a300000000, 0xae10938300000000, + 0xeddb350400000000, 0x6980af5700000000, 0x2a4b09d000000000, + 0xff788b1600000000, 0xbcb32d9100000000, 0x38e8b7c200000000, + 0x7b23114500000000, 0x305f836500000000, 0x739425e200000000, + 0xf7cfbfb100000000, 0xb404193600000000, 0xe69c69c900000000, + 0xa557cf4e00000000, 0x210c551d00000000, 0x62c7f39a00000000, + 0x29bb61ba00000000, 0x6a70c73d00000000, 0xee2b5d6e00000000, + 0xade0fbe900000000, 0x78d3792f00000000, 0x3b18dfa800000000, + 0xbf4345fb00000000, 0xfc88e37c00000000, 0xb7f4715c00000000, + 0xf43fd7db00000000, 0x70644d8800000000, 0x33afeb0f00000000, + 0x9b0538de00000000, 0xd8ce9e5900000000, 0x5c95040a00000000, + 0x1f5ea28d00000000, 0x542230ad00000000, 0x17e9962a00000000, + 0x93b20c7900000000, 0xd079aafe00000000, 0x054a283800000000, + 0x46818ebf00000000, 0xc2da14ec00000000, 0x8111b26b00000000, + 0xca6d204b00000000, 0x89a686cc00000000, 0x0dfd1c9f00000000, + 0x4e36ba1800000000}, + {0x0000000000000000, 0xe1b652ef00000000, 0x836bd40500000000, + 0x62dd86ea00000000, 0x06d7a80b00000000, 0xe761fae400000000, + 0x85bc7c0e00000000, 0x640a2ee100000000, 0x0cae511700000000, + 0xed1803f800000000, 0x8fc5851200000000, 0x6e73d7fd00000000, + 0x0a79f91c00000000, 0xebcfabf300000000, 0x89122d1900000000, + 0x68a47ff600000000, 0x185ca32e00000000, 0xf9eaf1c100000000, + 0x9b37772b00000000, 0x7a8125c400000000, 0x1e8b0b2500000000, + 0xff3d59ca00000000, 0x9de0df2000000000, 0x7c568dcf00000000, + 0x14f2f23900000000, 0xf544a0d600000000, 0x9799263c00000000, + 0x762f74d300000000, 0x12255a3200000000, 0xf39308dd00000000, + 0x914e8e3700000000, 0x70f8dcd800000000, 0x30b8465d00000000, + 0xd10e14b200000000, 0xb3d3925800000000, 0x5265c0b700000000, + 0x366fee5600000000, 0xd7d9bcb900000000, 0xb5043a5300000000, + 0x54b268bc00000000, 0x3c16174a00000000, 0xdda045a500000000, + 0xbf7dc34f00000000, 0x5ecb91a000000000, 0x3ac1bf4100000000, + 0xdb77edae00000000, 0xb9aa6b4400000000, 0x581c39ab00000000, + 0x28e4e57300000000, 0xc952b79c00000000, 0xab8f317600000000, + 0x4a39639900000000, 0x2e334d7800000000, 0xcf851f9700000000, + 0xad58997d00000000, 0x4ceecb9200000000, 0x244ab46400000000, + 0xc5fce68b00000000, 0xa721606100000000, 0x4697328e00000000, + 0x229d1c6f00000000, 0xc32b4e8000000000, 0xa1f6c86a00000000, + 0x40409a8500000000, 0x60708dba00000000, 0x81c6df5500000000, + 0xe31b59bf00000000, 0x02ad0b5000000000, 0x66a725b100000000, + 0x8711775e00000000, 0xe5ccf1b400000000, 0x047aa35b00000000, + 0x6cdedcad00000000, 0x8d688e4200000000, 0xefb508a800000000, + 0x0e035a4700000000, 0x6a0974a600000000, 0x8bbf264900000000, + 0xe962a0a300000000, 0x08d4f24c00000000, 0x782c2e9400000000, + 0x999a7c7b00000000, 0xfb47fa9100000000, 0x1af1a87e00000000, + 0x7efb869f00000000, 0x9f4dd47000000000, 0xfd90529a00000000, + 0x1c26007500000000, 0x74827f8300000000, 0x95342d6c00000000, + 0xf7e9ab8600000000, 0x165ff96900000000, 0x7255d78800000000, + 0x93e3856700000000, 0xf13e038d00000000, 0x1088516200000000, + 0x50c8cbe700000000, 0xb17e990800000000, 0xd3a31fe200000000, + 0x32154d0d00000000, 0x561f63ec00000000, 0xb7a9310300000000, + 0xd574b7e900000000, 0x34c2e50600000000, 0x5c669af000000000, + 0xbdd0c81f00000000, 0xdf0d4ef500000000, 0x3ebb1c1a00000000, + 0x5ab132fb00000000, 0xbb07601400000000, 0xd9dae6fe00000000, + 0x386cb41100000000, 0x489468c900000000, 0xa9223a2600000000, + 0xcbffbccc00000000, 0x2a49ee2300000000, 0x4e43c0c200000000, + 0xaff5922d00000000, 0xcd2814c700000000, 0x2c9e462800000000, + 0x443a39de00000000, 0xa58c6b3100000000, 0xc751eddb00000000, + 0x26e7bf3400000000, 0x42ed91d500000000, 0xa35bc33a00000000, + 0xc18645d000000000, 0x2030173f00000000, 0x81e66bae00000000, + 0x6050394100000000, 0x028dbfab00000000, 0xe33bed4400000000, + 0x8731c3a500000000, 0x6687914a00000000, 0x045a17a000000000, + 0xe5ec454f00000000, 0x8d483ab900000000, 0x6cfe685600000000, + 0x0e23eebc00000000, 0xef95bc5300000000, 0x8b9f92b200000000, + 0x6a29c05d00000000, 0x08f446b700000000, 0xe942145800000000, + 0x99bac88000000000, 0x780c9a6f00000000, 0x1ad11c8500000000, + 0xfb674e6a00000000, 0x9f6d608b00000000, 0x7edb326400000000, + 0x1c06b48e00000000, 0xfdb0e66100000000, 0x9514999700000000, + 0x74a2cb7800000000, 0x167f4d9200000000, 0xf7c91f7d00000000, + 0x93c3319c00000000, 0x7275637300000000, 0x10a8e59900000000, + 0xf11eb77600000000, 0xb15e2df300000000, 0x50e87f1c00000000, + 0x3235f9f600000000, 0xd383ab1900000000, 0xb78985f800000000, + 0x563fd71700000000, 0x34e251fd00000000, 0xd554031200000000, + 0xbdf07ce400000000, 0x5c462e0b00000000, 0x3e9ba8e100000000, + 0xdf2dfa0e00000000, 0xbb27d4ef00000000, 0x5a91860000000000, + 0x384c00ea00000000, 0xd9fa520500000000, 0xa9028edd00000000, + 0x48b4dc3200000000, 0x2a695ad800000000, 0xcbdf083700000000, + 0xafd526d600000000, 0x4e63743900000000, 0x2cbef2d300000000, + 0xcd08a03c00000000, 0xa5acdfca00000000, 0x441a8d2500000000, + 0x26c70bcf00000000, 0xc771592000000000, 0xa37b77c100000000, + 0x42cd252e00000000, 0x2010a3c400000000, 0xc1a6f12b00000000, + 0xe196e61400000000, 0x0020b4fb00000000, 0x62fd321100000000, + 0x834b60fe00000000, 0xe7414e1f00000000, 0x06f71cf000000000, + 0x642a9a1a00000000, 0x859cc8f500000000, 0xed38b70300000000, + 0x0c8ee5ec00000000, 0x6e53630600000000, 0x8fe531e900000000, + 0xebef1f0800000000, 0x0a594de700000000, 0x6884cb0d00000000, + 0x893299e200000000, 0xf9ca453a00000000, 0x187c17d500000000, + 0x7aa1913f00000000, 0x9b17c3d000000000, 0xff1ded3100000000, + 0x1eabbfde00000000, 0x7c76393400000000, 0x9dc06bdb00000000, + 0xf564142d00000000, 0x14d246c200000000, 0x760fc02800000000, + 0x97b992c700000000, 0xf3b3bc2600000000, 0x1205eec900000000, + 0x70d8682300000000, 0x916e3acc00000000, 0xd12ea04900000000, + 0x3098f2a600000000, 0x5245744c00000000, 0xb3f326a300000000, + 0xd7f9084200000000, 0x364f5aad00000000, 0x5492dc4700000000, + 0xb5248ea800000000, 0xdd80f15e00000000, 0x3c36a3b100000000, + 0x5eeb255b00000000, 0xbf5d77b400000000, 0xdb57595500000000, + 0x3ae10bba00000000, 0x583c8d5000000000, 0xb98adfbf00000000, + 0xc972036700000000, 0x28c4518800000000, 0x4a19d76200000000, + 0xabaf858d00000000, 0xcfa5ab6c00000000, 0x2e13f98300000000, + 0x4cce7f6900000000, 0xad782d8600000000, 0xc5dc527000000000, + 0x246a009f00000000, 0x46b7867500000000, 0xa701d49a00000000, + 0xc30bfa7b00000000, 0x22bda89400000000, 0x40602e7e00000000, + 0xa1d67c9100000000}, + {0x0000000000000000, 0x5880e2d700000000, 0xf106b47400000000, + 0xa98656a300000000, 0xe20d68e900000000, 0xba8d8a3e00000000, + 0x130bdc9d00000000, 0x4b8b3e4a00000000, 0x851da10900000000, + 0xdd9d43de00000000, 0x741b157d00000000, 0x2c9bf7aa00000000, + 0x6710c9e000000000, 0x3f902b3700000000, 0x96167d9400000000, + 0xce969f4300000000, 0x0a3b421300000000, 0x52bba0c400000000, + 0xfb3df66700000000, 0xa3bd14b000000000, 0xe8362afa00000000, + 0xb0b6c82d00000000, 0x19309e8e00000000, 0x41b07c5900000000, + 0x8f26e31a00000000, 0xd7a601cd00000000, 0x7e20576e00000000, + 0x26a0b5b900000000, 0x6d2b8bf300000000, 0x35ab692400000000, + 0x9c2d3f8700000000, 0xc4addd5000000000, 0x1476842600000000, + 0x4cf666f100000000, 0xe570305200000000, 0xbdf0d28500000000, + 0xf67beccf00000000, 0xaefb0e1800000000, 0x077d58bb00000000, + 0x5ffdba6c00000000, 0x916b252f00000000, 0xc9ebc7f800000000, + 0x606d915b00000000, 0x38ed738c00000000, 0x73664dc600000000, + 0x2be6af1100000000, 0x8260f9b200000000, 0xdae01b6500000000, + 0x1e4dc63500000000, 0x46cd24e200000000, 0xef4b724100000000, + 0xb7cb909600000000, 0xfc40aedc00000000, 0xa4c04c0b00000000, + 0x0d461aa800000000, 0x55c6f87f00000000, 0x9b50673c00000000, + 0xc3d085eb00000000, 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0xb5ca804c00000000, + 0x2b495ad300000000, 0x73cfbdba00000000, 0xed4c672500000000, + 0x0ece795e00000000, 0x904da3c100000000, 0x8af59a5100000000, + 0x147640ce00000000, 0xf7f45eb500000000, 0x6977842a00000000, + 0x31f1634300000000, 0xaf72b9dc00000000, 0x4cf0a7a700000000, + 0xd2737d3800000000, 0xfcfc687400000000, 0x627fb2eb00000000, + 0x81fdac9000000000, 0x1f7e760f00000000, 0x47f8916600000000, + 0xd97b4bf900000000, 0x3af9558200000000, 0xa47a8f1d00000000, + 0x66e77e1a00000000, 0xf864a48500000000, 0x1be6bafe00000000, + 0x8565606100000000, 0xdde3870800000000, 0x43605d9700000000, + 0xa0e243ec00000000, 0x3e61997300000000, 0x10ee8c3f00000000, + 0x8e6d56a000000000, 0x6def48db00000000, 0xf36c924400000000, + 0xabea752d00000000, 0x3569afb200000000, 0xd6ebb1c900000000, + 0x48686b5600000000}, + {0x0000000000000000, 0xc064281700000000, 0x80c9502e00000000, + 0x40ad783900000000, 0x0093a15c00000000, 0xc0f7894b00000000, + 0x805af17200000000, 0x403ed96500000000, 0x002643b900000000, + 0xc0426bae00000000, 0x80ef139700000000, 0x408b3b8000000000, + 0x00b5e2e500000000, 0xc0d1caf200000000, 0x807cb2cb00000000, + 0x40189adc00000000, 0x414af7a900000000, 0x812edfbe00000000, + 0xc183a78700000000, 0x01e78f9000000000, 0x41d956f500000000, + 0x81bd7ee200000000, 0xc11006db00000000, 0x01742ecc00000000, + 0x416cb41000000000, 0x81089c0700000000, 0xc1a5e43e00000000, + 0x01c1cc2900000000, 0x41ff154c00000000, 0x819b3d5b00000000, + 0xc136456200000000, 0x01526d7500000000, 0xc3929f8800000000, + 0x03f6b79f00000000, 0x435bcfa600000000, 0x833fe7b100000000, + 0xc3013ed400000000, 0x036516c300000000, 0x43c86efa00000000, + 0x83ac46ed00000000, 0xc3b4dc3100000000, 0x03d0f42600000000, + 0x437d8c1f00000000, 0x8319a40800000000, 0xc3277d6d00000000, + 0x0343557a00000000, 0x43ee2d4300000000, 0x838a055400000000, + 0x82d8682100000000, 0x42bc403600000000, 0x0211380f00000000, + 0xc275101800000000, 0x824bc97d00000000, 0x422fe16a00000000, + 0x0282995300000000, 0xc2e6b14400000000, 0x82fe2b9800000000, + 0x429a038f00000000, 0x02377bb600000000, 0xc25353a100000000, + 0x826d8ac400000000, 0x4209a2d300000000, 0x02a4daea00000000, + 0xc2c0f2fd00000000, 0xc7234eca00000000, 0x074766dd00000000, + 0x47ea1ee400000000, 0x878e36f300000000, 0xc7b0ef9600000000, + 0x07d4c78100000000, 0x4779bfb800000000, 0x871d97af00000000, + 0xc7050d7300000000, 0x0761256400000000, 0x47cc5d5d00000000, + 0x87a8754a00000000, 0xc796ac2f00000000, 0x07f2843800000000, + 0x475ffc0100000000, 0x873bd41600000000, 0x8669b96300000000, + 0x460d917400000000, 0x06a0e94d00000000, 0xc6c4c15a00000000, + 0x86fa183f00000000, 0x469e302800000000, 0x0633481100000000, + 0xc657600600000000, 0x864ffada00000000, 0x462bd2cd00000000, + 0x0686aaf400000000, 0xc6e282e300000000, 0x86dc5b8600000000, + 0x46b8739100000000, 0x06150ba800000000, 0xc67123bf00000000, + 0x04b1d14200000000, 0xc4d5f95500000000, 0x8478816c00000000, + 0x441ca97b00000000, 0x0422701e00000000, 0xc446580900000000, + 0x84eb203000000000, 0x448f082700000000, 0x049792fb00000000, + 0xc4f3baec00000000, 0x845ec2d500000000, 0x443aeac200000000, + 0x040433a700000000, 0xc4601bb000000000, 0x84cd638900000000, + 0x44a94b9e00000000, 0x45fb26eb00000000, 0x859f0efc00000000, + 0xc53276c500000000, 0x05565ed200000000, 0x456887b700000000, + 0x850cafa000000000, 0xc5a1d79900000000, 0x05c5ff8e00000000, + 0x45dd655200000000, 0x85b94d4500000000, 0xc514357c00000000, + 0x05701d6b00000000, 0x454ec40e00000000, 0x852aec1900000000, + 0xc587942000000000, 0x05e3bc3700000000, 0xcf41ed4f00000000, + 0x0f25c55800000000, 0x4f88bd6100000000, 0x8fec957600000000, + 0xcfd24c1300000000, 0x0fb6640400000000, 0x4f1b1c3d00000000, + 0x8f7f342a00000000, 0xcf67aef600000000, 0x0f0386e100000000, + 0x4faefed800000000, 0x8fcad6cf00000000, 0xcff40faa00000000, + 0x0f9027bd00000000, 0x4f3d5f8400000000, 0x8f59779300000000, + 0x8e0b1ae600000000, 0x4e6f32f100000000, 0x0ec24ac800000000, + 0xcea662df00000000, 0x8e98bbba00000000, 0x4efc93ad00000000, + 0x0e51eb9400000000, 0xce35c38300000000, 0x8e2d595f00000000, + 0x4e49714800000000, 0x0ee4097100000000, 0xce80216600000000, + 0x8ebef80300000000, 0x4edad01400000000, 0x0e77a82d00000000, + 0xce13803a00000000, 0x0cd372c700000000, 0xccb75ad000000000, + 0x8c1a22e900000000, 0x4c7e0afe00000000, 0x0c40d39b00000000, + 0xcc24fb8c00000000, 0x8c8983b500000000, 0x4cedaba200000000, + 0x0cf5317e00000000, 0xcc91196900000000, 0x8c3c615000000000, + 0x4c58494700000000, 0x0c66902200000000, 0xcc02b83500000000, + 0x8cafc00c00000000, 0x4ccbe81b00000000, 0x4d99856e00000000, + 0x8dfdad7900000000, 0xcd50d54000000000, 0x0d34fd5700000000, + 0x4d0a243200000000, 0x8d6e0c2500000000, 0xcdc3741c00000000, + 0x0da75c0b00000000, 0x4dbfc6d700000000, 0x8ddbeec000000000, + 0xcd7696f900000000, 0x0d12beee00000000, 0x4d2c678b00000000, + 0x8d484f9c00000000, 0xcde537a500000000, 0x0d811fb200000000, + 0x0862a38500000000, 0xc8068b9200000000, 0x88abf3ab00000000, + 0x48cfdbbc00000000, 0x08f102d900000000, 0xc8952ace00000000, + 0x883852f700000000, 0x485c7ae000000000, 0x0844e03c00000000, + 0xc820c82b00000000, 0x888db01200000000, 0x48e9980500000000, + 0x08d7416000000000, 0xc8b3697700000000, 0x881e114e00000000, + 0x487a395900000000, 0x4928542c00000000, 0x894c7c3b00000000, + 0xc9e1040200000000, 0x09852c1500000000, 0x49bbf57000000000, + 0x89dfdd6700000000, 0xc972a55e00000000, 0x09168d4900000000, + 0x490e179500000000, 0x896a3f8200000000, 0xc9c747bb00000000, + 0x09a36fac00000000, 0x499db6c900000000, 0x89f99ede00000000, + 0xc954e6e700000000, 0x0930cef000000000, 0xcbf03c0d00000000, + 0x0b94141a00000000, 0x4b396c2300000000, 0x8b5d443400000000, + 0xcb639d5100000000, 0x0b07b54600000000, 0x4baacd7f00000000, + 0x8bcee56800000000, 0xcbd67fb400000000, 0x0bb257a300000000, + 0x4b1f2f9a00000000, 0x8b7b078d00000000, 0xcb45dee800000000, + 0x0b21f6ff00000000, 0x4b8c8ec600000000, 0x8be8a6d100000000, + 0x8abacba400000000, 0x4adee3b300000000, 0x0a739b8a00000000, + 0xca17b39d00000000, 0x8a296af800000000, 0x4a4d42ef00000000, + 0x0ae03ad600000000, 0xca8412c100000000, 0x8a9c881d00000000, + 0x4af8a00a00000000, 0x0a55d83300000000, 0xca31f02400000000, + 0x8a0f294100000000, 0x4a6b015600000000, 0x0ac6796f00000000, + 0xcaa2517800000000}, + {0x0000000000000000, 0xd4ea739b00000000, 0xe9d396ed00000000, + 0x3d39e57600000000, 0x93a15c0000000000, 0x474b2f9b00000000, + 0x7a72caed00000000, 0xae98b97600000000, 0x2643b90000000000, + 0xf2a9ca9b00000000, 0xcf902fed00000000, 0x1b7a5c7600000000, + 0xb5e2e50000000000, 0x6108969b00000000, 0x5c3173ed00000000, + 0x88db007600000000, 0x4c86720100000000, 0x986c019a00000000, + 0xa555e4ec00000000, 0x71bf977700000000, 0xdf272e0100000000, + 0x0bcd5d9a00000000, 0x36f4b8ec00000000, 0xe21ecb7700000000, + 0x6ac5cb0100000000, 0xbe2fb89a00000000, 0x83165dec00000000, + 0x57fc2e7700000000, 0xf964970100000000, 0x2d8ee49a00000000, + 0x10b701ec00000000, 0xc45d727700000000, 0x980ce50200000000, + 0x4ce6969900000000, 0x71df73ef00000000, 0xa535007400000000, + 0x0badb90200000000, 0xdf47ca9900000000, 0xe27e2fef00000000, + 0x36945c7400000000, 0xbe4f5c0200000000, 0x6aa52f9900000000, + 0x579ccaef00000000, 0x8376b97400000000, 0x2dee000200000000, + 0xf904739900000000, 0xc43d96ef00000000, 0x10d7e57400000000, + 0xd48a970300000000, 0x0060e49800000000, 0x3d5901ee00000000, + 0xe9b3727500000000, 0x472bcb0300000000, 0x93c1b89800000000, + 0xaef85dee00000000, 0x7a122e7500000000, 0xf2c92e0300000000, + 0x26235d9800000000, 0x1b1ab8ee00000000, 0xcff0cb7500000000, + 0x6168720300000000, 0xb582019800000000, 0x88bbe4ee00000000, + 0x5c51977500000000, 0x3019ca0500000000, 0xe4f3b99e00000000, + 0xd9ca5ce800000000, 0x0d202f7300000000, 0xa3b8960500000000, + 0x7752e59e00000000, 0x4a6b00e800000000, 0x9e81737300000000, + 0x165a730500000000, 0xc2b0009e00000000, 0xff89e5e800000000, + 0x2b63967300000000, 0x85fb2f0500000000, 0x51115c9e00000000, + 0x6c28b9e800000000, 0xb8c2ca7300000000, 0x7c9fb80400000000, + 0xa875cb9f00000000, 0x954c2ee900000000, 0x41a65d7200000000, + 0xef3ee40400000000, 0x3bd4979f00000000, 0x06ed72e900000000, + 0xd207017200000000, 0x5adc010400000000, 0x8e36729f00000000, + 0xb30f97e900000000, 0x67e5e47200000000, 0xc97d5d0400000000, + 0x1d972e9f00000000, 0x20aecbe900000000, 0xf444b87200000000, + 0xa8152f0700000000, 0x7cff5c9c00000000, 0x41c6b9ea00000000, + 0x952cca7100000000, 0x3bb4730700000000, 0xef5e009c00000000, + 0xd267e5ea00000000, 0x068d967100000000, 0x8e56960700000000, + 0x5abce59c00000000, 0x678500ea00000000, 0xb36f737100000000, + 0x1df7ca0700000000, 0xc91db99c00000000, 0xf4245cea00000000, + 0x20ce2f7100000000, 0xe4935d0600000000, 0x30792e9d00000000, + 0x0d40cbeb00000000, 0xd9aab87000000000, 0x7732010600000000, + 0xa3d8729d00000000, 0x9ee197eb00000000, 0x4a0be47000000000, + 0xc2d0e40600000000, 0x163a979d00000000, 0x2b0372eb00000000, + 0xffe9017000000000, 0x5171b80600000000, 0x859bcb9d00000000, + 0xb8a22eeb00000000, 0x6c485d7000000000, 0x6032940b00000000, + 0xb4d8e79000000000, 0x89e102e600000000, 0x5d0b717d00000000, + 0xf393c80b00000000, 0x2779bb9000000000, 0x1a405ee600000000, + 0xceaa2d7d00000000, 0x46712d0b00000000, 0x929b5e9000000000, + 0xafa2bbe600000000, 0x7b48c87d00000000, 0xd5d0710b00000000, + 0x013a029000000000, 0x3c03e7e600000000, 0xe8e9947d00000000, + 0x2cb4e60a00000000, 0xf85e959100000000, 0xc56770e700000000, + 0x118d037c00000000, 0xbf15ba0a00000000, 0x6bffc99100000000, + 0x56c62ce700000000, 0x822c5f7c00000000, 0x0af75f0a00000000, + 0xde1d2c9100000000, 0xe324c9e700000000, 0x37ceba7c00000000, + 0x9956030a00000000, 0x4dbc709100000000, 0x708595e700000000, + 0xa46fe67c00000000, 0xf83e710900000000, 0x2cd4029200000000, + 0x11ede7e400000000, 0xc507947f00000000, 0x6b9f2d0900000000, + 0xbf755e9200000000, 0x824cbbe400000000, 0x56a6c87f00000000, + 0xde7dc80900000000, 0x0a97bb9200000000, 0x37ae5ee400000000, + 0xe3442d7f00000000, 0x4ddc940900000000, 0x9936e79200000000, + 0xa40f02e400000000, 0x70e5717f00000000, 0xb4b8030800000000, + 0x6052709300000000, 0x5d6b95e500000000, 0x8981e67e00000000, + 0x27195f0800000000, 0xf3f32c9300000000, 0xcecac9e500000000, + 0x1a20ba7e00000000, 0x92fbba0800000000, 0x4611c99300000000, + 0x7b282ce500000000, 0xafc25f7e00000000, 0x015ae60800000000, + 0xd5b0959300000000, 0xe88970e500000000, 0x3c63037e00000000, + 0x502b5e0e00000000, 0x84c12d9500000000, 0xb9f8c8e300000000, + 0x6d12bb7800000000, 0xc38a020e00000000, 0x1760719500000000, + 0x2a5994e300000000, 0xfeb3e77800000000, 0x7668e70e00000000, + 0xa282949500000000, 0x9fbb71e300000000, 0x4b51027800000000, + 0xe5c9bb0e00000000, 0x3123c89500000000, 0x0c1a2de300000000, + 0xd8f05e7800000000, 0x1cad2c0f00000000, 0xc8475f9400000000, + 0xf57ebae200000000, 0x2194c97900000000, 0x8f0c700f00000000, + 0x5be6039400000000, 0x66dfe6e200000000, 0xb235957900000000, + 0x3aee950f00000000, 0xee04e69400000000, 0xd33d03e200000000, + 0x07d7707900000000, 0xa94fc90f00000000, 0x7da5ba9400000000, + 0x409c5fe200000000, 0x94762c7900000000, 0xc827bb0c00000000, + 0x1ccdc89700000000, 0x21f42de100000000, 0xf51e5e7a00000000, + 0x5b86e70c00000000, 0x8f6c949700000000, 0xb25571e100000000, + 0x66bf027a00000000, 0xee64020c00000000, 0x3a8e719700000000, + 0x07b794e100000000, 0xd35de77a00000000, 0x7dc55e0c00000000, + 0xa92f2d9700000000, 0x9416c8e100000000, 0x40fcbb7a00000000, + 0x84a1c90d00000000, 0x504bba9600000000, 0x6d725fe000000000, + 0xb9982c7b00000000, 0x1700950d00000000, 0xc3eae69600000000, + 0xfed303e000000000, 0x2a39707b00000000, 0xa2e2700d00000000, + 0x7608039600000000, 0x4b31e6e000000000, 0x9fdb957b00000000, + 0x31432c0d00000000, 0xe5a95f9600000000, 0xd890bae000000000, + 0x0c7ac97b00000000}, + {0x0000000000000000, 0x2765258100000000, 0x0fcc3bd900000000, + 0x28a91e5800000000, 0x5f9e066900000000, 0x78fb23e800000000, + 0x50523db000000000, 0x7737183100000000, 0xbe3c0dd200000000, + 0x9959285300000000, 0xb1f0360b00000000, 0x9695138a00000000, + 0xe1a20bbb00000000, 0xc6c72e3a00000000, 0xee6e306200000000, + 0xc90b15e300000000, 0x3d7f6b7f00000000, 0x1a1a4efe00000000, + 0x32b350a600000000, 0x15d6752700000000, 0x62e16d1600000000, + 0x4584489700000000, 0x6d2d56cf00000000, 0x4a48734e00000000, + 0x834366ad00000000, 0xa426432c00000000, 0x8c8f5d7400000000, + 0xabea78f500000000, 0xdcdd60c400000000, 0xfbb8454500000000, + 0xd3115b1d00000000, 0xf4747e9c00000000, 0x7afed6fe00000000, + 0x5d9bf37f00000000, 0x7532ed2700000000, 0x5257c8a600000000, + 0x2560d09700000000, 0x0205f51600000000, 0x2aaceb4e00000000, + 0x0dc9cecf00000000, 0xc4c2db2c00000000, 0xe3a7fead00000000, + 0xcb0ee0f500000000, 0xec6bc57400000000, 0x9b5cdd4500000000, + 0xbc39f8c400000000, 0x9490e69c00000000, 0xb3f5c31d00000000, + 0x4781bd8100000000, 0x60e4980000000000, 0x484d865800000000, + 0x6f28a3d900000000, 0x181fbbe800000000, 0x3f7a9e6900000000, + 0x17d3803100000000, 0x30b6a5b000000000, 0xf9bdb05300000000, + 0xded895d200000000, 0xf6718b8a00000000, 0xd114ae0b00000000, + 0xa623b63a00000000, 0x814693bb00000000, 0xa9ef8de300000000, + 0x8e8aa86200000000, 0xb5fadc2600000000, 0x929ff9a700000000, + 0xba36e7ff00000000, 0x9d53c27e00000000, 0xea64da4f00000000, + 0xcd01ffce00000000, 0xe5a8e19600000000, 0xc2cdc41700000000, + 0x0bc6d1f400000000, 0x2ca3f47500000000, 0x040aea2d00000000, + 0x236fcfac00000000, 0x5458d79d00000000, 0x733df21c00000000, + 0x5b94ec4400000000, 0x7cf1c9c500000000, 0x8885b75900000000, + 0xafe092d800000000, 0x87498c8000000000, 0xa02ca90100000000, + 0xd71bb13000000000, 0xf07e94b100000000, 0xd8d78ae900000000, + 0xffb2af6800000000, 0x36b9ba8b00000000, 0x11dc9f0a00000000, + 0x3975815200000000, 0x1e10a4d300000000, 0x6927bce200000000, + 0x4e42996300000000, 0x66eb873b00000000, 0x418ea2ba00000000, + 0xcf040ad800000000, 0xe8612f5900000000, 0xc0c8310100000000, + 0xe7ad148000000000, 0x909a0cb100000000, 0xb7ff293000000000, + 0x9f56376800000000, 0xb83312e900000000, 0x7138070a00000000, + 0x565d228b00000000, 0x7ef43cd300000000, 0x5991195200000000, + 0x2ea6016300000000, 0x09c324e200000000, 0x216a3aba00000000, + 0x060f1f3b00000000, 0xf27b61a700000000, 0xd51e442600000000, + 0xfdb75a7e00000000, 0xdad27fff00000000, 0xade567ce00000000, + 0x8a80424f00000000, 0xa2295c1700000000, 0x854c799600000000, + 0x4c476c7500000000, 0x6b2249f400000000, 0x438b57ac00000000, + 0x64ee722d00000000, 0x13d96a1c00000000, 0x34bc4f9d00000000, + 0x1c1551c500000000, 0x3b70744400000000, 0x6af5b94d00000000, + 0x4d909ccc00000000, 0x6539829400000000, 0x425ca71500000000, + 0x356bbf2400000000, 0x120e9aa500000000, 0x3aa784fd00000000, + 0x1dc2a17c00000000, 0xd4c9b49f00000000, 0xf3ac911e00000000, + 0xdb058f4600000000, 0xfc60aac700000000, 0x8b57b2f600000000, + 0xac32977700000000, 0x849b892f00000000, 0xa3feacae00000000, + 0x578ad23200000000, 0x70eff7b300000000, 0x5846e9eb00000000, + 0x7f23cc6a00000000, 0x0814d45b00000000, 0x2f71f1da00000000, + 0x07d8ef8200000000, 0x20bdca0300000000, 0xe9b6dfe000000000, + 0xced3fa6100000000, 0xe67ae43900000000, 0xc11fc1b800000000, + 0xb628d98900000000, 0x914dfc0800000000, 0xb9e4e25000000000, + 0x9e81c7d100000000, 0x100b6fb300000000, 0x376e4a3200000000, + 0x1fc7546a00000000, 0x38a271eb00000000, 0x4f9569da00000000, + 0x68f04c5b00000000, 0x4059520300000000, 0x673c778200000000, + 0xae37626100000000, 0x895247e000000000, 0xa1fb59b800000000, + 0x869e7c3900000000, 0xf1a9640800000000, 0xd6cc418900000000, + 0xfe655fd100000000, 0xd9007a5000000000, 0x2d7404cc00000000, + 0x0a11214d00000000, 0x22b83f1500000000, 0x05dd1a9400000000, + 0x72ea02a500000000, 0x558f272400000000, 0x7d26397c00000000, + 0x5a431cfd00000000, 0x9348091e00000000, 0xb42d2c9f00000000, + 0x9c8432c700000000, 0xbbe1174600000000, 0xccd60f7700000000, + 0xebb32af600000000, 0xc31a34ae00000000, 0xe47f112f00000000, + 0xdf0f656b00000000, 0xf86a40ea00000000, 0xd0c35eb200000000, + 0xf7a67b3300000000, 0x8091630200000000, 0xa7f4468300000000, + 0x8f5d58db00000000, 0xa8387d5a00000000, 0x613368b900000000, + 0x46564d3800000000, 0x6eff536000000000, 0x499a76e100000000, + 0x3ead6ed000000000, 0x19c84b5100000000, 0x3161550900000000, + 0x1604708800000000, 0xe2700e1400000000, 0xc5152b9500000000, + 0xedbc35cd00000000, 0xcad9104c00000000, 0xbdee087d00000000, + 0x9a8b2dfc00000000, 0xb22233a400000000, 0x9547162500000000, + 0x5c4c03c600000000, 0x7b29264700000000, 0x5380381f00000000, + 0x74e51d9e00000000, 0x03d205af00000000, 0x24b7202e00000000, + 0x0c1e3e7600000000, 0x2b7b1bf700000000, 0xa5f1b39500000000, + 0x8294961400000000, 0xaa3d884c00000000, 0x8d58adcd00000000, + 0xfa6fb5fc00000000, 0xdd0a907d00000000, 0xf5a38e2500000000, + 0xd2c6aba400000000, 0x1bcdbe4700000000, 0x3ca89bc600000000, + 0x1401859e00000000, 0x3364a01f00000000, 0x4453b82e00000000, + 0x63369daf00000000, 0x4b9f83f700000000, 0x6cfaa67600000000, + 0x988ed8ea00000000, 0xbfebfd6b00000000, 0x9742e33300000000, + 0xb027c6b200000000, 0xc710de8300000000, 0xe075fb0200000000, + 0xc8dce55a00000000, 0xefb9c0db00000000, 0x26b2d53800000000, + 0x01d7f0b900000000, 0x297eeee100000000, 0x0e1bcb6000000000, + 0x792cd35100000000, 0x5e49f6d000000000, 0x76e0e88800000000, + 0x5185cd0900000000}}; + +#else /* W == 4 */ + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0x9ba54c6f, 0xec3b9e9f, 0x779ed2f0, 0x03063b7f, + 0x98a37710, 0xef3da5e0, 0x7498e98f, 0x060c76fe, 0x9da93a91, + 0xea37e861, 0x7192a40e, 0x050a4d81, 0x9eaf01ee, 0xe931d31e, + 0x72949f71, 0x0c18edfc, 0x97bda193, 0xe0237363, 0x7b863f0c, + 0x0f1ed683, 0x94bb9aec, 0xe325481c, 0x78800473, 0x0a149b02, + 0x91b1d76d, 0xe62f059d, 0x7d8a49f2, 0x0912a07d, 0x92b7ec12, + 0xe5293ee2, 0x7e8c728d, 0x1831dbf8, 0x83949797, 0xf40a4567, + 0x6faf0908, 0x1b37e087, 0x8092ace8, 0xf70c7e18, 0x6ca93277, + 0x1e3dad06, 0x8598e169, 0xf2063399, 0x69a37ff6, 0x1d3b9679, + 0x869eda16, 0xf10008e6, 0x6aa54489, 0x14293604, 0x8f8c7a6b, + 0xf812a89b, 0x63b7e4f4, 0x172f0d7b, 0x8c8a4114, 0xfb1493e4, + 0x60b1df8b, 0x122540fa, 0x89800c95, 0xfe1ede65, 0x65bb920a, + 0x11237b85, 0x8a8637ea, 0xfd18e51a, 0x66bda975, 0x3063b7f0, + 0xabc6fb9f, 0xdc58296f, 0x47fd6500, 0x33658c8f, 0xa8c0c0e0, + 0xdf5e1210, 0x44fb5e7f, 0x366fc10e, 0xadca8d61, 0xda545f91, + 0x41f113fe, 0x3569fa71, 0xaeccb61e, 0xd95264ee, 0x42f72881, + 0x3c7b5a0c, 0xa7de1663, 0xd040c493, 0x4be588fc, 0x3f7d6173, + 0xa4d82d1c, 0xd346ffec, 0x48e3b383, 0x3a772cf2, 0xa1d2609d, + 0xd64cb26d, 0x4de9fe02, 0x3971178d, 0xa2d45be2, 0xd54a8912, + 0x4eefc57d, 0x28526c08, 0xb3f72067, 0xc469f297, 0x5fccbef8, + 0x2b545777, 0xb0f11b18, 0xc76fc9e8, 0x5cca8587, 0x2e5e1af6, + 0xb5fb5699, 0xc2658469, 0x59c0c806, 0x2d582189, 0xb6fd6de6, + 0xc163bf16, 0x5ac6f379, 0x244a81f4, 0xbfefcd9b, 0xc8711f6b, + 0x53d45304, 0x274cba8b, 0xbce9f6e4, 0xcb772414, 0x50d2687b, + 0x2246f70a, 0xb9e3bb65, 0xce7d6995, 0x55d825fa, 0x2140cc75, + 0xbae5801a, 0xcd7b52ea, 0x56de1e85, 0x60c76fe0, 0xfb62238f, + 0x8cfcf17f, 0x1759bd10, 0x63c1549f, 0xf86418f0, 0x8ffaca00, + 0x145f866f, 0x66cb191e, 0xfd6e5571, 0x8af08781, 0x1155cbee, + 0x65cd2261, 0xfe686e0e, 0x89f6bcfe, 0x1253f091, 0x6cdf821c, + 0xf77ace73, 0x80e41c83, 0x1b4150ec, 0x6fd9b963, 0xf47cf50c, + 0x83e227fc, 0x18476b93, 0x6ad3f4e2, 0xf176b88d, 0x86e86a7d, + 0x1d4d2612, 0x69d5cf9d, 0xf27083f2, 0x85ee5102, 0x1e4b1d6d, + 0x78f6b418, 0xe353f877, 0x94cd2a87, 0x0f6866e8, 0x7bf08f67, + 0xe055c308, 0x97cb11f8, 0x0c6e5d97, 0x7efac2e6, 0xe55f8e89, + 0x92c15c79, 0x09641016, 0x7dfcf999, 0xe659b5f6, 0x91c76706, + 0x0a622b69, 0x74ee59e4, 0xef4b158b, 0x98d5c77b, 0x03708b14, + 0x77e8629b, 0xec4d2ef4, 0x9bd3fc04, 0x0076b06b, 0x72e22f1a, + 0xe9476375, 0x9ed9b185, 0x057cfdea, 0x71e41465, 0xea41580a, + 0x9ddf8afa, 0x067ac695, 0x50a4d810, 0xcb01947f, 0xbc9f468f, + 0x273a0ae0, 0x53a2e36f, 0xc807af00, 0xbf997df0, 0x243c319f, + 0x56a8aeee, 0xcd0de281, 0xba933071, 0x21367c1e, 0x55ae9591, + 0xce0bd9fe, 0xb9950b0e, 0x22304761, 0x5cbc35ec, 0xc7197983, + 0xb087ab73, 0x2b22e71c, 0x5fba0e93, 0xc41f42fc, 0xb381900c, + 0x2824dc63, 0x5ab04312, 0xc1150f7d, 0xb68bdd8d, 0x2d2e91e2, + 0x59b6786d, 0xc2133402, 0xb58de6f2, 0x2e28aa9d, 0x489503e8, + 0xd3304f87, 0xa4ae9d77, 0x3f0bd118, 0x4b933897, 0xd03674f8, + 0xa7a8a608, 0x3c0dea67, 0x4e997516, 0xd53c3979, 0xa2a2eb89, + 0x3907a7e6, 0x4d9f4e69, 0xd63a0206, 0xa1a4d0f6, 0x3a019c99, + 0x448dee14, 0xdf28a27b, 0xa8b6708b, 0x33133ce4, 0x478bd56b, + 0xdc2e9904, 0xabb04bf4, 0x3015079b, 0x428198ea, 0xd924d485, + 0xaeba0675, 0x351f4a1a, 0x4187a395, 0xda22effa, 0xadbc3d0a, + 0x36197165}, + {0x00000000, 0xc18edfc0, 0x586cb9c1, 0x99e26601, 0xb0d97382, + 0x7157ac42, 0xe8b5ca43, 0x293b1583, 0xbac3e145, 0x7b4d3e85, + 0xe2af5884, 0x23218744, 0x0a1a92c7, 0xcb944d07, 0x52762b06, + 0x93f8f4c6, 0xaef6c4cb, 0x6f781b0b, 0xf69a7d0a, 0x3714a2ca, + 0x1e2fb749, 0xdfa16889, 0x46430e88, 0x87cdd148, 0x1435258e, + 0xd5bbfa4e, 0x4c599c4f, 0x8dd7438f, 0xa4ec560c, 0x656289cc, + 0xfc80efcd, 0x3d0e300d, 0x869c8fd7, 0x47125017, 0xdef03616, + 0x1f7ee9d6, 0x3645fc55, 0xf7cb2395, 0x6e294594, 0xafa79a54, + 0x3c5f6e92, 0xfdd1b152, 0x6433d753, 0xa5bd0893, 0x8c861d10, + 0x4d08c2d0, 0xd4eaa4d1, 0x15647b11, 0x286a4b1c, 0xe9e494dc, + 0x7006f2dd, 0xb1882d1d, 0x98b3389e, 0x593de75e, 0xc0df815f, + 0x01515e9f, 0x92a9aa59, 0x53277599, 0xcac51398, 0x0b4bcc58, + 0x2270d9db, 0xe3fe061b, 0x7a1c601a, 0xbb92bfda, 0xd64819ef, + 0x17c6c62f, 0x8e24a02e, 0x4faa7fee, 0x66916a6d, 0xa71fb5ad, + 0x3efdd3ac, 0xff730c6c, 0x6c8bf8aa, 0xad05276a, 0x34e7416b, + 0xf5699eab, 0xdc528b28, 0x1ddc54e8, 0x843e32e9, 0x45b0ed29, + 0x78bedd24, 0xb93002e4, 0x20d264e5, 0xe15cbb25, 0xc867aea6, + 0x09e97166, 0x900b1767, 0x5185c8a7, 0xc27d3c61, 0x03f3e3a1, + 0x9a1185a0, 0x5b9f5a60, 0x72a44fe3, 0xb32a9023, 0x2ac8f622, + 0xeb4629e2, 0x50d49638, 0x915a49f8, 0x08b82ff9, 0xc936f039, + 0xe00de5ba, 0x21833a7a, 0xb8615c7b, 0x79ef83bb, 0xea17777d, + 0x2b99a8bd, 0xb27bcebc, 0x73f5117c, 0x5ace04ff, 0x9b40db3f, + 0x02a2bd3e, 0xc32c62fe, 0xfe2252f3, 0x3fac8d33, 0xa64eeb32, + 0x67c034f2, 0x4efb2171, 0x8f75feb1, 0x169798b0, 0xd7194770, + 0x44e1b3b6, 0x856f6c76, 0x1c8d0a77, 0xdd03d5b7, 0xf438c034, + 0x35b61ff4, 0xac5479f5, 0x6ddaa635, 0x77e1359f, 0xb66fea5f, + 0x2f8d8c5e, 0xee03539e, 0xc738461d, 0x06b699dd, 0x9f54ffdc, + 0x5eda201c, 0xcd22d4da, 0x0cac0b1a, 0x954e6d1b, 0x54c0b2db, + 0x7dfba758, 0xbc757898, 0x25971e99, 0xe419c159, 0xd917f154, + 0x18992e94, 0x817b4895, 0x40f59755, 0x69ce82d6, 0xa8405d16, + 0x31a23b17, 0xf02ce4d7, 0x63d41011, 0xa25acfd1, 0x3bb8a9d0, + 0xfa367610, 0xd30d6393, 0x1283bc53, 0x8b61da52, 0x4aef0592, + 0xf17dba48, 0x30f36588, 0xa9110389, 0x689fdc49, 0x41a4c9ca, + 0x802a160a, 0x19c8700b, 0xd846afcb, 0x4bbe5b0d, 0x8a3084cd, + 0x13d2e2cc, 0xd25c3d0c, 0xfb67288f, 0x3ae9f74f, 0xa30b914e, + 0x62854e8e, 0x5f8b7e83, 0x9e05a143, 0x07e7c742, 0xc6691882, + 0xef520d01, 0x2edcd2c1, 0xb73eb4c0, 0x76b06b00, 0xe5489fc6, + 0x24c64006, 0xbd242607, 0x7caaf9c7, 0x5591ec44, 0x941f3384, + 0x0dfd5585, 0xcc738a45, 0xa1a92c70, 0x6027f3b0, 0xf9c595b1, + 0x384b4a71, 0x11705ff2, 0xd0fe8032, 0x491ce633, 0x889239f3, + 0x1b6acd35, 0xdae412f5, 0x430674f4, 0x8288ab34, 0xabb3beb7, + 0x6a3d6177, 0xf3df0776, 0x3251d8b6, 0x0f5fe8bb, 0xced1377b, + 0x5733517a, 0x96bd8eba, 0xbf869b39, 0x7e0844f9, 0xe7ea22f8, + 0x2664fd38, 0xb59c09fe, 0x7412d63e, 0xedf0b03f, 0x2c7e6fff, + 0x05457a7c, 0xc4cba5bc, 0x5d29c3bd, 0x9ca71c7d, 0x2735a3a7, + 0xe6bb7c67, 0x7f591a66, 0xbed7c5a6, 0x97ecd025, 0x56620fe5, + 0xcf8069e4, 0x0e0eb624, 0x9df642e2, 0x5c789d22, 0xc59afb23, + 0x041424e3, 0x2d2f3160, 0xeca1eea0, 0x754388a1, 0xb4cd5761, + 0x89c3676c, 0x484db8ac, 0xd1afdead, 0x1021016d, 0x391a14ee, + 0xf894cb2e, 0x6176ad2f, 0xa0f872ef, 0x33008629, 0xf28e59e9, + 0x6b6c3fe8, 0xaae2e028, 0x83d9f5ab, 0x42572a6b, 0xdbb54c6a, + 0x1a3b93aa}, + {0x00000000, 0xefc26b3e, 0x04f5d03d, 0xeb37bb03, 0x09eba07a, + 0xe629cb44, 0x0d1e7047, 0xe2dc1b79, 0x13d740f4, 0xfc152bca, + 0x172290c9, 0xf8e0fbf7, 0x1a3ce08e, 0xf5fe8bb0, 0x1ec930b3, + 0xf10b5b8d, 0x27ae81e8, 0xc86cead6, 0x235b51d5, 0xcc993aeb, + 0x2e452192, 0xc1874aac, 0x2ab0f1af, 0xc5729a91, 0x3479c11c, + 0xdbbbaa22, 0x308c1121, 0xdf4e7a1f, 0x3d926166, 0xd2500a58, + 0x3967b15b, 0xd6a5da65, 0x4f5d03d0, 0xa09f68ee, 0x4ba8d3ed, + 0xa46ab8d3, 0x46b6a3aa, 0xa974c894, 0x42437397, 0xad8118a9, + 0x5c8a4324, 0xb348281a, 0x587f9319, 0xb7bdf827, 0x5561e35e, + 0xbaa38860, 0x51943363, 0xbe56585d, 0x68f38238, 0x8731e906, + 0x6c065205, 0x83c4393b, 0x61182242, 0x8eda497c, 0x65edf27f, + 0x8a2f9941, 0x7b24c2cc, 0x94e6a9f2, 0x7fd112f1, 0x901379cf, + 0x72cf62b6, 0x9d0d0988, 0x763ab28b, 0x99f8d9b5, 0x9eba07a0, + 0x71786c9e, 0x9a4fd79d, 0x758dbca3, 0x9751a7da, 0x7893cce4, + 0x93a477e7, 0x7c661cd9, 0x8d6d4754, 0x62af2c6a, 0x89989769, + 0x665afc57, 0x8486e72e, 0x6b448c10, 0x80733713, 0x6fb15c2d, + 0xb9148648, 0x56d6ed76, 0xbde15675, 0x52233d4b, 0xb0ff2632, + 0x5f3d4d0c, 0xb40af60f, 0x5bc89d31, 0xaac3c6bc, 0x4501ad82, + 0xae361681, 0x41f47dbf, 0xa32866c6, 0x4cea0df8, 0xa7ddb6fb, + 0x481fddc5, 0xd1e70470, 0x3e256f4e, 0xd512d44d, 0x3ad0bf73, + 0xd80ca40a, 0x37cecf34, 0xdcf97437, 0x333b1f09, 0xc2304484, + 0x2df22fba, 0xc6c594b9, 0x2907ff87, 0xcbdbe4fe, 0x24198fc0, + 0xcf2e34c3, 0x20ec5ffd, 0xf6498598, 0x198beea6, 0xf2bc55a5, + 0x1d7e3e9b, 0xffa225e2, 0x10604edc, 0xfb57f5df, 0x14959ee1, + 0xe59ec56c, 0x0a5cae52, 0xe16b1551, 0x0ea97e6f, 0xec756516, + 0x03b70e28, 0xe880b52b, 0x0742de15, 0xe6050901, 0x09c7623f, + 0xe2f0d93c, 0x0d32b202, 0xefeea97b, 0x002cc245, 0xeb1b7946, + 0x04d91278, 0xf5d249f5, 0x1a1022cb, 0xf12799c8, 0x1ee5f2f6, + 0xfc39e98f, 0x13fb82b1, 0xf8cc39b2, 0x170e528c, 0xc1ab88e9, + 0x2e69e3d7, 0xc55e58d4, 0x2a9c33ea, 0xc8402893, 0x278243ad, + 0xccb5f8ae, 0x23779390, 0xd27cc81d, 0x3dbea323, 0xd6891820, + 0x394b731e, 0xdb976867, 0x34550359, 0xdf62b85a, 0x30a0d364, + 0xa9580ad1, 0x469a61ef, 0xadaddaec, 0x426fb1d2, 0xa0b3aaab, + 0x4f71c195, 0xa4467a96, 0x4b8411a8, 0xba8f4a25, 0x554d211b, + 0xbe7a9a18, 0x51b8f126, 0xb364ea5f, 0x5ca68161, 0xb7913a62, + 0x5853515c, 0x8ef68b39, 0x6134e007, 0x8a035b04, 0x65c1303a, + 0x871d2b43, 0x68df407d, 0x83e8fb7e, 0x6c2a9040, 0x9d21cbcd, + 0x72e3a0f3, 0x99d41bf0, 0x761670ce, 0x94ca6bb7, 0x7b080089, + 0x903fbb8a, 0x7ffdd0b4, 0x78bf0ea1, 0x977d659f, 0x7c4ade9c, + 0x9388b5a2, 0x7154aedb, 0x9e96c5e5, 0x75a17ee6, 0x9a6315d8, + 0x6b684e55, 0x84aa256b, 0x6f9d9e68, 0x805ff556, 0x6283ee2f, + 0x8d418511, 0x66763e12, 0x89b4552c, 0x5f118f49, 0xb0d3e477, + 0x5be45f74, 0xb426344a, 0x56fa2f33, 0xb938440d, 0x520fff0e, + 0xbdcd9430, 0x4cc6cfbd, 0xa304a483, 0x48331f80, 0xa7f174be, + 0x452d6fc7, 0xaaef04f9, 0x41d8bffa, 0xae1ad4c4, 0x37e20d71, + 0xd820664f, 0x3317dd4c, 0xdcd5b672, 0x3e09ad0b, 0xd1cbc635, + 0x3afc7d36, 0xd53e1608, 0x24354d85, 0xcbf726bb, 0x20c09db8, + 0xcf02f686, 0x2ddeedff, 0xc21c86c1, 0x292b3dc2, 0xc6e956fc, + 0x104c8c99, 0xff8ee7a7, 0x14b95ca4, 0xfb7b379a, 0x19a72ce3, + 0xf66547dd, 0x1d52fcde, 0xf29097e0, 0x039bcc6d, 0xec59a753, + 0x076e1c50, 0xe8ac776e, 0x0a706c17, 0xe5b20729, 0x0e85bc2a, + 0xe147d714}, + {0x00000000, 0x177b1443, 0x2ef62886, 0x398d3cc5, 0x5dec510c, + 0x4a97454f, 0x731a798a, 0x64616dc9, 0xbbd8a218, 0xaca3b65b, + 0x952e8a9e, 0x82559edd, 0xe634f314, 0xf14fe757, 0xc8c2db92, + 0xdfb9cfd1, 0xacc04271, 0xbbbb5632, 0x82366af7, 0x954d7eb4, + 0xf12c137d, 0xe657073e, 0xdfda3bfb, 0xc8a12fb8, 0x1718e069, + 0x0063f42a, 0x39eec8ef, 0x2e95dcac, 0x4af4b165, 0x5d8fa526, + 0x640299e3, 0x73798da0, 0x82f182a3, 0x958a96e0, 0xac07aa25, + 0xbb7cbe66, 0xdf1dd3af, 0xc866c7ec, 0xf1ebfb29, 0xe690ef6a, + 0x392920bb, 0x2e5234f8, 0x17df083d, 0x00a41c7e, 0x64c571b7, + 0x73be65f4, 0x4a335931, 0x5d484d72, 0x2e31c0d2, 0x394ad491, + 0x00c7e854, 0x17bcfc17, 0x73dd91de, 0x64a6859d, 0x5d2bb958, + 0x4a50ad1b, 0x95e962ca, 0x82927689, 0xbb1f4a4c, 0xac645e0f, + 0xc80533c6, 0xdf7e2785, 0xe6f31b40, 0xf1880f03, 0xde920307, + 0xc9e91744, 0xf0642b81, 0xe71f3fc2, 0x837e520b, 0x94054648, + 0xad887a8d, 0xbaf36ece, 0x654aa11f, 0x7231b55c, 0x4bbc8999, + 0x5cc79dda, 0x38a6f013, 0x2fdde450, 0x1650d895, 0x012bccd6, + 0x72524176, 0x65295535, 0x5ca469f0, 0x4bdf7db3, 0x2fbe107a, + 0x38c50439, 0x014838fc, 0x16332cbf, 0xc98ae36e, 0xdef1f72d, + 0xe77ccbe8, 0xf007dfab, 0x9466b262, 0x831da621, 0xba909ae4, + 0xadeb8ea7, 0x5c6381a4, 0x4b1895e7, 0x7295a922, 0x65eebd61, + 0x018fd0a8, 0x16f4c4eb, 0x2f79f82e, 0x3802ec6d, 0xe7bb23bc, + 0xf0c037ff, 0xc94d0b3a, 0xde361f79, 0xba5772b0, 0xad2c66f3, + 0x94a15a36, 0x83da4e75, 0xf0a3c3d5, 0xe7d8d796, 0xde55eb53, + 0xc92eff10, 0xad4f92d9, 0xba34869a, 0x83b9ba5f, 0x94c2ae1c, + 0x4b7b61cd, 0x5c00758e, 0x658d494b, 0x72f65d08, 0x169730c1, + 0x01ec2482, 0x38611847, 0x2f1a0c04, 0x6655004f, 0x712e140c, + 0x48a328c9, 0x5fd83c8a, 0x3bb95143, 0x2cc24500, 0x154f79c5, + 0x02346d86, 0xdd8da257, 0xcaf6b614, 0xf37b8ad1, 0xe4009e92, + 0x8061f35b, 0x971ae718, 0xae97dbdd, 0xb9eccf9e, 0xca95423e, + 0xddee567d, 0xe4636ab8, 0xf3187efb, 0x97791332, 0x80020771, + 0xb98f3bb4, 0xaef42ff7, 0x714de026, 0x6636f465, 0x5fbbc8a0, + 0x48c0dce3, 0x2ca1b12a, 0x3bdaa569, 0x025799ac, 0x152c8def, + 0xe4a482ec, 0xf3df96af, 0xca52aa6a, 0xdd29be29, 0xb948d3e0, + 0xae33c7a3, 0x97befb66, 0x80c5ef25, 0x5f7c20f4, 0x480734b7, + 0x718a0872, 0x66f11c31, 0x029071f8, 0x15eb65bb, 0x2c66597e, + 0x3b1d4d3d, 0x4864c09d, 0x5f1fd4de, 0x6692e81b, 0x71e9fc58, + 0x15889191, 0x02f385d2, 0x3b7eb917, 0x2c05ad54, 0xf3bc6285, + 0xe4c776c6, 0xdd4a4a03, 0xca315e40, 0xae503389, 0xb92b27ca, + 0x80a61b0f, 0x97dd0f4c, 0xb8c70348, 0xafbc170b, 0x96312bce, + 0x814a3f8d, 0xe52b5244, 0xf2504607, 0xcbdd7ac2, 0xdca66e81, + 0x031fa150, 0x1464b513, 0x2de989d6, 0x3a929d95, 0x5ef3f05c, + 0x4988e41f, 0x7005d8da, 0x677ecc99, 0x14074139, 0x037c557a, + 0x3af169bf, 0x2d8a7dfc, 0x49eb1035, 0x5e900476, 0x671d38b3, + 0x70662cf0, 0xafdfe321, 0xb8a4f762, 0x8129cba7, 0x9652dfe4, + 0xf233b22d, 0xe548a66e, 0xdcc59aab, 0xcbbe8ee8, 0x3a3681eb, + 0x2d4d95a8, 0x14c0a96d, 0x03bbbd2e, 0x67dad0e7, 0x70a1c4a4, + 0x492cf861, 0x5e57ec22, 0x81ee23f3, 0x969537b0, 0xaf180b75, + 0xb8631f36, 0xdc0272ff, 0xcb7966bc, 0xf2f45a79, 0xe58f4e3a, + 0x96f6c39a, 0x818dd7d9, 0xb800eb1c, 0xaf7bff5f, 0xcb1a9296, + 0xdc6186d5, 0xe5ecba10, 0xf297ae53, 0x2d2e6182, 0x3a5575c1, + 0x03d84904, 0x14a35d47, 0x70c2308e, 0x67b924cd, 0x5e341808, + 0x494f0c4b}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x00000000, 0x43147b17, 0x8628f62e, 0xc53c8d39, 0x0c51ec5d, + 0x4f45974a, 0x8a791a73, 0xc96d6164, 0x18a2d8bb, 0x5bb6a3ac, + 0x9e8a2e95, 0xdd9e5582, 0x14f334e6, 0x57e74ff1, 0x92dbc2c8, + 0xd1cfb9df, 0x7142c0ac, 0x3256bbbb, 0xf76a3682, 0xb47e4d95, + 0x7d132cf1, 0x3e0757e6, 0xfb3bdadf, 0xb82fa1c8, 0x69e01817, + 0x2af46300, 0xefc8ee39, 0xacdc952e, 0x65b1f44a, 0x26a58f5d, + 0xe3990264, 0xa08d7973, 0xa382f182, 0xe0968a95, 0x25aa07ac, + 0x66be7cbb, 0xafd31ddf, 0xecc766c8, 0x29fbebf1, 0x6aef90e6, + 0xbb202939, 0xf834522e, 0x3d08df17, 0x7e1ca400, 0xb771c564, + 0xf465be73, 0x3159334a, 0x724d485d, 0xd2c0312e, 0x91d44a39, + 0x54e8c700, 0x17fcbc17, 0xde91dd73, 0x9d85a664, 0x58b92b5d, + 0x1bad504a, 0xca62e995, 0x89769282, 0x4c4a1fbb, 0x0f5e64ac, + 0xc63305c8, 0x85277edf, 0x401bf3e6, 0x030f88f1, 0x070392de, + 0x4417e9c9, 0x812b64f0, 0xc23f1fe7, 0x0b527e83, 0x48460594, + 0x8d7a88ad, 0xce6ef3ba, 0x1fa14a65, 0x5cb53172, 0x9989bc4b, + 0xda9dc75c, 0x13f0a638, 0x50e4dd2f, 0x95d85016, 0xd6cc2b01, + 0x76415272, 0x35552965, 0xf069a45c, 0xb37ddf4b, 0x7a10be2f, + 0x3904c538, 0xfc384801, 0xbf2c3316, 0x6ee38ac9, 0x2df7f1de, + 0xe8cb7ce7, 0xabdf07f0, 0x62b26694, 0x21a61d83, 0xe49a90ba, + 0xa78eebad, 0xa481635c, 0xe795184b, 0x22a99572, 0x61bdee65, + 0xa8d08f01, 0xebc4f416, 0x2ef8792f, 0x6dec0238, 0xbc23bbe7, + 0xff37c0f0, 0x3a0b4dc9, 0x791f36de, 0xb07257ba, 0xf3662cad, + 0x365aa194, 0x754eda83, 0xd5c3a3f0, 0x96d7d8e7, 0x53eb55de, + 0x10ff2ec9, 0xd9924fad, 0x9a8634ba, 0x5fbab983, 0x1caec294, + 0xcd617b4b, 0x8e75005c, 0x4b498d65, 0x085df672, 0xc1309716, + 0x8224ec01, 0x47186138, 0x040c1a2f, 0x4f005566, 0x0c142e71, + 0xc928a348, 0x8a3cd85f, 0x4351b93b, 0x0045c22c, 0xc5794f15, + 0x866d3402, 0x57a28ddd, 0x14b6f6ca, 0xd18a7bf3, 0x929e00e4, + 0x5bf36180, 0x18e71a97, 0xdddb97ae, 0x9ecfecb9, 0x3e4295ca, + 0x7d56eedd, 0xb86a63e4, 0xfb7e18f3, 0x32137997, 0x71070280, + 0xb43b8fb9, 0xf72ff4ae, 0x26e04d71, 0x65f43666, 0xa0c8bb5f, + 0xe3dcc048, 0x2ab1a12c, 0x69a5da3b, 0xac995702, 0xef8d2c15, + 0xec82a4e4, 0xaf96dff3, 0x6aaa52ca, 0x29be29dd, 0xe0d348b9, + 0xa3c733ae, 0x66fbbe97, 0x25efc580, 0xf4207c5f, 0xb7340748, + 0x72088a71, 0x311cf166, 0xf8719002, 0xbb65eb15, 0x7e59662c, + 0x3d4d1d3b, 0x9dc06448, 0xded41f5f, 0x1be89266, 0x58fce971, + 0x91918815, 0xd285f302, 0x17b97e3b, 0x54ad052c, 0x8562bcf3, + 0xc676c7e4, 0x034a4add, 0x405e31ca, 0x893350ae, 0xca272bb9, + 0x0f1ba680, 0x4c0fdd97, 0x4803c7b8, 0x0b17bcaf, 0xce2b3196, + 0x8d3f4a81, 0x44522be5, 0x074650f2, 0xc27addcb, 0x816ea6dc, + 0x50a11f03, 0x13b56414, 0xd689e92d, 0x959d923a, 0x5cf0f35e, + 0x1fe48849, 0xdad80570, 0x99cc7e67, 0x39410714, 0x7a557c03, + 0xbf69f13a, 0xfc7d8a2d, 0x3510eb49, 0x7604905e, 0xb3381d67, + 0xf02c6670, 0x21e3dfaf, 0x62f7a4b8, 0xa7cb2981, 0xe4df5296, + 0x2db233f2, 0x6ea648e5, 0xab9ac5dc, 0xe88ebecb, 0xeb81363a, + 0xa8954d2d, 0x6da9c014, 0x2ebdbb03, 0xe7d0da67, 0xa4c4a170, + 0x61f82c49, 0x22ec575e, 0xf323ee81, 0xb0379596, 0x750b18af, + 0x361f63b8, 0xff7202dc, 0xbc6679cb, 0x795af4f2, 0x3a4e8fe5, + 0x9ac3f696, 0xd9d78d81, 0x1ceb00b8, 0x5fff7baf, 0x96921acb, + 0xd58661dc, 0x10baece5, 0x53ae97f2, 0x82612e2d, 0xc175553a, + 0x0449d803, 0x475da314, 0x8e30c270, 0xcd24b967, 0x0818345e, + 0x4b0c4f49}, + {0x00000000, 0x3e6bc2ef, 0x3dd0f504, 0x03bb37eb, 0x7aa0eb09, + 0x44cb29e6, 0x47701e0d, 0x791bdce2, 0xf440d713, 0xca2b15fc, + 0xc9902217, 0xf7fbe0f8, 0x8ee03c1a, 0xb08bfef5, 0xb330c91e, + 0x8d5b0bf1, 0xe881ae27, 0xd6ea6cc8, 0xd5515b23, 0xeb3a99cc, + 0x9221452e, 0xac4a87c1, 0xaff1b02a, 0x919a72c5, 0x1cc17934, + 0x22aabbdb, 0x21118c30, 0x1f7a4edf, 0x6661923d, 0x580a50d2, + 0x5bb16739, 0x65daa5d6, 0xd0035d4f, 0xee689fa0, 0xedd3a84b, + 0xd3b86aa4, 0xaaa3b646, 0x94c874a9, 0x97734342, 0xa91881ad, + 0x24438a5c, 0x1a2848b3, 0x19937f58, 0x27f8bdb7, 0x5ee36155, + 0x6088a3ba, 0x63339451, 0x5d5856be, 0x3882f368, 0x06e93187, + 0x0552066c, 0x3b39c483, 0x42221861, 0x7c49da8e, 0x7ff2ed65, + 0x41992f8a, 0xccc2247b, 0xf2a9e694, 0xf112d17f, 0xcf791390, + 0xb662cf72, 0x88090d9d, 0x8bb23a76, 0xb5d9f899, 0xa007ba9e, + 0x9e6c7871, 0x9dd74f9a, 0xa3bc8d75, 0xdaa75197, 0xe4cc9378, + 0xe777a493, 0xd91c667c, 0x54476d8d, 0x6a2caf62, 0x69979889, + 0x57fc5a66, 0x2ee78684, 0x108c446b, 0x13377380, 0x2d5cb16f, + 0x488614b9, 0x76edd656, 0x7556e1bd, 0x4b3d2352, 0x3226ffb0, + 0x0c4d3d5f, 0x0ff60ab4, 0x319dc85b, 0xbcc6c3aa, 0x82ad0145, + 0x811636ae, 0xbf7df441, 0xc66628a3, 0xf80dea4c, 0xfbb6dda7, + 0xc5dd1f48, 0x7004e7d1, 0x4e6f253e, 0x4dd412d5, 0x73bfd03a, + 0x0aa40cd8, 0x34cfce37, 0x3774f9dc, 0x091f3b33, 0x844430c2, + 0xba2ff22d, 0xb994c5c6, 0x87ff0729, 0xfee4dbcb, 0xc08f1924, + 0xc3342ecf, 0xfd5fec20, 0x988549f6, 0xa6ee8b19, 0xa555bcf2, + 0x9b3e7e1d, 0xe225a2ff, 0xdc4e6010, 0xdff557fb, 0xe19e9514, + 0x6cc59ee5, 0x52ae5c0a, 0x51156be1, 0x6f7ea90e, 0x166575ec, + 0x280eb703, 0x2bb580e8, 0x15de4207, 0x010905e6, 0x3f62c709, + 0x3cd9f0e2, 0x02b2320d, 0x7ba9eeef, 0x45c22c00, 0x46791beb, + 0x7812d904, 0xf549d2f5, 0xcb22101a, 0xc89927f1, 0xf6f2e51e, + 0x8fe939fc, 0xb182fb13, 0xb239ccf8, 0x8c520e17, 0xe988abc1, + 0xd7e3692e, 0xd4585ec5, 0xea339c2a, 0x932840c8, 0xad438227, + 0xaef8b5cc, 0x90937723, 0x1dc87cd2, 0x23a3be3d, 0x201889d6, + 0x1e734b39, 0x676897db, 0x59035534, 0x5ab862df, 0x64d3a030, + 0xd10a58a9, 0xef619a46, 0xecdaadad, 0xd2b16f42, 0xabaab3a0, + 0x95c1714f, 0x967a46a4, 0xa811844b, 0x254a8fba, 0x1b214d55, + 0x189a7abe, 0x26f1b851, 0x5fea64b3, 0x6181a65c, 0x623a91b7, + 0x5c515358, 0x398bf68e, 0x07e03461, 0x045b038a, 0x3a30c165, + 0x432b1d87, 0x7d40df68, 0x7efbe883, 0x40902a6c, 0xcdcb219d, + 0xf3a0e372, 0xf01bd499, 0xce701676, 0xb76bca94, 0x8900087b, + 0x8abb3f90, 0xb4d0fd7f, 0xa10ebf78, 0x9f657d97, 0x9cde4a7c, + 0xa2b58893, 0xdbae5471, 0xe5c5969e, 0xe67ea175, 0xd815639a, + 0x554e686b, 0x6b25aa84, 0x689e9d6f, 0x56f55f80, 0x2fee8362, + 0x1185418d, 0x123e7666, 0x2c55b489, 0x498f115f, 0x77e4d3b0, + 0x745fe45b, 0x4a3426b4, 0x332ffa56, 0x0d4438b9, 0x0eff0f52, + 0x3094cdbd, 0xbdcfc64c, 0x83a404a3, 0x801f3348, 0xbe74f1a7, + 0xc76f2d45, 0xf904efaa, 0xfabfd841, 0xc4d41aae, 0x710de237, + 0x4f6620d8, 0x4cdd1733, 0x72b6d5dc, 0x0bad093e, 0x35c6cbd1, + 0x367dfc3a, 0x08163ed5, 0x854d3524, 0xbb26f7cb, 0xb89dc020, + 0x86f602cf, 0xffedde2d, 0xc1861cc2, 0xc23d2b29, 0xfc56e9c6, + 0x998c4c10, 0xa7e78eff, 0xa45cb914, 0x9a377bfb, 0xe32ca719, + 0xdd4765f6, 0xdefc521d, 0xe09790f2, 0x6dcc9b03, 0x53a759ec, + 0x501c6e07, 0x6e77ace8, 0x176c700a, 0x2907b2e5, 0x2abc850e, + 0x14d747e1}, + {0x00000000, 0xc0df8ec1, 0xc1b96c58, 0x0166e299, 0x8273d9b0, + 0x42ac5771, 0x43cab5e8, 0x83153b29, 0x45e1c3ba, 0x853e4d7b, + 0x8458afe2, 0x44872123, 0xc7921a0a, 0x074d94cb, 0x062b7652, + 0xc6f4f893, 0xcbc4f6ae, 0x0b1b786f, 0x0a7d9af6, 0xcaa21437, + 0x49b72f1e, 0x8968a1df, 0x880e4346, 0x48d1cd87, 0x8e253514, + 0x4efabbd5, 0x4f9c594c, 0x8f43d78d, 0x0c56eca4, 0xcc896265, + 0xcdef80fc, 0x0d300e3d, 0xd78f9c86, 0x17501247, 0x1636f0de, + 0xd6e97e1f, 0x55fc4536, 0x9523cbf7, 0x9445296e, 0x549aa7af, + 0x926e5f3c, 0x52b1d1fd, 0x53d73364, 0x9308bda5, 0x101d868c, + 0xd0c2084d, 0xd1a4ead4, 0x117b6415, 0x1c4b6a28, 0xdc94e4e9, + 0xddf20670, 0x1d2d88b1, 0x9e38b398, 0x5ee73d59, 0x5f81dfc0, + 0x9f5e5101, 0x59aaa992, 0x99752753, 0x9813c5ca, 0x58cc4b0b, + 0xdbd97022, 0x1b06fee3, 0x1a601c7a, 0xdabf92bb, 0xef1948d6, + 0x2fc6c617, 0x2ea0248e, 0xee7faa4f, 0x6d6a9166, 0xadb51fa7, + 0xacd3fd3e, 0x6c0c73ff, 0xaaf88b6c, 0x6a2705ad, 0x6b41e734, + 0xab9e69f5, 0x288b52dc, 0xe854dc1d, 0xe9323e84, 0x29edb045, + 0x24ddbe78, 0xe40230b9, 0xe564d220, 0x25bb5ce1, 0xa6ae67c8, + 0x6671e909, 0x67170b90, 0xa7c88551, 0x613c7dc2, 0xa1e3f303, + 0xa085119a, 0x605a9f5b, 0xe34fa472, 0x23902ab3, 0x22f6c82a, + 0xe22946eb, 0x3896d450, 0xf8495a91, 0xf92fb808, 0x39f036c9, + 0xbae50de0, 0x7a3a8321, 0x7b5c61b8, 0xbb83ef79, 0x7d7717ea, + 0xbda8992b, 0xbcce7bb2, 0x7c11f573, 0xff04ce5a, 0x3fdb409b, + 0x3ebda202, 0xfe622cc3, 0xf35222fe, 0x338dac3f, 0x32eb4ea6, + 0xf234c067, 0x7121fb4e, 0xb1fe758f, 0xb0989716, 0x704719d7, + 0xb6b3e144, 0x766c6f85, 0x770a8d1c, 0xb7d503dd, 0x34c038f4, + 0xf41fb635, 0xf57954ac, 0x35a6da6d, 0x9f35e177, 0x5fea6fb6, + 0x5e8c8d2f, 0x9e5303ee, 0x1d4638c7, 0xdd99b606, 0xdcff549f, + 0x1c20da5e, 0xdad422cd, 0x1a0bac0c, 0x1b6d4e95, 0xdbb2c054, + 0x58a7fb7d, 0x987875bc, 0x991e9725, 0x59c119e4, 0x54f117d9, + 0x942e9918, 0x95487b81, 0x5597f540, 0xd682ce69, 0x165d40a8, + 0x173ba231, 0xd7e42cf0, 0x1110d463, 0xd1cf5aa2, 0xd0a9b83b, + 0x107636fa, 0x93630dd3, 0x53bc8312, 0x52da618b, 0x9205ef4a, + 0x48ba7df1, 0x8865f330, 0x890311a9, 0x49dc9f68, 0xcac9a441, + 0x0a162a80, 0x0b70c819, 0xcbaf46d8, 0x0d5bbe4b, 0xcd84308a, + 0xcce2d213, 0x0c3d5cd2, 0x8f2867fb, 0x4ff7e93a, 0x4e910ba3, + 0x8e4e8562, 0x837e8b5f, 0x43a1059e, 0x42c7e707, 0x821869c6, + 0x010d52ef, 0xc1d2dc2e, 0xc0b43eb7, 0x006bb076, 0xc69f48e5, + 0x0640c624, 0x072624bd, 0xc7f9aa7c, 0x44ec9155, 0x84331f94, + 0x8555fd0d, 0x458a73cc, 0x702ca9a1, 0xb0f32760, 0xb195c5f9, + 0x714a4b38, 0xf25f7011, 0x3280fed0, 0x33e61c49, 0xf3399288, + 0x35cd6a1b, 0xf512e4da, 0xf4740643, 0x34ab8882, 0xb7beb3ab, + 0x77613d6a, 0x7607dff3, 0xb6d85132, 0xbbe85f0f, 0x7b37d1ce, + 0x7a513357, 0xba8ebd96, 0x399b86bf, 0xf944087e, 0xf822eae7, + 0x38fd6426, 0xfe099cb5, 0x3ed61274, 0x3fb0f0ed, 0xff6f7e2c, + 0x7c7a4505, 0xbca5cbc4, 0xbdc3295d, 0x7d1ca79c, 0xa7a33527, + 0x677cbbe6, 0x661a597f, 0xa6c5d7be, 0x25d0ec97, 0xe50f6256, + 0xe46980cf, 0x24b60e0e, 0xe242f69d, 0x229d785c, 0x23fb9ac5, + 0xe3241404, 0x60312f2d, 0xa0eea1ec, 0xa1884375, 0x6157cdb4, + 0x6c67c389, 0xacb84d48, 0xaddeafd1, 0x6d012110, 0xee141a39, + 0x2ecb94f8, 0x2fad7661, 0xef72f8a0, 0x29860033, 0xe9598ef2, + 0xe83f6c6b, 0x28e0e2aa, 0xabf5d983, 0x6b2a5742, 0x6a4cb5db, + 0xaa933b1a}, + {0x00000000, 0x6f4ca59b, 0x9f9e3bec, 0xf0d29e77, 0x7f3b0603, + 0x1077a398, 0xe0a53def, 0x8fe99874, 0xfe760c06, 0x913aa99d, + 0x61e837ea, 0x0ea49271, 0x814d0a05, 0xee01af9e, 0x1ed331e9, + 0x719f9472, 0xfced180c, 0x93a1bd97, 0x637323e0, 0x0c3f867b, + 0x83d61e0f, 0xec9abb94, 0x1c4825e3, 0x73048078, 0x029b140a, + 0x6dd7b191, 0x9d052fe6, 0xf2498a7d, 0x7da01209, 0x12ecb792, + 0xe23e29e5, 0x8d728c7e, 0xf8db3118, 0x97979483, 0x67450af4, + 0x0809af6f, 0x87e0371b, 0xe8ac9280, 0x187e0cf7, 0x7732a96c, + 0x06ad3d1e, 0x69e19885, 0x993306f2, 0xf67fa369, 0x79963b1d, + 0x16da9e86, 0xe60800f1, 0x8944a56a, 0x04362914, 0x6b7a8c8f, + 0x9ba812f8, 0xf4e4b763, 0x7b0d2f17, 0x14418a8c, 0xe49314fb, + 0x8bdfb160, 0xfa402512, 0x950c8089, 0x65de1efe, 0x0a92bb65, + 0x857b2311, 0xea37868a, 0x1ae518fd, 0x75a9bd66, 0xf0b76330, + 0x9ffbc6ab, 0x6f2958dc, 0x0065fd47, 0x8f8c6533, 0xe0c0c0a8, + 0x10125edf, 0x7f5efb44, 0x0ec16f36, 0x618dcaad, 0x915f54da, + 0xfe13f141, 0x71fa6935, 0x1eb6ccae, 0xee6452d9, 0x8128f742, + 0x0c5a7b3c, 0x6316dea7, 0x93c440d0, 0xfc88e54b, 0x73617d3f, + 0x1c2dd8a4, 0xecff46d3, 0x83b3e348, 0xf22c773a, 0x9d60d2a1, + 0x6db24cd6, 0x02fee94d, 0x8d177139, 0xe25bd4a2, 0x12894ad5, + 0x7dc5ef4e, 0x086c5228, 0x6720f7b3, 0x97f269c4, 0xf8becc5f, + 0x7757542b, 0x181bf1b0, 0xe8c96fc7, 0x8785ca5c, 0xf61a5e2e, + 0x9956fbb5, 0x698465c2, 0x06c8c059, 0x8921582d, 0xe66dfdb6, + 0x16bf63c1, 0x79f3c65a, 0xf4814a24, 0x9bcdefbf, 0x6b1f71c8, + 0x0453d453, 0x8bba4c27, 0xe4f6e9bc, 0x142477cb, 0x7b68d250, + 0x0af74622, 0x65bbe3b9, 0x95697dce, 0xfa25d855, 0x75cc4021, + 0x1a80e5ba, 0xea527bcd, 0x851ede56, 0xe06fc760, 0x8f2362fb, + 0x7ff1fc8c, 0x10bd5917, 0x9f54c163, 0xf01864f8, 0x00cafa8f, + 0x6f865f14, 0x1e19cb66, 0x71556efd, 0x8187f08a, 0xeecb5511, + 0x6122cd65, 0x0e6e68fe, 0xfebcf689, 0x91f05312, 0x1c82df6c, + 0x73ce7af7, 0x831ce480, 0xec50411b, 0x63b9d96f, 0x0cf57cf4, + 0xfc27e283, 0x936b4718, 0xe2f4d36a, 0x8db876f1, 0x7d6ae886, + 0x12264d1d, 0x9dcfd569, 0xf28370f2, 0x0251ee85, 0x6d1d4b1e, + 0x18b4f678, 0x77f853e3, 0x872acd94, 0xe866680f, 0x678ff07b, + 0x08c355e0, 0xf811cb97, 0x975d6e0c, 0xe6c2fa7e, 0x898e5fe5, + 0x795cc192, 0x16106409, 0x99f9fc7d, 0xf6b559e6, 0x0667c791, + 0x692b620a, 0xe459ee74, 0x8b154bef, 0x7bc7d598, 0x148b7003, + 0x9b62e877, 0xf42e4dec, 0x04fcd39b, 0x6bb07600, 0x1a2fe272, + 0x756347e9, 0x85b1d99e, 0xeafd7c05, 0x6514e471, 0x0a5841ea, + 0xfa8adf9d, 0x95c67a06, 0x10d8a450, 0x7f9401cb, 0x8f469fbc, + 0xe00a3a27, 0x6fe3a253, 0x00af07c8, 0xf07d99bf, 0x9f313c24, + 0xeeaea856, 0x81e20dcd, 0x713093ba, 0x1e7c3621, 0x9195ae55, + 0xfed90bce, 0x0e0b95b9, 0x61473022, 0xec35bc5c, 0x837919c7, + 0x73ab87b0, 0x1ce7222b, 0x930eba5f, 0xfc421fc4, 0x0c9081b3, + 0x63dc2428, 0x1243b05a, 0x7d0f15c1, 0x8ddd8bb6, 0xe2912e2d, + 0x6d78b659, 0x023413c2, 0xf2e68db5, 0x9daa282e, 0xe8039548, + 0x874f30d3, 0x779daea4, 0x18d10b3f, 0x9738934b, 0xf87436d0, + 0x08a6a8a7, 0x67ea0d3c, 0x1675994e, 0x79393cd5, 0x89eba2a2, + 0xe6a70739, 0x694e9f4d, 0x06023ad6, 0xf6d0a4a1, 0x999c013a, + 0x14ee8d44, 0x7ba228df, 0x8b70b6a8, 0xe43c1333, 0x6bd58b47, + 0x04992edc, 0xf44bb0ab, 0x9b071530, 0xea988142, 0x85d424d9, + 0x7506baae, 0x1a4a1f35, 0x95a38741, 0xfaef22da, 0x0a3dbcad, + 0x65711936}}; + +#endif + +#endif + +#if N == 4 + +#if W == 8 + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0xf1da05aa, 0x38c50d15, 0xc91f08bf, 0x718a1a2a, + 0x80501f80, 0x494f173f, 0xb8951295, 0xe3143454, 0x12ce31fe, + 0xdbd13941, 0x2a0b3ceb, 0x929e2e7e, 0x63442bd4, 0xaa5b236b, + 0x5b8126c1, 0x1d596ee9, 0xec836b43, 0x259c63fc, 0xd4466656, + 0x6cd374c3, 0x9d097169, 0x541679d6, 0xa5cc7c7c, 0xfe4d5abd, + 0x0f975f17, 0xc68857a8, 0x37525202, 0x8fc74097, 0x7e1d453d, + 0xb7024d82, 0x46d84828, 0x3ab2ddd2, 0xcb68d878, 0x0277d0c7, + 0xf3add56d, 0x4b38c7f8, 0xbae2c252, 0x73fdcaed, 0x8227cf47, + 0xd9a6e986, 0x287cec2c, 0xe163e493, 0x10b9e139, 0xa82cf3ac, + 0x59f6f606, 0x90e9feb9, 0x6133fb13, 0x27ebb33b, 0xd631b691, + 0x1f2ebe2e, 0xeef4bb84, 0x5661a911, 0xa7bbacbb, 0x6ea4a404, + 0x9f7ea1ae, 0xc4ff876f, 0x352582c5, 0xfc3a8a7a, 0x0de08fd0, + 0xb5759d45, 0x44af98ef, 0x8db09050, 0x7c6a95fa, 0x7565bba4, + 0x84bfbe0e, 0x4da0b6b1, 0xbc7ab31b, 0x04efa18e, 0xf535a424, + 0x3c2aac9b, 0xcdf0a931, 0x96718ff0, 0x67ab8a5a, 0xaeb482e5, + 0x5f6e874f, 0xe7fb95da, 0x16219070, 0xdf3e98cf, 0x2ee49d65, + 0x683cd54d, 0x99e6d0e7, 0x50f9d858, 0xa123ddf2, 0x19b6cf67, + 0xe86ccacd, 0x2173c272, 0xd0a9c7d8, 0x8b28e119, 0x7af2e4b3, + 0xb3edec0c, 0x4237e9a6, 0xfaa2fb33, 0x0b78fe99, 0xc267f626, + 0x33bdf38c, 0x4fd76676, 0xbe0d63dc, 0x77126b63, 0x86c86ec9, + 0x3e5d7c5c, 0xcf8779f6, 0x06987149, 0xf74274e3, 0xacc35222, + 0x5d195788, 0x94065f37, 0x65dc5a9d, 0xdd494808, 0x2c934da2, + 0xe58c451d, 0x145640b7, 0x528e089f, 0xa3540d35, 0x6a4b058a, + 0x9b910020, 0x230412b5, 0xd2de171f, 0x1bc11fa0, 0xea1b1a0a, + 0xb19a3ccb, 0x40403961, 0x895f31de, 0x78853474, 0xc01026e1, + 0x31ca234b, 0xf8d52bf4, 0x090f2e5e, 0xeacb7748, 0x1b1172e2, + 0xd20e7a5d, 0x23d47ff7, 0x9b416d62, 0x6a9b68c8, 0xa3846077, + 0x525e65dd, 0x09df431c, 0xf80546b6, 0x311a4e09, 0xc0c04ba3, + 0x78555936, 0x898f5c9c, 0x40905423, 0xb14a5189, 0xf79219a1, + 0x06481c0b, 0xcf5714b4, 0x3e8d111e, 0x8618038b, 0x77c20621, + 0xbedd0e9e, 0x4f070b34, 0x14862df5, 0xe55c285f, 0x2c4320e0, + 0xdd99254a, 0x650c37df, 0x94d63275, 0x5dc93aca, 0xac133f60, + 0xd079aa9a, 0x21a3af30, 0xe8bca78f, 0x1966a225, 0xa1f3b0b0, + 0x5029b51a, 0x9936bda5, 0x68ecb80f, 0x336d9ece, 0xc2b79b64, + 0x0ba893db, 0xfa729671, 0x42e784e4, 0xb33d814e, 0x7a2289f1, + 0x8bf88c5b, 0xcd20c473, 0x3cfac1d9, 0xf5e5c966, 0x043fcccc, + 0xbcaade59, 0x4d70dbf3, 0x846fd34c, 0x75b5d6e6, 0x2e34f027, + 0xdfeef58d, 0x16f1fd32, 0xe72bf898, 0x5fbeea0d, 0xae64efa7, + 0x677be718, 0x96a1e2b2, 0x9faeccec, 0x6e74c946, 0xa76bc1f9, + 0x56b1c453, 0xee24d6c6, 0x1ffed36c, 0xd6e1dbd3, 0x273bde79, + 0x7cbaf8b8, 0x8d60fd12, 0x447ff5ad, 0xb5a5f007, 0x0d30e292, + 0xfceae738, 0x35f5ef87, 0xc42fea2d, 0x82f7a205, 0x732da7af, + 0xba32af10, 0x4be8aaba, 0xf37db82f, 0x02a7bd85, 0xcbb8b53a, + 0x3a62b090, 0x61e39651, 0x903993fb, 0x59269b44, 0xa8fc9eee, + 0x10698c7b, 0xe1b389d1, 0x28ac816e, 0xd97684c4, 0xa51c113e, + 0x54c61494, 0x9dd91c2b, 0x6c031981, 0xd4960b14, 0x254c0ebe, + 0xec530601, 0x1d8903ab, 0x4608256a, 0xb7d220c0, 0x7ecd287f, + 0x8f172dd5, 0x37823f40, 0xc6583aea, 0x0f473255, 0xfe9d37ff, + 0xb8457fd7, 0x499f7a7d, 0x808072c2, 0x715a7768, 0xc9cf65fd, + 0x38156057, 0xf10a68e8, 0x00d06d42, 0x5b514b83, 0xaa8b4e29, + 0x63944696, 0x924e433c, 0x2adb51a9, 0xdb015403, 0x121e5cbc, + 0xe3c45916}, + {0x00000000, 0x0ee7e8d1, 0x1dcfd1a2, 0x13283973, 0x3b9fa344, + 0x35784b95, 0x265072e6, 0x28b79a37, 0x773f4688, 0x79d8ae59, + 0x6af0972a, 0x64177ffb, 0x4ca0e5cc, 0x42470d1d, 0x516f346e, + 0x5f88dcbf, 0xee7e8d10, 0xe09965c1, 0xf3b15cb2, 0xfd56b463, + 0xd5e12e54, 0xdb06c685, 0xc82efff6, 0xc6c91727, 0x9941cb98, + 0x97a62349, 0x848e1a3a, 0x8a69f2eb, 0xa2de68dc, 0xac39800d, + 0xbf11b97e, 0xb1f651af, 0x078c1c61, 0x096bf4b0, 0x1a43cdc3, + 0x14a42512, 0x3c13bf25, 0x32f457f4, 0x21dc6e87, 0x2f3b8656, + 0x70b35ae9, 0x7e54b238, 0x6d7c8b4b, 0x639b639a, 0x4b2cf9ad, + 0x45cb117c, 0x56e3280f, 0x5804c0de, 0xe9f29171, 0xe71579a0, + 0xf43d40d3, 0xfadaa802, 0xd26d3235, 0xdc8adae4, 0xcfa2e397, + 0xc1450b46, 0x9ecdd7f9, 0x902a3f28, 0x8302065b, 0x8de5ee8a, + 0xa55274bd, 0xabb59c6c, 0xb89da51f, 0xb67a4dce, 0x0f1838c2, + 0x01ffd013, 0x12d7e960, 0x1c3001b1, 0x34879b86, 0x3a607357, + 0x29484a24, 0x27afa2f5, 0x78277e4a, 0x76c0969b, 0x65e8afe8, + 0x6b0f4739, 0x43b8dd0e, 0x4d5f35df, 0x5e770cac, 0x5090e47d, + 0xe166b5d2, 0xef815d03, 0xfca96470, 0xf24e8ca1, 0xdaf91696, + 0xd41efe47, 0xc736c734, 0xc9d12fe5, 0x9659f35a, 0x98be1b8b, + 0x8b9622f8, 0x8571ca29, 0xadc6501e, 0xa321b8cf, 0xb00981bc, + 0xbeee696d, 0x089424a3, 0x0673cc72, 0x155bf501, 0x1bbc1dd0, + 0x330b87e7, 0x3dec6f36, 0x2ec45645, 0x2023be94, 0x7fab622b, + 0x714c8afa, 0x6264b389, 0x6c835b58, 0x4434c16f, 0x4ad329be, + 0x59fb10cd, 0x571cf81c, 0xe6eaa9b3, 0xe80d4162, 0xfb257811, + 0xf5c290c0, 0xdd750af7, 0xd392e226, 0xc0badb55, 0xce5d3384, + 0x91d5ef3b, 0x9f3207ea, 0x8c1a3e99, 0x82fdd648, 0xaa4a4c7f, + 0xa4ada4ae, 0xb7859ddd, 0xb962750c, 0x1e307184, 0x10d79955, + 0x03ffa026, 0x0d1848f7, 0x25afd2c0, 0x2b483a11, 0x38600362, + 0x3687ebb3, 0x690f370c, 0x67e8dfdd, 0x74c0e6ae, 0x7a270e7f, + 0x52909448, 0x5c777c99, 0x4f5f45ea, 0x41b8ad3b, 0xf04efc94, + 0xfea91445, 0xed812d36, 0xe366c5e7, 0xcbd15fd0, 0xc536b701, + 0xd61e8e72, 0xd8f966a3, 0x8771ba1c, 0x899652cd, 0x9abe6bbe, + 0x9459836f, 0xbcee1958, 0xb209f189, 0xa121c8fa, 0xafc6202b, + 0x19bc6de5, 0x175b8534, 0x0473bc47, 0x0a945496, 0x2223cea1, + 0x2cc42670, 0x3fec1f03, 0x310bf7d2, 0x6e832b6d, 0x6064c3bc, + 0x734cfacf, 0x7dab121e, 0x551c8829, 0x5bfb60f8, 0x48d3598b, + 0x4634b15a, 0xf7c2e0f5, 0xf9250824, 0xea0d3157, 0xe4ead986, + 0xcc5d43b1, 0xc2baab60, 0xd1929213, 0xdf757ac2, 0x80fda67d, + 0x8e1a4eac, 0x9d3277df, 0x93d59f0e, 0xbb620539, 0xb585ede8, + 0xa6add49b, 0xa84a3c4a, 0x11284946, 0x1fcfa197, 0x0ce798e4, + 0x02007035, 0x2ab7ea02, 0x245002d3, 0x37783ba0, 0x399fd371, + 0x66170fce, 0x68f0e71f, 0x7bd8de6c, 0x753f36bd, 0x5d88ac8a, + 0x536f445b, 0x40477d28, 0x4ea095f9, 0xff56c456, 0xf1b12c87, + 0xe29915f4, 0xec7efd25, 0xc4c96712, 0xca2e8fc3, 0xd906b6b0, + 0xd7e15e61, 0x886982de, 0x868e6a0f, 0x95a6537c, 0x9b41bbad, + 0xb3f6219a, 0xbd11c94b, 0xae39f038, 0xa0de18e9, 0x16a45527, + 0x1843bdf6, 0x0b6b8485, 0x058c6c54, 0x2d3bf663, 0x23dc1eb2, + 0x30f427c1, 0x3e13cf10, 0x619b13af, 0x6f7cfb7e, 0x7c54c20d, + 0x72b32adc, 0x5a04b0eb, 0x54e3583a, 0x47cb6149, 0x492c8998, + 0xf8dad837, 0xf63d30e6, 0xe5150995, 0xebf2e144, 0xc3457b73, + 0xcda293a2, 0xde8aaad1, 0xd06d4200, 0x8fe59ebf, 0x8102766e, + 0x922a4f1d, 0x9ccda7cc, 0xb47a3dfb, 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0x4a52d4b1, 0x488cd396, 0x49392e8b, 0xdafe8e80, 0xdb4b739d, + 0xd99574ba, 0xd82089a7, 0xdc297af4, 0xdd9c87e9, 0xdf4280ce, + 0xdef77dd3, 0xd7516668, 0xd6e49b75, 0xd43a9c52, 0xd58f614f, + 0xd186921c, 0xd0336f01, 0xd2ed6826, 0xd358953b, 0xc1a15f50, + 0xc014a24d, 0xc2caa56a, 0xc37f5877, 0xc776ab24, 0xc6c35639, + 0xc41d511e, 0xc5a8ac03, 0xcc0eb7b8, 0xcdbb4aa5, 0xcf654d82, + 0xced0b09f, 0xcad943cc, 0xcb6cbed1, 0xc9b2b9f6, 0xc80744eb, + 0xec412d20, 0xedf4d03d, 0xef2ad71a, 0xee9f2a07, 0xea96d954, + 0xeb232449, 0xe9fd236e, 0xe848de73, 0xe1eec5c8, 0xe05b38d5, + 0xe2853ff2, 0xe330c2ef, 0xe73931bc, 0xe68ccca1, 0xe452cb86, + 0xe5e7369b, 0xf71efcf0, 0xf6ab01ed, 0xf47506ca, 0xf5c0fbd7, + 0xf1c90884, 0xf07cf599, 0xf2a2f2be, 0xf3170fa3, 0xfab11418, + 0xfb04e905, 0xf9daee22, 0xf86f133f, 0xfc66e06c, 0xfdd31d71, + 0xff0d1a56, 0xfeb8e74b, 0xb781c9c0, 0xb63434dd, 0xb4ea33fa, + 0xb55fcee7, 0xb1563db4, 0xb0e3c0a9, 0xb23dc78e, 0xb3883a93, + 0xba2e2128, 0xbb9bdc35, 0xb945db12, 0xb8f0260f, 0xbcf9d55c, + 0xbd4c2841, 0xbf922f66, 0xbe27d27b, 0xacde1810, 0xad6be50d, + 0xafb5e22a, 0xae001f37, 0xaa09ec64, 0xabbc1179, 0xa962165e, + 0xa8d7eb43, 0xa171f0f8, 0xa0c40de5, 0xa21a0ac2, 0xa3aff7df, + 0xa7a6048c, 0xa613f991, 0xa4cdfeb6, 0xa57803ab, 0x813e6a60, + 0x808b977d, 0x8255905a, 0x83e06d47, 0x87e99e14, 0x865c6309, + 0x8482642e, 0x85379933, 0x8c918288, 0x8d247f95, 0x8ffa78b2, + 0x8e4f85af, 0x8a4676fc, 0x8bf38be1, 0x892d8cc6, 0x889871db, + 0x9a61bbb0, 0x9bd446ad, 0x990a418a, 0x98bfbc97, 0x9cb64fc4, + 0x9d03b2d9, 0x9fddb5fe, 0x9e6848e3, 0x97ce5358, 0x967bae45, + 0x94a5a962, 0x9510547f, 0x9119a72c, 0x90ac5a31, 0x92725d16, + 0x93c7a00b}, + {0x00000000, 0x6e8c1b41, 0xdd183682, 0xb3942dc3, 0x61416b45, + 0x0fcd7004, 0xbc595dc7, 0xd2d54686, 0xc282d68a, 0xac0ecdcb, + 0x1f9ae008, 0x7116fb49, 0xa3c3bdcf, 0xcd4fa68e, 0x7edb8b4d, + 0x1057900c, 0x5e74ab55, 0x30f8b014, 0x836c9dd7, 0xede08696, + 0x3f35c010, 0x51b9db51, 0xe22df692, 0x8ca1edd3, 0x9cf67ddf, + 0xf27a669e, 0x41ee4b5d, 0x2f62501c, 0xfdb7169a, 0x933b0ddb, + 0x20af2018, 0x4e233b59, 0xbce956aa, 0xd2654deb, 0x61f16028, + 0x0f7d7b69, 0xdda83def, 0xb32426ae, 0x00b00b6d, 0x6e3c102c, + 0x7e6b8020, 0x10e79b61, 0xa373b6a2, 0xcdffade3, 0x1f2aeb65, + 0x71a6f024, 0xc232dde7, 0xacbec6a6, 0xe29dfdff, 0x8c11e6be, + 0x3f85cb7d, 0x5109d03c, 0x83dc96ba, 0xed508dfb, 0x5ec4a038, + 0x3048bb79, 0x201f2b75, 0x4e933034, 0xfd071df7, 0x938b06b6, + 0x415e4030, 0x2fd25b71, 0x9c4676b2, 0xf2ca6df3, 0xa2a3ab15, + 0xcc2fb054, 0x7fbb9d97, 0x113786d6, 0xc3e2c050, 0xad6edb11, + 0x1efaf6d2, 0x7076ed93, 0x60217d9f, 0x0ead66de, 0xbd394b1d, + 0xd3b5505c, 0x016016da, 0x6fec0d9b, 0xdc782058, 0xb2f43b19, + 0xfcd70040, 0x925b1b01, 0x21cf36c2, 0x4f432d83, 0x9d966b05, + 0xf31a7044, 0x408e5d87, 0x2e0246c6, 0x3e55d6ca, 0x50d9cd8b, + 0xe34de048, 0x8dc1fb09, 0x5f14bd8f, 0x3198a6ce, 0x820c8b0d, + 0xec80904c, 0x1e4afdbf, 0x70c6e6fe, 0xc352cb3d, 0xadded07c, + 0x7f0b96fa, 0x11878dbb, 0xa213a078, 0xcc9fbb39, 0xdcc82b35, + 0xb2443074, 0x01d01db7, 0x6f5c06f6, 0xbd894070, 0xd3055b31, + 0x609176f2, 0x0e1d6db3, 0x403e56ea, 0x2eb24dab, 0x9d266068, + 0xf3aa7b29, 0x217f3daf, 0x4ff326ee, 0xfc670b2d, 0x92eb106c, + 0x82bc8060, 0xec309b21, 0x5fa4b6e2, 0x3128ada3, 0xe3fdeb25, + 0x8d71f064, 0x3ee5dda7, 0x5069c6e6, 0x9e36506b, 0xf0ba4b2a, + 0x432e66e9, 0x2da27da8, 0xff773b2e, 0x91fb206f, 0x226f0dac, + 0x4ce316ed, 0x5cb486e1, 0x32389da0, 0x81acb063, 0xef20ab22, + 0x3df5eda4, 0x5379f6e5, 0xe0eddb26, 0x8e61c067, 0xc042fb3e, + 0xaecee07f, 0x1d5acdbc, 0x73d6d6fd, 0xa103907b, 0xcf8f8b3a, + 0x7c1ba6f9, 0x1297bdb8, 0x02c02db4, 0x6c4c36f5, 0xdfd81b36, + 0xb1540077, 0x638146f1, 0x0d0d5db0, 0xbe997073, 0xd0156b32, + 0x22df06c1, 0x4c531d80, 0xffc73043, 0x914b2b02, 0x439e6d84, + 0x2d1276c5, 0x9e865b06, 0xf00a4047, 0xe05dd04b, 0x8ed1cb0a, + 0x3d45e6c9, 0x53c9fd88, 0x811cbb0e, 0xef90a04f, 0x5c048d8c, + 0x328896cd, 0x7cabad94, 0x1227b6d5, 0xa1b39b16, 0xcf3f8057, + 0x1deac6d1, 0x7366dd90, 0xc0f2f053, 0xae7eeb12, 0xbe297b1e, + 0xd0a5605f, 0x63314d9c, 0x0dbd56dd, 0xdf68105b, 0xb1e40b1a, + 0x027026d9, 0x6cfc3d98, 0x3c95fb7e, 0x5219e03f, 0xe18dcdfc, + 0x8f01d6bd, 0x5dd4903b, 0x33588b7a, 0x80cca6b9, 0xee40bdf8, + 0xfe172df4, 0x909b36b5, 0x230f1b76, 0x4d830037, 0x9f5646b1, + 0xf1da5df0, 0x424e7033, 0x2cc26b72, 0x62e1502b, 0x0c6d4b6a, + 0xbff966a9, 0xd1757de8, 0x03a03b6e, 0x6d2c202f, 0xdeb80dec, + 0xb03416ad, 0xa06386a1, 0xceef9de0, 0x7d7bb023, 0x13f7ab62, + 0xc122ede4, 0xafaef6a5, 0x1c3adb66, 0x72b6c027, 0x807cadd4, + 0xeef0b695, 0x5d649b56, 0x33e88017, 0xe13dc691, 0x8fb1ddd0, + 0x3c25f013, 0x52a9eb52, 0x42fe7b5e, 0x2c72601f, 0x9fe64ddc, + 0xf16a569d, 0x23bf101b, 0x4d330b5a, 0xfea72699, 0x902b3dd8, + 0xde080681, 0xb0841dc0, 0x03103003, 0x6d9c2b42, 0xbf496dc4, + 0xd1c57685, 0x62515b46, 0x0cdd4007, 0x1c8ad00b, 0x7206cb4a, + 0xc192e689, 0xaf1efdc8, 0x7dcbbb4e, 0x1347a00f, 0xa0d38dcc, + 0xce5f968d}, + {0x00000000, 0xe71da697, 0x154a4b6f, 0xf257edf8, 0x2a9496de, + 0xcd893049, 0x3fdeddb1, 0xd8c37b26, 0x55292dbc, 0xb2348b2b, + 0x406366d3, 0xa77ec044, 0x7fbdbb62, 0x98a01df5, 0x6af7f00d, + 0x8dea569a, 0xaa525b78, 0x4d4ffdef, 0xbf181017, 0x5805b680, + 0x80c6cda6, 0x67db6b31, 0x958c86c9, 0x7291205e, 0xff7b76c4, + 0x1866d053, 0xea313dab, 0x0d2c9b3c, 0xd5efe01a, 0x32f2468d, + 0xc0a5ab75, 0x27b80de2, 0x8fd5b0b1, 0x68c81626, 0x9a9ffbde, + 0x7d825d49, 0xa541266f, 0x425c80f8, 0xb00b6d00, 0x5716cb97, + 0xdafc9d0d, 0x3de13b9a, 0xcfb6d662, 0x28ab70f5, 0xf0680bd3, + 0x1775ad44, 0xe52240bc, 0x023fe62b, 0x2587ebc9, 0xc29a4d5e, + 0x30cda0a6, 0xd7d00631, 0x0f137d17, 0xe80edb80, 0x1a593678, + 0xfd4490ef, 0x70aec675, 0x97b360e2, 0x65e48d1a, 0x82f92b8d, + 0x5a3a50ab, 0xbd27f63c, 0x4f701bc4, 0xa86dbd53, 0xc4da6723, + 0x23c7c1b4, 0xd1902c4c, 0x368d8adb, 0xee4ef1fd, 0x0953576a, + 0xfb04ba92, 0x1c191c05, 0x91f34a9f, 0x76eeec08, 0x84b901f0, + 0x63a4a767, 0xbb67dc41, 0x5c7a7ad6, 0xae2d972e, 0x493031b9, + 0x6e883c5b, 0x89959acc, 0x7bc27734, 0x9cdfd1a3, 0x441caa85, + 0xa3010c12, 0x5156e1ea, 0xb64b477d, 0x3ba111e7, 0xdcbcb770, + 0x2eeb5a88, 0xc9f6fc1f, 0x11358739, 0xf62821ae, 0x047fcc56, + 0xe3626ac1, 0x4b0fd792, 0xac127105, 0x5e459cfd, 0xb9583a6a, + 0x619b414c, 0x8686e7db, 0x74d10a23, 0x93ccacb4, 0x1e26fa2e, + 0xf93b5cb9, 0x0b6cb141, 0xec7117d6, 0x34b26cf0, 0xd3afca67, + 0x21f8279f, 0xc6e58108, 0xe15d8cea, 0x06402a7d, 0xf417c785, + 0x130a6112, 0xcbc91a34, 0x2cd4bca3, 0xde83515b, 0x399ef7cc, + 0xb474a156, 0x536907c1, 0xa13eea39, 0x46234cae, 0x9ee03788, + 0x79fd911f, 0x8baa7ce7, 0x6cb7da70, 0x52c5c807, 0xb5d86e90, + 0x478f8368, 0xa09225ff, 0x78515ed9, 0x9f4cf84e, 0x6d1b15b6, + 0x8a06b321, 0x07ece5bb, 0xe0f1432c, 0x12a6aed4, 0xf5bb0843, + 0x2d787365, 0xca65d5f2, 0x3832380a, 0xdf2f9e9d, 0xf897937f, + 0x1f8a35e8, 0xedddd810, 0x0ac07e87, 0xd20305a1, 0x351ea336, + 0xc7494ece, 0x2054e859, 0xadbebec3, 0x4aa31854, 0xb8f4f5ac, + 0x5fe9533b, 0x872a281d, 0x60378e8a, 0x92606372, 0x757dc5e5, + 0xdd1078b6, 0x3a0dde21, 0xc85a33d9, 0x2f47954e, 0xf784ee68, + 0x109948ff, 0xe2cea507, 0x05d30390, 0x8839550a, 0x6f24f39d, + 0x9d731e65, 0x7a6eb8f2, 0xa2adc3d4, 0x45b06543, 0xb7e788bb, + 0x50fa2e2c, 0x774223ce, 0x905f8559, 0x620868a1, 0x8515ce36, + 0x5dd6b510, 0xbacb1387, 0x489cfe7f, 0xaf8158e8, 0x226b0e72, + 0xc576a8e5, 0x3721451d, 0xd03ce38a, 0x08ff98ac, 0xefe23e3b, + 0x1db5d3c3, 0xfaa87554, 0x961faf24, 0x710209b3, 0x8355e44b, + 0x644842dc, 0xbc8b39fa, 0x5b969f6d, 0xa9c17295, 0x4edcd402, + 0xc3368298, 0x242b240f, 0xd67cc9f7, 0x31616f60, 0xe9a21446, + 0x0ebfb2d1, 0xfce85f29, 0x1bf5f9be, 0x3c4df45c, 0xdb5052cb, + 0x2907bf33, 0xce1a19a4, 0x16d96282, 0xf1c4c415, 0x039329ed, + 0xe48e8f7a, 0x6964d9e0, 0x8e797f77, 0x7c2e928f, 0x9b333418, + 0x43f04f3e, 0xa4ede9a9, 0x56ba0451, 0xb1a7a2c6, 0x19ca1f95, + 0xfed7b902, 0x0c8054fa, 0xeb9df26d, 0x335e894b, 0xd4432fdc, + 0x2614c224, 0xc10964b3, 0x4ce33229, 0xabfe94be, 0x59a97946, + 0xbeb4dfd1, 0x6677a4f7, 0x816a0260, 0x733def98, 0x9420490f, + 0xb39844ed, 0x5485e27a, 0xa6d20f82, 0x41cfa915, 0x990cd233, + 0x7e1174a4, 0x8c46995c, 0x6b5b3fcb, 0xe6b16951, 0x01accfc6, + 0xf3fb223e, 0x14e684a9, 0xcc25ff8f, 0x2b385918, 0xd96fb4e0, + 0x3e721277}, + {0x00000000, 0xa58b900e, 0x9066265d, 0x35edb653, 0xfbbd4afb, + 0x5e36daf5, 0x6bdb6ca6, 0xce50fca8, 0x2c0b93b7, 0x898003b9, + 0xbc6db5ea, 0x19e625e4, 0xd7b6d94c, 0x723d4942, 0x47d0ff11, + 0xe25b6f1f, 0x5817276e, 0xfd9cb760, 0xc8710133, 0x6dfa913d, + 0xa3aa6d95, 0x0621fd9b, 0x33cc4bc8, 0x9647dbc6, 0x741cb4d9, + 0xd19724d7, 0xe47a9284, 0x41f1028a, 0x8fa1fe22, 0x2a2a6e2c, + 0x1fc7d87f, 0xba4c4871, 0xb02e4edc, 0x15a5ded2, 0x20486881, + 0x85c3f88f, 0x4b930427, 0xee189429, 0xdbf5227a, 0x7e7eb274, + 0x9c25dd6b, 0x39ae4d65, 0x0c43fb36, 0xa9c86b38, 0x67989790, + 0xc213079e, 0xf7feb1cd, 0x527521c3, 0xe83969b2, 0x4db2f9bc, + 0x785f4fef, 0xddd4dfe1, 0x13842349, 0xb60fb347, 0x83e20514, + 0x2669951a, 0xc432fa05, 0x61b96a0b, 0x5454dc58, 0xf1df4c56, + 0x3f8fb0fe, 0x9a0420f0, 0xafe996a3, 0x0a6206ad, 0xbb2d9bf9, + 0x1ea60bf7, 0x2b4bbda4, 0x8ec02daa, 0x4090d102, 0xe51b410c, + 0xd0f6f75f, 0x757d6751, 0x9726084e, 0x32ad9840, 0x07402e13, + 0xa2cbbe1d, 0x6c9b42b5, 0xc910d2bb, 0xfcfd64e8, 0x5976f4e6, + 0xe33abc97, 0x46b12c99, 0x735c9aca, 0xd6d70ac4, 0x1887f66c, + 0xbd0c6662, 0x88e1d031, 0x2d6a403f, 0xcf312f20, 0x6ababf2e, + 0x5f57097d, 0xfadc9973, 0x348c65db, 0x9107f5d5, 0xa4ea4386, + 0x0161d388, 0x0b03d525, 0xae88452b, 0x9b65f378, 0x3eee6376, + 0xf0be9fde, 0x55350fd0, 0x60d8b983, 0xc553298d, 0x27084692, + 0x8283d69c, 0xb76e60cf, 0x12e5f0c1, 0xdcb50c69, 0x793e9c67, + 0x4cd32a34, 0xe958ba3a, 0x5314f24b, 0xf69f6245, 0xc372d416, + 0x66f94418, 0xa8a9b8b0, 0x0d2228be, 0x38cf9eed, 0x9d440ee3, + 0x7f1f61fc, 0xda94f1f2, 0xef7947a1, 0x4af2d7af, 0x84a22b07, + 0x2129bb09, 0x14c40d5a, 0xb14f9d54, 0xad2a31b3, 0x08a1a1bd, + 0x3d4c17ee, 0x98c787e0, 0x56977b48, 0xf31ceb46, 0xc6f15d15, + 0x637acd1b, 0x8121a204, 0x24aa320a, 0x11478459, 0xb4cc1457, + 0x7a9ce8ff, 0xdf1778f1, 0xeafacea2, 0x4f715eac, 0xf53d16dd, + 0x50b686d3, 0x655b3080, 0xc0d0a08e, 0x0e805c26, 0xab0bcc28, + 0x9ee67a7b, 0x3b6dea75, 0xd936856a, 0x7cbd1564, 0x4950a337, + 0xecdb3339, 0x228bcf91, 0x87005f9f, 0xb2ede9cc, 0x176679c2, + 0x1d047f6f, 0xb88fef61, 0x8d625932, 0x28e9c93c, 0xe6b93594, + 0x4332a59a, 0x76df13c9, 0xd35483c7, 0x310fecd8, 0x94847cd6, + 0xa169ca85, 0x04e25a8b, 0xcab2a623, 0x6f39362d, 0x5ad4807e, + 0xff5f1070, 0x45135801, 0xe098c80f, 0xd5757e5c, 0x70feee52, + 0xbeae12fa, 0x1b2582f4, 0x2ec834a7, 0x8b43a4a9, 0x6918cbb6, + 0xcc935bb8, 0xf97eedeb, 0x5cf57de5, 0x92a5814d, 0x372e1143, + 0x02c3a710, 0xa748371e, 0x1607aa4a, 0xb38c3a44, 0x86618c17, + 0x23ea1c19, 0xedbae0b1, 0x483170bf, 0x7ddcc6ec, 0xd85756e2, + 0x3a0c39fd, 0x9f87a9f3, 0xaa6a1fa0, 0x0fe18fae, 0xc1b17306, + 0x643ae308, 0x51d7555b, 0xf45cc555, 0x4e108d24, 0xeb9b1d2a, + 0xde76ab79, 0x7bfd3b77, 0xb5adc7df, 0x102657d1, 0x25cbe182, + 0x8040718c, 0x621b1e93, 0xc7908e9d, 0xf27d38ce, 0x57f6a8c0, + 0x99a65468, 0x3c2dc466, 0x09c07235, 0xac4be23b, 0xa629e496, + 0x03a27498, 0x364fc2cb, 0x93c452c5, 0x5d94ae6d, 0xf81f3e63, + 0xcdf28830, 0x6879183e, 0x8a227721, 0x2fa9e72f, 0x1a44517c, + 0xbfcfc172, 0x719f3dda, 0xd414add4, 0xe1f91b87, 0x44728b89, + 0xfe3ec3f8, 0x5bb553f6, 0x6e58e5a5, 0xcbd375ab, 0x05838903, + 0xa008190d, 0x95e5af5e, 0x306e3f50, 0xd235504f, 0x77bec041, + 0x42537612, 0xe7d8e61c, 0x29881ab4, 0x8c038aba, 0xb9ee3ce9, + 0x1c65ace7}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x0000000000000000, 0x0e908ba500000000, 0x5d26669000000000, + 0x53b6ed3500000000, 0xfb4abdfb00000000, 0xf5da365e00000000, + 0xa66cdb6b00000000, 0xa8fc50ce00000000, 0xb7930b2c00000000, + 0xb903808900000000, 0xeab56dbc00000000, 0xe425e61900000000, + 0x4cd9b6d700000000, 0x42493d7200000000, 0x11ffd04700000000, + 0x1f6f5be200000000, 0x6e27175800000000, 0x60b79cfd00000000, + 0x330171c800000000, 0x3d91fa6d00000000, 0x956daaa300000000, + 0x9bfd210600000000, 0xc84bcc3300000000, 0xc6db479600000000, + 0xd9b41c7400000000, 0xd72497d100000000, 0x84927ae400000000, + 0x8a02f14100000000, 0x22fea18f00000000, 0x2c6e2a2a00000000, + 0x7fd8c71f00000000, 0x71484cba00000000, 0xdc4e2eb000000000, + 0xd2dea51500000000, 0x8168482000000000, 0x8ff8c38500000000, + 0x2704934b00000000, 0x299418ee00000000, 0x7a22f5db00000000, + 0x74b27e7e00000000, 0x6bdd259c00000000, 0x654dae3900000000, + 0x36fb430c00000000, 0x386bc8a900000000, 0x9097986700000000, + 0x9e0713c200000000, 0xcdb1fef700000000, 0xc321755200000000, + 0xb26939e800000000, 0xbcf9b24d00000000, 0xef4f5f7800000000, + 0xe1dfd4dd00000000, 0x4923841300000000, 0x47b30fb600000000, + 0x1405e28300000000, 0x1a95692600000000, 0x05fa32c400000000, + 0x0b6ab96100000000, 0x58dc545400000000, 0x564cdff100000000, + 0xfeb08f3f00000000, 0xf020049a00000000, 0xa396e9af00000000, + 0xad06620a00000000, 0xf99b2dbb00000000, 0xf70ba61e00000000, + 0xa4bd4b2b00000000, 0xaa2dc08e00000000, 0x02d1904000000000, + 0x0c411be500000000, 0x5ff7f6d000000000, 0x51677d7500000000, + 0x4e08269700000000, 0x4098ad3200000000, 0x132e400700000000, + 0x1dbecba200000000, 0xb5429b6c00000000, 0xbbd210c900000000, + 0xe864fdfc00000000, 0xe6f4765900000000, 0x97bc3ae300000000, + 0x992cb14600000000, 0xca9a5c7300000000, 0xc40ad7d600000000, + 0x6cf6871800000000, 0x62660cbd00000000, 0x31d0e18800000000, + 0x3f406a2d00000000, 0x202f31cf00000000, 0x2ebfba6a00000000, + 0x7d09575f00000000, 0x7399dcfa00000000, 0xdb658c3400000000, + 0xd5f5079100000000, 0x8643eaa400000000, 0x88d3610100000000, + 0x25d5030b00000000, 0x2b4588ae00000000, 0x78f3659b00000000, + 0x7663ee3e00000000, 0xde9fbef000000000, 0xd00f355500000000, + 0x83b9d86000000000, 0x8d2953c500000000, 0x9246082700000000, + 0x9cd6838200000000, 0xcf606eb700000000, 0xc1f0e51200000000, + 0x690cb5dc00000000, 0x679c3e7900000000, 0x342ad34c00000000, + 0x3aba58e900000000, 0x4bf2145300000000, 0x45629ff600000000, + 0x16d472c300000000, 0x1844f96600000000, 0xb0b8a9a800000000, + 0xbe28220d00000000, 0xed9ecf3800000000, 0xe30e449d00000000, + 0xfc611f7f00000000, 0xf2f194da00000000, 0xa14779ef00000000, + 0xafd7f24a00000000, 0x072ba28400000000, 0x09bb292100000000, + 0x5a0dc41400000000, 0x549d4fb100000000, 0xb3312aad00000000, + 0xbda1a10800000000, 0xee174c3d00000000, 0xe087c79800000000, + 0x487b975600000000, 0x46eb1cf300000000, 0x155df1c600000000, + 0x1bcd7a6300000000, 0x04a2218100000000, 0x0a32aa2400000000, + 0x5984471100000000, 0x5714ccb400000000, 0xffe89c7a00000000, + 0xf17817df00000000, 0xa2cefaea00000000, 0xac5e714f00000000, + 0xdd163df500000000, 0xd386b65000000000, 0x80305b6500000000, + 0x8ea0d0c000000000, 0x265c800e00000000, 0x28cc0bab00000000, + 0x7b7ae69e00000000, 0x75ea6d3b00000000, 0x6a8536d900000000, + 0x6415bd7c00000000, 0x37a3504900000000, 0x3933dbec00000000, + 0x91cf8b2200000000, 0x9f5f008700000000, 0xcce9edb200000000, + 0xc279661700000000, 0x6f7f041d00000000, 0x61ef8fb800000000, + 0x3259628d00000000, 0x3cc9e92800000000, 0x9435b9e600000000, + 0x9aa5324300000000, 0xc913df7600000000, 0xc78354d300000000, + 0xd8ec0f3100000000, 0xd67c849400000000, 0x85ca69a100000000, + 0x8b5ae20400000000, 0x23a6b2ca00000000, 0x2d36396f00000000, + 0x7e80d45a00000000, 0x70105fff00000000, 0x0158134500000000, + 0x0fc898e000000000, 0x5c7e75d500000000, 0x52eefe7000000000, + 0xfa12aebe00000000, 0xf482251b00000000, 0xa734c82e00000000, + 0xa9a4438b00000000, 0xb6cb186900000000, 0xb85b93cc00000000, + 0xebed7ef900000000, 0xe57df55c00000000, 0x4d81a59200000000, + 0x43112e3700000000, 0x10a7c30200000000, 0x1e3748a700000000, + 0x4aaa071600000000, 0x443a8cb300000000, 0x178c618600000000, + 0x191cea2300000000, 0xb1e0baed00000000, 0xbf70314800000000, + 0xecc6dc7d00000000, 0xe25657d800000000, 0xfd390c3a00000000, + 0xf3a9879f00000000, 0xa01f6aaa00000000, 0xae8fe10f00000000, + 0x0673b1c100000000, 0x08e33a6400000000, 0x5b55d75100000000, + 0x55c55cf400000000, 0x248d104e00000000, 0x2a1d9beb00000000, + 0x79ab76de00000000, 0x773bfd7b00000000, 0xdfc7adb500000000, + 0xd157261000000000, 0x82e1cb2500000000, 0x8c71408000000000, + 0x931e1b6200000000, 0x9d8e90c700000000, 0xce387df200000000, + 0xc0a8f65700000000, 0x6854a69900000000, 0x66c42d3c00000000, + 0x3572c00900000000, 0x3be24bac00000000, 0x96e429a600000000, + 0x9874a20300000000, 0xcbc24f3600000000, 0xc552c49300000000, + 0x6dae945d00000000, 0x633e1ff800000000, 0x3088f2cd00000000, + 0x3e18796800000000, 0x2177228a00000000, 0x2fe7a92f00000000, + 0x7c51441a00000000, 0x72c1cfbf00000000, 0xda3d9f7100000000, + 0xd4ad14d400000000, 0x871bf9e100000000, 0x898b724400000000, + 0xf8c33efe00000000, 0xf653b55b00000000, 0xa5e5586e00000000, + 0xab75d3cb00000000, 0x0389830500000000, 0x0d1908a000000000, + 0x5eafe59500000000, 0x503f6e3000000000, 0x4f5035d200000000, + 0x41c0be7700000000, 0x1276534200000000, 0x1ce6d8e700000000, + 0xb41a882900000000, 0xba8a038c00000000, 0xe93ceeb900000000, + 0xe7ac651c00000000}, + {0x0000000000000000, 0x97a61de700000000, 0x6f4b4a1500000000, + 0xf8ed57f200000000, 0xde96942a00000000, 0x493089cd00000000, + 0xb1ddde3f00000000, 0x267bc3d800000000, 0xbc2d295500000000, + 0x2b8b34b200000000, 0xd366634000000000, 0x44c07ea700000000, + 0x62bbbd7f00000000, 0xf51da09800000000, 0x0df0f76a00000000, + 0x9a56ea8d00000000, 0x785b52aa00000000, 0xeffd4f4d00000000, + 0x171018bf00000000, 0x80b6055800000000, 0xa6cdc68000000000, + 0x316bdb6700000000, 0xc9868c9500000000, 0x5e20917200000000, + 0xc4767bff00000000, 0x53d0661800000000, 0xab3d31ea00000000, + 0x3c9b2c0d00000000, 0x1ae0efd500000000, 0x8d46f23200000000, + 0x75aba5c000000000, 0xe20db82700000000, 0xb1b0d58f00000000, + 0x2616c86800000000, 0xdefb9f9a00000000, 0x495d827d00000000, + 0x6f2641a500000000, 0xf8805c4200000000, 0x006d0bb000000000, + 0x97cb165700000000, 0x0d9dfcda00000000, 0x9a3be13d00000000, + 0x62d6b6cf00000000, 0xf570ab2800000000, 0xd30b68f000000000, + 0x44ad751700000000, 0xbc4022e500000000, 0x2be63f0200000000, + 0xc9eb872500000000, 0x5e4d9ac200000000, 0xa6a0cd3000000000, + 0x3106d0d700000000, 0x177d130f00000000, 0x80db0ee800000000, + 0x7836591a00000000, 0xef9044fd00000000, 0x75c6ae7000000000, + 0xe260b39700000000, 0x1a8de46500000000, 0x8d2bf98200000000, + 0xab503a5a00000000, 0x3cf627bd00000000, 0xc41b704f00000000, + 0x53bd6da800000000, 0x2367dac400000000, 0xb4c1c72300000000, + 0x4c2c90d100000000, 0xdb8a8d3600000000, 0xfdf14eee00000000, + 0x6a57530900000000, 0x92ba04fb00000000, 0x051c191c00000000, + 0x9f4af39100000000, 0x08ecee7600000000, 0xf001b98400000000, + 0x67a7a46300000000, 0x41dc67bb00000000, 0xd67a7a5c00000000, + 0x2e972dae00000000, 0xb931304900000000, 0x5b3c886e00000000, + 0xcc9a958900000000, 0x3477c27b00000000, 0xa3d1df9c00000000, + 0x85aa1c4400000000, 0x120c01a300000000, 0xeae1565100000000, + 0x7d474bb600000000, 0xe711a13b00000000, 0x70b7bcdc00000000, + 0x885aeb2e00000000, 0x1ffcf6c900000000, 0x3987351100000000, + 0xae2128f600000000, 0x56cc7f0400000000, 0xc16a62e300000000, + 0x92d70f4b00000000, 0x057112ac00000000, 0xfd9c455e00000000, + 0x6a3a58b900000000, 0x4c419b6100000000, 0xdbe7868600000000, + 0x230ad17400000000, 0xb4accc9300000000, 0x2efa261e00000000, + 0xb95c3bf900000000, 0x41b16c0b00000000, 0xd61771ec00000000, + 0xf06cb23400000000, 0x67caafd300000000, 0x9f27f82100000000, + 0x0881e5c600000000, 0xea8c5de100000000, 0x7d2a400600000000, + 0x85c717f400000000, 0x12610a1300000000, 0x341ac9cb00000000, + 0xa3bcd42c00000000, 0x5b5183de00000000, 0xccf79e3900000000, + 0x56a174b400000000, 0xc107695300000000, 0x39ea3ea100000000, + 0xae4c234600000000, 0x8837e09e00000000, 0x1f91fd7900000000, + 0xe77caa8b00000000, 0x70dab76c00000000, 0x07c8c55200000000, + 0x906ed8b500000000, 0x68838f4700000000, 0xff2592a000000000, + 0xd95e517800000000, 0x4ef84c9f00000000, 0xb6151b6d00000000, + 0x21b3068a00000000, 0xbbe5ec0700000000, 0x2c43f1e000000000, + 0xd4aea61200000000, 0x4308bbf500000000, 0x6573782d00000000, + 0xf2d565ca00000000, 0x0a38323800000000, 0x9d9e2fdf00000000, + 0x7f9397f800000000, 0xe8358a1f00000000, 0x10d8dded00000000, + 0x877ec00a00000000, 0xa10503d200000000, 0x36a31e3500000000, + 0xce4e49c700000000, 0x59e8542000000000, 0xc3bebead00000000, + 0x5418a34a00000000, 0xacf5f4b800000000, 0x3b53e95f00000000, + 0x1d282a8700000000, 0x8a8e376000000000, 0x7263609200000000, + 0xe5c57d7500000000, 0xb67810dd00000000, 0x21de0d3a00000000, + 0xd9335ac800000000, 0x4e95472f00000000, 0x68ee84f700000000, + 0xff48991000000000, 0x07a5cee200000000, 0x9003d30500000000, + 0x0a55398800000000, 0x9df3246f00000000, 0x651e739d00000000, + 0xf2b86e7a00000000, 0xd4c3ada200000000, 0x4365b04500000000, + 0xbb88e7b700000000, 0x2c2efa5000000000, 0xce23427700000000, + 0x59855f9000000000, 0xa168086200000000, 0x36ce158500000000, + 0x10b5d65d00000000, 0x8713cbba00000000, 0x7ffe9c4800000000, + 0xe85881af00000000, 0x720e6b2200000000, 0xe5a876c500000000, + 0x1d45213700000000, 0x8ae33cd000000000, 0xac98ff0800000000, + 0x3b3ee2ef00000000, 0xc3d3b51d00000000, 0x5475a8fa00000000, + 0x24af1f9600000000, 0xb309027100000000, 0x4be4558300000000, + 0xdc42486400000000, 0xfa398bbc00000000, 0x6d9f965b00000000, + 0x9572c1a900000000, 0x02d4dc4e00000000, 0x988236c300000000, + 0x0f242b2400000000, 0xf7c97cd600000000, 0x606f613100000000, + 0x4614a2e900000000, 0xd1b2bf0e00000000, 0x295fe8fc00000000, + 0xbef9f51b00000000, 0x5cf44d3c00000000, 0xcb5250db00000000, + 0x33bf072900000000, 0xa4191ace00000000, 0x8262d91600000000, + 0x15c4c4f100000000, 0xed29930300000000, 0x7a8f8ee400000000, + 0xe0d9646900000000, 0x777f798e00000000, 0x8f922e7c00000000, + 0x1834339b00000000, 0x3e4ff04300000000, 0xa9e9eda400000000, + 0x5104ba5600000000, 0xc6a2a7b100000000, 0x951fca1900000000, + 0x02b9d7fe00000000, 0xfa54800c00000000, 0x6df29deb00000000, + 0x4b895e3300000000, 0xdc2f43d400000000, 0x24c2142600000000, + 0xb36409c100000000, 0x2932e34c00000000, 0xbe94feab00000000, + 0x4679a95900000000, 0xd1dfb4be00000000, 0xf7a4776600000000, + 0x60026a8100000000, 0x98ef3d7300000000, 0x0f49209400000000, + 0xed4498b300000000, 0x7ae2855400000000, 0x820fd2a600000000, + 0x15a9cf4100000000, 0x33d20c9900000000, 0xa474117e00000000, + 0x5c99468c00000000, 0xcb3f5b6b00000000, 0x5169b1e600000000, + 0xc6cfac0100000000, 0x3e22fbf300000000, 0xa984e61400000000, + 0x8fff25cc00000000, 0x1859382b00000000, 0xe0b46fd900000000, + 0x7712723e00000000}, + {0x0000000000000000, 0x411b8c6e00000000, 0x823618dd00000000, + 0xc32d94b300000000, 0x456b416100000000, 0x0470cd0f00000000, + 0xc75d59bc00000000, 0x8646d5d200000000, 0x8ad682c200000000, + 0xcbcd0eac00000000, 0x08e09a1f00000000, 0x49fb167100000000, + 0xcfbdc3a300000000, 0x8ea64fcd00000000, 0x4d8bdb7e00000000, + 0x0c90571000000000, 0x55ab745e00000000, 0x14b0f83000000000, + 0xd79d6c8300000000, 0x9686e0ed00000000, 0x10c0353f00000000, + 0x51dbb95100000000, 0x92f62de200000000, 0xd3eda18c00000000, + 0xdf7df69c00000000, 0x9e667af200000000, 0x5d4bee4100000000, + 0x1c50622f00000000, 0x9a16b7fd00000000, 0xdb0d3b9300000000, + 0x1820af2000000000, 0x593b234e00000000, 0xaa56e9bc00000000, + 0xeb4d65d200000000, 0x2860f16100000000, 0x697b7d0f00000000, + 0xef3da8dd00000000, 0xae2624b300000000, 0x6d0bb00000000000, + 0x2c103c6e00000000, 0x20806b7e00000000, 0x619be71000000000, + 0xa2b673a300000000, 0xe3adffcd00000000, 0x65eb2a1f00000000, + 0x24f0a67100000000, 0xe7dd32c200000000, 0xa6c6beac00000000, + 0xfffd9de200000000, 0xbee6118c00000000, 0x7dcb853f00000000, + 0x3cd0095100000000, 0xba96dc8300000000, 0xfb8d50ed00000000, + 0x38a0c45e00000000, 0x79bb483000000000, 0x752b1f2000000000, + 0x3430934e00000000, 0xf71d07fd00000000, 0xb6068b9300000000, + 0x30405e4100000000, 0x715bd22f00000000, 0xb276469c00000000, + 0xf36dcaf200000000, 0x15aba3a200000000, 0x54b02fcc00000000, + 0x979dbb7f00000000, 0xd686371100000000, 0x50c0e2c300000000, + 0x11db6ead00000000, 0xd2f6fa1e00000000, 0x93ed767000000000, + 0x9f7d216000000000, 0xde66ad0e00000000, 0x1d4b39bd00000000, + 0x5c50b5d300000000, 0xda16600100000000, 0x9b0dec6f00000000, + 0x582078dc00000000, 0x193bf4b200000000, 0x4000d7fc00000000, + 0x011b5b9200000000, 0xc236cf2100000000, 0x832d434f00000000, + 0x056b969d00000000, 0x44701af300000000, 0x875d8e4000000000, + 0xc646022e00000000, 0xcad6553e00000000, 0x8bcdd95000000000, + 0x48e04de300000000, 0x09fbc18d00000000, 0x8fbd145f00000000, + 0xcea6983100000000, 0x0d8b0c8200000000, 0x4c9080ec00000000, + 0xbffd4a1e00000000, 0xfee6c67000000000, 0x3dcb52c300000000, + 0x7cd0dead00000000, 0xfa960b7f00000000, 0xbb8d871100000000, + 0x78a013a200000000, 0x39bb9fcc00000000, 0x352bc8dc00000000, + 0x743044b200000000, 0xb71dd00100000000, 0xf6065c6f00000000, + 0x704089bd00000000, 0x315b05d300000000, 0xf276916000000000, + 0xb36d1d0e00000000, 0xea563e4000000000, 0xab4db22e00000000, + 0x6860269d00000000, 0x297baaf300000000, 0xaf3d7f2100000000, + 0xee26f34f00000000, 0x2d0b67fc00000000, 0x6c10eb9200000000, + 0x6080bc8200000000, 0x219b30ec00000000, 0xe2b6a45f00000000, + 0xa3ad283100000000, 0x25ebfde300000000, 0x64f0718d00000000, + 0xa7dde53e00000000, 0xe6c6695000000000, 0x6b50369e00000000, + 0x2a4bbaf000000000, 0xe9662e4300000000, 0xa87da22d00000000, + 0x2e3b77ff00000000, 0x6f20fb9100000000, 0xac0d6f2200000000, + 0xed16e34c00000000, 0xe186b45c00000000, 0xa09d383200000000, + 0x63b0ac8100000000, 0x22ab20ef00000000, 0xa4edf53d00000000, + 0xe5f6795300000000, 0x26dbede000000000, 0x67c0618e00000000, + 0x3efb42c000000000, 0x7fe0ceae00000000, 0xbccd5a1d00000000, + 0xfdd6d67300000000, 0x7b9003a100000000, 0x3a8b8fcf00000000, + 0xf9a61b7c00000000, 0xb8bd971200000000, 0xb42dc00200000000, + 0xf5364c6c00000000, 0x361bd8df00000000, 0x770054b100000000, + 0xf146816300000000, 0xb05d0d0d00000000, 0x737099be00000000, + 0x326b15d000000000, 0xc106df2200000000, 0x801d534c00000000, + 0x4330c7ff00000000, 0x022b4b9100000000, 0x846d9e4300000000, + 0xc576122d00000000, 0x065b869e00000000, 0x47400af000000000, + 0x4bd05de000000000, 0x0acbd18e00000000, 0xc9e6453d00000000, + 0x88fdc95300000000, 0x0ebb1c8100000000, 0x4fa090ef00000000, + 0x8c8d045c00000000, 0xcd96883200000000, 0x94adab7c00000000, + 0xd5b6271200000000, 0x169bb3a100000000, 0x57803fcf00000000, + 0xd1c6ea1d00000000, 0x90dd667300000000, 0x53f0f2c000000000, + 0x12eb7eae00000000, 0x1e7b29be00000000, 0x5f60a5d000000000, + 0x9c4d316300000000, 0xdd56bd0d00000000, 0x5b1068df00000000, + 0x1a0be4b100000000, 0xd926700200000000, 0x983dfc6c00000000, + 0x7efb953c00000000, 0x3fe0195200000000, 0xfccd8de100000000, + 0xbdd6018f00000000, 0x3b90d45d00000000, 0x7a8b583300000000, + 0xb9a6cc8000000000, 0xf8bd40ee00000000, 0xf42d17fe00000000, + 0xb5369b9000000000, 0x761b0f2300000000, 0x3700834d00000000, + 0xb146569f00000000, 0xf05ddaf100000000, 0x33704e4200000000, + 0x726bc22c00000000, 0x2b50e16200000000, 0x6a4b6d0c00000000, + 0xa966f9bf00000000, 0xe87d75d100000000, 0x6e3ba00300000000, + 0x2f202c6d00000000, 0xec0db8de00000000, 0xad1634b000000000, + 0xa18663a000000000, 0xe09defce00000000, 0x23b07b7d00000000, + 0x62abf71300000000, 0xe4ed22c100000000, 0xa5f6aeaf00000000, + 0x66db3a1c00000000, 0x27c0b67200000000, 0xd4ad7c8000000000, + 0x95b6f0ee00000000, 0x569b645d00000000, 0x1780e83300000000, + 0x91c63de100000000, 0xd0ddb18f00000000, 0x13f0253c00000000, + 0x52eba95200000000, 0x5e7bfe4200000000, 0x1f60722c00000000, + 0xdc4de69f00000000, 0x9d566af100000000, 0x1b10bf2300000000, + 0x5a0b334d00000000, 0x9926a7fe00000000, 0xd83d2b9000000000, + 0x810608de00000000, 0xc01d84b000000000, 0x0330100300000000, + 0x422b9c6d00000000, 0xc46d49bf00000000, 0x8576c5d100000000, + 0x465b516200000000, 0x0740dd0c00000000, 0x0bd08a1c00000000, + 0x4acb067200000000, 0x89e692c100000000, 0xc8fd1eaf00000000, + 0x4ebbcb7d00000000, 0x0fa0471300000000, 0xcc8dd3a000000000, + 0x8d965fce00000000}, + {0x0000000000000000, 0x1dfdb50100000000, 0x3afa6b0300000000, + 0x2707de0200000000, 0x74f4d70600000000, 0x6909620700000000, + 0x4e0ebc0500000000, 0x53f3090400000000, 0xe8e8af0d00000000, + 0xf5151a0c00000000, 0xd212c40e00000000, 0xcfef710f00000000, + 0x9c1c780b00000000, 0x81e1cd0a00000000, 0xa6e6130800000000, + 0xbb1ba60900000000, 0xd0d15f1b00000000, 0xcd2cea1a00000000, + 0xea2b341800000000, 0xf7d6811900000000, 0xa425881d00000000, + 0xb9d83d1c00000000, 0x9edfe31e00000000, 0x8322561f00000000, + 0x3839f01600000000, 0x25c4451700000000, 0x02c39b1500000000, + 0x1f3e2e1400000000, 0x4ccd271000000000, 0x5130921100000000, + 0x76374c1300000000, 0x6bcaf91200000000, 0xa0a3bf3600000000, + 0xbd5e0a3700000000, 0x9a59d43500000000, 0x87a4613400000000, + 0xd457683000000000, 0xc9aadd3100000000, 0xeead033300000000, + 0xf350b63200000000, 0x484b103b00000000, 0x55b6a53a00000000, + 0x72b17b3800000000, 0x6f4cce3900000000, 0x3cbfc73d00000000, + 0x2142723c00000000, 0x0645ac3e00000000, 0x1bb8193f00000000, + 0x7072e02d00000000, 0x6d8f552c00000000, 0x4a888b2e00000000, + 0x57753e2f00000000, 0x0486372b00000000, 0x197b822a00000000, + 0x3e7c5c2800000000, 0x2381e92900000000, 0x989a4f2000000000, + 0x8567fa2100000000, 0xa260242300000000, 0xbf9d912200000000, + 0xec6e982600000000, 0xf1932d2700000000, 0xd694f32500000000, + 0xcb69462400000000, 0x40477f6d00000000, 0x5dbaca6c00000000, + 0x7abd146e00000000, 0x6740a16f00000000, 0x34b3a86b00000000, + 0x294e1d6a00000000, 0x0e49c36800000000, 0x13b4766900000000, + 0xa8afd06000000000, 0xb552656100000000, 0x9255bb6300000000, + 0x8fa80e6200000000, 0xdc5b076600000000, 0xc1a6b26700000000, + 0xe6a16c6500000000, 0xfb5cd96400000000, 0x9096207600000000, + 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0xd5bd168400000000, 0xcd98b7c000000000, + 0xc57bd7fc00000000, 0xfdd2f54900000000, 0xf531957500000000, + 0xed14343100000000, 0xe5f7540d00000000, 0xdc40008000000000, + 0xd4a360bc00000000, 0xcc86c1f800000000, 0xc465a1c400000000, + 0xfccc837100000000, 0xf42fe34d00000000, 0xec0a420900000000, + 0xe4e9223500000000}, + {0x0000000000000000, 0xd1e8e70e00000000, 0xa2d1cf1d00000000, + 0x7339281300000000, 0x44a39f3b00000000, 0x954b783500000000, + 0xe672502600000000, 0x379ab72800000000, 0x88463f7700000000, + 0x59aed87900000000, 0x2a97f06a00000000, 0xfb7f176400000000, + 0xcce5a04c00000000, 0x1d0d474200000000, 0x6e346f5100000000, + 0xbfdc885f00000000, 0x108d7eee00000000, 0xc16599e000000000, + 0xb25cb1f300000000, 0x63b456fd00000000, 0x542ee1d500000000, + 0x85c606db00000000, 0xf6ff2ec800000000, 0x2717c9c600000000, + 0x98cb419900000000, 0x4923a69700000000, 0x3a1a8e8400000000, + 0xebf2698a00000000, 0xdc68dea200000000, 0x0d8039ac00000000, + 0x7eb911bf00000000, 0xaf51f6b100000000, 0x611c8c0700000000, + 0xb0f46b0900000000, 0xc3cd431a00000000, 0x1225a41400000000, + 0x25bf133c00000000, 0xf457f43200000000, 0x876edc2100000000, + 0x56863b2f00000000, 0xe95ab37000000000, 0x38b2547e00000000, + 0x4b8b7c6d00000000, 0x9a639b6300000000, 0xadf92c4b00000000, + 0x7c11cb4500000000, 0x0f28e35600000000, 0xdec0045800000000, + 0x7191f2e900000000, 0xa07915e700000000, 0xd3403df400000000, + 0x02a8dafa00000000, 0x35326dd200000000, 0xe4da8adc00000000, + 0x97e3a2cf00000000, 0x460b45c100000000, 0xf9d7cd9e00000000, + 0x283f2a9000000000, 0x5b06028300000000, 0x8aeee58d00000000, + 0xbd7452a500000000, 0x6c9cb5ab00000000, 0x1fa59db800000000, + 0xce4d7ab600000000, 0xc238180f00000000, 0x13d0ff0100000000, + 0x60e9d71200000000, 0xb101301c00000000, 0x869b873400000000, + 0x5773603a00000000, 0x244a482900000000, 0xf5a2af2700000000, + 0x4a7e277800000000, 0x9b96c07600000000, 0xe8afe86500000000, + 0x39470f6b00000000, 0x0eddb84300000000, 0xdf355f4d00000000, + 0xac0c775e00000000, 0x7de4905000000000, 0xd2b566e100000000, + 0x035d81ef00000000, 0x7064a9fc00000000, 0xa18c4ef200000000, + 0x9616f9da00000000, 0x47fe1ed400000000, 0x34c736c700000000, + 0xe52fd1c900000000, 0x5af3599600000000, 0x8b1bbe9800000000, + 0xf822968b00000000, 0x29ca718500000000, 0x1e50c6ad00000000, + 0xcfb821a300000000, 0xbc8109b000000000, 0x6d69eebe00000000, + 0xa324940800000000, 0x72cc730600000000, 0x01f55b1500000000, + 0xd01dbc1b00000000, 0xe7870b3300000000, 0x366fec3d00000000, + 0x4556c42e00000000, 0x94be232000000000, 0x2b62ab7f00000000, + 0xfa8a4c7100000000, 0x89b3646200000000, 0x585b836c00000000, + 0x6fc1344400000000, 0xbe29d34a00000000, 0xcd10fb5900000000, + 0x1cf81c5700000000, 0xb3a9eae600000000, 0x62410de800000000, + 0x117825fb00000000, 0xc090c2f500000000, 0xf70a75dd00000000, + 0x26e292d300000000, 0x55dbbac000000000, 0x84335dce00000000, + 0x3befd59100000000, 0xea07329f00000000, 0x993e1a8c00000000, + 0x48d6fd8200000000, 0x7f4c4aaa00000000, 0xaea4ada400000000, + 0xdd9d85b700000000, 0x0c7562b900000000, 0x8471301e00000000, + 0x5599d71000000000, 0x26a0ff0300000000, 0xf748180d00000000, + 0xc0d2af2500000000, 0x113a482b00000000, 0x6203603800000000, + 0xb3eb873600000000, 0x0c370f6900000000, 0xdddfe86700000000, + 0xaee6c07400000000, 0x7f0e277a00000000, 0x4894905200000000, + 0x997c775c00000000, 0xea455f4f00000000, 0x3badb84100000000, + 0x94fc4ef000000000, 0x4514a9fe00000000, 0x362d81ed00000000, + 0xe7c566e300000000, 0xd05fd1cb00000000, 0x01b736c500000000, + 0x728e1ed600000000, 0xa366f9d800000000, 0x1cba718700000000, + 0xcd52968900000000, 0xbe6bbe9a00000000, 0x6f83599400000000, + 0x5819eebc00000000, 0x89f109b200000000, 0xfac821a100000000, + 0x2b20c6af00000000, 0xe56dbc1900000000, 0x34855b1700000000, + 0x47bc730400000000, 0x9654940a00000000, 0xa1ce232200000000, + 0x7026c42c00000000, 0x031fec3f00000000, 0xd2f70b3100000000, + 0x6d2b836e00000000, 0xbcc3646000000000, 0xcffa4c7300000000, + 0x1e12ab7d00000000, 0x29881c5500000000, 0xf860fb5b00000000, + 0x8b59d34800000000, 0x5ab1344600000000, 0xf5e0c2f700000000, + 0x240825f900000000, 0x57310dea00000000, 0x86d9eae400000000, + 0xb1435dcc00000000, 0x60abbac200000000, 0x139292d100000000, + 0xc27a75df00000000, 0x7da6fd8000000000, 0xac4e1a8e00000000, + 0xdf77329d00000000, 0x0e9fd59300000000, 0x390562bb00000000, + 0xe8ed85b500000000, 0x9bd4ada600000000, 0x4a3c4aa800000000, + 0x4649281100000000, 0x97a1cf1f00000000, 0xe498e70c00000000, + 0x3570000200000000, 0x02eab72a00000000, 0xd302502400000000, + 0xa03b783700000000, 0x71d39f3900000000, 0xce0f176600000000, + 0x1fe7f06800000000, 0x6cded87b00000000, 0xbd363f7500000000, + 0x8aac885d00000000, 0x5b446f5300000000, 0x287d474000000000, + 0xf995a04e00000000, 0x56c456ff00000000, 0x872cb1f100000000, + 0xf41599e200000000, 0x25fd7eec00000000, 0x1267c9c400000000, + 0xc38f2eca00000000, 0xb0b606d900000000, 0x615ee1d700000000, + 0xde82698800000000, 0x0f6a8e8600000000, 0x7c53a69500000000, + 0xadbb419b00000000, 0x9a21f6b300000000, 0x4bc911bd00000000, + 0x38f039ae00000000, 0xe918dea000000000, 0x2755a41600000000, + 0xf6bd431800000000, 0x85846b0b00000000, 0x546c8c0500000000, + 0x63f63b2d00000000, 0xb21edc2300000000, 0xc127f43000000000, + 0x10cf133e00000000, 0xaf139b6100000000, 0x7efb7c6f00000000, + 0x0dc2547c00000000, 0xdc2ab37200000000, 0xebb0045a00000000, + 0x3a58e35400000000, 0x4961cb4700000000, 0x98892c4900000000, + 0x37d8daf800000000, 0xe6303df600000000, 0x950915e500000000, + 0x44e1f2eb00000000, 0x737b45c300000000, 0xa293a2cd00000000, + 0xd1aa8ade00000000, 0x00426dd000000000, 0xbf9ee58f00000000, + 0x6e76028100000000, 0x1d4f2a9200000000, 0xcca7cd9c00000000, + 0xfb3d7ab400000000, 0x2ad59dba00000000, 0x59ecb5a900000000, + 0x880452a700000000}, + {0x0000000000000000, 0xaa05daf100000000, 0x150dc53800000000, + 0xbf081fc900000000, 0x2a1a8a7100000000, 0x801f508000000000, + 0x3f174f4900000000, 0x951295b800000000, 0x543414e300000000, + 0xfe31ce1200000000, 0x4139d1db00000000, 0xeb3c0b2a00000000, + 0x7e2e9e9200000000, 0xd42b446300000000, 0x6b235baa00000000, + 0xc126815b00000000, 0xe96e591d00000000, 0x436b83ec00000000, + 0xfc639c2500000000, 0x566646d400000000, 0xc374d36c00000000, + 0x6971099d00000000, 0xd679165400000000, 0x7c7ccca500000000, + 0xbd5a4dfe00000000, 0x175f970f00000000, 0xa85788c600000000, + 0x0252523700000000, 0x9740c78f00000000, 0x3d451d7e00000000, + 0x824d02b700000000, 0x2848d84600000000, 0xd2ddb23a00000000, + 0x78d868cb00000000, 0xc7d0770200000000, 0x6dd5adf300000000, + 0xf8c7384b00000000, 0x52c2e2ba00000000, 0xedcafd7300000000, + 0x47cf278200000000, 0x86e9a6d900000000, 0x2cec7c2800000000, + 0x93e463e100000000, 0x39e1b91000000000, 0xacf32ca800000000, + 0x06f6f65900000000, 0xb9fee99000000000, 0x13fb336100000000, + 0x3bb3eb2700000000, 0x91b631d600000000, 0x2ebe2e1f00000000, + 0x84bbf4ee00000000, 0x11a9615600000000, 0xbbacbba700000000, + 0x04a4a46e00000000, 0xaea17e9f00000000, 0x6f87ffc400000000, + 0xc582253500000000, 0x7a8a3afc00000000, 0xd08fe00d00000000, + 0x459d75b500000000, 0xef98af4400000000, 0x5090b08d00000000, + 0xfa956a7c00000000, 0xa4bb657500000000, 0x0ebebf8400000000, + 0xb1b6a04d00000000, 0x1bb37abc00000000, 0x8ea1ef0400000000, + 0x24a435f500000000, 0x9bac2a3c00000000, 0x31a9f0cd00000000, + 0xf08f719600000000, 0x5a8aab6700000000, 0xe582b4ae00000000, + 0x4f876e5f00000000, 0xda95fbe700000000, 0x7090211600000000, + 0xcf983edf00000000, 0x659de42e00000000, 0x4dd53c6800000000, + 0xe7d0e69900000000, 0x58d8f95000000000, 0xf2dd23a100000000, + 0x67cfb61900000000, 0xcdca6ce800000000, 0x72c2732100000000, + 0xd8c7a9d000000000, 0x19e1288b00000000, 0xb3e4f27a00000000, + 0x0cecedb300000000, 0xa6e9374200000000, 0x33fba2fa00000000, + 0x99fe780b00000000, 0x26f667c200000000, 0x8cf3bd3300000000, + 0x7666d74f00000000, 0xdc630dbe00000000, 0x636b127700000000, + 0xc96ec88600000000, 0x5c7c5d3e00000000, 0xf67987cf00000000, + 0x4971980600000000, 0xe37442f700000000, 0x2252c3ac00000000, + 0x8857195d00000000, 0x375f069400000000, 0x9d5adc6500000000, + 0x084849dd00000000, 0xa24d932c00000000, 0x1d458ce500000000, + 0xb740561400000000, 0x9f088e5200000000, 0x350d54a300000000, + 0x8a054b6a00000000, 0x2000919b00000000, 0xb512042300000000, + 0x1f17ded200000000, 0xa01fc11b00000000, 0x0a1a1bea00000000, + 0xcb3c9ab100000000, 0x6139404000000000, 0xde315f8900000000, + 0x7434857800000000, 0xe12610c000000000, 0x4b23ca3100000000, + 0xf42bd5f800000000, 0x5e2e0f0900000000, 0x4877cbea00000000, + 0xe272111b00000000, 0x5d7a0ed200000000, 0xf77fd42300000000, + 0x626d419b00000000, 0xc8689b6a00000000, 0x776084a300000000, + 0xdd655e5200000000, 0x1c43df0900000000, 0xb64605f800000000, + 0x094e1a3100000000, 0xa34bc0c000000000, 0x3659557800000000, + 0x9c5c8f8900000000, 0x2354904000000000, 0x89514ab100000000, + 0xa11992f700000000, 0x0b1c480600000000, 0xb41457cf00000000, + 0x1e118d3e00000000, 0x8b03188600000000, 0x2106c27700000000, + 0x9e0eddbe00000000, 0x340b074f00000000, 0xf52d861400000000, + 0x5f285ce500000000, 0xe020432c00000000, 0x4a2599dd00000000, + 0xdf370c6500000000, 0x7532d69400000000, 0xca3ac95d00000000, + 0x603f13ac00000000, 0x9aaa79d000000000, 0x30afa32100000000, + 0x8fa7bce800000000, 0x25a2661900000000, 0xb0b0f3a100000000, + 0x1ab5295000000000, 0xa5bd369900000000, 0x0fb8ec6800000000, + 0xce9e6d3300000000, 0x649bb7c200000000, 0xdb93a80b00000000, + 0x719672fa00000000, 0xe484e74200000000, 0x4e813db300000000, + 0xf189227a00000000, 0x5b8cf88b00000000, 0x73c420cd00000000, + 0xd9c1fa3c00000000, 0x66c9e5f500000000, 0xcccc3f0400000000, + 0x59deaabc00000000, 0xf3db704d00000000, 0x4cd36f8400000000, + 0xe6d6b57500000000, 0x27f0342e00000000, 0x8df5eedf00000000, + 0x32fdf11600000000, 0x98f82be700000000, 0x0deabe5f00000000, + 0xa7ef64ae00000000, 0x18e77b6700000000, 0xb2e2a19600000000, + 0xecccae9f00000000, 0x46c9746e00000000, 0xf9c16ba700000000, + 0x53c4b15600000000, 0xc6d624ee00000000, 0x6cd3fe1f00000000, + 0xd3dbe1d600000000, 0x79de3b2700000000, 0xb8f8ba7c00000000, + 0x12fd608d00000000, 0xadf57f4400000000, 0x07f0a5b500000000, + 0x92e2300d00000000, 0x38e7eafc00000000, 0x87eff53500000000, + 0x2dea2fc400000000, 0x05a2f78200000000, 0xafa72d7300000000, + 0x10af32ba00000000, 0xbaaae84b00000000, 0x2fb87df300000000, + 0x85bda70200000000, 0x3ab5b8cb00000000, 0x90b0623a00000000, + 0x5196e36100000000, 0xfb93399000000000, 0x449b265900000000, + 0xee9efca800000000, 0x7b8c691000000000, 0xd189b3e100000000, + 0x6e81ac2800000000, 0xc48476d900000000, 0x3e111ca500000000, + 0x9414c65400000000, 0x2b1cd99d00000000, 0x8119036c00000000, + 0x140b96d400000000, 0xbe0e4c2500000000, 0x010653ec00000000, + 0xab03891d00000000, 0x6a25084600000000, 0xc020d2b700000000, + 0x7f28cd7e00000000, 0xd52d178f00000000, 0x403f823700000000, + 0xea3a58c600000000, 0x5532470f00000000, 0xff379dfe00000000, + 0xd77f45b800000000, 0x7d7a9f4900000000, 0xc272808000000000, + 0x68775a7100000000, 0xfd65cfc900000000, 0x5760153800000000, + 0xe8680af100000000, 0x426dd00000000000, 0x834b515b00000000, + 0x294e8baa00000000, 0x9646946300000000, 0x3c434e9200000000, + 0xa951db2a00000000, 0x035401db00000000, 0xbc5c1e1200000000, + 0x1659c4e300000000}}; + +#else /* W == 4 */ + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0xae689191, 0x87a02563, 0x29c8b4f2, 0xd4314c87, + 0x7a59dd16, 0x539169e4, 0xfdf9f875, 0x73139f4f, 0xdd7b0ede, + 0xf4b3ba2c, 0x5adb2bbd, 0xa722d3c8, 0x094a4259, 0x2082f6ab, + 0x8eea673a, 0xe6273e9e, 0x484faf0f, 0x61871bfd, 0xcfef8a6c, + 0x32167219, 0x9c7ee388, 0xb5b6577a, 0x1bdec6eb, 0x9534a1d1, + 0x3b5c3040, 0x129484b2, 0xbcfc1523, 0x4105ed56, 0xef6d7cc7, + 0xc6a5c835, 0x68cd59a4, 0x173f7b7d, 0xb957eaec, 0x909f5e1e, + 0x3ef7cf8f, 0xc30e37fa, 0x6d66a66b, 0x44ae1299, 0xeac68308, + 0x642ce432, 0xca4475a3, 0xe38cc151, 0x4de450c0, 0xb01da8b5, + 0x1e753924, 0x37bd8dd6, 0x99d51c47, 0xf11845e3, 0x5f70d472, + 0x76b86080, 0xd8d0f111, 0x25290964, 0x8b4198f5, 0xa2892c07, + 0x0ce1bd96, 0x820bdaac, 0x2c634b3d, 0x05abffcf, 0xabc36e5e, + 0x563a962b, 0xf85207ba, 0xd19ab348, 0x7ff222d9, 0x2e7ef6fa, + 0x8016676b, 0xa9ded399, 0x07b64208, 0xfa4fba7d, 0x54272bec, + 0x7def9f1e, 0xd3870e8f, 0x5d6d69b5, 0xf305f824, 0xdacd4cd6, + 0x74a5dd47, 0x895c2532, 0x2734b4a3, 0x0efc0051, 0xa09491c0, + 0xc859c864, 0x663159f5, 0x4ff9ed07, 0xe1917c96, 0x1c6884e3, + 0xb2001572, 0x9bc8a180, 0x35a03011, 0xbb4a572b, 0x1522c6ba, + 0x3cea7248, 0x9282e3d9, 0x6f7b1bac, 0xc1138a3d, 0xe8db3ecf, + 0x46b3af5e, 0x39418d87, 0x97291c16, 0xbee1a8e4, 0x10893975, + 0xed70c100, 0x43185091, 0x6ad0e463, 0xc4b875f2, 0x4a5212c8, + 0xe43a8359, 0xcdf237ab, 0x639aa63a, 0x9e635e4f, 0x300bcfde, + 0x19c37b2c, 0xb7abeabd, 0xdf66b319, 0x710e2288, 0x58c6967a, + 0xf6ae07eb, 0x0b57ff9e, 0xa53f6e0f, 0x8cf7dafd, 0x229f4b6c, + 0xac752c56, 0x021dbdc7, 0x2bd50935, 0x85bd98a4, 0x784460d1, + 0xd62cf140, 0xffe445b2, 0x518cd423, 0x5cfdedf4, 0xf2957c65, + 0xdb5dc897, 0x75355906, 0x88cca173, 0x26a430e2, 0x0f6c8410, + 0xa1041581, 0x2fee72bb, 0x8186e32a, 0xa84e57d8, 0x0626c649, + 0xfbdf3e3c, 0x55b7afad, 0x7c7f1b5f, 0xd2178ace, 0xbadad36a, + 0x14b242fb, 0x3d7af609, 0x93126798, 0x6eeb9fed, 0xc0830e7c, + 0xe94bba8e, 0x47232b1f, 0xc9c94c25, 0x67a1ddb4, 0x4e696946, + 0xe001f8d7, 0x1df800a2, 0xb3909133, 0x9a5825c1, 0x3430b450, + 0x4bc29689, 0xe5aa0718, 0xcc62b3ea, 0x620a227b, 0x9ff3da0e, + 0x319b4b9f, 0x1853ff6d, 0xb63b6efc, 0x38d109c6, 0x96b99857, + 0xbf712ca5, 0x1119bd34, 0xece04541, 0x4288d4d0, 0x6b406022, + 0xc528f1b3, 0xade5a817, 0x038d3986, 0x2a458d74, 0x842d1ce5, + 0x79d4e490, 0xd7bc7501, 0xfe74c1f3, 0x501c5062, 0xdef63758, + 0x709ea6c9, 0x5956123b, 0xf73e83aa, 0x0ac77bdf, 0xa4afea4e, + 0x8d675ebc, 0x230fcf2d, 0x72831b0e, 0xdceb8a9f, 0xf5233e6d, + 0x5b4baffc, 0xa6b25789, 0x08dac618, 0x211272ea, 0x8f7ae37b, + 0x01908441, 0xaff815d0, 0x8630a122, 0x285830b3, 0xd5a1c8c6, + 0x7bc95957, 0x5201eda5, 0xfc697c34, 0x94a42590, 0x3accb401, + 0x130400f3, 0xbd6c9162, 0x40956917, 0xeefdf886, 0xc7354c74, + 0x695ddde5, 0xe7b7badf, 0x49df2b4e, 0x60179fbc, 0xce7f0e2d, + 0x3386f658, 0x9dee67c9, 0xb426d33b, 0x1a4e42aa, 0x65bc6073, + 0xcbd4f1e2, 0xe21c4510, 0x4c74d481, 0xb18d2cf4, 0x1fe5bd65, + 0x362d0997, 0x98459806, 0x16afff3c, 0xb8c76ead, 0x910fda5f, + 0x3f674bce, 0xc29eb3bb, 0x6cf6222a, 0x453e96d8, 0xeb560749, + 0x839b5eed, 0x2df3cf7c, 0x043b7b8e, 0xaa53ea1f, 0x57aa126a, + 0xf9c283fb, 0xd00a3709, 0x7e62a698, 0xf088c1a2, 0x5ee05033, + 0x7728e4c1, 0xd9407550, 0x24b98d25, 0x8ad11cb4, 0xa319a846, + 0x0d7139d7}, + {0x00000000, 0xb9fbdbe8, 0xa886b191, 0x117d6a79, 0x8a7c6563, + 0x3387be8b, 0x22fad4f2, 0x9b010f1a, 0xcf89cc87, 0x7672176f, + 0x670f7d16, 0xdef4a6fe, 0x45f5a9e4, 0xfc0e720c, 0xed731875, + 0x5488c39d, 0x44629f4f, 0xfd9944a7, 0xece42ede, 0x551ff536, + 0xce1efa2c, 0x77e521c4, 0x66984bbd, 0xdf639055, 0x8beb53c8, + 0x32108820, 0x236de259, 0x9a9639b1, 0x019736ab, 0xb86ced43, + 0xa911873a, 0x10ea5cd2, 0x88c53e9e, 0x313ee576, 0x20438f0f, + 0x99b854e7, 0x02b95bfd, 0xbb428015, 0xaa3fea6c, 0x13c43184, + 0x474cf219, 0xfeb729f1, 0xefca4388, 0x56319860, 0xcd30977a, + 0x74cb4c92, 0x65b626eb, 0xdc4dfd03, 0xcca7a1d1, 0x755c7a39, + 0x64211040, 0xdddacba8, 0x46dbc4b2, 0xff201f5a, 0xee5d7523, + 0x57a6aecb, 0x032e6d56, 0xbad5b6be, 0xaba8dcc7, 0x1253072f, + 0x89520835, 0x30a9d3dd, 0x21d4b9a4, 0x982f624c, 0xcafb7b7d, + 0x7300a095, 0x627dcaec, 0xdb861104, 0x40871e1e, 0xf97cc5f6, + 0xe801af8f, 0x51fa7467, 0x0572b7fa, 0xbc896c12, 0xadf4066b, + 0x140fdd83, 0x8f0ed299, 0x36f50971, 0x27886308, 0x9e73b8e0, + 0x8e99e432, 0x37623fda, 0x261f55a3, 0x9fe48e4b, 0x04e58151, + 0xbd1e5ab9, 0xac6330c0, 0x1598eb28, 0x411028b5, 0xf8ebf35d, + 0xe9969924, 0x506d42cc, 0xcb6c4dd6, 0x7297963e, 0x63eafc47, + 0xda1127af, 0x423e45e3, 0xfbc59e0b, 0xeab8f472, 0x53432f9a, + 0xc8422080, 0x71b9fb68, 0x60c49111, 0xd93f4af9, 0x8db78964, + 0x344c528c, 0x253138f5, 0x9ccae31d, 0x07cbec07, 0xbe3037ef, + 0xaf4d5d96, 0x16b6867e, 0x065cdaac, 0xbfa70144, 0xaeda6b3d, + 0x1721b0d5, 0x8c20bfcf, 0x35db6427, 0x24a60e5e, 0x9d5dd5b6, + 0xc9d5162b, 0x702ecdc3, 0x6153a7ba, 0xd8a87c52, 0x43a97348, + 0xfa52a8a0, 0xeb2fc2d9, 0x52d41931, 0x4e87f0bb, 0xf77c2b53, + 0xe601412a, 0x5ffa9ac2, 0xc4fb95d8, 0x7d004e30, 0x6c7d2449, + 0xd586ffa1, 0x810e3c3c, 0x38f5e7d4, 0x29888dad, 0x90735645, + 0x0b72595f, 0xb28982b7, 0xa3f4e8ce, 0x1a0f3326, 0x0ae56ff4, + 0xb31eb41c, 0xa263de65, 0x1b98058d, 0x80990a97, 0x3962d17f, + 0x281fbb06, 0x91e460ee, 0xc56ca373, 0x7c97789b, 0x6dea12e2, + 0xd411c90a, 0x4f10c610, 0xf6eb1df8, 0xe7967781, 0x5e6dac69, + 0xc642ce25, 0x7fb915cd, 0x6ec47fb4, 0xd73fa45c, 0x4c3eab46, + 0xf5c570ae, 0xe4b81ad7, 0x5d43c13f, 0x09cb02a2, 0xb030d94a, + 0xa14db333, 0x18b668db, 0x83b767c1, 0x3a4cbc29, 0x2b31d650, + 0x92ca0db8, 0x8220516a, 0x3bdb8a82, 0x2aa6e0fb, 0x935d3b13, + 0x085c3409, 0xb1a7efe1, 0xa0da8598, 0x19215e70, 0x4da99ded, + 0xf4524605, 0xe52f2c7c, 0x5cd4f794, 0xc7d5f88e, 0x7e2e2366, + 0x6f53491f, 0xd6a892f7, 0x847c8bc6, 0x3d87502e, 0x2cfa3a57, + 0x9501e1bf, 0x0e00eea5, 0xb7fb354d, 0xa6865f34, 0x1f7d84dc, + 0x4bf54741, 0xf20e9ca9, 0xe373f6d0, 0x5a882d38, 0xc1892222, + 0x7872f9ca, 0x690f93b3, 0xd0f4485b, 0xc01e1489, 0x79e5cf61, + 0x6898a518, 0xd1637ef0, 0x4a6271ea, 0xf399aa02, 0xe2e4c07b, + 0x5b1f1b93, 0x0f97d80e, 0xb66c03e6, 0xa711699f, 0x1eeab277, + 0x85ebbd6d, 0x3c106685, 0x2d6d0cfc, 0x9496d714, 0x0cb9b558, + 0xb5426eb0, 0xa43f04c9, 0x1dc4df21, 0x86c5d03b, 0x3f3e0bd3, + 0x2e4361aa, 0x97b8ba42, 0xc33079df, 0x7acba237, 0x6bb6c84e, + 0xd24d13a6, 0x494c1cbc, 0xf0b7c754, 0xe1caad2d, 0x583176c5, + 0x48db2a17, 0xf120f1ff, 0xe05d9b86, 0x59a6406e, 0xc2a74f74, + 0x7b5c949c, 0x6a21fee5, 0xd3da250d, 0x8752e690, 0x3ea93d78, + 0x2fd45701, 0x962f8ce9, 0x0d2e83f3, 0xb4d5581b, 0xa5a83262, + 0x1c53e98a}, + {0x00000000, 0x9d0fe176, 0xe16ec4ad, 0x7c6125db, 0x19ac8f1b, + 0x84a36e6d, 0xf8c24bb6, 0x65cdaac0, 0x33591e36, 0xae56ff40, + 0xd237da9b, 0x4f383bed, 0x2af5912d, 0xb7fa705b, 0xcb9b5580, + 0x5694b4f6, 0x66b23c6c, 0xfbbddd1a, 0x87dcf8c1, 0x1ad319b7, + 0x7f1eb377, 0xe2115201, 0x9e7077da, 0x037f96ac, 0x55eb225a, + 0xc8e4c32c, 0xb485e6f7, 0x298a0781, 0x4c47ad41, 0xd1484c37, + 0xad2969ec, 0x3026889a, 0xcd6478d8, 0x506b99ae, 0x2c0abc75, + 0xb1055d03, 0xd4c8f7c3, 0x49c716b5, 0x35a6336e, 0xa8a9d218, + 0xfe3d66ee, 0x63328798, 0x1f53a243, 0x825c4335, 0xe791e9f5, + 0x7a9e0883, 0x06ff2d58, 0x9bf0cc2e, 0xabd644b4, 0x36d9a5c2, + 0x4ab88019, 0xd7b7616f, 0xb27acbaf, 0x2f752ad9, 0x53140f02, + 0xce1bee74, 0x988f5a82, 0x0580bbf4, 0x79e19e2f, 0xe4ee7f59, + 0x8123d599, 0x1c2c34ef, 0x604d1134, 0xfd42f042, 0x41b9f7f1, + 0xdcb61687, 0xa0d7335c, 0x3dd8d22a, 0x581578ea, 0xc51a999c, + 0xb97bbc47, 0x24745d31, 0x72e0e9c7, 0xefef08b1, 0x938e2d6a, + 0x0e81cc1c, 0x6b4c66dc, 0xf64387aa, 0x8a22a271, 0x172d4307, + 0x270bcb9d, 0xba042aeb, 0xc6650f30, 0x5b6aee46, 0x3ea74486, + 0xa3a8a5f0, 0xdfc9802b, 0x42c6615d, 0x1452d5ab, 0x895d34dd, + 0xf53c1106, 0x6833f070, 0x0dfe5ab0, 0x90f1bbc6, 0xec909e1d, + 0x719f7f6b, 0x8cdd8f29, 0x11d26e5f, 0x6db34b84, 0xf0bcaaf2, + 0x95710032, 0x087ee144, 0x741fc49f, 0xe91025e9, 0xbf84911f, + 0x228b7069, 0x5eea55b2, 0xc3e5b4c4, 0xa6281e04, 0x3b27ff72, + 0x4746daa9, 0xda493bdf, 0xea6fb345, 0x77605233, 0x0b0177e8, + 0x960e969e, 0xf3c33c5e, 0x6eccdd28, 0x12adf8f3, 0x8fa21985, + 0xd936ad73, 0x44394c05, 0x385869de, 0xa55788a8, 0xc09a2268, + 0x5d95c31e, 0x21f4e6c5, 0xbcfb07b3, 0x8373efe2, 0x1e7c0e94, + 0x621d2b4f, 0xff12ca39, 0x9adf60f9, 0x07d0818f, 0x7bb1a454, + 0xe6be4522, 0xb02af1d4, 0x2d2510a2, 0x51443579, 0xcc4bd40f, + 0xa9867ecf, 0x34899fb9, 0x48e8ba62, 0xd5e75b14, 0xe5c1d38e, + 0x78ce32f8, 0x04af1723, 0x99a0f655, 0xfc6d5c95, 0x6162bde3, + 0x1d039838, 0x800c794e, 0xd698cdb8, 0x4b972cce, 0x37f60915, + 0xaaf9e863, 0xcf3442a3, 0x523ba3d5, 0x2e5a860e, 0xb3556778, + 0x4e17973a, 0xd318764c, 0xaf795397, 0x3276b2e1, 0x57bb1821, + 0xcab4f957, 0xb6d5dc8c, 0x2bda3dfa, 0x7d4e890c, 0xe041687a, + 0x9c204da1, 0x012facd7, 0x64e20617, 0xf9ede761, 0x858cc2ba, + 0x188323cc, 0x28a5ab56, 0xb5aa4a20, 0xc9cb6ffb, 0x54c48e8d, + 0x3109244d, 0xac06c53b, 0xd067e0e0, 0x4d680196, 0x1bfcb560, + 0x86f35416, 0xfa9271cd, 0x679d90bb, 0x02503a7b, 0x9f5fdb0d, + 0xe33efed6, 0x7e311fa0, 0xc2ca1813, 0x5fc5f965, 0x23a4dcbe, + 0xbeab3dc8, 0xdb669708, 0x4669767e, 0x3a0853a5, 0xa707b2d3, + 0xf1930625, 0x6c9ce753, 0x10fdc288, 0x8df223fe, 0xe83f893e, + 0x75306848, 0x09514d93, 0x945eace5, 0xa478247f, 0x3977c509, + 0x4516e0d2, 0xd81901a4, 0xbdd4ab64, 0x20db4a12, 0x5cba6fc9, + 0xc1b58ebf, 0x97213a49, 0x0a2edb3f, 0x764ffee4, 0xeb401f92, + 0x8e8db552, 0x13825424, 0x6fe371ff, 0xf2ec9089, 0x0fae60cb, + 0x92a181bd, 0xeec0a466, 0x73cf4510, 0x1602efd0, 0x8b0d0ea6, + 0xf76c2b7d, 0x6a63ca0b, 0x3cf77efd, 0xa1f89f8b, 0xdd99ba50, + 0x40965b26, 0x255bf1e6, 0xb8541090, 0xc435354b, 0x593ad43d, + 0x691c5ca7, 0xf413bdd1, 0x8872980a, 0x157d797c, 0x70b0d3bc, + 0xedbf32ca, 0x91de1711, 0x0cd1f667, 0x5a454291, 0xc74aa3e7, + 0xbb2b863c, 0x2624674a, 0x43e9cd8a, 0xdee62cfc, 0xa2870927, + 0x3f88e851}, + {0x00000000, 0xdd96d985, 0x605cb54b, 0xbdca6cce, 0xc0b96a96, + 0x1d2fb313, 0xa0e5dfdd, 0x7d730658, 0x5a03d36d, 0x87950ae8, + 0x3a5f6626, 0xe7c9bfa3, 0x9abab9fb, 0x472c607e, 0xfae60cb0, + 0x2770d535, 0xb407a6da, 0x69917f5f, 0xd45b1391, 0x09cdca14, + 0x74becc4c, 0xa92815c9, 0x14e27907, 0xc974a082, 0xee0475b7, + 0x3392ac32, 0x8e58c0fc, 0x53ce1979, 0x2ebd1f21, 0xf32bc6a4, + 0x4ee1aa6a, 0x937773ef, 0xb37e4bf5, 0x6ee89270, 0xd322febe, + 0x0eb4273b, 0x73c72163, 0xae51f8e6, 0x139b9428, 0xce0d4dad, + 0xe97d9898, 0x34eb411d, 0x89212dd3, 0x54b7f456, 0x29c4f20e, + 0xf4522b8b, 0x49984745, 0x940e9ec0, 0x0779ed2f, 0xdaef34aa, + 0x67255864, 0xbab381e1, 0xc7c087b9, 0x1a565e3c, 0xa79c32f2, + 0x7a0aeb77, 0x5d7a3e42, 0x80ece7c7, 0x3d268b09, 0xe0b0528c, + 0x9dc354d4, 0x40558d51, 0xfd9fe19f, 0x2009381a, 0xbd8d91ab, + 0x601b482e, 0xddd124e0, 0x0047fd65, 0x7d34fb3d, 0xa0a222b8, + 0x1d684e76, 0xc0fe97f3, 0xe78e42c6, 0x3a189b43, 0x87d2f78d, + 0x5a442e08, 0x27372850, 0xfaa1f1d5, 0x476b9d1b, 0x9afd449e, + 0x098a3771, 0xd41ceef4, 0x69d6823a, 0xb4405bbf, 0xc9335de7, + 0x14a58462, 0xa96fe8ac, 0x74f93129, 0x5389e41c, 0x8e1f3d99, + 0x33d55157, 0xee4388d2, 0x93308e8a, 0x4ea6570f, 0xf36c3bc1, + 0x2efae244, 0x0ef3da5e, 0xd36503db, 0x6eaf6f15, 0xb339b690, + 0xce4ab0c8, 0x13dc694d, 0xae160583, 0x7380dc06, 0x54f00933, + 0x8966d0b6, 0x34acbc78, 0xe93a65fd, 0x944963a5, 0x49dfba20, + 0xf415d6ee, 0x29830f6b, 0xbaf47c84, 0x6762a501, 0xdaa8c9cf, + 0x073e104a, 0x7a4d1612, 0xa7dbcf97, 0x1a11a359, 0xc7877adc, + 0xe0f7afe9, 0x3d61766c, 0x80ab1aa2, 0x5d3dc327, 0x204ec57f, + 0xfdd81cfa, 0x40127034, 0x9d84a9b1, 0xa06a2517, 0x7dfcfc92, + 0xc036905c, 0x1da049d9, 0x60d34f81, 0xbd459604, 0x008ffaca, + 0xdd19234f, 0xfa69f67a, 0x27ff2fff, 0x9a354331, 0x47a39ab4, + 0x3ad09cec, 0xe7464569, 0x5a8c29a7, 0x871af022, 0x146d83cd, + 0xc9fb5a48, 0x74313686, 0xa9a7ef03, 0xd4d4e95b, 0x094230de, + 0xb4885c10, 0x691e8595, 0x4e6e50a0, 0x93f88925, 0x2e32e5eb, + 0xf3a43c6e, 0x8ed73a36, 0x5341e3b3, 0xee8b8f7d, 0x331d56f8, + 0x13146ee2, 0xce82b767, 0x7348dba9, 0xaede022c, 0xd3ad0474, + 0x0e3bddf1, 0xb3f1b13f, 0x6e6768ba, 0x4917bd8f, 0x9481640a, + 0x294b08c4, 0xf4ddd141, 0x89aed719, 0x54380e9c, 0xe9f26252, + 0x3464bbd7, 0xa713c838, 0x7a8511bd, 0xc74f7d73, 0x1ad9a4f6, + 0x67aaa2ae, 0xba3c7b2b, 0x07f617e5, 0xda60ce60, 0xfd101b55, + 0x2086c2d0, 0x9d4cae1e, 0x40da779b, 0x3da971c3, 0xe03fa846, + 0x5df5c488, 0x80631d0d, 0x1de7b4bc, 0xc0716d39, 0x7dbb01f7, + 0xa02dd872, 0xdd5ede2a, 0x00c807af, 0xbd026b61, 0x6094b2e4, + 0x47e467d1, 0x9a72be54, 0x27b8d29a, 0xfa2e0b1f, 0x875d0d47, + 0x5acbd4c2, 0xe701b80c, 0x3a976189, 0xa9e01266, 0x7476cbe3, + 0xc9bca72d, 0x142a7ea8, 0x695978f0, 0xb4cfa175, 0x0905cdbb, + 0xd493143e, 0xf3e3c10b, 0x2e75188e, 0x93bf7440, 0x4e29adc5, + 0x335aab9d, 0xeecc7218, 0x53061ed6, 0x8e90c753, 0xae99ff49, + 0x730f26cc, 0xcec54a02, 0x13539387, 0x6e2095df, 0xb3b64c5a, + 0x0e7c2094, 0xd3eaf911, 0xf49a2c24, 0x290cf5a1, 0x94c6996f, + 0x495040ea, 0x342346b2, 0xe9b59f37, 0x547ff3f9, 0x89e92a7c, + 0x1a9e5993, 0xc7088016, 0x7ac2ecd8, 0xa754355d, 0xda273305, + 0x07b1ea80, 0xba7b864e, 0x67ed5fcb, 0x409d8afe, 0x9d0b537b, + 0x20c13fb5, 0xfd57e630, 0x8024e068, 0x5db239ed, 0xe0785523, + 0x3dee8ca6}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x00000000, 0x85d996dd, 0x4bb55c60, 0xce6ccabd, 0x966ab9c0, + 0x13b32f1d, 0xdddfe5a0, 0x5806737d, 0x6dd3035a, 0xe80a9587, + 0x26665f3a, 0xa3bfc9e7, 0xfbb9ba9a, 0x7e602c47, 0xb00ce6fa, + 0x35d57027, 0xdaa607b4, 0x5f7f9169, 0x91135bd4, 0x14cacd09, + 0x4cccbe74, 0xc91528a9, 0x0779e214, 0x82a074c9, 0xb77504ee, + 0x32ac9233, 0xfcc0588e, 0x7919ce53, 0x211fbd2e, 0xa4c62bf3, + 0x6aaae14e, 0xef737793, 0xf54b7eb3, 0x7092e86e, 0xbefe22d3, + 0x3b27b40e, 0x6321c773, 0xe6f851ae, 0x28949b13, 0xad4d0dce, + 0x98987de9, 0x1d41eb34, 0xd32d2189, 0x56f4b754, 0x0ef2c429, + 0x8b2b52f4, 0x45479849, 0xc09e0e94, 0x2fed7907, 0xaa34efda, + 0x64582567, 0xe181b3ba, 0xb987c0c7, 0x3c5e561a, 0xf2329ca7, + 0x77eb0a7a, 0x423e7a5d, 0xc7e7ec80, 0x098b263d, 0x8c52b0e0, + 0xd454c39d, 0x518d5540, 0x9fe19ffd, 0x1a380920, 0xab918dbd, + 0x2e481b60, 0xe024d1dd, 0x65fd4700, 0x3dfb347d, 0xb822a2a0, + 0x764e681d, 0xf397fec0, 0xc6428ee7, 0x439b183a, 0x8df7d287, + 0x082e445a, 0x50283727, 0xd5f1a1fa, 0x1b9d6b47, 0x9e44fd9a, + 0x71378a09, 0xf4ee1cd4, 0x3a82d669, 0xbf5b40b4, 0xe75d33c9, + 0x6284a514, 0xace86fa9, 0x2931f974, 0x1ce48953, 0x993d1f8e, + 0x5751d533, 0xd28843ee, 0x8a8e3093, 0x0f57a64e, 0xc13b6cf3, + 0x44e2fa2e, 0x5edaf30e, 0xdb0365d3, 0x156faf6e, 0x90b639b3, + 0xc8b04ace, 0x4d69dc13, 0x830516ae, 0x06dc8073, 0x3309f054, + 0xb6d06689, 0x78bcac34, 0xfd653ae9, 0xa5634994, 0x20badf49, + 0xeed615f4, 0x6b0f8329, 0x847cf4ba, 0x01a56267, 0xcfc9a8da, + 0x4a103e07, 0x12164d7a, 0x97cfdba7, 0x59a3111a, 0xdc7a87c7, + 0xe9aff7e0, 0x6c76613d, 0xa21aab80, 0x27c33d5d, 0x7fc54e20, + 0xfa1cd8fd, 0x34701240, 0xb1a9849d, 0x17256aa0, 0x92fcfc7d, + 0x5c9036c0, 0xd949a01d, 0x814fd360, 0x049645bd, 0xcafa8f00, + 0x4f2319dd, 0x7af669fa, 0xff2fff27, 0x3143359a, 0xb49aa347, + 0xec9cd03a, 0x694546e7, 0xa7298c5a, 0x22f01a87, 0xcd836d14, + 0x485afbc9, 0x86363174, 0x03efa7a9, 0x5be9d4d4, 0xde304209, + 0x105c88b4, 0x95851e69, 0xa0506e4e, 0x2589f893, 0xebe5322e, + 0x6e3ca4f3, 0x363ad78e, 0xb3e34153, 0x7d8f8bee, 0xf8561d33, + 0xe26e1413, 0x67b782ce, 0xa9db4873, 0x2c02deae, 0x7404add3, + 0xf1dd3b0e, 0x3fb1f1b3, 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0x0883c6ea, + 0x32e42c64, 0xa37544ca, 0x51c18ce3, 0xc050e44d, 0xb5a81db0, + 0x2439751e, 0xd68dbd37, 0x471cd599, 0xe34518f1, 0x72d4705f, + 0x8060b876, 0x11f1d0d8, 0x64092925, 0xf598418b, 0x072c89a2, + 0x96bde10c, 0xacda0b82, 0x3d4b632c, 0xcfffab05, 0x5e6ec3ab, + 0x2b963a56, 0xba0752f8, 0x48b39ad1, 0xd922f27f, 0xfaf67e2e, + 0x6b671680, 0x99d3dea9, 0x0842b607, 0x7dba4ffa, 0xec2b2754, + 0x1e9fef7d, 0x8f0e87d3, 0xb5696d5d, 0x24f805f3, 0xd64ccdda, + 0x47dda574, 0x32255c89, 0xa3b43427, 0x5100fc0e, 0xc09194a0, + 0x64c859c8, 0xf5593166, 0x07edf94f, 0x967c91e1, 0xe384681c, + 0x721500b2, 0x80a1c89b, 0x1130a035, 0x2b574abb, 0xbac62215, + 0x4872ea3c, 0xd9e38292, 0xac1b7b6f, 0x3d8a13c1, 0xcf3edbe8, + 0x5eafb346, 0x878d4139, 0x161c2997, 0xe4a8e1be, 0x75398910, + 0x00c170ed, 0x91501843, 0x63e4d06a, 0xf275b8c4, 0xc812524a, + 0x59833ae4, 0xab37f2cd, 0x3aa69a63, 0x4f5e639e, 0xdecf0b30, + 0x2c7bc319, 0xbdeaabb7, 0x19b366df, 0x88220e71, 0x7a96c658, + 0xeb07aef6, 0x9eff570b, 0x0f6e3fa5, 0xfddaf78c, 0x6c4b9f22, + 0x562c75ac, 0xc7bd1d02, 0x3509d52b, 0xa498bd85, 0xd1604478, + 0x40f12cd6, 0xb245e4ff, 0x23d48c51, 0xf4edfd5c, 0x657c95f2, + 0x97c85ddb, 0x06593575, 0x73a1cc88, 0xe230a426, 0x10846c0f, + 0x811504a1, 0xbb72ee2f, 0x2ae38681, 0xd8574ea8, 0x49c62606, + 0x3c3edffb, 0xadafb755, 0x5f1b7f7c, 0xce8a17d2, 0x6ad3daba, + 0xfb42b214, 0x09f67a3d, 0x98671293, 0xed9feb6e, 0x7c0e83c0, + 0x8eba4be9, 0x1f2b2347, 0x254cc9c9, 0xb4dda167, 0x4669694e, + 0xd7f801e0, 0xa200f81d, 0x339190b3, 0xc125589a, 0x50b43034, + 0x8996c24b, 0x1807aae5, 0xeab362cc, 0x7b220a62, 0x0edaf39f, + 0x9f4b9b31, 0x6dff5318, 0xfc6e3bb6, 0xc609d138, 0x5798b996, + 0xa52c71bf, 0x34bd1911, 0x4145e0ec, 0xd0d48842, 0x2260406b, + 0xb3f128c5, 0x17a8e5ad, 0x86398d03, 0x748d452a, 0xe51c2d84, + 0x90e4d479, 0x0175bcd7, 0xf3c174fe, 0x62501c50, 0x5837f6de, + 0xc9a69e70, 0x3b125659, 0xaa833ef7, 0xdf7bc70a, 0x4eeaafa4, + 0xbc5e678d, 0x2dcf0f23, 0x0e1b8372, 0x9f8aebdc, 0x6d3e23f5, + 0xfcaf4b5b, 0x8957b2a6, 0x18c6da08, 0xea721221, 0x7be37a8f, + 0x41849001, 0xd015f8af, 0x22a13086, 0xb3305828, 0xc6c8a1d5, + 0x5759c97b, 0xa5ed0152, 0x347c69fc, 0x9025a494, 0x01b4cc3a, + 0xf3000413, 0x62916cbd, 0x17699540, 0x86f8fdee, 0x744c35c7, + 0xe5dd5d69, 0xdfbab7e7, 0x4e2bdf49, 0xbc9f1760, 0x2d0e7fce, + 0x58f68633, 0xc967ee9d, 0x3bd326b4, 0xaa424e1a, 0x7360bc65, + 0xe2f1d4cb, 0x10451ce2, 0x81d4744c, 0xf42c8db1, 0x65bde51f, + 0x97092d36, 0x06984598, 0x3cffaf16, 0xad6ec7b8, 0x5fda0f91, + 0xce4b673f, 0xbbb39ec2, 0x2a22f66c, 0xd8963e45, 0x490756eb, + 0xed5e9b83, 0x7ccff32d, 0x8e7b3b04, 0x1fea53aa, 0x6a12aa57, + 0xfb83c2f9, 0x09370ad0, 0x98a6627e, 0xa2c188f0, 0x3350e05e, + 0xc1e42877, 0x507540d9, 0x258db924, 0xb41cd18a, 0x46a819a3, + 0xd739710d}}; + +#endif + +#endif + +#if N == 5 + +#if W == 8 + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0xaf449247, 0x85f822cf, 0x2abcb088, 0xd08143df, + 0x7fc5d198, 0x55796110, 0xfa3df357, 0x7a7381ff, 0xd53713b8, + 0xff8ba330, 0x50cf3177, 0xaaf2c220, 0x05b65067, 0x2f0ae0ef, + 0x804e72a8, 0xf4e703fe, 0x5ba391b9, 0x711f2131, 0xde5bb376, + 0x24664021, 0x8b22d266, 0xa19e62ee, 0x0edaf0a9, 0x8e948201, + 0x21d01046, 0x0b6ca0ce, 0xa4283289, 0x5e15c1de, 0xf1515399, + 0xdbede311, 0x74a97156, 0x32bf01bd, 0x9dfb93fa, 0xb7472372, + 0x1803b135, 0xe23e4262, 0x4d7ad025, 0x67c660ad, 0xc882f2ea, + 0x48cc8042, 0xe7881205, 0xcd34a28d, 0x627030ca, 0x984dc39d, + 0x370951da, 0x1db5e152, 0xb2f17315, 0xc6580243, 0x691c9004, + 0x43a0208c, 0xece4b2cb, 0x16d9419c, 0xb99dd3db, 0x93216353, + 0x3c65f114, 0xbc2b83bc, 0x136f11fb, 0x39d3a173, 0x96973334, + 0x6caac063, 0xc3ee5224, 0xe952e2ac, 0x461670eb, 0x657e037a, + 0xca3a913d, 0xe08621b5, 0x4fc2b3f2, 0xb5ff40a5, 0x1abbd2e2, + 0x3007626a, 0x9f43f02d, 0x1f0d8285, 0xb04910c2, 0x9af5a04a, + 0x35b1320d, 0xcf8cc15a, 0x60c8531d, 0x4a74e395, 0xe53071d2, + 0x91990084, 0x3edd92c3, 0x1461224b, 0xbb25b00c, 0x4118435b, + 0xee5cd11c, 0xc4e06194, 0x6ba4f3d3, 0xebea817b, 0x44ae133c, + 0x6e12a3b4, 0xc15631f3, 0x3b6bc2a4, 0x942f50e3, 0xbe93e06b, + 0x11d7722c, 0x57c102c7, 0xf8859080, 0xd2392008, 0x7d7db24f, + 0x87404118, 0x2804d35f, 0x02b863d7, 0xadfcf190, 0x2db28338, + 0x82f6117f, 0xa84aa1f7, 0x070e33b0, 0xfd33c0e7, 0x527752a0, + 0x78cbe228, 0xd78f706f, 0xa3260139, 0x0c62937e, 0x26de23f6, + 0x899ab1b1, 0x73a742e6, 0xdce3d0a1, 0xf65f6029, 0x591bf26e, + 0xd95580c6, 0x76111281, 0x5cada209, 0xf3e9304e, 0x09d4c319, + 0xa690515e, 0x8c2ce1d6, 0x23687391, 0xcafc06f4, 0x65b894b3, + 0x4f04243b, 0xe040b67c, 0x1a7d452b, 0xb539d76c, 0x9f8567e4, + 0x30c1f5a3, 0xb08f870b, 0x1fcb154c, 0x3577a5c4, 0x9a333783, + 0x600ec4d4, 0xcf4a5693, 0xe5f6e61b, 0x4ab2745c, 0x3e1b050a, + 0x915f974d, 0xbbe327c5, 0x14a7b582, 0xee9a46d5, 0x41ded492, + 0x6b62641a, 0xc426f65d, 0x446884f5, 0xeb2c16b2, 0xc190a63a, + 0x6ed4347d, 0x94e9c72a, 0x3bad556d, 0x1111e5e5, 0xbe5577a2, + 0xf8430749, 0x5707950e, 0x7dbb2586, 0xd2ffb7c1, 0x28c24496, + 0x8786d6d1, 0xad3a6659, 0x027ef41e, 0x823086b6, 0x2d7414f1, + 0x07c8a479, 0xa88c363e, 0x52b1c569, 0xfdf5572e, 0xd749e7a6, + 0x780d75e1, 0x0ca404b7, 0xa3e096f0, 0x895c2678, 0x2618b43f, + 0xdc254768, 0x7361d52f, 0x59dd65a7, 0xf699f7e0, 0x76d78548, + 0xd993170f, 0xf32fa787, 0x5c6b35c0, 0xa656c697, 0x091254d0, + 0x23aee458, 0x8cea761f, 0xaf82058e, 0x00c697c9, 0x2a7a2741, + 0x853eb506, 0x7f034651, 0xd047d416, 0xfafb649e, 0x55bff6d9, + 0xd5f18471, 0x7ab51636, 0x5009a6be, 0xff4d34f9, 0x0570c7ae, + 0xaa3455e9, 0x8088e561, 0x2fcc7726, 0x5b650670, 0xf4219437, + 0xde9d24bf, 0x71d9b6f8, 0x8be445af, 0x24a0d7e8, 0x0e1c6760, + 0xa158f527, 0x2116878f, 0x8e5215c8, 0xa4eea540, 0x0baa3707, + 0xf197c450, 0x5ed35617, 0x746fe69f, 0xdb2b74d8, 0x9d3d0433, + 0x32799674, 0x18c526fc, 0xb781b4bb, 0x4dbc47ec, 0xe2f8d5ab, + 0xc8446523, 0x6700f764, 0xe74e85cc, 0x480a178b, 0x62b6a703, + 0xcdf23544, 0x37cfc613, 0x988b5454, 0xb237e4dc, 0x1d73769b, + 0x69da07cd, 0xc69e958a, 0xec222502, 0x4366b745, 0xb95b4412, + 0x161fd655, 0x3ca366dd, 0x93e7f49a, 0x13a98632, 0xbced1475, + 0x9651a4fd, 0x391536ba, 0xc328c5ed, 0x6c6c57aa, 0x46d0e722, + 0xe9947565}, + {0x00000000, 0x4e890ba9, 0x9d121752, 0xd39b1cfb, 0xe15528e5, + 0xafdc234c, 0x7c473fb7, 0x32ce341e, 0x19db578b, 0x57525c22, + 0x84c940d9, 0xca404b70, 0xf88e7f6e, 0xb60774c7, 0x659c683c, + 0x2b156395, 0x33b6af16, 0x7d3fa4bf, 0xaea4b844, 0xe02db3ed, + 0xd2e387f3, 0x9c6a8c5a, 0x4ff190a1, 0x01789b08, 0x2a6df89d, + 0x64e4f334, 0xb77fefcf, 0xf9f6e466, 0xcb38d078, 0x85b1dbd1, + 0x562ac72a, 0x18a3cc83, 0x676d5e2c, 0x29e45585, 0xfa7f497e, + 0xb4f642d7, 0x863876c9, 0xc8b17d60, 0x1b2a619b, 0x55a36a32, + 0x7eb609a7, 0x303f020e, 0xe3a41ef5, 0xad2d155c, 0x9fe32142, + 0xd16a2aeb, 0x02f13610, 0x4c783db9, 0x54dbf13a, 0x1a52fa93, + 0xc9c9e668, 0x8740edc1, 0xb58ed9df, 0xfb07d276, 0x289cce8d, + 0x6615c524, 0x4d00a6b1, 0x0389ad18, 0xd012b1e3, 0x9e9bba4a, + 0xac558e54, 0xe2dc85fd, 0x31479906, 0x7fce92af, 0xcedabc58, + 0x8053b7f1, 0x53c8ab0a, 0x1d41a0a3, 0x2f8f94bd, 0x61069f14, + 0xb29d83ef, 0xfc148846, 0xd701ebd3, 0x9988e07a, 0x4a13fc81, + 0x049af728, 0x3654c336, 0x78ddc89f, 0xab46d464, 0xe5cfdfcd, + 0xfd6c134e, 0xb3e518e7, 0x607e041c, 0x2ef70fb5, 0x1c393bab, + 0x52b03002, 0x812b2cf9, 0xcfa22750, 0xe4b744c5, 0xaa3e4f6c, + 0x79a55397, 0x372c583e, 0x05e26c20, 0x4b6b6789, 0x98f07b72, + 0xd67970db, 0xa9b7e274, 0xe73ee9dd, 0x34a5f526, 0x7a2cfe8f, + 0x48e2ca91, 0x066bc138, 0xd5f0ddc3, 0x9b79d66a, 0xb06cb5ff, + 0xfee5be56, 0x2d7ea2ad, 0x63f7a904, 0x51399d1a, 0x1fb096b3, + 0xcc2b8a48, 0x82a281e1, 0x9a014d62, 0xd48846cb, 0x07135a30, + 0x499a5199, 0x7b546587, 0x35dd6e2e, 0xe64672d5, 0xa8cf797c, + 0x83da1ae9, 0xcd531140, 0x1ec80dbb, 0x50410612, 0x628f320c, + 0x2c0639a5, 0xff9d255e, 0xb1142ef7, 0x46c47ef1, 0x084d7558, + 0xdbd669a3, 0x955f620a, 0xa7915614, 0xe9185dbd, 0x3a834146, + 0x740a4aef, 0x5f1f297a, 0x119622d3, 0xc20d3e28, 0x8c843581, + 0xbe4a019f, 0xf0c30a36, 0x235816cd, 0x6dd11d64, 0x7572d1e7, + 0x3bfbda4e, 0xe860c6b5, 0xa6e9cd1c, 0x9427f902, 0xdaaef2ab, + 0x0935ee50, 0x47bce5f9, 0x6ca9866c, 0x22208dc5, 0xf1bb913e, + 0xbf329a97, 0x8dfcae89, 0xc375a520, 0x10eeb9db, 0x5e67b272, + 0x21a920dd, 0x6f202b74, 0xbcbb378f, 0xf2323c26, 0xc0fc0838, + 0x8e750391, 0x5dee1f6a, 0x136714c3, 0x38727756, 0x76fb7cff, + 0xa5606004, 0xebe96bad, 0xd9275fb3, 0x97ae541a, 0x443548e1, + 0x0abc4348, 0x121f8fcb, 0x5c968462, 0x8f0d9899, 0xc1849330, + 0xf34aa72e, 0xbdc3ac87, 0x6e58b07c, 0x20d1bbd5, 0x0bc4d840, + 0x454dd3e9, 0x96d6cf12, 0xd85fc4bb, 0xea91f0a5, 0xa418fb0c, + 0x7783e7f7, 0x390aec5e, 0x881ec2a9, 0xc697c900, 0x150cd5fb, + 0x5b85de52, 0x694bea4c, 0x27c2e1e5, 0xf459fd1e, 0xbad0f6b7, + 0x91c59522, 0xdf4c9e8b, 0x0cd78270, 0x425e89d9, 0x7090bdc7, + 0x3e19b66e, 0xed82aa95, 0xa30ba13c, 0xbba86dbf, 0xf5216616, + 0x26ba7aed, 0x68337144, 0x5afd455a, 0x14744ef3, 0xc7ef5208, + 0x896659a1, 0xa2733a34, 0xecfa319d, 0x3f612d66, 0x71e826cf, + 0x432612d1, 0x0daf1978, 0xde340583, 0x90bd0e2a, 0xef739c85, + 0xa1fa972c, 0x72618bd7, 0x3ce8807e, 0x0e26b460, 0x40afbfc9, + 0x9334a332, 0xddbda89b, 0xf6a8cb0e, 0xb821c0a7, 0x6bbadc5c, + 0x2533d7f5, 0x17fde3eb, 0x5974e842, 0x8aeff4b9, 0xc466ff10, + 0xdcc53393, 0x924c383a, 0x41d724c1, 0x0f5e2f68, 0x3d901b76, + 0x731910df, 0xa0820c24, 0xee0b078d, 0xc51e6418, 0x8b976fb1, + 0x580c734a, 0x168578e3, 0x244b4cfd, 0x6ac24754, 0xb9595baf, + 0xf7d05006}, + {0x00000000, 0x8d88fde2, 0xc060fd85, 0x4de80067, 0x5bb0fd4b, + 0xd63800a9, 0x9bd000ce, 0x1658fd2c, 0xb761fa96, 0x3ae90774, + 0x77010713, 0xfa89faf1, 0xecd107dd, 0x6159fa3f, 0x2cb1fa58, + 0xa13907ba, 0xb5b2f36d, 0x383a0e8f, 0x75d20ee8, 0xf85af30a, + 0xee020e26, 0x638af3c4, 0x2e62f3a3, 0xa3ea0e41, 0x02d309fb, + 0x8f5bf419, 0xc2b3f47e, 0x4f3b099c, 0x5963f4b0, 0xd4eb0952, + 0x99030935, 0x148bf4d7, 0xb014e09b, 0x3d9c1d79, 0x70741d1e, + 0xfdfce0fc, 0xeba41dd0, 0x662ce032, 0x2bc4e055, 0xa64c1db7, + 0x07751a0d, 0x8afde7ef, 0xc715e788, 0x4a9d1a6a, 0x5cc5e746, + 0xd14d1aa4, 0x9ca51ac3, 0x112de721, 0x05a613f6, 0x882eee14, + 0xc5c6ee73, 0x484e1391, 0x5e16eebd, 0xd39e135f, 0x9e761338, + 0x13feeeda, 0xb2c7e960, 0x3f4f1482, 0x72a714e5, 0xff2fe907, + 0xe977142b, 0x64ffe9c9, 0x2917e9ae, 0xa49f144c, 0xbb58c777, + 0x36d03a95, 0x7b383af2, 0xf6b0c710, 0xe0e83a3c, 0x6d60c7de, + 0x2088c7b9, 0xad003a5b, 0x0c393de1, 0x81b1c003, 0xcc59c064, + 0x41d13d86, 0x5789c0aa, 0xda013d48, 0x97e93d2f, 0x1a61c0cd, + 0x0eea341a, 0x8362c9f8, 0xce8ac99f, 0x4302347d, 0x555ac951, + 0xd8d234b3, 0x953a34d4, 0x18b2c936, 0xb98bce8c, 0x3403336e, + 0x79eb3309, 0xf463ceeb, 0xe23b33c7, 0x6fb3ce25, 0x225bce42, + 0xafd333a0, 0x0b4c27ec, 0x86c4da0e, 0xcb2cda69, 0x46a4278b, + 0x50fcdaa7, 0xdd742745, 0x909c2722, 0x1d14dac0, 0xbc2ddd7a, + 0x31a52098, 0x7c4d20ff, 0xf1c5dd1d, 0xe79d2031, 0x6a15ddd3, + 0x27fdddb4, 0xaa752056, 0xbefed481, 0x33762963, 0x7e9e2904, + 0xf316d4e6, 0xe54e29ca, 0x68c6d428, 0x252ed44f, 0xa8a629ad, + 0x099f2e17, 0x8417d3f5, 0xc9ffd392, 0x44772e70, 0x522fd35c, + 0xdfa72ebe, 0x924f2ed9, 0x1fc7d33b, 0xadc088af, 0x2048754d, + 0x6da0752a, 0xe02888c8, 0xf67075e4, 0x7bf88806, 0x36108861, + 0xbb987583, 0x1aa17239, 0x97298fdb, 0xdac18fbc, 0x5749725e, + 0x41118f72, 0xcc997290, 0x817172f7, 0x0cf98f15, 0x18727bc2, + 0x95fa8620, 0xd8128647, 0x559a7ba5, 0x43c28689, 0xce4a7b6b, + 0x83a27b0c, 0x0e2a86ee, 0xaf138154, 0x229b7cb6, 0x6f737cd1, + 0xe2fb8133, 0xf4a37c1f, 0x792b81fd, 0x34c3819a, 0xb94b7c78, + 0x1dd46834, 0x905c95d6, 0xddb495b1, 0x503c6853, 0x4664957f, + 0xcbec689d, 0x860468fa, 0x0b8c9518, 0xaab592a2, 0x273d6f40, + 0x6ad56f27, 0xe75d92c5, 0xf1056fe9, 0x7c8d920b, 0x3165926c, + 0xbced6f8e, 0xa8669b59, 0x25ee66bb, 0x680666dc, 0xe58e9b3e, + 0xf3d66612, 0x7e5e9bf0, 0x33b69b97, 0xbe3e6675, 0x1f0761cf, + 0x928f9c2d, 0xdf679c4a, 0x52ef61a8, 0x44b79c84, 0xc93f6166, + 0x84d76101, 0x095f9ce3, 0x16984fd8, 0x9b10b23a, 0xd6f8b25d, + 0x5b704fbf, 0x4d28b293, 0xc0a04f71, 0x8d484f16, 0x00c0b2f4, + 0xa1f9b54e, 0x2c7148ac, 0x619948cb, 0xec11b529, 0xfa494805, + 0x77c1b5e7, 0x3a29b580, 0xb7a14862, 0xa32abcb5, 0x2ea24157, + 0x634a4130, 0xeec2bcd2, 0xf89a41fe, 0x7512bc1c, 0x38fabc7b, + 0xb5724199, 0x144b4623, 0x99c3bbc1, 0xd42bbba6, 0x59a34644, + 0x4ffbbb68, 0xc273468a, 0x8f9b46ed, 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0x626e9f98, 0x7b6c9ffb, 0xb4f28833, 0x3f21b62a, 0xf0bfa1e2, + 0xf3f6cc59, 0x3c68db91, 0xb7bbe588, 0x7825f240, 0xb1293efe, + 0x7eb72936, 0xf564172f, 0x3afa00e7, 0x39b36d5c, 0xf62d7a94, + 0x7dfe448d, 0xb2605345, 0x3496dbb0, 0xfb08cc78, 0x70dbf261, + 0xbf45e5a9, 0xbc0c8812, 0x73929fda, 0xf841a1c3, 0x37dfb60b, + 0xfed37ab5, 0x314d6d7d, 0xba9e5364, 0x750044ac, 0x76492917, + 0xb9d73edf, 0x320400c6, 0xfd9a170e, 0x1241289b, 0xdddf3f53, + 0x560c014a, 0x99921682, 0x9adb7b39, 0x55456cf1, 0xde9652e8, + 0x11084520, 0xd804899e, 0x179a9e56, 0x9c49a04f, 0x53d7b787, + 0x509eda3c, 0x9f00cdf4, 0x14d3f3ed, 0xdb4de425, 0x5dbb6cd0, + 0x92257b18, 0x19f64501, 0xd66852c9, 0xd5213f72, 0x1abf28ba, + 0x916c16a3, 0x5ef2016b, 0x97fecdd5, 0x5860da1d, 0xd3b3e404, + 0x1c2df3cc, 0x1f649e77, 0xd0fa89bf, 0x5b29b7a6, 0x94b7a06e, + 0x8db5a00d, 0x422bb7c5, 0xc9f889dc, 0x06669e14, 0x052ff3af, + 0xcab1e467, 0x4162da7e, 0x8efccdb6, 0x47f00108, 0x886e16c0, + 0x03bd28d9, 0xcc233f11, 0xcf6a52aa, 0x00f44562, 0x8b277b7b, + 0x44b96cb3, 0xc24fe446, 0x0dd1f38e, 0x8602cd97, 0x499cda5f, + 0x4ad5b7e4, 0x854ba02c, 0x0e989e35, 0xc10689fd, 0x080a4543, + 0xc794528b, 0x4c476c92, 0x83d97b5a, 0x809016e1, 0x4f0e0129, + 0xc4dd3f30, 0x0b4328f8, 0xf6d93ff6, 0x3947283e, 0xb2941627, + 0x7d0a01ef, 0x7e436c54, 0xb1dd7b9c, 0x3a0e4585, 0xf590524d, + 0x3c9c9ef3, 0xf302893b, 0x78d1b722, 0xb74fa0ea, 0xb406cd51, + 0x7b98da99, 0xf04be480, 0x3fd5f348, 0xb9237bbd, 0x76bd6c75, + 0xfd6e526c, 0x32f045a4, 0x31b9281f, 0xfe273fd7, 0x75f401ce, + 0xba6a1606, 0x7366dab8, 0xbcf8cd70, 0x372bf369, 0xf8b5e4a1, + 0xfbfc891a, 0x34629ed2, 0xbfb1a0cb, 0x702fb703, 0x692db760, + 0xa6b3a0a8, 0x2d609eb1, 0xe2fe8979, 0xe1b7e4c2, 0x2e29f30a, + 0xa5facd13, 0x6a64dadb, 0xa3681665, 0x6cf601ad, 0xe7253fb4, + 0x28bb287c, 0x2bf245c7, 0xe46c520f, 0x6fbf6c16, 0xa0217bde, + 0x26d7f32b, 0xe949e4e3, 0x629adafa, 0xad04cd32, 0xae4da089, + 0x61d3b741, 0xea008958, 0x259e9e90, 0xec92522e, 0x230c45e6, + 0xa8df7bff, 0x67416c37, 0x6408018c, 0xab961644, 0x2045285d, + 0xefdb3f95}, + {0x00000000, 0x24825136, 0x4904a26c, 0x6d86f35a, 0x920944d8, + 0xb68b15ee, 0xdb0de6b4, 0xff8fb782, 0xff638ff1, 0xdbe1dec7, + 0xb6672d9d, 0x92e57cab, 0x6d6acb29, 0x49e89a1f, 0x246e6945, + 0x00ec3873, 0x25b619a3, 0x01344895, 0x6cb2bbcf, 0x4830eaf9, + 0xb7bf5d7b, 0x933d0c4d, 0xfebbff17, 0xda39ae21, 0xdad59652, + 0xfe57c764, 0x93d1343e, 0xb7536508, 0x48dcd28a, 0x6c5e83bc, + 0x01d870e6, 0x255a21d0, 0x4b6c3346, 0x6fee6270, 0x0268912a, + 0x26eac01c, 0xd965779e, 0xfde726a8, 0x9061d5f2, 0xb4e384c4, + 0xb40fbcb7, 0x908ded81, 0xfd0b1edb, 0xd9894fed, 0x2606f86f, + 0x0284a959, 0x6f025a03, 0x4b800b35, 0x6eda2ae5, 0x4a587bd3, + 0x27de8889, 0x035cd9bf, 0xfcd36e3d, 0xd8513f0b, 0xb5d7cc51, + 0x91559d67, 0x91b9a514, 0xb53bf422, 0xd8bd0778, 0xfc3f564e, + 0x03b0e1cc, 0x2732b0fa, 0x4ab443a0, 0x6e361296, 0x96d8668c, + 0xb25a37ba, 0xdfdcc4e0, 0xfb5e95d6, 0x04d12254, 0x20537362, + 0x4dd58038, 0x6957d10e, 0x69bbe97d, 0x4d39b84b, 0x20bf4b11, + 0x043d1a27, 0xfbb2ada5, 0xdf30fc93, 0xb2b60fc9, 0x96345eff, + 0xb36e7f2f, 0x97ec2e19, 0xfa6add43, 0xdee88c75, 0x21673bf7, + 0x05e56ac1, 0x6863999b, 0x4ce1c8ad, 0x4c0df0de, 0x688fa1e8, + 0x050952b2, 0x218b0384, 0xde04b406, 0xfa86e530, 0x9700166a, + 0xb382475c, 0xddb455ca, 0xf93604fc, 0x94b0f7a6, 0xb032a690, + 0x4fbd1112, 0x6b3f4024, 0x06b9b37e, 0x223be248, 0x22d7da3b, + 0x06558b0d, 0x6bd37857, 0x4f512961, 0xb0de9ee3, 0x945ccfd5, + 0xf9da3c8f, 0xdd586db9, 0xf8024c69, 0xdc801d5f, 0xb106ee05, + 0x9584bf33, 0x6a0b08b1, 0x4e895987, 0x230faadd, 0x078dfbeb, + 0x0761c398, 0x23e392ae, 0x4e6561f4, 0x6ae730c2, 0x95688740, + 0xb1ead676, 0xdc6c252c, 0xf8ee741a, 0xf6c1cb59, 0xd2439a6f, + 0xbfc56935, 0x9b473803, 0x64c88f81, 0x404adeb7, 0x2dcc2ded, + 0x094e7cdb, 0x09a244a8, 0x2d20159e, 0x40a6e6c4, 0x6424b7f2, + 0x9bab0070, 0xbf295146, 0xd2afa21c, 0xf62df32a, 0xd377d2fa, + 0xf7f583cc, 0x9a737096, 0xbef121a0, 0x417e9622, 0x65fcc714, + 0x087a344e, 0x2cf86578, 0x2c145d0b, 0x08960c3d, 0x6510ff67, + 0x4192ae51, 0xbe1d19d3, 0x9a9f48e5, 0xf719bbbf, 0xd39bea89, + 0xbdadf81f, 0x992fa929, 0xf4a95a73, 0xd02b0b45, 0x2fa4bcc7, + 0x0b26edf1, 0x66a01eab, 0x42224f9d, 0x42ce77ee, 0x664c26d8, + 0x0bcad582, 0x2f4884b4, 0xd0c73336, 0xf4456200, 0x99c3915a, + 0xbd41c06c, 0x981be1bc, 0xbc99b08a, 0xd11f43d0, 0xf59d12e6, + 0x0a12a564, 0x2e90f452, 0x43160708, 0x6794563e, 0x67786e4d, + 0x43fa3f7b, 0x2e7ccc21, 0x0afe9d17, 0xf5712a95, 0xd1f37ba3, + 0xbc7588f9, 0x98f7d9cf, 0x6019add5, 0x449bfce3, 0x291d0fb9, + 0x0d9f5e8f, 0xf210e90d, 0xd692b83b, 0xbb144b61, 0x9f961a57, + 0x9f7a2224, 0xbbf87312, 0xd67e8048, 0xf2fcd17e, 0x0d7366fc, + 0x29f137ca, 0x4477c490, 0x60f595a6, 0x45afb476, 0x612de540, + 0x0cab161a, 0x2829472c, 0xd7a6f0ae, 0xf324a198, 0x9ea252c2, + 0xba2003f4, 0xbacc3b87, 0x9e4e6ab1, 0xf3c899eb, 0xd74ac8dd, + 0x28c57f5f, 0x0c472e69, 0x61c1dd33, 0x45438c05, 0x2b759e93, + 0x0ff7cfa5, 0x62713cff, 0x46f36dc9, 0xb97cda4b, 0x9dfe8b7d, + 0xf0787827, 0xd4fa2911, 0xd4161162, 0xf0944054, 0x9d12b30e, + 0xb990e238, 0x461f55ba, 0x629d048c, 0x0f1bf7d6, 0x2b99a6e0, + 0x0ec38730, 0x2a41d606, 0x47c7255c, 0x6345746a, 0x9ccac3e8, + 0xb84892de, 0xd5ce6184, 0xf14c30b2, 0xf1a008c1, 0xd52259f7, + 0xb8a4aaad, 0x9c26fb9b, 0x63a94c19, 0x472b1d2f, 0x2aadee75, + 0x0e2fbf43}, + {0x00000000, 0x36f290f3, 0x6de521e6, 0x5b17b115, 0xdbca43cc, + 0xed38d33f, 0xb62f622a, 0x80ddf2d9, 0x6ce581d9, 0x5a17112a, + 0x0100a03f, 0x37f230cc, 0xb72fc215, 0x81dd52e6, 0xdacae3f3, + 0xec387300, 0xd9cb03b2, 0xef399341, 0xb42e2254, 0x82dcb2a7, + 0x0201407e, 0x34f3d08d, 0x6fe46198, 0x5916f16b, 0xb52e826b, + 0x83dc1298, 0xd8cba38d, 0xee39337e, 0x6ee4c1a7, 0x58165154, + 0x0301e041, 0x35f370b2, 0x68e70125, 0x5e1591d6, 0x050220c3, + 0x33f0b030, 0xb32d42e9, 0x85dfd21a, 0xdec8630f, 0xe83af3fc, + 0x040280fc, 0x32f0100f, 0x69e7a11a, 0x5f1531e9, 0xdfc8c330, + 0xe93a53c3, 0xb22de2d6, 0x84df7225, 0xb12c0297, 0x87de9264, + 0xdcc92371, 0xea3bb382, 0x6ae6415b, 0x5c14d1a8, 0x070360bd, + 0x31f1f04e, 0xddc9834e, 0xeb3b13bd, 0xb02ca2a8, 0x86de325b, + 0x0603c082, 0x30f15071, 0x6be6e164, 0x5d147197, 0xd1ce024a, + 0xe73c92b9, 0xbc2b23ac, 0x8ad9b35f, 0x0a044186, 0x3cf6d175, + 0x67e16060, 0x5113f093, 0xbd2b8393, 0x8bd91360, 0xd0cea275, + 0xe63c3286, 0x66e1c05f, 0x501350ac, 0x0b04e1b9, 0x3df6714a, + 0x080501f8, 0x3ef7910b, 0x65e0201e, 0x5312b0ed, 0xd3cf4234, + 0xe53dd2c7, 0xbe2a63d2, 0x88d8f321, 0x64e08021, 0x521210d2, + 0x0905a1c7, 0x3ff73134, 0xbf2ac3ed, 0x89d8531e, 0xd2cfe20b, + 0xe43d72f8, 0xb929036f, 0x8fdb939c, 0xd4cc2289, 0xe23eb27a, + 0x62e340a3, 0x5411d050, 0x0f066145, 0x39f4f1b6, 0xd5cc82b6, + 0xe33e1245, 0xb829a350, 0x8edb33a3, 0x0e06c17a, 0x38f45189, + 0x63e3e09c, 0x5511706f, 0x60e200dd, 0x5610902e, 0x0d07213b, + 0x3bf5b1c8, 0xbb284311, 0x8ddad3e2, 0xd6cd62f7, 0xe03ff204, + 0x0c078104, 0x3af511f7, 0x61e2a0e2, 0x57103011, 0xd7cdc2c8, + 0xe13f523b, 0xba28e32e, 0x8cda73dd, 0x78ed02d5, 0x4e1f9226, + 0x15082333, 0x23fab3c0, 0xa3274119, 0x95d5d1ea, 0xcec260ff, + 0xf830f00c, 0x1408830c, 0x22fa13ff, 0x79eda2ea, 0x4f1f3219, + 0xcfc2c0c0, 0xf9305033, 0xa227e126, 0x94d571d5, 0xa1260167, + 0x97d49194, 0xccc32081, 0xfa31b072, 0x7aec42ab, 0x4c1ed258, + 0x1709634d, 0x21fbf3be, 0xcdc380be, 0xfb31104d, 0xa026a158, + 0x96d431ab, 0x1609c372, 0x20fb5381, 0x7bece294, 0x4d1e7267, + 0x100a03f0, 0x26f89303, 0x7def2216, 0x4b1db2e5, 0xcbc0403c, + 0xfd32d0cf, 0xa62561da, 0x90d7f129, 0x7cef8229, 0x4a1d12da, + 0x110aa3cf, 0x27f8333c, 0xa725c1e5, 0x91d75116, 0xcac0e003, + 0xfc3270f0, 0xc9c10042, 0xff3390b1, 0xa42421a4, 0x92d6b157, + 0x120b438e, 0x24f9d37d, 0x7fee6268, 0x491cf29b, 0xa524819b, + 0x93d61168, 0xc8c1a07d, 0xfe33308e, 0x7eeec257, 0x481c52a4, + 0x130be3b1, 0x25f97342, 0xa923009f, 0x9fd1906c, 0xc4c62179, + 0xf234b18a, 0x72e94353, 0x441bd3a0, 0x1f0c62b5, 0x29fef246, + 0xc5c68146, 0xf33411b5, 0xa823a0a0, 0x9ed13053, 0x1e0cc28a, + 0x28fe5279, 0x73e9e36c, 0x451b739f, 0x70e8032d, 0x461a93de, + 0x1d0d22cb, 0x2bffb238, 0xab2240e1, 0x9dd0d012, 0xc6c76107, + 0xf035f1f4, 0x1c0d82f4, 0x2aff1207, 0x71e8a312, 0x471a33e1, + 0xc7c7c138, 0xf13551cb, 0xaa22e0de, 0x9cd0702d, 0xc1c401ba, + 0xf7369149, 0xac21205c, 0x9ad3b0af, 0x1a0e4276, 0x2cfcd285, + 0x77eb6390, 0x4119f363, 0xad218063, 0x9bd31090, 0xc0c4a185, + 0xf6363176, 0x76ebc3af, 0x4019535c, 0x1b0ee249, 0x2dfc72ba, + 0x180f0208, 0x2efd92fb, 0x75ea23ee, 0x4318b31d, 0xc3c541c4, + 0xf537d137, 0xae206022, 0x98d2f0d1, 0x74ea83d1, 0x42181322, + 0x190fa237, 0x2ffd32c4, 0xaf20c01d, 0x99d250ee, 0xc2c5e1fb, + 0xf4377108}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x0000000000000000, 0xf390f23600000000, 0xe621e56d00000000, + 0x15b1175b00000000, 0xcc43cadb00000000, 0x3fd338ed00000000, + 0x2a622fb600000000, 0xd9f2dd8000000000, 0xd981e56c00000000, + 0x2a11175a00000000, 0x3fa0000100000000, 0xcc30f23700000000, + 0x15c22fb700000000, 0xe652dd8100000000, 0xf3e3cada00000000, + 0x007338ec00000000, 0xb203cbd900000000, 0x419339ef00000000, + 0x54222eb400000000, 0xa7b2dc8200000000, 0x7e40010200000000, + 0x8dd0f33400000000, 0x9861e46f00000000, 0x6bf1165900000000, + 0x6b822eb500000000, 0x9812dc8300000000, 0x8da3cbd800000000, + 0x7e3339ee00000000, 0xa7c1e46e00000000, 0x5451165800000000, + 0x41e0010300000000, 0xb270f33500000000, 0x2501e76800000000, + 0xd691155e00000000, 0xc320020500000000, 0x30b0f03300000000, + 0xe9422db300000000, 0x1ad2df8500000000, 0x0f63c8de00000000, + 0xfcf33ae800000000, 0xfc80020400000000, 0x0f10f03200000000, + 0x1aa1e76900000000, 0xe931155f00000000, 0x30c3c8df00000000, + 0xc3533ae900000000, 0xd6e22db200000000, 0x2572df8400000000, + 0x97022cb100000000, 0x6492de8700000000, 0x7123c9dc00000000, + 0x82b33bea00000000, 0x5b41e66a00000000, 0xa8d1145c00000000, + 0xbd60030700000000, 0x4ef0f13100000000, 0x4e83c9dd00000000, + 0xbd133beb00000000, 0xa8a22cb000000000, 0x5b32de8600000000, + 0x82c0030600000000, 0x7150f13000000000, 0x64e1e66b00000000, + 0x9771145d00000000, 0x4a02ced100000000, 0xb9923ce700000000, + 0xac232bbc00000000, 0x5fb3d98a00000000, 0x8641040a00000000, + 0x75d1f63c00000000, 0x6060e16700000000, 0x93f0135100000000, + 0x93832bbd00000000, 0x6013d98b00000000, 0x75a2ced000000000, + 0x86323ce600000000, 0x5fc0e16600000000, 0xac50135000000000, + 0xb9e1040b00000000, 0x4a71f63d00000000, 0xf801050800000000, + 0x0b91f73e00000000, 0x1e20e06500000000, 0xedb0125300000000, + 0x3442cfd300000000, 0xc7d23de500000000, 0xd2632abe00000000, + 0x21f3d88800000000, 0x2180e06400000000, 0xd210125200000000, + 0xc7a1050900000000, 0x3431f73f00000000, 0xedc32abf00000000, + 0x1e53d88900000000, 0x0be2cfd200000000, 0xf8723de400000000, + 0x6f0329b900000000, 0x9c93db8f00000000, 0x8922ccd400000000, + 0x7ab23ee200000000, 0xa340e36200000000, 0x50d0115400000000, + 0x4561060f00000000, 0xb6f1f43900000000, 0xb682ccd500000000, + 0x45123ee300000000, 0x50a329b800000000, 0xa333db8e00000000, + 0x7ac1060e00000000, 0x8951f43800000000, 0x9ce0e36300000000, + 0x6f70115500000000, 0xdd00e26000000000, 0x2e90105600000000, + 0x3b21070d00000000, 0xc8b1f53b00000000, 0x114328bb00000000, + 0xe2d3da8d00000000, 0xf762cdd600000000, 0x04f23fe000000000, + 0x0481070c00000000, 0xf711f53a00000000, 0xe2a0e26100000000, + 0x1130105700000000, 0xc8c2cdd700000000, 0x3b523fe100000000, + 0x2ee328ba00000000, 0xdd73da8c00000000, 0xd502ed7800000000, + 0x26921f4e00000000, 0x3323081500000000, 0xc0b3fa2300000000, + 0x194127a300000000, 0xead1d59500000000, 0xff60c2ce00000000, + 0x0cf030f800000000, 0x0c83081400000000, 0xff13fa2200000000, + 0xeaa2ed7900000000, 0x19321f4f00000000, 0xc0c0c2cf00000000, + 0x335030f900000000, 0x26e127a200000000, 0xd571d59400000000, + 0x670126a100000000, 0x9491d49700000000, 0x8120c3cc00000000, + 0x72b031fa00000000, 0xab42ec7a00000000, 0x58d21e4c00000000, + 0x4d63091700000000, 0xbef3fb2100000000, 0xbe80c3cd00000000, + 0x4d1031fb00000000, 0x58a126a000000000, 0xab31d49600000000, + 0x72c3091600000000, 0x8153fb2000000000, 0x94e2ec7b00000000, + 0x67721e4d00000000, 0xf0030a1000000000, 0x0393f82600000000, + 0x1622ef7d00000000, 0xe5b21d4b00000000, 0x3c40c0cb00000000, + 0xcfd032fd00000000, 0xda6125a600000000, 0x29f1d79000000000, + 0x2982ef7c00000000, 0xda121d4a00000000, 0xcfa30a1100000000, + 0x3c33f82700000000, 0xe5c125a700000000, 0x1651d79100000000, + 0x03e0c0ca00000000, 0xf07032fc00000000, 0x4200c1c900000000, + 0xb19033ff00000000, 0xa42124a400000000, 0x57b1d69200000000, + 0x8e430b1200000000, 0x7dd3f92400000000, 0x6862ee7f00000000, + 0x9bf21c4900000000, 0x9b8124a500000000, 0x6811d69300000000, + 0x7da0c1c800000000, 0x8e3033fe00000000, 0x57c2ee7e00000000, + 0xa4521c4800000000, 0xb1e30b1300000000, 0x4273f92500000000, + 0x9f0023a900000000, 0x6c90d19f00000000, 0x7921c6c400000000, + 0x8ab134f200000000, 0x5343e97200000000, 0xa0d31b4400000000, + 0xb5620c1f00000000, 0x46f2fe2900000000, 0x4681c6c500000000, + 0xb51134f300000000, 0xa0a023a800000000, 0x5330d19e00000000, + 0x8ac20c1e00000000, 0x7952fe2800000000, 0x6ce3e97300000000, + 0x9f731b4500000000, 0x2d03e87000000000, 0xde931a4600000000, + 0xcb220d1d00000000, 0x38b2ff2b00000000, 0xe14022ab00000000, + 0x12d0d09d00000000, 0x0761c7c600000000, 0xf4f135f000000000, + 0xf4820d1c00000000, 0x0712ff2a00000000, 0x12a3e87100000000, + 0xe1331a4700000000, 0x38c1c7c700000000, 0xcb5135f100000000, + 0xdee022aa00000000, 0x2d70d09c00000000, 0xba01c4c100000000, + 0x499136f700000000, 0x5c2021ac00000000, 0xafb0d39a00000000, + 0x76420e1a00000000, 0x85d2fc2c00000000, 0x9063eb7700000000, + 0x63f3194100000000, 0x638021ad00000000, 0x9010d39b00000000, + 0x85a1c4c000000000, 0x763136f600000000, 0xafc3eb7600000000, + 0x5c53194000000000, 0x49e20e1b00000000, 0xba72fc2d00000000, + 0x08020f1800000000, 0xfb92fd2e00000000, 0xee23ea7500000000, + 0x1db3184300000000, 0xc441c5c300000000, 0x37d137f500000000, + 0x226020ae00000000, 0xd1f0d29800000000, 0xd183ea7400000000, + 0x2213184200000000, 0x37a20f1900000000, 0xc432fd2f00000000, + 0x1dc020af00000000, 0xee50d29900000000, 0xfbe1c5c200000000, + 0x087137f400000000}, + {0x0000000000000000, 0x3651822400000000, 0x6ca2044900000000, + 0x5af3866d00000000, 0xd844099200000000, 0xee158bb600000000, + 0xb4e60ddb00000000, 0x82b78fff00000000, 0xf18f63ff00000000, + 0xc7dee1db00000000, 0x9d2d67b600000000, 0xab7ce59200000000, + 0x29cb6a6d00000000, 0x1f9ae84900000000, 0x45696e2400000000, + 0x7338ec0000000000, 0xa319b62500000000, 0x9548340100000000, + 0xcfbbb26c00000000, 0xf9ea304800000000, 0x7b5dbfb700000000, + 0x4d0c3d9300000000, 0x17ffbbfe00000000, 0x21ae39da00000000, + 0x5296d5da00000000, 0x64c757fe00000000, 0x3e34d19300000000, + 0x086553b700000000, 0x8ad2dc4800000000, 0xbc835e6c00000000, + 0xe670d80100000000, 0xd0215a2500000000, 0x46336c4b00000000, + 0x7062ee6f00000000, 0x2a91680200000000, 0x1cc0ea2600000000, + 0x9e7765d900000000, 0xa826e7fd00000000, 0xf2d5619000000000, + 0xc484e3b400000000, 0xb7bc0fb400000000, 0x81ed8d9000000000, + 0xdb1e0bfd00000000, 0xed4f89d900000000, 0x6ff8062600000000, + 0x59a9840200000000, 0x035a026f00000000, 0x350b804b00000000, + 0xe52ada6e00000000, 0xd37b584a00000000, 0x8988de2700000000, + 0xbfd95c0300000000, 0x3d6ed3fc00000000, 0x0b3f51d800000000, + 0x51ccd7b500000000, 0x679d559100000000, 0x14a5b99100000000, + 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0x9d31faec00000000, 0x662d613f00000000, + 0xcf26e87100000000, 0xd112264300000000, 0x7819af0d00000000, + 0x830534de00000000, 0x2a0ebd9000000000, 0x859c73ef00000000, + 0x2c97faa100000000, 0xd78b617200000000, 0x7e80e83c00000000, + 0x60b4260e00000000, 0xc9bfaf4000000000, 0x32a3349300000000, + 0x9ba8bddd00000000, 0x0ecba8f600000000, 0xa7c021b800000000, + 0x5cdcba6b00000000, 0xf5d7332500000000, 0xebe3fd1700000000, + 0x42e8745900000000, 0xb9f4ef8a00000000, 0x10ff66c400000000, + 0x9333c5dc00000000, 0x3a384c9200000000, 0xc124d74100000000, + 0x682f5e0f00000000, 0x761b903d00000000, 0xdf10197300000000, + 0x240c82a000000000, 0x8d070bee00000000, 0x18641ec500000000, + 0xb16f978b00000000, 0x4a730c5800000000, 0xe378851600000000, + 0xfd4c4b2400000000, 0x5447c26a00000000, 0xaf5b59b900000000, + 0x0650d0f700000000}, + {0x0000000000000000, 0x479244af00000000, 0xcf22f88500000000, + 0x88b0bc2a00000000, 0xdf4381d000000000, 0x98d1c57f00000000, + 0x1061795500000000, 0x57f33dfa00000000, 0xff81737a00000000, + 0xb81337d500000000, 0x30a38bff00000000, 0x7731cf5000000000, + 0x20c2f2aa00000000, 0x6750b60500000000, 0xefe00a2f00000000, + 0xa8724e8000000000, 0xfe03e7f400000000, 0xb991a35b00000000, + 0x31211f7100000000, 0x76b35bde00000000, 0x2140662400000000, + 0x66d2228b00000000, 0xee629ea100000000, 0xa9f0da0e00000000, + 0x0182948e00000000, 0x4610d02100000000, 0xcea06c0b00000000, + 0x893228a400000000, 0xdec1155e00000000, 0x995351f100000000, + 0x11e3eddb00000000, 0x5671a97400000000, 0xbd01bf3200000000, + 0xfa93fb9d00000000, 0x722347b700000000, 0x35b1031800000000, + 0x62423ee200000000, 0x25d07a4d00000000, 0xad60c66700000000, + 0xeaf282c800000000, 0x4280cc4800000000, 0x051288e700000000, + 0x8da234cd00000000, 0xca30706200000000, 0x9dc34d9800000000, + 0xda51093700000000, 0x52e1b51d00000000, 0x1573f1b200000000, + 0x430258c600000000, 0x04901c6900000000, 0x8c20a04300000000, + 0xcbb2e4ec00000000, 0x9c41d91600000000, 0xdbd39db900000000, + 0x5363219300000000, 0x14f1653c00000000, 0xbc832bbc00000000, + 0xfb116f1300000000, 0x73a1d33900000000, 0x3433979600000000, + 0x63c0aa6c00000000, 0x2452eec300000000, 0xace252e900000000, + 0xeb70164600000000, 0x7a037e6500000000, 0x3d913aca00000000, + 0xb52186e000000000, 0xf2b3c24f00000000, 0xa540ffb500000000, + 0xe2d2bb1a00000000, 0x6a62073000000000, 0x2df0439f00000000, + 0x85820d1f00000000, 0xc21049b000000000, 0x4aa0f59a00000000, + 0x0d32b13500000000, 0x5ac18ccf00000000, 0x1d53c86000000000, + 0x95e3744a00000000, 0xd27130e500000000, 0x8400999100000000, + 0xc392dd3e00000000, 0x4b22611400000000, 0x0cb025bb00000000, + 0x5b43184100000000, 0x1cd15cee00000000, 0x9461e0c400000000, + 0xd3f3a46b00000000, 0x7b81eaeb00000000, 0x3c13ae4400000000, + 0xb4a3126e00000000, 0xf33156c100000000, 0xa4c26b3b00000000, + 0xe3502f9400000000, 0x6be093be00000000, 0x2c72d71100000000, + 0xc702c15700000000, 0x809085f800000000, 0x082039d200000000, + 0x4fb27d7d00000000, 0x1841408700000000, 0x5fd3042800000000, + 0xd763b80200000000, 0x90f1fcad00000000, 0x3883b22d00000000, + 0x7f11f68200000000, 0xf7a14aa800000000, 0xb0330e0700000000, + 0xe7c033fd00000000, 0xa052775200000000, 0x28e2cb7800000000, + 0x6f708fd700000000, 0x390126a300000000, 0x7e93620c00000000, + 0xf623de2600000000, 0xb1b19a8900000000, 0xe642a77300000000, + 0xa1d0e3dc00000000, 0x29605ff600000000, 0x6ef21b5900000000, + 0xc68055d900000000, 0x8112117600000000, 0x09a2ad5c00000000, + 0x4e30e9f300000000, 0x19c3d40900000000, 0x5e5190a600000000, + 0xd6e12c8c00000000, 0x9173682300000000, 0xf406fcca00000000, + 0xb394b86500000000, 0x3b24044f00000000, 0x7cb640e000000000, + 0x2b457d1a00000000, 0x6cd739b500000000, 0xe467859f00000000, + 0xa3f5c13000000000, 0x0b878fb000000000, 0x4c15cb1f00000000, + 0xc4a5773500000000, 0x8337339a00000000, 0xd4c40e6000000000, + 0x93564acf00000000, 0x1be6f6e500000000, 0x5c74b24a00000000, + 0x0a051b3e00000000, 0x4d975f9100000000, 0xc527e3bb00000000, + 0x82b5a71400000000, 0xd5469aee00000000, 0x92d4de4100000000, + 0x1a64626b00000000, 0x5df626c400000000, 0xf584684400000000, + 0xb2162ceb00000000, 0x3aa690c100000000, 0x7d34d46e00000000, + 0x2ac7e99400000000, 0x6d55ad3b00000000, 0xe5e5111100000000, + 0xa27755be00000000, 0x490743f800000000, 0x0e95075700000000, + 0x8625bb7d00000000, 0xc1b7ffd200000000, 0x9644c22800000000, + 0xd1d6868700000000, 0x59663aad00000000, 0x1ef47e0200000000, + 0xb686308200000000, 0xf114742d00000000, 0x79a4c80700000000, + 0x3e368ca800000000, 0x69c5b15200000000, 0x2e57f5fd00000000, + 0xa6e749d700000000, 0xe1750d7800000000, 0xb704a40c00000000, + 0xf096e0a300000000, 0x78265c8900000000, 0x3fb4182600000000, + 0x684725dc00000000, 0x2fd5617300000000, 0xa765dd5900000000, + 0xe0f799f600000000, 0x4885d77600000000, 0x0f1793d900000000, + 0x87a72ff300000000, 0xc0356b5c00000000, 0x97c656a600000000, + 0xd054120900000000, 0x58e4ae2300000000, 0x1f76ea8c00000000, + 0x8e0582af00000000, 0xc997c60000000000, 0x41277a2a00000000, + 0x06b53e8500000000, 0x5146037f00000000, 0x16d447d000000000, + 0x9e64fbfa00000000, 0xd9f6bf5500000000, 0x7184f1d500000000, + 0x3616b57a00000000, 0xbea6095000000000, 0xf9344dff00000000, + 0xaec7700500000000, 0xe95534aa00000000, 0x61e5888000000000, + 0x2677cc2f00000000, 0x7006655b00000000, 0x379421f400000000, + 0xbf249dde00000000, 0xf8b6d97100000000, 0xaf45e48b00000000, + 0xe8d7a02400000000, 0x60671c0e00000000, 0x27f558a100000000, + 0x8f87162100000000, 0xc815528e00000000, 0x40a5eea400000000, + 0x0737aa0b00000000, 0x50c497f100000000, 0x1756d35e00000000, + 0x9fe66f7400000000, 0xd8742bdb00000000, 0x33043d9d00000000, + 0x7496793200000000, 0xfc26c51800000000, 0xbbb481b700000000, + 0xec47bc4d00000000, 0xabd5f8e200000000, 0x236544c800000000, + 0x64f7006700000000, 0xcc854ee700000000, 0x8b170a4800000000, + 0x03a7b66200000000, 0x4435f2cd00000000, 0x13c6cf3700000000, + 0x54548b9800000000, 0xdce437b200000000, 0x9b76731d00000000, + 0xcd07da6900000000, 0x8a959ec600000000, 0x022522ec00000000, + 0x45b7664300000000, 0x12445bb900000000, 0x55d61f1600000000, + 0xdd66a33c00000000, 0x9af4e79300000000, 0x3286a91300000000, + 0x7514edbc00000000, 0xfda4519600000000, 0xba36153900000000, + 0xedc528c300000000, 0xaa576c6c00000000, 0x22e7d04600000000, + 0x657594e900000000}}; + +#else /* W == 4 */ + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0x65673b46, 0xcace768c, 0xafa94dca, 0x4eedeb59, + 0x2b8ad01f, 0x84239dd5, 0xe144a693, 0x9ddbd6b2, 0xf8bcedf4, + 0x5715a03e, 0x32729b78, 0xd3363deb, 0xb65106ad, 0x19f84b67, + 0x7c9f7021, 0xe0c6ab25, 0x85a19063, 0x2a08dda9, 0x4f6fe6ef, + 0xae2b407c, 0xcb4c7b3a, 0x64e536f0, 0x01820db6, 0x7d1d7d97, + 0x187a46d1, 0xb7d30b1b, 0xd2b4305d, 0x33f096ce, 0x5697ad88, + 0xf93ee042, 0x9c59db04, 0x1afc500b, 0x7f9b6b4d, 0xd0322687, + 0xb5551dc1, 0x5411bb52, 0x31768014, 0x9edfcdde, 0xfbb8f698, + 0x872786b9, 0xe240bdff, 0x4de9f035, 0x288ecb73, 0xc9ca6de0, + 0xacad56a6, 0x03041b6c, 0x6663202a, 0xfa3afb2e, 0x9f5dc068, + 0x30f48da2, 0x5593b6e4, 0xb4d71077, 0xd1b02b31, 0x7e1966fb, + 0x1b7e5dbd, 0x67e12d9c, 0x028616da, 0xad2f5b10, 0xc8486056, + 0x290cc6c5, 0x4c6bfd83, 0xe3c2b049, 0x86a58b0f, 0x35f8a016, + 0x509f9b50, 0xff36d69a, 0x9a51eddc, 0x7b154b4f, 0x1e727009, + 0xb1db3dc3, 0xd4bc0685, 0xa82376a4, 0xcd444de2, 0x62ed0028, + 0x078a3b6e, 0xe6ce9dfd, 0x83a9a6bb, 0x2c00eb71, 0x4967d037, + 0xd53e0b33, 0xb0593075, 0x1ff07dbf, 0x7a9746f9, 0x9bd3e06a, + 0xfeb4db2c, 0x511d96e6, 0x347aada0, 0x48e5dd81, 0x2d82e6c7, + 0x822bab0d, 0xe74c904b, 0x060836d8, 0x636f0d9e, 0xccc64054, + 0xa9a17b12, 0x2f04f01d, 0x4a63cb5b, 0xe5ca8691, 0x80adbdd7, + 0x61e91b44, 0x048e2002, 0xab276dc8, 0xce40568e, 0xb2df26af, + 0xd7b81de9, 0x78115023, 0x1d766b65, 0xfc32cdf6, 0x9955f6b0, + 0x36fcbb7a, 0x539b803c, 0xcfc25b38, 0xaaa5607e, 0x050c2db4, + 0x606b16f2, 0x812fb061, 0xe4488b27, 0x4be1c6ed, 0x2e86fdab, + 0x52198d8a, 0x377eb6cc, 0x98d7fb06, 0xfdb0c040, 0x1cf466d3, + 0x79935d95, 0xd63a105f, 0xb35d2b19, 0x6bf1402c, 0x0e967b6a, + 0xa13f36a0, 0xc4580de6, 0x251cab75, 0x407b9033, 0xefd2ddf9, + 0x8ab5e6bf, 0xf62a969e, 0x934dadd8, 0x3ce4e012, 0x5983db54, + 0xb8c77dc7, 0xdda04681, 0x72090b4b, 0x176e300d, 0x8b37eb09, + 0xee50d04f, 0x41f99d85, 0x249ea6c3, 0xc5da0050, 0xa0bd3b16, + 0x0f1476dc, 0x6a734d9a, 0x16ec3dbb, 0x738b06fd, 0xdc224b37, + 0xb9457071, 0x5801d6e2, 0x3d66eda4, 0x92cfa06e, 0xf7a89b28, + 0x710d1027, 0x146a2b61, 0xbbc366ab, 0xdea45ded, 0x3fe0fb7e, + 0x5a87c038, 0xf52e8df2, 0x9049b6b4, 0xecd6c695, 0x89b1fdd3, + 0x2618b019, 0x437f8b5f, 0xa23b2dcc, 0xc75c168a, 0x68f55b40, + 0x0d926006, 0x91cbbb02, 0xf4ac8044, 0x5b05cd8e, 0x3e62f6c8, + 0xdf26505b, 0xba416b1d, 0x15e826d7, 0x708f1d91, 0x0c106db0, + 0x697756f6, 0xc6de1b3c, 0xa3b9207a, 0x42fd86e9, 0x279abdaf, + 0x8833f065, 0xed54cb23, 0x5e09e03a, 0x3b6edb7c, 0x94c796b6, + 0xf1a0adf0, 0x10e40b63, 0x75833025, 0xda2a7def, 0xbf4d46a9, + 0xc3d23688, 0xa6b50dce, 0x091c4004, 0x6c7b7b42, 0x8d3fddd1, + 0xe858e697, 0x47f1ab5d, 0x2296901b, 0xbecf4b1f, 0xdba87059, + 0x74013d93, 0x116606d5, 0xf022a046, 0x95459b00, 0x3aecd6ca, + 0x5f8bed8c, 0x23149dad, 0x4673a6eb, 0xe9daeb21, 0x8cbdd067, + 0x6df976f4, 0x089e4db2, 0xa7370078, 0xc2503b3e, 0x44f5b031, + 0x21928b77, 0x8e3bc6bd, 0xeb5cfdfb, 0x0a185b68, 0x6f7f602e, + 0xc0d62de4, 0xa5b116a2, 0xd92e6683, 0xbc495dc5, 0x13e0100f, + 0x76872b49, 0x97c38dda, 0xf2a4b69c, 0x5d0dfb56, 0x386ac010, + 0xa4331b14, 0xc1542052, 0x6efd6d98, 0x0b9a56de, 0xeadef04d, + 0x8fb9cb0b, 0x201086c1, 0x4577bd87, 0x39e8cda6, 0x5c8ff6e0, + 0xf326bb2a, 0x9641806c, 0x770526ff, 0x12621db9, 0xbdcb5073, + 0xd8ac6b35}, + {0x00000000, 0xd7e28058, 0x74b406f1, 0xa35686a9, 0xe9680de2, + 0x3e8a8dba, 0x9ddc0b13, 0x4a3e8b4b, 0x09a11d85, 0xde439ddd, + 0x7d151b74, 0xaaf79b2c, 0xe0c91067, 0x372b903f, 0x947d1696, + 0x439f96ce, 0x13423b0a, 0xc4a0bb52, 0x67f63dfb, 0xb014bda3, + 0xfa2a36e8, 0x2dc8b6b0, 0x8e9e3019, 0x597cb041, 0x1ae3268f, + 0xcd01a6d7, 0x6e57207e, 0xb9b5a026, 0xf38b2b6d, 0x2469ab35, + 0x873f2d9c, 0x50ddadc4, 0x26847614, 0xf166f64c, 0x523070e5, + 0x85d2f0bd, 0xcfec7bf6, 0x180efbae, 0xbb587d07, 0x6cbafd5f, + 0x2f256b91, 0xf8c7ebc9, 0x5b916d60, 0x8c73ed38, 0xc64d6673, + 0x11afe62b, 0xb2f96082, 0x651be0da, 0x35c64d1e, 0xe224cd46, + 0x41724bef, 0x9690cbb7, 0xdcae40fc, 0x0b4cc0a4, 0xa81a460d, + 0x7ff8c655, 0x3c67509b, 0xeb85d0c3, 0x48d3566a, 0x9f31d632, + 0xd50f5d79, 0x02eddd21, 0xa1bb5b88, 0x7659dbd0, 0x4d08ec28, + 0x9aea6c70, 0x39bcead9, 0xee5e6a81, 0xa460e1ca, 0x73826192, + 0xd0d4e73b, 0x07366763, 0x44a9f1ad, 0x934b71f5, 0x301df75c, + 0xe7ff7704, 0xadc1fc4f, 0x7a237c17, 0xd975fabe, 0x0e977ae6, + 0x5e4ad722, 0x89a8577a, 0x2afed1d3, 0xfd1c518b, 0xb722dac0, + 0x60c05a98, 0xc396dc31, 0x14745c69, 0x57ebcaa7, 0x80094aff, + 0x235fcc56, 0xf4bd4c0e, 0xbe83c745, 0x6961471d, 0xca37c1b4, + 0x1dd541ec, 0x6b8c9a3c, 0xbc6e1a64, 0x1f389ccd, 0xc8da1c95, + 0x82e497de, 0x55061786, 0xf650912f, 0x21b21177, 0x622d87b9, + 0xb5cf07e1, 0x16998148, 0xc17b0110, 0x8b458a5b, 0x5ca70a03, + 0xfff18caa, 0x28130cf2, 0x78cea136, 0xaf2c216e, 0x0c7aa7c7, + 0xdb98279f, 0x91a6acd4, 0x46442c8c, 0xe512aa25, 0x32f02a7d, + 0x716fbcb3, 0xa68d3ceb, 0x05dbba42, 0xd2393a1a, 0x9807b151, + 0x4fe53109, 0xecb3b7a0, 0x3b5137f8, 0x9a11d850, 0x4df35808, + 0xeea5dea1, 0x39475ef9, 0x7379d5b2, 0xa49b55ea, 0x07cdd343, + 0xd02f531b, 0x93b0c5d5, 0x4452458d, 0xe704c324, 0x30e6437c, + 0x7ad8c837, 0xad3a486f, 0x0e6ccec6, 0xd98e4e9e, 0x8953e35a, + 0x5eb16302, 0xfde7e5ab, 0x2a0565f3, 0x603beeb8, 0xb7d96ee0, + 0x148fe849, 0xc36d6811, 0x80f2fedf, 0x57107e87, 0xf446f82e, + 0x23a47876, 0x699af33d, 0xbe787365, 0x1d2ef5cc, 0xcacc7594, + 0xbc95ae44, 0x6b772e1c, 0xc821a8b5, 0x1fc328ed, 0x55fda3a6, + 0x821f23fe, 0x2149a557, 0xf6ab250f, 0xb534b3c1, 0x62d63399, + 0xc180b530, 0x16623568, 0x5c5cbe23, 0x8bbe3e7b, 0x28e8b8d2, + 0xff0a388a, 0xafd7954e, 0x78351516, 0xdb6393bf, 0x0c8113e7, + 0x46bf98ac, 0x915d18f4, 0x320b9e5d, 0xe5e91e05, 0xa67688cb, + 0x71940893, 0xd2c28e3a, 0x05200e62, 0x4f1e8529, 0x98fc0571, + 0x3baa83d8, 0xec480380, 0xd7193478, 0x00fbb420, 0xa3ad3289, + 0x744fb2d1, 0x3e71399a, 0xe993b9c2, 0x4ac53f6b, 0x9d27bf33, + 0xdeb829fd, 0x095aa9a5, 0xaa0c2f0c, 0x7deeaf54, 0x37d0241f, + 0xe032a447, 0x436422ee, 0x9486a2b6, 0xc45b0f72, 0x13b98f2a, + 0xb0ef0983, 0x670d89db, 0x2d330290, 0xfad182c8, 0x59870461, + 0x8e658439, 0xcdfa12f7, 0x1a1892af, 0xb94e1406, 0x6eac945e, + 0x24921f15, 0xf3709f4d, 0x502619e4, 0x87c499bc, 0xf19d426c, + 0x267fc234, 0x8529449d, 0x52cbc4c5, 0x18f54f8e, 0xcf17cfd6, + 0x6c41497f, 0xbba3c927, 0xf83c5fe9, 0x2fdedfb1, 0x8c885918, + 0x5b6ad940, 0x1154520b, 0xc6b6d253, 0x65e054fa, 0xb202d4a2, + 0xe2df7966, 0x353df93e, 0x966b7f97, 0x4189ffcf, 0x0bb77484, + 0xdc55f4dc, 0x7f037275, 0xa8e1f22d, 0xeb7e64e3, 0x3c9ce4bb, + 0x9fca6212, 0x4828e24a, 0x02166901, 0xd5f4e959, 0x76a26ff0, + 0xa140efa8}, + {0x00000000, 0xef52b6e1, 0x05d46b83, 0xea86dd62, 0x0ba8d706, + 0xe4fa61e7, 0x0e7cbc85, 0xe12e0a64, 0x1751ae0c, 0xf80318ed, + 0x1285c58f, 0xfdd7736e, 0x1cf9790a, 0xf3abcfeb, 0x192d1289, + 0xf67fa468, 0x2ea35c18, 0xc1f1eaf9, 0x2b77379b, 0xc425817a, + 0x250b8b1e, 0xca593dff, 0x20dfe09d, 0xcf8d567c, 0x39f2f214, + 0xd6a044f5, 0x3c269997, 0xd3742f76, 0x325a2512, 0xdd0893f3, + 0x378e4e91, 0xd8dcf870, 0x5d46b830, 0xb2140ed1, 0x5892d3b3, + 0xb7c06552, 0x56ee6f36, 0xb9bcd9d7, 0x533a04b5, 0xbc68b254, + 0x4a17163c, 0xa545a0dd, 0x4fc37dbf, 0xa091cb5e, 0x41bfc13a, + 0xaeed77db, 0x446baab9, 0xab391c58, 0x73e5e428, 0x9cb752c9, + 0x76318fab, 0x9963394a, 0x784d332e, 0x971f85cf, 0x7d9958ad, + 0x92cbee4c, 0x64b44a24, 0x8be6fcc5, 0x616021a7, 0x8e329746, + 0x6f1c9d22, 0x804e2bc3, 0x6ac8f6a1, 0x859a4040, 0xba8d7060, + 0x55dfc681, 0xbf591be3, 0x500bad02, 0xb125a766, 0x5e771187, + 0xb4f1cce5, 0x5ba37a04, 0xaddcde6c, 0x428e688d, 0xa808b5ef, + 0x475a030e, 0xa674096a, 0x4926bf8b, 0xa3a062e9, 0x4cf2d408, + 0x942e2c78, 0x7b7c9a99, 0x91fa47fb, 0x7ea8f11a, 0x9f86fb7e, + 0x70d44d9f, 0x9a5290fd, 0x7500261c, 0x837f8274, 0x6c2d3495, + 0x86abe9f7, 0x69f95f16, 0x88d75572, 0x6785e393, 0x8d033ef1, + 0x62518810, 0xe7cbc850, 0x08997eb1, 0xe21fa3d3, 0x0d4d1532, + 0xec631f56, 0x0331a9b7, 0xe9b774d5, 0x06e5c234, 0xf09a665c, + 0x1fc8d0bd, 0xf54e0ddf, 0x1a1cbb3e, 0xfb32b15a, 0x146007bb, + 0xfee6dad9, 0x11b46c38, 0xc9689448, 0x263a22a9, 0xccbcffcb, + 0x23ee492a, 0xc2c0434e, 0x2d92f5af, 0xc71428cd, 0x28469e2c, + 0xde393a44, 0x316b8ca5, 0xdbed51c7, 0x34bfe726, 0xd591ed42, + 0x3ac35ba3, 0xd04586c1, 0x3f173020, 0xae6be681, 0x41395060, + 0xabbf8d02, 0x44ed3be3, 0xa5c33187, 0x4a918766, 0xa0175a04, + 0x4f45ece5, 0xb93a488d, 0x5668fe6c, 0xbcee230e, 0x53bc95ef, + 0xb2929f8b, 0x5dc0296a, 0xb746f408, 0x581442e9, 0x80c8ba99, + 0x6f9a0c78, 0x851cd11a, 0x6a4e67fb, 0x8b606d9f, 0x6432db7e, + 0x8eb4061c, 0x61e6b0fd, 0x97991495, 0x78cba274, 0x924d7f16, + 0x7d1fc9f7, 0x9c31c393, 0x73637572, 0x99e5a810, 0x76b71ef1, + 0xf32d5eb1, 0x1c7fe850, 0xf6f93532, 0x19ab83d3, 0xf88589b7, + 0x17d73f56, 0xfd51e234, 0x120354d5, 0xe47cf0bd, 0x0b2e465c, + 0xe1a89b3e, 0x0efa2ddf, 0xefd427bb, 0x0086915a, 0xea004c38, + 0x0552fad9, 0xdd8e02a9, 0x32dcb448, 0xd85a692a, 0x3708dfcb, + 0xd626d5af, 0x3974634e, 0xd3f2be2c, 0x3ca008cd, 0xcadfaca5, + 0x258d1a44, 0xcf0bc726, 0x205971c7, 0xc1777ba3, 0x2e25cd42, + 0xc4a31020, 0x2bf1a6c1, 0x14e696e1, 0xfbb42000, 0x1132fd62, + 0xfe604b83, 0x1f4e41e7, 0xf01cf706, 0x1a9a2a64, 0xf5c89c85, + 0x03b738ed, 0xece58e0c, 0x0663536e, 0xe931e58f, 0x081fefeb, + 0xe74d590a, 0x0dcb8468, 0xe2993289, 0x3a45caf9, 0xd5177c18, + 0x3f91a17a, 0xd0c3179b, 0x31ed1dff, 0xdebfab1e, 0x3439767c, + 0xdb6bc09d, 0x2d1464f5, 0xc246d214, 0x28c00f76, 0xc792b997, + 0x26bcb3f3, 0xc9ee0512, 0x2368d870, 0xcc3a6e91, 0x49a02ed1, + 0xa6f29830, 0x4c744552, 0xa326f3b3, 0x4208f9d7, 0xad5a4f36, + 0x47dc9254, 0xa88e24b5, 0x5ef180dd, 0xb1a3363c, 0x5b25eb5e, + 0xb4775dbf, 0x555957db, 0xba0be13a, 0x508d3c58, 0xbfdf8ab9, + 0x670372c9, 0x8851c428, 0x62d7194a, 0x8d85afab, 0x6caba5cf, + 0x83f9132e, 0x697fce4c, 0x862d78ad, 0x7052dcc5, 0x9f006a24, + 0x7586b746, 0x9ad401a7, 0x7bfa0bc3, 0x94a8bd22, 0x7e2e6040, + 0x917cd6a1}, + {0x00000000, 0x87a6cb43, 0xd43c90c7, 0x539a5b84, 0x730827cf, + 0xf4aeec8c, 0xa734b708, 0x20927c4b, 0xe6104f9e, 0x61b684dd, + 0x322cdf59, 0xb58a141a, 0x95186851, 0x12bea312, 0x4124f896, + 0xc68233d5, 0x1751997d, 0x90f7523e, 0xc36d09ba, 0x44cbc2f9, + 0x6459beb2, 0xe3ff75f1, 0xb0652e75, 0x37c3e536, 0xf141d6e3, + 0x76e71da0, 0x257d4624, 0xa2db8d67, 0x8249f12c, 0x05ef3a6f, + 0x567561eb, 0xd1d3aaa8, 0x2ea332fa, 0xa905f9b9, 0xfa9fa23d, + 0x7d39697e, 0x5dab1535, 0xda0dde76, 0x899785f2, 0x0e314eb1, + 0xc8b37d64, 0x4f15b627, 0x1c8feda3, 0x9b2926e0, 0xbbbb5aab, + 0x3c1d91e8, 0x6f87ca6c, 0xe821012f, 0x39f2ab87, 0xbe5460c4, + 0xedce3b40, 0x6a68f003, 0x4afa8c48, 0xcd5c470b, 0x9ec61c8f, + 0x1960d7cc, 0xdfe2e419, 0x58442f5a, 0x0bde74de, 0x8c78bf9d, + 0xaceac3d6, 0x2b4c0895, 0x78d65311, 0xff709852, 0x5d4665f4, + 0xdae0aeb7, 0x897af533, 0x0edc3e70, 0x2e4e423b, 0xa9e88978, + 0xfa72d2fc, 0x7dd419bf, 0xbb562a6a, 0x3cf0e129, 0x6f6abaad, + 0xe8cc71ee, 0xc85e0da5, 0x4ff8c6e6, 0x1c629d62, 0x9bc45621, + 0x4a17fc89, 0xcdb137ca, 0x9e2b6c4e, 0x198da70d, 0x391fdb46, + 0xbeb91005, 0xed234b81, 0x6a8580c2, 0xac07b317, 0x2ba17854, + 0x783b23d0, 0xff9de893, 0xdf0f94d8, 0x58a95f9b, 0x0b33041f, + 0x8c95cf5c, 0x73e5570e, 0xf4439c4d, 0xa7d9c7c9, 0x207f0c8a, + 0x00ed70c1, 0x874bbb82, 0xd4d1e006, 0x53772b45, 0x95f51890, + 0x1253d3d3, 0x41c98857, 0xc66f4314, 0xe6fd3f5f, 0x615bf41c, + 0x32c1af98, 0xb56764db, 0x64b4ce73, 0xe3120530, 0xb0885eb4, + 0x372e95f7, 0x17bce9bc, 0x901a22ff, 0xc380797b, 0x4426b238, + 0x82a481ed, 0x05024aae, 0x5698112a, 0xd13eda69, 0xf1aca622, + 0x760a6d61, 0x259036e5, 0xa236fda6, 0xba8ccbe8, 0x3d2a00ab, + 0x6eb05b2f, 0xe916906c, 0xc984ec27, 0x4e222764, 0x1db87ce0, + 0x9a1eb7a3, 0x5c9c8476, 0xdb3a4f35, 0x88a014b1, 0x0f06dff2, + 0x2f94a3b9, 0xa83268fa, 0xfba8337e, 0x7c0ef83d, 0xaddd5295, + 0x2a7b99d6, 0x79e1c252, 0xfe470911, 0xded5755a, 0x5973be19, + 0x0ae9e59d, 0x8d4f2ede, 0x4bcd1d0b, 0xcc6bd648, 0x9ff18dcc, + 0x1857468f, 0x38c53ac4, 0xbf63f187, 0xecf9aa03, 0x6b5f6140, + 0x942ff912, 0x13893251, 0x401369d5, 0xc7b5a296, 0xe727dedd, + 0x6081159e, 0x331b4e1a, 0xb4bd8559, 0x723fb68c, 0xf5997dcf, + 0xa603264b, 0x21a5ed08, 0x01379143, 0x86915a00, 0xd50b0184, + 0x52adcac7, 0x837e606f, 0x04d8ab2c, 0x5742f0a8, 0xd0e43beb, + 0xf07647a0, 0x77d08ce3, 0x244ad767, 0xa3ec1c24, 0x656e2ff1, + 0xe2c8e4b2, 0xb152bf36, 0x36f47475, 0x1666083e, 0x91c0c37d, + 0xc25a98f9, 0x45fc53ba, 0xe7caae1c, 0x606c655f, 0x33f63edb, + 0xb450f598, 0x94c289d3, 0x13644290, 0x40fe1914, 0xc758d257, + 0x01dae182, 0x867c2ac1, 0xd5e67145, 0x5240ba06, 0x72d2c64d, + 0xf5740d0e, 0xa6ee568a, 0x21489dc9, 0xf09b3761, 0x773dfc22, + 0x24a7a7a6, 0xa3016ce5, 0x839310ae, 0x0435dbed, 0x57af8069, + 0xd0094b2a, 0x168b78ff, 0x912db3bc, 0xc2b7e838, 0x4511237b, + 0x65835f30, 0xe2259473, 0xb1bfcff7, 0x361904b4, 0xc9699ce6, + 0x4ecf57a5, 0x1d550c21, 0x9af3c762, 0xba61bb29, 0x3dc7706a, + 0x6e5d2bee, 0xe9fbe0ad, 0x2f79d378, 0xa8df183b, 0xfb4543bf, + 0x7ce388fc, 0x5c71f4b7, 0xdbd73ff4, 0x884d6470, 0x0febaf33, + 0xde38059b, 0x599eced8, 0x0a04955c, 0x8da25e1f, 0xad302254, + 0x2a96e917, 0x790cb293, 0xfeaa79d0, 0x38284a05, 0xbf8e8146, + 0xec14dac2, 0x6bb21181, 0x4b206dca, 0xcc86a689, 0x9f1cfd0d, + 0x18ba364e}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x00000000, 0x43cba687, 0xc7903cd4, 0x845b9a53, 0xcf270873, + 0x8cecaef4, 0x08b734a7, 0x4b7c9220, 0x9e4f10e6, 0xdd84b661, + 0x59df2c32, 0x1a148ab5, 0x51681895, 0x12a3be12, 0x96f82441, + 0xd53382c6, 0x7d995117, 0x3e52f790, 0xba096dc3, 0xf9c2cb44, + 0xb2be5964, 0xf175ffe3, 0x752e65b0, 0x36e5c337, 0xe3d641f1, + 0xa01de776, 0x24467d25, 0x678ddba2, 0x2cf14982, 0x6f3aef05, + 0xeb617556, 0xa8aad3d1, 0xfa32a32e, 0xb9f905a9, 0x3da29ffa, + 0x7e69397d, 0x3515ab5d, 0x76de0dda, 0xf2859789, 0xb14e310e, + 0x647db3c8, 0x27b6154f, 0xa3ed8f1c, 0xe026299b, 0xab5abbbb, + 0xe8911d3c, 0x6cca876f, 0x2f0121e8, 0x87abf239, 0xc46054be, + 0x403bceed, 0x03f0686a, 0x488cfa4a, 0x0b475ccd, 0x8f1cc69e, + 0xccd76019, 0x19e4e2df, 0x5a2f4458, 0xde74de0b, 0x9dbf788c, + 0xd6c3eaac, 0x95084c2b, 0x1153d678, 0x529870ff, 0xf465465d, + 0xb7aee0da, 0x33f57a89, 0x703edc0e, 0x3b424e2e, 0x7889e8a9, + 0xfcd272fa, 0xbf19d47d, 0x6a2a56bb, 0x29e1f03c, 0xadba6a6f, + 0xee71cce8, 0xa50d5ec8, 0xe6c6f84f, 0x629d621c, 0x2156c49b, + 0x89fc174a, 0xca37b1cd, 0x4e6c2b9e, 0x0da78d19, 0x46db1f39, + 0x0510b9be, 0x814b23ed, 0xc280856a, 0x17b307ac, 0x5478a12b, + 0xd0233b78, 0x93e89dff, 0xd8940fdf, 0x9b5fa958, 0x1f04330b, + 0x5ccf958c, 0x0e57e573, 0x4d9c43f4, 0xc9c7d9a7, 0x8a0c7f20, + 0xc170ed00, 0x82bb4b87, 0x06e0d1d4, 0x452b7753, 0x9018f595, + 0xd3d35312, 0x5788c941, 0x14436fc6, 0x5f3ffde6, 0x1cf45b61, + 0x98afc132, 0xdb6467b5, 0x73ceb464, 0x300512e3, 0xb45e88b0, + 0xf7952e37, 0xbce9bc17, 0xff221a90, 0x7b7980c3, 0x38b22644, + 0xed81a482, 0xae4a0205, 0x2a119856, 0x69da3ed1, 0x22a6acf1, + 0x616d0a76, 0xe5369025, 0xa6fd36a2, 0xe8cb8cba, 0xab002a3d, + 0x2f5bb06e, 0x6c9016e9, 0x27ec84c9, 0x6427224e, 0xe07cb81d, + 0xa3b71e9a, 0x76849c5c, 0x354f3adb, 0xb114a088, 0xf2df060f, + 0xb9a3942f, 0xfa6832a8, 0x7e33a8fb, 0x3df80e7c, 0x9552ddad, + 0xd6997b2a, 0x52c2e179, 0x110947fe, 0x5a75d5de, 0x19be7359, + 0x9de5e90a, 0xde2e4f8d, 0x0b1dcd4b, 0x48d66bcc, 0xcc8df19f, + 0x8f465718, 0xc43ac538, 0x87f163bf, 0x03aaf9ec, 0x40615f6b, + 0x12f92f94, 0x51328913, 0xd5691340, 0x96a2b5c7, 0xddde27e7, + 0x9e158160, 0x1a4e1b33, 0x5985bdb4, 0x8cb63f72, 0xcf7d99f5, + 0x4b2603a6, 0x08eda521, 0x43913701, 0x005a9186, 0x84010bd5, + 0xc7caad52, 0x6f607e83, 0x2cabd804, 0xa8f04257, 0xeb3be4d0, + 0xa04776f0, 0xe38cd077, 0x67d74a24, 0x241ceca3, 0xf12f6e65, + 0xb2e4c8e2, 0x36bf52b1, 0x7574f436, 0x3e086616, 0x7dc3c091, + 0xf9985ac2, 0xba53fc45, 0x1caecae7, 0x5f656c60, 0xdb3ef633, + 0x98f550b4, 0xd389c294, 0x90426413, 0x1419fe40, 0x57d258c7, + 0x82e1da01, 0xc12a7c86, 0x4571e6d5, 0x06ba4052, 0x4dc6d272, + 0x0e0d74f5, 0x8a56eea6, 0xc99d4821, 0x61379bf0, 0x22fc3d77, + 0xa6a7a724, 0xe56c01a3, 0xae109383, 0xeddb3504, 0x6980af57, + 0x2a4b09d0, 0xff788b16, 0xbcb32d91, 0x38e8b7c2, 0x7b231145, + 0x305f8365, 0x739425e2, 0xf7cfbfb1, 0xb4041936, 0xe69c69c9, + 0xa557cf4e, 0x210c551d, 0x62c7f39a, 0x29bb61ba, 0x6a70c73d, + 0xee2b5d6e, 0xade0fbe9, 0x78d3792f, 0x3b18dfa8, 0xbf4345fb, + 0xfc88e37c, 0xb7f4715c, 0xf43fd7db, 0x70644d88, 0x33afeb0f, + 0x9b0538de, 0xd8ce9e59, 0x5c95040a, 0x1f5ea28d, 0x542230ad, + 0x17e9962a, 0x93b20c79, 0xd079aafe, 0x054a2838, 0x46818ebf, + 0xc2da14ec, 0x8111b26b, 0xca6d204b, 0x89a686cc, 0x0dfd1c9f, + 0x4e36ba18}, + {0x00000000, 0xe1b652ef, 0x836bd405, 0x62dd86ea, 0x06d7a80b, + 0xe761fae4, 0x85bc7c0e, 0x640a2ee1, 0x0cae5117, 0xed1803f8, + 0x8fc58512, 0x6e73d7fd, 0x0a79f91c, 0xebcfabf3, 0x89122d19, + 0x68a47ff6, 0x185ca32e, 0xf9eaf1c1, 0x9b37772b, 0x7a8125c4, + 0x1e8b0b25, 0xff3d59ca, 0x9de0df20, 0x7c568dcf, 0x14f2f239, + 0xf544a0d6, 0x9799263c, 0x762f74d3, 0x12255a32, 0xf39308dd, + 0x914e8e37, 0x70f8dcd8, 0x30b8465d, 0xd10e14b2, 0xb3d39258, + 0x5265c0b7, 0x366fee56, 0xd7d9bcb9, 0xb5043a53, 0x54b268bc, + 0x3c16174a, 0xdda045a5, 0xbf7dc34f, 0x5ecb91a0, 0x3ac1bf41, + 0xdb77edae, 0xb9aa6b44, 0x581c39ab, 0x28e4e573, 0xc952b79c, + 0xab8f3176, 0x4a396399, 0x2e334d78, 0xcf851f97, 0xad58997d, + 0x4ceecb92, 0x244ab464, 0xc5fce68b, 0xa7216061, 0x4697328e, + 0x229d1c6f, 0xc32b4e80, 0xa1f6c86a, 0x40409a85, 0x60708dba, + 0x81c6df55, 0xe31b59bf, 0x02ad0b50, 0x66a725b1, 0x8711775e, + 0xe5ccf1b4, 0x047aa35b, 0x6cdedcad, 0x8d688e42, 0xefb508a8, + 0x0e035a47, 0x6a0974a6, 0x8bbf2649, 0xe962a0a3, 0x08d4f24c, + 0x782c2e94, 0x999a7c7b, 0xfb47fa91, 0x1af1a87e, 0x7efb869f, + 0x9f4dd470, 0xfd90529a, 0x1c260075, 0x74827f83, 0x95342d6c, + 0xf7e9ab86, 0x165ff969, 0x7255d788, 0x93e38567, 0xf13e038d, + 0x10885162, 0x50c8cbe7, 0xb17e9908, 0xd3a31fe2, 0x32154d0d, + 0x561f63ec, 0xb7a93103, 0xd574b7e9, 0x34c2e506, 0x5c669af0, + 0xbdd0c81f, 0xdf0d4ef5, 0x3ebb1c1a, 0x5ab132fb, 0xbb076014, + 0xd9dae6fe, 0x386cb411, 0x489468c9, 0xa9223a26, 0xcbffbccc, + 0x2a49ee23, 0x4e43c0c2, 0xaff5922d, 0xcd2814c7, 0x2c9e4628, + 0x443a39de, 0xa58c6b31, 0xc751eddb, 0x26e7bf34, 0x42ed91d5, + 0xa35bc33a, 0xc18645d0, 0x2030173f, 0x81e66bae, 0x60503941, + 0x028dbfab, 0xe33bed44, 0x8731c3a5, 0x6687914a, 0x045a17a0, + 0xe5ec454f, 0x8d483ab9, 0x6cfe6856, 0x0e23eebc, 0xef95bc53, + 0x8b9f92b2, 0x6a29c05d, 0x08f446b7, 0xe9421458, 0x99bac880, + 0x780c9a6f, 0x1ad11c85, 0xfb674e6a, 0x9f6d608b, 0x7edb3264, + 0x1c06b48e, 0xfdb0e661, 0x95149997, 0x74a2cb78, 0x167f4d92, + 0xf7c91f7d, 0x93c3319c, 0x72756373, 0x10a8e599, 0xf11eb776, + 0xb15e2df3, 0x50e87f1c, 0x3235f9f6, 0xd383ab19, 0xb78985f8, + 0x563fd717, 0x34e251fd, 0xd5540312, 0xbdf07ce4, 0x5c462e0b, + 0x3e9ba8e1, 0xdf2dfa0e, 0xbb27d4ef, 0x5a918600, 0x384c00ea, + 0xd9fa5205, 0xa9028edd, 0x48b4dc32, 0x2a695ad8, 0xcbdf0837, + 0xafd526d6, 0x4e637439, 0x2cbef2d3, 0xcd08a03c, 0xa5acdfca, + 0x441a8d25, 0x26c70bcf, 0xc7715920, 0xa37b77c1, 0x42cd252e, + 0x2010a3c4, 0xc1a6f12b, 0xe196e614, 0x0020b4fb, 0x62fd3211, + 0x834b60fe, 0xe7414e1f, 0x06f71cf0, 0x642a9a1a, 0x859cc8f5, + 0xed38b703, 0x0c8ee5ec, 0x6e536306, 0x8fe531e9, 0xebef1f08, + 0x0a594de7, 0x6884cb0d, 0x893299e2, 0xf9ca453a, 0x187c17d5, + 0x7aa1913f, 0x9b17c3d0, 0xff1ded31, 0x1eabbfde, 0x7c763934, + 0x9dc06bdb, 0xf564142d, 0x14d246c2, 0x760fc028, 0x97b992c7, + 0xf3b3bc26, 0x1205eec9, 0x70d86823, 0x916e3acc, 0xd12ea049, + 0x3098f2a6, 0x5245744c, 0xb3f326a3, 0xd7f90842, 0x364f5aad, + 0x5492dc47, 0xb5248ea8, 0xdd80f15e, 0x3c36a3b1, 0x5eeb255b, + 0xbf5d77b4, 0xdb575955, 0x3ae10bba, 0x583c8d50, 0xb98adfbf, + 0xc9720367, 0x28c45188, 0x4a19d762, 0xabaf858d, 0xcfa5ab6c, + 0x2e13f983, 0x4cce7f69, 0xad782d86, 0xc5dc5270, 0x246a009f, + 0x46b78675, 0xa701d49a, 0xc30bfa7b, 0x22bda894, 0x40602e7e, + 0xa1d67c91}, + {0x00000000, 0x5880e2d7, 0xf106b474, 0xa98656a3, 0xe20d68e9, + 0xba8d8a3e, 0x130bdc9d, 0x4b8b3e4a, 0x851da109, 0xdd9d43de, + 0x741b157d, 0x2c9bf7aa, 0x6710c9e0, 0x3f902b37, 0x96167d94, + 0xce969f43, 0x0a3b4213, 0x52bba0c4, 0xfb3df667, 0xa3bd14b0, + 0xe8362afa, 0xb0b6c82d, 0x19309e8e, 0x41b07c59, 0x8f26e31a, + 0xd7a601cd, 0x7e20576e, 0x26a0b5b9, 0x6d2b8bf3, 0x35ab6924, + 0x9c2d3f87, 0xc4addd50, 0x14768426, 0x4cf666f1, 0xe5703052, + 0xbdf0d285, 0xf67beccf, 0xaefb0e18, 0x077d58bb, 0x5ffdba6c, + 0x916b252f, 0xc9ebc7f8, 0x606d915b, 0x38ed738c, 0x73664dc6, + 0x2be6af11, 0x8260f9b2, 0xdae01b65, 0x1e4dc635, 0x46cd24e2, + 0xef4b7241, 0xb7cb9096, 0xfc40aedc, 0xa4c04c0b, 0x0d461aa8, + 0x55c6f87f, 0x9b50673c, 0xc3d085eb, 0x6a56d348, 0x32d6319f, + 0x795d0fd5, 0x21dded02, 0x885bbba1, 0xd0db5976, 0x28ec084d, + 0x706cea9a, 0xd9eabc39, 0x816a5eee, 0xcae160a4, 0x92618273, + 0x3be7d4d0, 0x63673607, 0xadf1a944, 0xf5714b93, 0x5cf71d30, + 0x0477ffe7, 0x4ffcc1ad, 0x177c237a, 0xbefa75d9, 0xe67a970e, + 0x22d74a5e, 0x7a57a889, 0xd3d1fe2a, 0x8b511cfd, 0xc0da22b7, + 0x985ac060, 0x31dc96c3, 0x695c7414, 0xa7caeb57, 0xff4a0980, + 0x56cc5f23, 0x0e4cbdf4, 0x45c783be, 0x1d476169, 0xb4c137ca, + 0xec41d51d, 0x3c9a8c6b, 0x641a6ebc, 0xcd9c381f, 0x951cdac8, + 0xde97e482, 0x86170655, 0x2f9150f6, 0x7711b221, 0xb9872d62, + 0xe107cfb5, 0x48819916, 0x10017bc1, 0x5b8a458b, 0x030aa75c, + 0xaa8cf1ff, 0xf20c1328, 0x36a1ce78, 0x6e212caf, 0xc7a77a0c, + 0x9f2798db, 0xd4aca691, 0x8c2c4446, 0x25aa12e5, 0x7d2af032, + 0xb3bc6f71, 0xeb3c8da6, 0x42badb05, 0x1a3a39d2, 0x51b10798, + 0x0931e54f, 0xa0b7b3ec, 0xf837513b, 0x50d8119a, 0x0858f34d, + 0xa1dea5ee, 0xf95e4739, 0xb2d57973, 0xea559ba4, 0x43d3cd07, + 0x1b532fd0, 0xd5c5b093, 0x8d455244, 0x24c304e7, 0x7c43e630, + 0x37c8d87a, 0x6f483aad, 0xc6ce6c0e, 0x9e4e8ed9, 0x5ae35389, + 0x0263b15e, 0xabe5e7fd, 0xf365052a, 0xb8ee3b60, 0xe06ed9b7, + 0x49e88f14, 0x11686dc3, 0xdffef280, 0x877e1057, 0x2ef846f4, + 0x7678a423, 0x3df39a69, 0x657378be, 0xccf52e1d, 0x9475ccca, + 0x44ae95bc, 0x1c2e776b, 0xb5a821c8, 0xed28c31f, 0xa6a3fd55, + 0xfe231f82, 0x57a54921, 0x0f25abf6, 0xc1b334b5, 0x9933d662, + 0x30b580c1, 0x68356216, 0x23be5c5c, 0x7b3ebe8b, 0xd2b8e828, + 0x8a380aff, 0x4e95d7af, 0x16153578, 0xbf9363db, 0xe713810c, + 0xac98bf46, 0xf4185d91, 0x5d9e0b32, 0x051ee9e5, 0xcb8876a6, + 0x93089471, 0x3a8ec2d2, 0x620e2005, 0x29851e4f, 0x7105fc98, + 0xd883aa3b, 0x800348ec, 0x783419d7, 0x20b4fb00, 0x8932ada3, + 0xd1b24f74, 0x9a39713e, 0xc2b993e9, 0x6b3fc54a, 0x33bf279d, + 0xfd29b8de, 0xa5a95a09, 0x0c2f0caa, 0x54afee7d, 0x1f24d037, + 0x47a432e0, 0xee226443, 0xb6a28694, 0x720f5bc4, 0x2a8fb913, + 0x8309efb0, 0xdb890d67, 0x9002332d, 0xc882d1fa, 0x61048759, + 0x3984658e, 0xf712facd, 0xaf92181a, 0x06144eb9, 0x5e94ac6e, + 0x151f9224, 0x4d9f70f3, 0xe4192650, 0xbc99c487, 0x6c429df1, + 0x34c27f26, 0x9d442985, 0xc5c4cb52, 0x8e4ff518, 0xd6cf17cf, + 0x7f49416c, 0x27c9a3bb, 0xe95f3cf8, 0xb1dfde2f, 0x1859888c, + 0x40d96a5b, 0x0b525411, 0x53d2b6c6, 0xfa54e065, 0xa2d402b2, + 0x6679dfe2, 0x3ef93d35, 0x977f6b96, 0xcfff8941, 0x8474b70b, + 0xdcf455dc, 0x7572037f, 0x2df2e1a8, 0xe3647eeb, 0xbbe49c3c, + 0x1262ca9f, 0x4ae22848, 0x01691602, 0x59e9f4d5, 0xf06fa276, + 0xa8ef40a1}, + {0x00000000, 0x463b6765, 0x8c76ceca, 0xca4da9af, 0x59ebed4e, + 0x1fd08a2b, 0xd59d2384, 0x93a644e1, 0xb2d6db9d, 0xf4edbcf8, + 0x3ea01557, 0x789b7232, 0xeb3d36d3, 0xad0651b6, 0x674bf819, + 0x21709f7c, 0x25abc6e0, 0x6390a185, 0xa9dd082a, 0xefe66f4f, + 0x7c402bae, 0x3a7b4ccb, 0xf036e564, 0xb60d8201, 0x977d1d7d, + 0xd1467a18, 0x1b0bd3b7, 0x5d30b4d2, 0xce96f033, 0x88ad9756, + 0x42e03ef9, 0x04db599c, 0x0b50fc1a, 0x4d6b9b7f, 0x872632d0, + 0xc11d55b5, 0x52bb1154, 0x14807631, 0xdecddf9e, 0x98f6b8fb, + 0xb9862787, 0xffbd40e2, 0x35f0e94d, 0x73cb8e28, 0xe06dcac9, + 0xa656adac, 0x6c1b0403, 0x2a206366, 0x2efb3afa, 0x68c05d9f, + 0xa28df430, 0xe4b69355, 0x7710d7b4, 0x312bb0d1, 0xfb66197e, + 0xbd5d7e1b, 0x9c2de167, 0xda168602, 0x105b2fad, 0x566048c8, + 0xc5c60c29, 0x83fd6b4c, 0x49b0c2e3, 0x0f8ba586, 0x16a0f835, + 0x509b9f50, 0x9ad636ff, 0xdced519a, 0x4f4b157b, 0x0970721e, + 0xc33ddbb1, 0x8506bcd4, 0xa47623a8, 0xe24d44cd, 0x2800ed62, + 0x6e3b8a07, 0xfd9dcee6, 0xbba6a983, 0x71eb002c, 0x37d06749, + 0x330b3ed5, 0x753059b0, 0xbf7df01f, 0xf946977a, 0x6ae0d39b, + 0x2cdbb4fe, 0xe6961d51, 0xa0ad7a34, 0x81dde548, 0xc7e6822d, + 0x0dab2b82, 0x4b904ce7, 0xd8360806, 0x9e0d6f63, 0x5440c6cc, + 0x127ba1a9, 0x1df0042f, 0x5bcb634a, 0x9186cae5, 0xd7bdad80, + 0x441be961, 0x02208e04, 0xc86d27ab, 0x8e5640ce, 0xaf26dfb2, + 0xe91db8d7, 0x23501178, 0x656b761d, 0xf6cd32fc, 0xb0f65599, + 0x7abbfc36, 0x3c809b53, 0x385bc2cf, 0x7e60a5aa, 0xb42d0c05, + 0xf2166b60, 0x61b02f81, 0x278b48e4, 0xedc6e14b, 0xabfd862e, + 0x8a8d1952, 0xccb67e37, 0x06fbd798, 0x40c0b0fd, 0xd366f41c, + 0x955d9379, 0x5f103ad6, 0x192b5db3, 0x2c40f16b, 0x6a7b960e, + 0xa0363fa1, 0xe60d58c4, 0x75ab1c25, 0x33907b40, 0xf9ddd2ef, + 0xbfe6b58a, 0x9e962af6, 0xd8ad4d93, 0x12e0e43c, 0x54db8359, + 0xc77dc7b8, 0x8146a0dd, 0x4b0b0972, 0x0d306e17, 0x09eb378b, + 0x4fd050ee, 0x859df941, 0xc3a69e24, 0x5000dac5, 0x163bbda0, + 0xdc76140f, 0x9a4d736a, 0xbb3dec16, 0xfd068b73, 0x374b22dc, + 0x717045b9, 0xe2d60158, 0xa4ed663d, 0x6ea0cf92, 0x289ba8f7, + 0x27100d71, 0x612b6a14, 0xab66c3bb, 0xed5da4de, 0x7efbe03f, + 0x38c0875a, 0xf28d2ef5, 0xb4b64990, 0x95c6d6ec, 0xd3fdb189, + 0x19b01826, 0x5f8b7f43, 0xcc2d3ba2, 0x8a165cc7, 0x405bf568, + 0x0660920d, 0x02bbcb91, 0x4480acf4, 0x8ecd055b, 0xc8f6623e, + 0x5b5026df, 0x1d6b41ba, 0xd726e815, 0x911d8f70, 0xb06d100c, + 0xf6567769, 0x3c1bdec6, 0x7a20b9a3, 0xe986fd42, 0xafbd9a27, + 0x65f03388, 0x23cb54ed, 0x3ae0095e, 0x7cdb6e3b, 0xb696c794, + 0xf0ada0f1, 0x630be410, 0x25308375, 0xef7d2ada, 0xa9464dbf, + 0x8836d2c3, 0xce0db5a6, 0x04401c09, 0x427b7b6c, 0xd1dd3f8d, + 0x97e658e8, 0x5dabf147, 0x1b909622, 0x1f4bcfbe, 0x5970a8db, + 0x933d0174, 0xd5066611, 0x46a022f0, 0x009b4595, 0xcad6ec3a, + 0x8ced8b5f, 0xad9d1423, 0xeba67346, 0x21ebdae9, 0x67d0bd8c, + 0xf476f96d, 0xb24d9e08, 0x780037a7, 0x3e3b50c2, 0x31b0f544, + 0x778b9221, 0xbdc63b8e, 0xfbfd5ceb, 0x685b180a, 0x2e607f6f, + 0xe42dd6c0, 0xa216b1a5, 0x83662ed9, 0xc55d49bc, 0x0f10e013, + 0x492b8776, 0xda8dc397, 0x9cb6a4f2, 0x56fb0d5d, 0x10c06a38, + 0x141b33a4, 0x522054c1, 0x986dfd6e, 0xde569a0b, 0x4df0deea, + 0x0bcbb98f, 0xc1861020, 0x87bd7745, 0xa6cde839, 0xe0f68f5c, + 0x2abb26f3, 0x6c804196, 0xff260577, 0xb91d6212, 0x7350cbbd, + 0x356bacd8}}; + +#endif + +#endif + +#if N == 6 + +#if W == 8 + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0x3db1ecdc, 0x7b63d9b8, 0x46d23564, 0xf6c7b370, + 0xcb765fac, 0x8da46ac8, 0xb0158614, 0x36fe60a1, 0x0b4f8c7d, + 0x4d9db919, 0x702c55c5, 0xc039d3d1, 0xfd883f0d, 0xbb5a0a69, + 0x86ebe6b5, 0x6dfcc142, 0x504d2d9e, 0x169f18fa, 0x2b2ef426, + 0x9b3b7232, 0xa68a9eee, 0xe058ab8a, 0xdde94756, 0x5b02a1e3, + 0x66b34d3f, 0x2061785b, 0x1dd09487, 0xadc51293, 0x9074fe4f, + 0xd6a6cb2b, 0xeb1727f7, 0xdbf98284, 0xe6486e58, 0xa09a5b3c, + 0x9d2bb7e0, 0x2d3e31f4, 0x108fdd28, 0x565de84c, 0x6bec0490, + 0xed07e225, 0xd0b60ef9, 0x96643b9d, 0xabd5d741, 0x1bc05155, + 0x2671bd89, 0x60a388ed, 0x5d126431, 0xb60543c6, 0x8bb4af1a, + 0xcd669a7e, 0xf0d776a2, 0x40c2f0b6, 0x7d731c6a, 0x3ba1290e, + 0x0610c5d2, 0x80fb2367, 0xbd4acfbb, 0xfb98fadf, 0xc6291603, + 0x763c9017, 0x4b8d7ccb, 0x0d5f49af, 0x30eea573, 0x6c820349, + 0x5133ef95, 0x17e1daf1, 0x2a50362d, 0x9a45b039, 0xa7f45ce5, + 0xe1266981, 0xdc97855d, 0x5a7c63e8, 0x67cd8f34, 0x211fba50, + 0x1cae568c, 0xacbbd098, 0x910a3c44, 0xd7d80920, 0xea69e5fc, + 0x017ec20b, 0x3ccf2ed7, 0x7a1d1bb3, 0x47acf76f, 0xf7b9717b, + 0xca089da7, 0x8cdaa8c3, 0xb16b441f, 0x3780a2aa, 0x0a314e76, + 0x4ce37b12, 0x715297ce, 0xc14711da, 0xfcf6fd06, 0xba24c862, + 0x879524be, 0xb77b81cd, 0x8aca6d11, 0xcc185875, 0xf1a9b4a9, + 0x41bc32bd, 0x7c0dde61, 0x3adfeb05, 0x076e07d9, 0x8185e16c, + 0xbc340db0, 0xfae638d4, 0xc757d408, 0x7742521c, 0x4af3bec0, + 0x0c218ba4, 0x31906778, 0xda87408f, 0xe736ac53, 0xa1e49937, + 0x9c5575eb, 0x2c40f3ff, 0x11f11f23, 0x57232a47, 0x6a92c69b, + 0xec79202e, 0xd1c8ccf2, 0x971af996, 0xaaab154a, 0x1abe935e, + 0x270f7f82, 0x61dd4ae6, 0x5c6ca63a, 0xd9040692, 0xe4b5ea4e, + 0xa267df2a, 0x9fd633f6, 0x2fc3b5e2, 0x1272593e, 0x54a06c5a, + 0x69118086, 0xeffa6633, 0xd24b8aef, 0x9499bf8b, 0xa9285357, + 0x193dd543, 0x248c399f, 0x625e0cfb, 0x5fefe027, 0xb4f8c7d0, + 0x89492b0c, 0xcf9b1e68, 0xf22af2b4, 0x423f74a0, 0x7f8e987c, + 0x395cad18, 0x04ed41c4, 0x8206a771, 0xbfb74bad, 0xf9657ec9, + 0xc4d49215, 0x74c11401, 0x4970f8dd, 0x0fa2cdb9, 0x32132165, + 0x02fd8416, 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0xede02156, 0xd5dbaa25, 0x74e22ecb, 0xa5acbcc3, 0x0495382d, + 0x3caeb35e, 0x9d9737b0, 0x4542910f, 0xe47b15e1, 0xdc409e92, + 0x7d791a7c, 0xac378874, 0x0d0e0c9a, 0x353587e9, 0x940c0307, + 0x5fefccd6, 0xfed64838, 0xc6edc34b, 0x67d447a5, 0xb69ad5ad, + 0x17a35143, 0x2f98da30, 0x8ea15ede, 0x5674f861, 0xf74d7c8f, + 0xcf76f7fc, 0x6e4f7312, 0xbf01e11a, 0x1e3865f4, 0x2603ee87, + 0x873a6a69, 0x6ab57764, 0xcb8cf38a, 0xf3b778f9, 0x528efc17, + 0x83c06e1f, 0x22f9eaf1, 0x1ac26182, 0xbbfbe56c, 0x632e43d3, + 0xc217c73d, 0xfa2c4c4e, 0x5b15c8a0, 0x8a5b5aa8, 0x2b62de46, + 0x13595535, 0xb260d1db, 0x79831e0a, 0xd8ba9ae4, 0xe0811197, + 0x41b89579, 0x90f60771, 0x31cf839f, 0x09f408ec, 0xa8cd8c02, + 0x70182abd, 0xd121ae53, 0xe91a2520, 0x4823a1ce, 0x996d33c6, + 0x3854b728, 0x006f3c5b, 0xa156b8b5, 0x99b34b70, 0x388acf9e, + 0x00b144ed, 0xa188c003, 0x70c6520b, 0xd1ffd6e5, 0xe9c45d96, + 0x48fdd978, 0x90287fc7, 0x3111fb29, 0x092a705a, 0xa813f4b4, + 0x795d66bc, 0xd864e252, 0xe05f6921, 0x4166edcf, 0x8a85221e, + 0x2bbca6f0, 0x13872d83, 0xb2bea96d, 0x63f03b65, 0xc2c9bf8b, + 0xfaf234f8, 0x5bcbb016, 0x831e16a9, 0x22279247, 0x1a1c1934, + 0xbb259dda, 0x6a6b0fd2, 0xcb528b3c, 0xf369004f, 0x525084a1, + 0xbfdf99ac, 0x1ee61d42, 0x26dd9631, 0x87e412df, 0x56aa80d7, + 0xf7930439, 0xcfa88f4a, 0x6e910ba4, 0xb644ad1b, 0x177d29f5, + 0x2f46a286, 0x8e7f2668, 0x5f31b460, 0xfe08308e, 0xc633bbfd, + 0x670a3f13, 0xace9f0c2, 0x0dd0742c, 0x35ebff5f, 0x94d27bb1, + 0x459ce9b9, 0xe4a56d57, 0xdc9ee624, 0x7da762ca, 0xa572c475, + 0x044b409b, 0x3c70cbe8, 0x9d494f06, 0x4c07dd0e, 0xed3e59e0, + 0xd505d293, 0x743c567d, 0xd56aeec8, 0x74536a26, 0x4c68e155, + 0xed5165bb, 0x3c1ff7b3, 0x9d26735d, 0xa51df82e, 0x04247cc0, + 0xdcf1da7f, 0x7dc85e91, 0x45f3d5e2, 0xe4ca510c, 0x3584c304, + 0x94bd47ea, 0xac86cc99, 0x0dbf4877, 0xc65c87a6, 0x67650348, + 0x5f5e883b, 0xfe670cd5, 0x2f299edd, 0x8e101a33, 0xb62b9140, + 0x171215ae, 0xcfc7b311, 0x6efe37ff, 0x56c5bc8c, 0xf7fc3862, + 0x26b2aa6a, 0x878b2e84, 0xbfb0a5f7, 0x1e892119, 0xf3063c14, + 0x523fb8fa, 0x6a043389, 0xcb3db767, 0x1a73256f, 0xbb4aa181, + 0x83712af2, 0x2248ae1c, 0xfa9d08a3, 0x5ba48c4d, 0x639f073e, + 0xc2a683d0, 0x13e811d8, 0xb2d19536, 0x8aea1e45, 0x2bd39aab, + 0xe030557a, 0x4109d194, 0x79325ae7, 0xd80bde09, 0x09454c01, + 0xa87cc8ef, 0x9047439c, 0x317ec772, 0xe9ab61cd, 0x4892e523, + 0x70a96e50, 0xd190eabe, 0x00de78b6, 0xa1e7fc58, 0x99dc772b, + 0x38e5f3c5}, + {0x00000000, 0xe81790a1, 0x0b5e2703, 0xe349b7a2, 0x16bc4e06, + 0xfeabdea7, 0x1de26905, 0xf5f5f9a4, 0x2d789c0c, 0xc56f0cad, + 0x2626bb0f, 0xce312bae, 0x3bc4d20a, 0xd3d342ab, 0x309af509, + 0xd88d65a8, 0x5af13818, 0xb2e6a8b9, 0x51af1f1b, 0xb9b88fba, + 0x4c4d761e, 0xa45ae6bf, 0x4713511d, 0xaf04c1bc, 0x7789a414, + 0x9f9e34b5, 0x7cd78317, 0x94c013b6, 0x6135ea12, 0x89227ab3, + 0x6a6bcd11, 0x827c5db0, 0xb5e27030, 0x5df5e091, 0xbebc5733, + 0x56abc792, 0xa35e3e36, 0x4b49ae97, 0xa8001935, 0x40178994, + 0x989aec3c, 0x708d7c9d, 0x93c4cb3f, 0x7bd35b9e, 0x8e26a23a, + 0x6631329b, 0x85788539, 0x6d6f1598, 0xef134828, 0x0704d889, + 0xe44d6f2b, 0x0c5aff8a, 0xf9af062e, 0x11b8968f, 0xf2f1212d, + 0x1ae6b18c, 0xc26bd424, 0x2a7c4485, 0xc935f327, 0x21226386, + 0xd4d79a22, 0x3cc00a83, 0xdf89bd21, 0x379e2d80, 0xb0b5e621, + 0x58a27680, 0xbbebc122, 0x53fc5183, 0xa609a827, 0x4e1e3886, + 0xad578f24, 0x45401f85, 0x9dcd7a2d, 0x75daea8c, 0x96935d2e, + 0x7e84cd8f, 0x8b71342b, 0x6366a48a, 0x802f1328, 0x68388389, + 0xea44de39, 0x02534e98, 0xe11af93a, 0x090d699b, 0xfcf8903f, + 0x14ef009e, 0xf7a6b73c, 0x1fb1279d, 0xc73c4235, 0x2f2bd294, + 0xcc626536, 0x2475f597, 0xd1800c33, 0x39979c92, 0xdade2b30, + 0x32c9bb91, 0x05579611, 0xed4006b0, 0x0e09b112, 0xe61e21b3, + 0x13ebd817, 0xfbfc48b6, 0x18b5ff14, 0xf0a26fb5, 0x282f0a1d, + 0xc0389abc, 0x23712d1e, 0xcb66bdbf, 0x3e93441b, 0xd684d4ba, + 0x35cd6318, 0xdddaf3b9, 0x5fa6ae09, 0xb7b13ea8, 0x54f8890a, + 0xbcef19ab, 0x491ae00f, 0xa10d70ae, 0x4244c70c, 0xaa5357ad, + 0x72de3205, 0x9ac9a2a4, 0x79801506, 0x919785a7, 0x64627c03, + 0x8c75eca2, 0x6f3c5b00, 0x872bcba1, 0xba1aca03, 0x520d5aa2, + 0xb144ed00, 0x59537da1, 0xaca68405, 0x44b114a4, 0xa7f8a306, + 0x4fef33a7, 0x9762560f, 0x7f75c6ae, 0x9c3c710c, 0x742be1ad, + 0x81de1809, 0x69c988a8, 0x8a803f0a, 0x6297afab, 0xe0ebf21b, + 0x08fc62ba, 0xebb5d518, 0x03a245b9, 0xf657bc1d, 0x1e402cbc, + 0xfd099b1e, 0x151e0bbf, 0xcd936e17, 0x2584feb6, 0xc6cd4914, + 0x2edad9b5, 0xdb2f2011, 0x3338b0b0, 0xd0710712, 0x386697b3, + 0x0ff8ba33, 0xe7ef2a92, 0x04a69d30, 0xecb10d91, 0x1944f435, + 0xf1536494, 0x121ad336, 0xfa0d4397, 0x2280263f, 0xca97b69e, + 0x29de013c, 0xc1c9919d, 0x343c6839, 0xdc2bf898, 0x3f624f3a, + 0xd775df9b, 0x5509822b, 0xbd1e128a, 0x5e57a528, 0xb6403589, + 0x43b5cc2d, 0xaba25c8c, 0x48ebeb2e, 0xa0fc7b8f, 0x78711e27, + 0x90668e86, 0x732f3924, 0x9b38a985, 0x6ecd5021, 0x86dac080, + 0x65937722, 0x8d84e783, 0x0aaf2c22, 0xe2b8bc83, 0x01f10b21, + 0xe9e69b80, 0x1c136224, 0xf404f285, 0x174d4527, 0xff5ad586, + 0x27d7b02e, 0xcfc0208f, 0x2c89972d, 0xc49e078c, 0x316bfe28, + 0xd97c6e89, 0x3a35d92b, 0xd222498a, 0x505e143a, 0xb849849b, + 0x5b003339, 0xb317a398, 0x46e25a3c, 0xaef5ca9d, 0x4dbc7d3f, + 0xa5abed9e, 0x7d268836, 0x95311897, 0x7678af35, 0x9e6f3f94, + 0x6b9ac630, 0x838d5691, 0x60c4e133, 0x88d37192, 0xbf4d5c12, + 0x575accb3, 0xb4137b11, 0x5c04ebb0, 0xa9f11214, 0x41e682b5, + 0xa2af3517, 0x4ab8a5b6, 0x9235c01e, 0x7a2250bf, 0x996be71d, + 0x717c77bc, 0x84898e18, 0x6c9e1eb9, 0x8fd7a91b, 0x67c039ba, + 0xe5bc640a, 0x0dabf4ab, 0xeee24309, 0x06f5d3a8, 0xf3002a0c, + 0x1b17baad, 0xf85e0d0f, 0x10499dae, 0xc8c4f806, 0x20d368a7, + 0xc39adf05, 0x2b8d4fa4, 0xde78b600, 0x366f26a1, 0xd5269103, + 0x3d3101a2}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x0000000000000000, 0xa19017e800000000, 0x03275e0b00000000, + 0xa2b749e300000000, 0x064ebc1600000000, 0xa7deabfe00000000, + 0x0569e21d00000000, 0xa4f9f5f500000000, 0x0c9c782d00000000, + 0xad0c6fc500000000, 0x0fbb262600000000, 0xae2b31ce00000000, + 0x0ad2c43b00000000, 0xab42d3d300000000, 0x09f59a3000000000, + 0xa8658dd800000000, 0x1838f15a00000000, 0xb9a8e6b200000000, + 0x1b1faf5100000000, 0xba8fb8b900000000, 0x1e764d4c00000000, + 0xbfe65aa400000000, 0x1d51134700000000, 0xbcc104af00000000, + 0x14a4897700000000, 0xb5349e9f00000000, 0x1783d77c00000000, + 0xb613c09400000000, 0x12ea356100000000, 0xb37a228900000000, + 0x11cd6b6a00000000, 0xb05d7c8200000000, 0x3070e2b500000000, + 0x91e0f55d00000000, 0x3357bcbe00000000, 0x92c7ab5600000000, + 0x363e5ea300000000, 0x97ae494b00000000, 0x351900a800000000, + 0x9489174000000000, 0x3cec9a9800000000, 0x9d7c8d7000000000, + 0x3fcbc49300000000, 0x9e5bd37b00000000, 0x3aa2268e00000000, + 0x9b32316600000000, 0x3985788500000000, 0x98156f6d00000000, + 0x284813ef00000000, 0x89d8040700000000, 0x2b6f4de400000000, + 0x8aff5a0c00000000, 0x2e06aff900000000, 0x8f96b81100000000, + 0x2d21f1f200000000, 0x8cb1e61a00000000, 0x24d46bc200000000, + 0x85447c2a00000000, 0x27f335c900000000, 0x8663222100000000, + 0x229ad7d400000000, 0x830ac03c00000000, 0x21bd89df00000000, + 0x802d9e3700000000, 0x21e6b5b000000000, 0x8076a25800000000, + 0x22c1ebbb00000000, 0x8351fc5300000000, 0x27a809a600000000, + 0x86381e4e00000000, 0x248f57ad00000000, 0x851f404500000000, + 0x2d7acd9d00000000, 0x8ceada7500000000, 0x2e5d939600000000, + 0x8fcd847e00000000, 0x2b34718b00000000, 0x8aa4666300000000, + 0x28132f8000000000, 0x8983386800000000, 0x39de44ea00000000, + 0x984e530200000000, 0x3af91ae100000000, 0x9b690d0900000000, + 0x3f90f8fc00000000, 0x9e00ef1400000000, 0x3cb7a6f700000000, + 0x9d27b11f00000000, 0x35423cc700000000, 0x94d22b2f00000000, + 0x366562cc00000000, 0x97f5752400000000, 0x330c80d100000000, + 0x929c973900000000, 0x302bdeda00000000, 0x91bbc93200000000, + 0x1196570500000000, 0xb00640ed00000000, 0x12b1090e00000000, + 0xb3211ee600000000, 0x17d8eb1300000000, 0xb648fcfb00000000, + 0x14ffb51800000000, 0xb56fa2f000000000, 0x1d0a2f2800000000, + 0xbc9a38c000000000, 0x1e2d712300000000, 0xbfbd66cb00000000, + 0x1b44933e00000000, 0xbad484d600000000, 0x1863cd3500000000, + 0xb9f3dadd00000000, 0x09aea65f00000000, 0xa83eb1b700000000, + 0x0a89f85400000000, 0xab19efbc00000000, 0x0fe01a4900000000, + 0xae700da100000000, 0x0cc7444200000000, 0xad5753aa00000000, + 0x0532de7200000000, 0xa4a2c99a00000000, 0x0615807900000000, + 0xa785979100000000, 0x037c626400000000, 0xa2ec758c00000000, + 0x005b3c6f00000000, 0xa1cb2b8700000000, 0x03ca1aba00000000, + 0xa25a0d5200000000, 0x00ed44b100000000, 0xa17d535900000000, + 0x0584a6ac00000000, 0xa414b14400000000, 0x06a3f8a700000000, + 0xa733ef4f00000000, 0x0f56629700000000, 0xaec6757f00000000, + 0x0c713c9c00000000, 0xade12b7400000000, 0x0918de8100000000, + 0xa888c96900000000, 0x0a3f808a00000000, 0xabaf976200000000, + 0x1bf2ebe000000000, 0xba62fc0800000000, 0x18d5b5eb00000000, + 0xb945a20300000000, 0x1dbc57f600000000, 0xbc2c401e00000000, + 0x1e9b09fd00000000, 0xbf0b1e1500000000, 0x176e93cd00000000, + 0xb6fe842500000000, 0x1449cdc600000000, 0xb5d9da2e00000000, + 0x11202fdb00000000, 0xb0b0383300000000, 0x120771d000000000, + 0xb397663800000000, 0x33baf80f00000000, 0x922aefe700000000, + 0x309da60400000000, 0x910db1ec00000000, 0x35f4441900000000, + 0x946453f100000000, 0x36d31a1200000000, 0x97430dfa00000000, + 0x3f26802200000000, 0x9eb697ca00000000, 0x3c01de2900000000, + 0x9d91c9c100000000, 0x39683c3400000000, 0x98f82bdc00000000, + 0x3a4f623f00000000, 0x9bdf75d700000000, 0x2b82095500000000, + 0x8a121ebd00000000, 0x28a5575e00000000, 0x893540b600000000, + 0x2dccb54300000000, 0x8c5ca2ab00000000, 0x2eebeb4800000000, + 0x8f7bfca000000000, 0x271e717800000000, 0x868e669000000000, + 0x24392f7300000000, 0x85a9389b00000000, 0x2150cd6e00000000, + 0x80c0da8600000000, 0x2277936500000000, 0x83e7848d00000000, + 0x222caf0a00000000, 0x83bcb8e200000000, 0x210bf10100000000, + 0x809be6e900000000, 0x2462131c00000000, 0x85f204f400000000, + 0x27454d1700000000, 0x86d55aff00000000, 0x2eb0d72700000000, + 0x8f20c0cf00000000, 0x2d97892c00000000, 0x8c079ec400000000, + 0x28fe6b3100000000, 0x896e7cd900000000, 0x2bd9353a00000000, + 0x8a4922d200000000, 0x3a145e5000000000, 0x9b8449b800000000, + 0x3933005b00000000, 0x98a317b300000000, 0x3c5ae24600000000, + 0x9dcaf5ae00000000, 0x3f7dbc4d00000000, 0x9eedaba500000000, + 0x3688267d00000000, 0x9718319500000000, 0x35af787600000000, + 0x943f6f9e00000000, 0x30c69a6b00000000, 0x91568d8300000000, + 0x33e1c46000000000, 0x9271d38800000000, 0x125c4dbf00000000, + 0xb3cc5a5700000000, 0x117b13b400000000, 0xb0eb045c00000000, + 0x1412f1a900000000, 0xb582e64100000000, 0x1735afa200000000, + 0xb6a5b84a00000000, 0x1ec0359200000000, 0xbf50227a00000000, + 0x1de76b9900000000, 0xbc777c7100000000, 0x188e898400000000, + 0xb91e9e6c00000000, 0x1ba9d78f00000000, 0xba39c06700000000, + 0x0a64bce500000000, 0xabf4ab0d00000000, 0x0943e2ee00000000, + 0xa8d3f50600000000, 0x0c2a00f300000000, 0xadba171b00000000, + 0x0f0d5ef800000000, 0xae9d491000000000, 0x06f8c4c800000000, + 0xa768d32000000000, 0x05df9ac300000000, 0xa44f8d2b00000000, + 0x00b678de00000000, 0xa1266f3600000000, 0x039126d500000000, + 0xa201313d00000000}, + {0x0000000000000000, 0xee8439a100000000, 0x9d0f029900000000, + 0x738b3b3800000000, 0x7b1975e900000000, 0x959d4c4800000000, + 0xe616777000000000, 0x08924ed100000000, 0xb7349b0900000000, + 0x59b0a2a800000000, 0x2a3b999000000000, 0xc4bfa03100000000, + 0xcc2deee000000000, 0x22a9d74100000000, 0x5122ec7900000000, + 0xbfa6d5d800000000, 0x6e69361300000000, 0x80ed0fb200000000, + 0xf366348a00000000, 0x1de20d2b00000000, 0x157043fa00000000, + 0xfbf47a5b00000000, 0x887f416300000000, 0x66fb78c200000000, + 0xd95dad1a00000000, 0x37d994bb00000000, 0x4452af8300000000, + 0xaad6962200000000, 0xa244d8f300000000, 0x4cc0e15200000000, + 0x3f4bda6a00000000, 0xd1cfe3cb00000000, 0xdcd26c2600000000, + 0x3256558700000000, 0x41dd6ebf00000000, 0xaf59571e00000000, + 0xa7cb19cf00000000, 0x494f206e00000000, 0x3ac41b5600000000, + 0xd44022f700000000, 0x6be6f72f00000000, 0x8562ce8e00000000, + 0xf6e9f5b600000000, 0x186dcc1700000000, 0x10ff82c600000000, + 0xfe7bbb6700000000, 0x8df0805f00000000, 0x6374b9fe00000000, + 0xb2bb5a3500000000, 0x5c3f639400000000, 0x2fb458ac00000000, + 0xc130610d00000000, 0xc9a22fdc00000000, 0x2726167d00000000, + 0x54ad2d4500000000, 0xba2914e400000000, 0x058fc13c00000000, + 0xeb0bf89d00000000, 0x9880c3a500000000, 0x7604fa0400000000, + 0x7e96b4d500000000, 0x90128d7400000000, 0xe399b64c00000000, + 0x0d1d8fed00000000, 0xb8a5d94c00000000, 0x5621e0ed00000000, + 0x25aadbd500000000, 0xcb2ee27400000000, 0xc3bcaca500000000, + 0x2d38950400000000, 0x5eb3ae3c00000000, 0xb037979d00000000, + 0x0f91424500000000, 0xe1157be400000000, 0x929e40dc00000000, + 0x7c1a797d00000000, 0x748837ac00000000, 0x9a0c0e0d00000000, + 0xe987353500000000, 0x07030c9400000000, 0xd6ccef5f00000000, + 0x3848d6fe00000000, 0x4bc3edc600000000, 0xa547d46700000000, + 0xadd59ab600000000, 0x4351a31700000000, 0x30da982f00000000, + 0xde5ea18e00000000, 0x61f8745600000000, 0x8f7c4df700000000, + 0xfcf776cf00000000, 0x12734f6e00000000, 0x1ae101bf00000000, + 0xf465381e00000000, 0x87ee032600000000, 0x696a3a8700000000, + 0x6477b56a00000000, 0x8af38ccb00000000, 0xf978b7f300000000, + 0x17fc8e5200000000, 0x1f6ec08300000000, 0xf1eaf92200000000, + 0x8261c21a00000000, 0x6ce5fbbb00000000, 0xd3432e6300000000, + 0x3dc717c200000000, 0x4e4c2cfa00000000, 0xa0c8155b00000000, + 0xa85a5b8a00000000, 0x46de622b00000000, 0x3555591300000000, + 0xdbd160b200000000, 0x0a1e837900000000, 0xe49abad800000000, + 0x971181e000000000, 0x7995b84100000000, 0x7107f69000000000, + 0x9f83cf3100000000, 0xec08f40900000000, 0x028ccda800000000, + 0xbd2a187000000000, 0x53ae21d100000000, 0x20251ae900000000, + 0xcea1234800000000, 0xc6336d9900000000, 0x28b7543800000000, + 0x5b3c6f0000000000, 0xb5b856a100000000, 0x704bb39900000000, + 0x9ecf8a3800000000, 0xed44b10000000000, 0x03c088a100000000, + 0x0b52c67000000000, 0xe5d6ffd100000000, 0x965dc4e900000000, + 0x78d9fd4800000000, 0xc77f289000000000, 0x29fb113100000000, + 0x5a702a0900000000, 0xb4f413a800000000, 0xbc665d7900000000, + 0x52e264d800000000, 0x21695fe000000000, 0xcfed664100000000, + 0x1e22858a00000000, 0xf0a6bc2b00000000, 0x832d871300000000, + 0x6da9beb200000000, 0x653bf06300000000, 0x8bbfc9c200000000, + 0xf834f2fa00000000, 0x16b0cb5b00000000, 0xa9161e8300000000, + 0x4792272200000000, 0x34191c1a00000000, 0xda9d25bb00000000, + 0xd20f6b6a00000000, 0x3c8b52cb00000000, 0x4f0069f300000000, + 0xa184505200000000, 0xac99dfbf00000000, 0x421de61e00000000, + 0x3196dd2600000000, 0xdf12e48700000000, 0xd780aa5600000000, + 0x390493f700000000, 0x4a8fa8cf00000000, 0xa40b916e00000000, + 0x1bad44b600000000, 0xf5297d1700000000, 0x86a2462f00000000, + 0x68267f8e00000000, 0x60b4315f00000000, 0x8e3008fe00000000, + 0xfdbb33c600000000, 0x133f0a6700000000, 0xc2f0e9ac00000000, + 0x2c74d00d00000000, 0x5fffeb3500000000, 0xb17bd29400000000, + 0xb9e99c4500000000, 0x576da5e400000000, 0x24e69edc00000000, + 0xca62a77d00000000, 0x75c472a500000000, 0x9b404b0400000000, + 0xe8cb703c00000000, 0x064f499d00000000, 0x0edd074c00000000, + 0xe0593eed00000000, 0x93d205d500000000, 0x7d563c7400000000, + 0xc8ee6ad500000000, 0x266a537400000000, 0x55e1684c00000000, + 0xbb6551ed00000000, 0xb3f71f3c00000000, 0x5d73269d00000000, + 0x2ef81da500000000, 0xc07c240400000000, 0x7fdaf1dc00000000, + 0x915ec87d00000000, 0xe2d5f34500000000, 0x0c51cae400000000, + 0x04c3843500000000, 0xea47bd9400000000, 0x99cc86ac00000000, + 0x7748bf0d00000000, 0xa6875cc600000000, 0x4803656700000000, + 0x3b885e5f00000000, 0xd50c67fe00000000, 0xdd9e292f00000000, + 0x331a108e00000000, 0x40912bb600000000, 0xae15121700000000, + 0x11b3c7cf00000000, 0xff37fe6e00000000, 0x8cbcc55600000000, + 0x6238fcf700000000, 0x6aaab22600000000, 0x842e8b8700000000, + 0xf7a5b0bf00000000, 0x1921891e00000000, 0x143c06f300000000, + 0xfab83f5200000000, 0x8933046a00000000, 0x67b73dcb00000000, + 0x6f25731a00000000, 0x81a14abb00000000, 0xf22a718300000000, + 0x1cae482200000000, 0xa3089dfa00000000, 0x4d8ca45b00000000, + 0x3e079f6300000000, 0xd083a6c200000000, 0xd811e81300000000, + 0x3695d1b200000000, 0x451eea8a00000000, 0xab9ad32b00000000, + 0x7a5530e000000000, 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0x0c2b498900000000, 0x681e9bcf00000000, + 0xb4f22af200000000, 0xa0743f4200000000, 0x7c988e7f00000000, + 0x18ad5c3900000000, 0xc441ed0400000000, 0x71a7068200000000, + 0xad4bb7bf00000000, 0xc97e65f900000000, 0x1592d4c400000000, + 0x0114c17400000000, 0xddf8704900000000, 0xb9cda20f00000000, + 0x6521133200000000, 0x1684fd0200000000, 0xca684c3f00000000, + 0xae5d9e7900000000, 0x72b12f4400000000, 0x66373af400000000, + 0xbadb8bc900000000, 0xdeee598f00000000, 0x0202e8b200000000, + 0xb7e4033400000000, 0x6b08b20900000000, 0x0f3d604f00000000, + 0xd3d1d17200000000, 0xc757c4c200000000, 0x1bbb75ff00000000, + 0x7f8ea7b900000000, 0xa362168400000000, 0x5445016f00000000, + 0x88a9b05200000000, 0xec9c621400000000, 0x3070d32900000000, + 0x24f6c69900000000, 0xf81a77a400000000, 0x9c2fa5e200000000, + 0x40c314df00000000, 0xf525ff5900000000, 0x29c94e6400000000, + 0x4dfc9c2200000000, 0x91102d1f00000000, 0x859638af00000000, + 0x597a899200000000, 0x3d4f5bd400000000, 0xe1a3eae900000000, + 0xdb0586b500000000, 0x07e9378800000000, 0x63dce5ce00000000, + 0xbf3054f300000000, 0xabb6414300000000, 0x775af07e00000000, + 0x136f223800000000, 0xcf83930500000000, 0x7a65788300000000, + 0xa689c9be00000000, 0xc2bc1bf800000000, 0x1e50aac500000000, + 0x0ad6bf7500000000, 0xd63a0e4800000000, 0xb20fdc0e00000000, + 0x6ee36d3300000000, 0x99c47ad800000000, 0x4528cbe500000000, + 0x211d19a300000000, 0xfdf1a89e00000000, 0xe977bd2e00000000, + 0x359b0c1300000000, 0x51aede5500000000, 0x8d426f6800000000, + 0x38a484ee00000000, 0xe44835d300000000, 0x807de79500000000, + 0x5c9156a800000000, 0x4817431800000000, 0x94fbf22500000000, + 0xf0ce206300000000, 0x2c22915e00000000, 0x5f877f6e00000000, + 0x836bce5300000000, 0xe75e1c1500000000, 0x3bb2ad2800000000, + 0x2f34b89800000000, 0xf3d809a500000000, 0x97eddbe300000000, + 0x4b016ade00000000, 0xfee7815800000000, 0x220b306500000000, + 0x463ee22300000000, 0x9ad2531e00000000, 0x8e5446ae00000000, + 0x52b8f79300000000, 0x368d25d500000000, 0xea6194e800000000, + 0x1d46830300000000, 0xc1aa323e00000000, 0xa59fe07800000000, + 0x7973514500000000, 0x6df544f500000000, 0xb119f5c800000000, + 0xd52c278e00000000, 0x09c096b300000000, 0xbc267d3500000000, + 0x60cacc0800000000, 0x04ff1e4e00000000, 0xd813af7300000000, + 0xcc95bac300000000, 0x10790bfe00000000, 0x744cd9b800000000, + 0xa8a0688500000000}}; + +#else /* W == 4 */ + +local const z_crc_t FAR crc_braid_table[][256] = { + {0x00000000, 0x81256527, 0xd93bcc0f, 0x581ea928, 0x69069e5f, + 0xe823fb78, 0xb03d5250, 0x31183777, 0xd20d3cbe, 0x53285999, + 0x0b36f0b1, 0x8a139596, 0xbb0ba2e1, 0x3a2ec7c6, 0x62306eee, + 0xe3150bc9, 0x7f6b7f3d, 0xfe4e1a1a, 0xa650b332, 0x2775d615, + 0x166de162, 0x97488445, 0xcf562d6d, 0x4e73484a, 0xad664383, + 0x2c4326a4, 0x745d8f8c, 0xf578eaab, 0xc460dddc, 0x4545b8fb, + 0x1d5b11d3, 0x9c7e74f4, 0xfed6fe7a, 0x7ff39b5d, 0x27ed3275, + 0xa6c85752, 0x97d06025, 0x16f50502, 0x4eebac2a, 0xcfcec90d, + 0x2cdbc2c4, 0xadfea7e3, 0xf5e00ecb, 0x74c56bec, 0x45dd5c9b, + 0xc4f839bc, 0x9ce69094, 0x1dc3f5b3, 0x81bd8147, 0x0098e460, + 0x58864d48, 0xd9a3286f, 0xe8bb1f18, 0x699e7a3f, 0x3180d317, + 0xb0a5b630, 0x53b0bdf9, 0xd295d8de, 0x8a8b71f6, 0x0bae14d1, + 0x3ab623a6, 0xbb934681, 0xe38defa9, 0x62a88a8e, 0x26dcfab5, + 0xa7f99f92, 0xffe736ba, 0x7ec2539d, 0x4fda64ea, 0xceff01cd, + 0x96e1a8e5, 0x17c4cdc2, 0xf4d1c60b, 0x75f4a32c, 0x2dea0a04, + 0xaccf6f23, 0x9dd75854, 0x1cf23d73, 0x44ec945b, 0xc5c9f17c, + 0x59b78588, 0xd892e0af, 0x808c4987, 0x01a92ca0, 0x30b11bd7, + 0xb1947ef0, 0xe98ad7d8, 0x68afb2ff, 0x8bbab936, 0x0a9fdc11, + 0x52817539, 0xd3a4101e, 0xe2bc2769, 0x6399424e, 0x3b87eb66, + 0xbaa28e41, 0xd80a04cf, 0x592f61e8, 0x0131c8c0, 0x8014ade7, + 0xb10c9a90, 0x3029ffb7, 0x6837569f, 0xe91233b8, 0x0a073871, + 0x8b225d56, 0xd33cf47e, 0x52199159, 0x6301a62e, 0xe224c309, + 0xba3a6a21, 0x3b1f0f06, 0xa7617bf2, 0x26441ed5, 0x7e5ab7fd, + 0xff7fd2da, 0xce67e5ad, 0x4f42808a, 0x175c29a2, 0x96794c85, + 0x756c474c, 0xf449226b, 0xac578b43, 0x2d72ee64, 0x1c6ad913, + 0x9d4fbc34, 0xc551151c, 0x4474703b, 0x4db9f56a, 0xcc9c904d, + 0x94823965, 0x15a75c42, 0x24bf6b35, 0xa59a0e12, 0xfd84a73a, + 0x7ca1c21d, 0x9fb4c9d4, 0x1e91acf3, 0x468f05db, 0xc7aa60fc, + 0xf6b2578b, 0x779732ac, 0x2f899b84, 0xaeacfea3, 0x32d28a57, + 0xb3f7ef70, 0xebe94658, 0x6acc237f, 0x5bd41408, 0xdaf1712f, + 0x82efd807, 0x03cabd20, 0xe0dfb6e9, 0x61fad3ce, 0x39e47ae6, + 0xb8c11fc1, 0x89d928b6, 0x08fc4d91, 0x50e2e4b9, 0xd1c7819e, + 0xb36f0b10, 0x324a6e37, 0x6a54c71f, 0xeb71a238, 0xda69954f, + 0x5b4cf068, 0x03525940, 0x82773c67, 0x616237ae, 0xe0475289, + 0xb859fba1, 0x397c9e86, 0x0864a9f1, 0x8941ccd6, 0xd15f65fe, + 0x507a00d9, 0xcc04742d, 0x4d21110a, 0x153fb822, 0x941add05, + 0xa502ea72, 0x24278f55, 0x7c39267d, 0xfd1c435a, 0x1e094893, + 0x9f2c2db4, 0xc732849c, 0x4617e1bb, 0x770fd6cc, 0xf62ab3eb, + 0xae341ac3, 0x2f117fe4, 0x6b650fdf, 0xea406af8, 0xb25ec3d0, + 0x337ba6f7, 0x02639180, 0x8346f4a7, 0xdb585d8f, 0x5a7d38a8, + 0xb9683361, 0x384d5646, 0x6053ff6e, 0xe1769a49, 0xd06ead3e, + 0x514bc819, 0x09556131, 0x88700416, 0x140e70e2, 0x952b15c5, + 0xcd35bced, 0x4c10d9ca, 0x7d08eebd, 0xfc2d8b9a, 0xa43322b2, + 0x25164795, 0xc6034c5c, 0x4726297b, 0x1f388053, 0x9e1de574, + 0xaf05d203, 0x2e20b724, 0x763e1e0c, 0xf71b7b2b, 0x95b3f1a5, + 0x14969482, 0x4c883daa, 0xcdad588d, 0xfcb56ffa, 0x7d900add, + 0x258ea3f5, 0xa4abc6d2, 0x47becd1b, 0xc69ba83c, 0x9e850114, + 0x1fa06433, 0x2eb85344, 0xaf9d3663, 0xf7839f4b, 0x76a6fa6c, + 0xead88e98, 0x6bfdebbf, 0x33e34297, 0xb2c627b0, 0x83de10c7, + 0x02fb75e0, 0x5ae5dcc8, 0xdbc0b9ef, 0x38d5b226, 0xb9f0d701, + 0xe1ee7e29, 0x60cb1b0e, 0x51d32c79, 0xd0f6495e, 0x88e8e076, + 0x09cd8551}, + {0x00000000, 0x9b73ead4, 0xed96d3e9, 0x76e5393d, 0x005ca193, + 0x9b2f4b47, 0xedca727a, 0x76b998ae, 0x00b94326, 0x9bcaa9f2, + 0xed2f90cf, 0x765c7a1b, 0x00e5e2b5, 0x9b960861, 0xed73315c, + 0x7600db88, 0x0172864c, 0x9a016c98, 0xece455a5, 0x7797bf71, + 0x012e27df, 0x9a5dcd0b, 0xecb8f436, 0x77cb1ee2, 0x01cbc56a, + 0x9ab82fbe, 0xec5d1683, 0x772efc57, 0x019764f9, 0x9ae48e2d, + 0xec01b710, 0x77725dc4, 0x02e50c98, 0x9996e64c, 0xef73df71, + 0x740035a5, 0x02b9ad0b, 0x99ca47df, 0xef2f7ee2, 0x745c9436, + 0x025c4fbe, 0x992fa56a, 0xefca9c57, 0x74b97683, 0x0200ee2d, + 0x997304f9, 0xef963dc4, 0x74e5d710, 0x03978ad4, 0x98e46000, + 0xee01593d, 0x7572b3e9, 0x03cb2b47, 0x98b8c193, 0xee5df8ae, + 0x752e127a, 0x032ec9f2, 0x985d2326, 0xeeb81a1b, 0x75cbf0cf, + 0x03726861, 0x980182b5, 0xeee4bb88, 0x7597515c, 0x05ca1930, + 0x9eb9f3e4, 0xe85ccad9, 0x732f200d, 0x0596b8a3, 0x9ee55277, + 0xe8006b4a, 0x7373819e, 0x05735a16, 0x9e00b0c2, 0xe8e589ff, + 0x7396632b, 0x052ffb85, 0x9e5c1151, 0xe8b9286c, 0x73cac2b8, + 0x04b89f7c, 0x9fcb75a8, 0xe92e4c95, 0x725da641, 0x04e43eef, + 0x9f97d43b, 0xe972ed06, 0x720107d2, 0x0401dc5a, 0x9f72368e, + 0xe9970fb3, 0x72e4e567, 0x045d7dc9, 0x9f2e971d, 0xe9cbae20, + 0x72b844f4, 0x072f15a8, 0x9c5cff7c, 0xeab9c641, 0x71ca2c95, + 0x0773b43b, 0x9c005eef, 0xeae567d2, 0x71968d06, 0x0796568e, + 0x9ce5bc5a, 0xea008567, 0x71736fb3, 0x07caf71d, 0x9cb91dc9, + 0xea5c24f4, 0x712fce20, 0x065d93e4, 0x9d2e7930, 0xebcb400d, + 0x70b8aad9, 0x06013277, 0x9d72d8a3, 0xeb97e19e, 0x70e40b4a, + 0x06e4d0c2, 0x9d973a16, 0xeb72032b, 0x7001e9ff, 0x06b87151, + 0x9dcb9b85, 0xeb2ea2b8, 0x705d486c, 0x0b943260, 0x90e7d8b4, + 0xe602e189, 0x7d710b5d, 0x0bc893f3, 0x90bb7927, 0xe65e401a, + 0x7d2daace, 0x0b2d7146, 0x905e9b92, 0xe6bba2af, 0x7dc8487b, + 0x0b71d0d5, 0x90023a01, 0xe6e7033c, 0x7d94e9e8, 0x0ae6b42c, + 0x91955ef8, 0xe77067c5, 0x7c038d11, 0x0aba15bf, 0x91c9ff6b, + 0xe72cc656, 0x7c5f2c82, 0x0a5ff70a, 0x912c1dde, 0xe7c924e3, + 0x7cbace37, 0x0a035699, 0x9170bc4d, 0xe7958570, 0x7ce66fa4, + 0x09713ef8, 0x9202d42c, 0xe4e7ed11, 0x7f9407c5, 0x092d9f6b, + 0x925e75bf, 0xe4bb4c82, 0x7fc8a656, 0x09c87dde, 0x92bb970a, + 0xe45eae37, 0x7f2d44e3, 0x0994dc4d, 0x92e73699, 0xe4020fa4, + 0x7f71e570, 0x0803b8b4, 0x93705260, 0xe5956b5d, 0x7ee68189, + 0x085f1927, 0x932cf3f3, 0xe5c9cace, 0x7eba201a, 0x08bafb92, + 0x93c91146, 0xe52c287b, 0x7e5fc2af, 0x08e65a01, 0x9395b0d5, + 0xe57089e8, 0x7e03633c, 0x0e5e2b50, 0x952dc184, 0xe3c8f8b9, + 0x78bb126d, 0x0e028ac3, 0x95716017, 0xe394592a, 0x78e7b3fe, + 0x0ee76876, 0x959482a2, 0xe371bb9f, 0x7802514b, 0x0ebbc9e5, + 0x95c82331, 0xe32d1a0c, 0x785ef0d8, 0x0f2cad1c, 0x945f47c8, + 0xe2ba7ef5, 0x79c99421, 0x0f700c8f, 0x9403e65b, 0xe2e6df66, + 0x799535b2, 0x0f95ee3a, 0x94e604ee, 0xe2033dd3, 0x7970d707, + 0x0fc94fa9, 0x94baa57d, 0xe25f9c40, 0x792c7694, 0x0cbb27c8, + 0x97c8cd1c, 0xe12df421, 0x7a5e1ef5, 0x0ce7865b, 0x97946c8f, + 0xe17155b2, 0x7a02bf66, 0x0c0264ee, 0x97718e3a, 0xe194b707, + 0x7ae75dd3, 0x0c5ec57d, 0x972d2fa9, 0xe1c81694, 0x7abbfc40, + 0x0dc9a184, 0x96ba4b50, 0xe05f726d, 0x7b2c98b9, 0x0d950017, + 0x96e6eac3, 0xe003d3fe, 0x7b70392a, 0x0d70e2a2, 0x96030876, + 0xe0e6314b, 0x7b95db9f, 0x0d2c4331, 0x965fa9e5, 0xe0ba90d8, + 0x7bc97a0c}, + {0x00000000, 0x172864c0, 0x2e50c980, 0x3978ad40, 0x5ca19300, + 0x4b89f7c0, 0x72f15a80, 0x65d93e40, 0xb9432600, 0xae6b42c0, + 0x9713ef80, 0x803b8b40, 0xe5e2b500, 0xf2cad1c0, 0xcbb27c80, + 0xdc9a1840, 0xa9f74a41, 0xbedf2e81, 0x87a783c1, 0x908fe701, + 0xf556d941, 0xe27ebd81, 0xdb0610c1, 0xcc2e7401, 0x10b46c41, + 0x079c0881, 0x3ee4a5c1, 0x29ccc101, 0x4c15ff41, 0x5b3d9b81, + 0x624536c1, 0x756d5201, 0x889f92c3, 0x9fb7f603, 0xa6cf5b43, + 0xb1e73f83, 0xd43e01c3, 0xc3166503, 0xfa6ec843, 0xed46ac83, + 0x31dcb4c3, 0x26f4d003, 0x1f8c7d43, 0x08a41983, 0x6d7d27c3, + 0x7a554303, 0x432dee43, 0x54058a83, 0x2168d882, 0x3640bc42, + 0x0f381102, 0x181075c2, 0x7dc94b82, 0x6ae12f42, 0x53998202, + 0x44b1e6c2, 0x982bfe82, 0x8f039a42, 0xb67b3702, 0xa15353c2, + 0xc48a6d82, 0xd3a20942, 0xeadaa402, 0xfdf2c0c2, 0xca4e23c7, + 0xdd664707, 0xe41eea47, 0xf3368e87, 0x96efb0c7, 0x81c7d407, + 0xb8bf7947, 0xaf971d87, 0x730d05c7, 0x64256107, 0x5d5dcc47, + 0x4a75a887, 0x2fac96c7, 0x3884f207, 0x01fc5f47, 0x16d43b87, + 0x63b96986, 0x74910d46, 0x4de9a006, 0x5ac1c4c6, 0x3f18fa86, + 0x28309e46, 0x11483306, 0x066057c6, 0xdafa4f86, 0xcdd22b46, + 0xf4aa8606, 0xe382e2c6, 0x865bdc86, 0x9173b846, 0xa80b1506, + 0xbf2371c6, 0x42d1b104, 0x55f9d5c4, 0x6c817884, 0x7ba91c44, + 0x1e702204, 0x095846c4, 0x3020eb84, 0x27088f44, 0xfb929704, + 0xecbaf3c4, 0xd5c25e84, 0xc2ea3a44, 0xa7330404, 0xb01b60c4, + 0x8963cd84, 0x9e4ba944, 0xeb26fb45, 0xfc0e9f85, 0xc57632c5, + 0xd25e5605, 0xb7876845, 0xa0af0c85, 0x99d7a1c5, 0x8effc505, + 0x5265dd45, 0x454db985, 0x7c3514c5, 0x6b1d7005, 0x0ec44e45, + 0x19ec2a85, 0x209487c5, 0x37bce305, 0x4fed41cf, 0x58c5250f, + 0x61bd884f, 0x7695ec8f, 0x134cd2cf, 0x0464b60f, 0x3d1c1b4f, + 0x2a347f8f, 0xf6ae67cf, 0xe186030f, 0xd8feae4f, 0xcfd6ca8f, + 0xaa0ff4cf, 0xbd27900f, 0x845f3d4f, 0x9377598f, 0xe61a0b8e, + 0xf1326f4e, 0xc84ac20e, 0xdf62a6ce, 0xbabb988e, 0xad93fc4e, + 0x94eb510e, 0x83c335ce, 0x5f592d8e, 0x4871494e, 0x7109e40e, + 0x662180ce, 0x03f8be8e, 0x14d0da4e, 0x2da8770e, 0x3a8013ce, + 0xc772d30c, 0xd05ab7cc, 0xe9221a8c, 0xfe0a7e4c, 0x9bd3400c, + 0x8cfb24cc, 0xb583898c, 0xa2abed4c, 0x7e31f50c, 0x691991cc, + 0x50613c8c, 0x4749584c, 0x2290660c, 0x35b802cc, 0x0cc0af8c, + 0x1be8cb4c, 0x6e85994d, 0x79adfd8d, 0x40d550cd, 0x57fd340d, + 0x32240a4d, 0x250c6e8d, 0x1c74c3cd, 0x0b5ca70d, 0xd7c6bf4d, + 0xc0eedb8d, 0xf99676cd, 0xeebe120d, 0x8b672c4d, 0x9c4f488d, + 0xa537e5cd, 0xb21f810d, 0x85a36208, 0x928b06c8, 0xabf3ab88, + 0xbcdbcf48, 0xd902f108, 0xce2a95c8, 0xf7523888, 0xe07a5c48, + 0x3ce04408, 0x2bc820c8, 0x12b08d88, 0x0598e948, 0x6041d708, + 0x7769b3c8, 0x4e111e88, 0x59397a48, 0x2c542849, 0x3b7c4c89, + 0x0204e1c9, 0x152c8509, 0x70f5bb49, 0x67dddf89, 0x5ea572c9, + 0x498d1609, 0x95170e49, 0x823f6a89, 0xbb47c7c9, 0xac6fa309, + 0xc9b69d49, 0xde9ef989, 0xe7e654c9, 0xf0ce3009, 0x0d3cf0cb, + 0x1a14940b, 0x236c394b, 0x34445d8b, 0x519d63cb, 0x46b5070b, + 0x7fcdaa4b, 0x68e5ce8b, 0xb47fd6cb, 0xa357b20b, 0x9a2f1f4b, + 0x8d077b8b, 0xe8de45cb, 0xfff6210b, 0xc68e8c4b, 0xd1a6e88b, + 0xa4cbba8a, 0xb3e3de4a, 0x8a9b730a, 0x9db317ca, 0xf86a298a, + 0xef424d4a, 0xd63ae00a, 0xc11284ca, 0x1d889c8a, 0x0aa0f84a, + 0x33d8550a, 0x24f031ca, 0x41290f8a, 0x56016b4a, 0x6f79c60a, + 0x7851a2ca}, + {0x00000000, 0x9fda839e, 0xe4c4017d, 0x7b1e82e3, 0x12f904bb, + 0x8d238725, 0xf63d05c6, 0x69e78658, 0x25f20976, 0xba288ae8, + 0xc136080b, 0x5eec8b95, 0x370b0dcd, 0xa8d18e53, 0xd3cf0cb0, + 0x4c158f2e, 0x4be412ec, 0xd43e9172, 0xaf201391, 0x30fa900f, + 0x591d1657, 0xc6c795c9, 0xbdd9172a, 0x220394b4, 0x6e161b9a, + 0xf1cc9804, 0x8ad21ae7, 0x15089979, 0x7cef1f21, 0xe3359cbf, + 0x982b1e5c, 0x07f19dc2, 0x97c825d8, 0x0812a646, 0x730c24a5, + 0xecd6a73b, 0x85312163, 0x1aeba2fd, 0x61f5201e, 0xfe2fa380, + 0xb23a2cae, 0x2de0af30, 0x56fe2dd3, 0xc924ae4d, 0xa0c32815, + 0x3f19ab8b, 0x44072968, 0xdbddaaf6, 0xdc2c3734, 0x43f6b4aa, + 0x38e83649, 0xa732b5d7, 0xced5338f, 0x510fb011, 0x2a1132f2, + 0xb5cbb16c, 0xf9de3e42, 0x6604bddc, 0x1d1a3f3f, 0x82c0bca1, + 0xeb273af9, 0x74fdb967, 0x0fe33b84, 0x9039b81a, 0xf4e14df1, + 0x6b3bce6f, 0x10254c8c, 0x8fffcf12, 0xe618494a, 0x79c2cad4, + 0x02dc4837, 0x9d06cba9, 0xd1134487, 0x4ec9c719, 0x35d745fa, + 0xaa0dc664, 0xc3ea403c, 0x5c30c3a2, 0x272e4141, 0xb8f4c2df, + 0xbf055f1d, 0x20dfdc83, 0x5bc15e60, 0xc41bddfe, 0xadfc5ba6, + 0x3226d838, 0x49385adb, 0xd6e2d945, 0x9af7566b, 0x052dd5f5, + 0x7e335716, 0xe1e9d488, 0x880e52d0, 0x17d4d14e, 0x6cca53ad, + 0xf310d033, 0x63296829, 0xfcf3ebb7, 0x87ed6954, 0x1837eaca, + 0x71d06c92, 0xee0aef0c, 0x95146def, 0x0aceee71, 0x46db615f, + 0xd901e2c1, 0xa21f6022, 0x3dc5e3bc, 0x542265e4, 0xcbf8e67a, + 0xb0e66499, 0x2f3ce707, 0x28cd7ac5, 0xb717f95b, 0xcc097bb8, + 0x53d3f826, 0x3a347e7e, 0xa5eefde0, 0xdef07f03, 0x412afc9d, + 0x0d3f73b3, 0x92e5f02d, 0xe9fb72ce, 0x7621f150, 0x1fc67708, + 0x801cf496, 0xfb027675, 0x64d8f5eb, 0x32b39da3, 0xad691e3d, + 0xd6779cde, 0x49ad1f40, 0x204a9918, 0xbf901a86, 0xc48e9865, + 0x5b541bfb, 0x174194d5, 0x889b174b, 0xf38595a8, 0x6c5f1636, + 0x05b8906e, 0x9a6213f0, 0xe17c9113, 0x7ea6128d, 0x79578f4f, + 0xe68d0cd1, 0x9d938e32, 0x02490dac, 0x6bae8bf4, 0xf474086a, + 0x8f6a8a89, 0x10b00917, 0x5ca58639, 0xc37f05a7, 0xb8618744, + 0x27bb04da, 0x4e5c8282, 0xd186011c, 0xaa9883ff, 0x35420061, + 0xa57bb87b, 0x3aa13be5, 0x41bfb906, 0xde653a98, 0xb782bcc0, + 0x28583f5e, 0x5346bdbd, 0xcc9c3e23, 0x8089b10d, 0x1f533293, + 0x644db070, 0xfb9733ee, 0x9270b5b6, 0x0daa3628, 0x76b4b4cb, + 0xe96e3755, 0xee9faa97, 0x71452909, 0x0a5babea, 0x95812874, + 0xfc66ae2c, 0x63bc2db2, 0x18a2af51, 0x87782ccf, 0xcb6da3e1, + 0x54b7207f, 0x2fa9a29c, 0xb0732102, 0xd994a75a, 0x464e24c4, + 0x3d50a627, 0xa28a25b9, 0xc652d052, 0x598853cc, 0x2296d12f, + 0xbd4c52b1, 0xd4abd4e9, 0x4b715777, 0x306fd594, 0xafb5560a, + 0xe3a0d924, 0x7c7a5aba, 0x0764d859, 0x98be5bc7, 0xf159dd9f, + 0x6e835e01, 0x159ddce2, 0x8a475f7c, 0x8db6c2be, 0x126c4120, + 0x6972c3c3, 0xf6a8405d, 0x9f4fc605, 0x0095459b, 0x7b8bc778, + 0xe45144e6, 0xa844cbc8, 0x379e4856, 0x4c80cab5, 0xd35a492b, + 0xbabdcf73, 0x25674ced, 0x5e79ce0e, 0xc1a34d90, 0x519af58a, + 0xce407614, 0xb55ef4f7, 0x2a847769, 0x4363f131, 0xdcb972af, + 0xa7a7f04c, 0x387d73d2, 0x7468fcfc, 0xebb27f62, 0x90acfd81, + 0x0f767e1f, 0x6691f847, 0xf94b7bd9, 0x8255f93a, 0x1d8f7aa4, + 0x1a7ee766, 0x85a464f8, 0xfebae61b, 0x61606585, 0x0887e3dd, + 0x975d6043, 0xec43e2a0, 0x7399613e, 0x3f8cee10, 0xa0566d8e, + 0xdb48ef6d, 0x44926cf3, 0x2d75eaab, 0xb2af6935, 0xc9b1ebd6, + 0x566b6848}}; + +local const z_word_t FAR crc_braid_big_table[][256] = { + {0x00000000, 0x9e83da9f, 0x7d01c4e4, 0xe3821e7b, 0xbb04f912, + 0x2587238d, 0xc6053df6, 0x5886e769, 0x7609f225, 0xe88a28ba, + 0x0b0836c1, 0x958bec5e, 0xcd0d0b37, 0x538ed1a8, 0xb00ccfd3, + 0x2e8f154c, 0xec12e44b, 0x72913ed4, 0x911320af, 0x0f90fa30, + 0x57161d59, 0xc995c7c6, 0x2a17d9bd, 0xb4940322, 0x9a1b166e, + 0x0498ccf1, 0xe71ad28a, 0x79990815, 0x211fef7c, 0xbf9c35e3, + 0x5c1e2b98, 0xc29df107, 0xd825c897, 0x46a61208, 0xa5240c73, + 0x3ba7d6ec, 0x63213185, 0xfda2eb1a, 0x1e20f561, 0x80a32ffe, + 0xae2c3ab2, 0x30afe02d, 0xd32dfe56, 0x4dae24c9, 0x1528c3a0, + 0x8bab193f, 0x68290744, 0xf6aadddb, 0x34372cdc, 0xaab4f643, + 0x4936e838, 0xd7b532a7, 0x8f33d5ce, 0x11b00f51, 0xf232112a, + 0x6cb1cbb5, 0x423edef9, 0xdcbd0466, 0x3f3f1a1d, 0xa1bcc082, + 0xf93a27eb, 0x67b9fd74, 0x843be30f, 0x1ab83990, 0xf14de1f4, + 0x6fce3b6b, 0x8c4c2510, 0x12cfff8f, 0x4a4918e6, 0xd4cac279, + 0x3748dc02, 0xa9cb069d, 0x874413d1, 0x19c7c94e, 0xfa45d735, + 0x64c60daa, 0x3c40eac3, 0xa2c3305c, 0x41412e27, 0xdfc2f4b8, + 0x1d5f05bf, 0x83dcdf20, 0x605ec15b, 0xfedd1bc4, 0xa65bfcad, + 0x38d82632, 0xdb5a3849, 0x45d9e2d6, 0x6b56f79a, 0xf5d52d05, + 0x1657337e, 0x88d4e9e1, 0xd0520e88, 0x4ed1d417, 0xad53ca6c, + 0x33d010f3, 0x29682963, 0xb7ebf3fc, 0x5469ed87, 0xcaea3718, + 0x926cd071, 0x0cef0aee, 0xef6d1495, 0x71eece0a, 0x5f61db46, + 0xc1e201d9, 0x22601fa2, 0xbce3c53d, 0xe4652254, 0x7ae6f8cb, + 0x9964e6b0, 0x07e73c2f, 0xc57acd28, 0x5bf917b7, 0xb87b09cc, + 0x26f8d353, 0x7e7e343a, 0xe0fdeea5, 0x037ff0de, 0x9dfc2a41, + 0xb3733f0d, 0x2df0e592, 0xce72fbe9, 0x50f12176, 0x0877c61f, + 0x96f41c80, 0x757602fb, 0xebf5d864, 0xa39db332, 0x3d1e69ad, + 0xde9c77d6, 0x401fad49, 0x18994a20, 0x861a90bf, 0x65988ec4, + 0xfb1b545b, 0xd5944117, 0x4b179b88, 0xa89585f3, 0x36165f6c, + 0x6e90b805, 0xf013629a, 0x13917ce1, 0x8d12a67e, 0x4f8f5779, + 0xd10c8de6, 0x328e939d, 0xac0d4902, 0xf48bae6b, 0x6a0874f4, + 0x898a6a8f, 0x1709b010, 0x3986a55c, 0xa7057fc3, 0x448761b8, + 0xda04bb27, 0x82825c4e, 0x1c0186d1, 0xff8398aa, 0x61004235, + 0x7bb87ba5, 0xe53ba13a, 0x06b9bf41, 0x983a65de, 0xc0bc82b7, + 0x5e3f5828, 0xbdbd4653, 0x233e9ccc, 0x0db18980, 0x9332531f, + 0x70b04d64, 0xee3397fb, 0xb6b57092, 0x2836aa0d, 0xcbb4b476, + 0x55376ee9, 0x97aa9fee, 0x09294571, 0xeaab5b0a, 0x74288195, + 0x2cae66fc, 0xb22dbc63, 0x51afa218, 0xcf2c7887, 0xe1a36dcb, + 0x7f20b754, 0x9ca2a92f, 0x022173b0, 0x5aa794d9, 0xc4244e46, + 0x27a6503d, 0xb9258aa2, 0x52d052c6, 0xcc538859, 0x2fd19622, + 0xb1524cbd, 0xe9d4abd4, 0x7757714b, 0x94d56f30, 0x0a56b5af, + 0x24d9a0e3, 0xba5a7a7c, 0x59d86407, 0xc75bbe98, 0x9fdd59f1, + 0x015e836e, 0xe2dc9d15, 0x7c5f478a, 0xbec2b68d, 0x20416c12, + 0xc3c37269, 0x5d40a8f6, 0x05c64f9f, 0x9b459500, 0x78c78b7b, + 0xe64451e4, 0xc8cb44a8, 0x56489e37, 0xb5ca804c, 0x2b495ad3, + 0x73cfbdba, 0xed4c6725, 0x0ece795e, 0x904da3c1, 0x8af59a51, + 0x147640ce, 0xf7f45eb5, 0x6977842a, 0x31f16343, 0xaf72b9dc, + 0x4cf0a7a7, 0xd2737d38, 0xfcfc6874, 0x627fb2eb, 0x81fdac90, + 0x1f7e760f, 0x47f89166, 0xd97b4bf9, 0x3af95582, 0xa47a8f1d, + 0x66e77e1a, 0xf864a485, 0x1be6bafe, 0x85656061, 0xdde38708, + 0x43605d97, 0xa0e243ec, 0x3e619973, 0x10ee8c3f, 0x8e6d56a0, + 0x6def48db, 0xf36c9244, 0xabea752d, 0x3569afb2, 0xd6ebb1c9, + 0x48686b56}, + {0x00000000, 0xc0642817, 0x80c9502e, 0x40ad7839, 0x0093a15c, + 0xc0f7894b, 0x805af172, 0x403ed965, 0x002643b9, 0xc0426bae, + 0x80ef1397, 0x408b3b80, 0x00b5e2e5, 0xc0d1caf2, 0x807cb2cb, + 0x40189adc, 0x414af7a9, 0x812edfbe, 0xc183a787, 0x01e78f90, + 0x41d956f5, 0x81bd7ee2, 0xc11006db, 0x01742ecc, 0x416cb410, + 0x81089c07, 0xc1a5e43e, 0x01c1cc29, 0x41ff154c, 0x819b3d5b, + 0xc1364562, 0x01526d75, 0xc3929f88, 0x03f6b79f, 0x435bcfa6, + 0x833fe7b1, 0xc3013ed4, 0x036516c3, 0x43c86efa, 0x83ac46ed, + 0xc3b4dc31, 0x03d0f426, 0x437d8c1f, 0x8319a408, 0xc3277d6d, + 0x0343557a, 0x43ee2d43, 0x838a0554, 0x82d86821, 0x42bc4036, + 0x0211380f, 0xc2751018, 0x824bc97d, 0x422fe16a, 0x02829953, + 0xc2e6b144, 0x82fe2b98, 0x429a038f, 0x02377bb6, 0xc25353a1, + 0x826d8ac4, 0x4209a2d3, 0x02a4daea, 0xc2c0f2fd, 0xc7234eca, + 0x074766dd, 0x47ea1ee4, 0x878e36f3, 0xc7b0ef96, 0x07d4c781, + 0x4779bfb8, 0x871d97af, 0xc7050d73, 0x07612564, 0x47cc5d5d, + 0x87a8754a, 0xc796ac2f, 0x07f28438, 0x475ffc01, 0x873bd416, + 0x8669b963, 0x460d9174, 0x06a0e94d, 0xc6c4c15a, 0x86fa183f, + 0x469e3028, 0x06334811, 0xc6576006, 0x864ffada, 0x462bd2cd, + 0x0686aaf4, 0xc6e282e3, 0x86dc5b86, 0x46b87391, 0x06150ba8, + 0xc67123bf, 0x04b1d142, 0xc4d5f955, 0x8478816c, 0x441ca97b, + 0x0422701e, 0xc4465809, 0x84eb2030, 0x448f0827, 0x049792fb, + 0xc4f3baec, 0x845ec2d5, 0x443aeac2, 0x040433a7, 0xc4601bb0, + 0x84cd6389, 0x44a94b9e, 0x45fb26eb, 0x859f0efc, 0xc53276c5, + 0x05565ed2, 0x456887b7, 0x850cafa0, 0xc5a1d799, 0x05c5ff8e, + 0x45dd6552, 0x85b94d45, 0xc514357c, 0x05701d6b, 0x454ec40e, + 0x852aec19, 0xc5879420, 0x05e3bc37, 0xcf41ed4f, 0x0f25c558, + 0x4f88bd61, 0x8fec9576, 0xcfd24c13, 0x0fb66404, 0x4f1b1c3d, + 0x8f7f342a, 0xcf67aef6, 0x0f0386e1, 0x4faefed8, 0x8fcad6cf, + 0xcff40faa, 0x0f9027bd, 0x4f3d5f84, 0x8f597793, 0x8e0b1ae6, + 0x4e6f32f1, 0x0ec24ac8, 0xcea662df, 0x8e98bbba, 0x4efc93ad, + 0x0e51eb94, 0xce35c383, 0x8e2d595f, 0x4e497148, 0x0ee40971, + 0xce802166, 0x8ebef803, 0x4edad014, 0x0e77a82d, 0xce13803a, + 0x0cd372c7, 0xccb75ad0, 0x8c1a22e9, 0x4c7e0afe, 0x0c40d39b, + 0xcc24fb8c, 0x8c8983b5, 0x4cedaba2, 0x0cf5317e, 0xcc911969, + 0x8c3c6150, 0x4c584947, 0x0c669022, 0xcc02b835, 0x8cafc00c, + 0x4ccbe81b, 0x4d99856e, 0x8dfdad79, 0xcd50d540, 0x0d34fd57, + 0x4d0a2432, 0x8d6e0c25, 0xcdc3741c, 0x0da75c0b, 0x4dbfc6d7, + 0x8ddbeec0, 0xcd7696f9, 0x0d12beee, 0x4d2c678b, 0x8d484f9c, + 0xcde537a5, 0x0d811fb2, 0x0862a385, 0xc8068b92, 0x88abf3ab, + 0x48cfdbbc, 0x08f102d9, 0xc8952ace, 0x883852f7, 0x485c7ae0, + 0x0844e03c, 0xc820c82b, 0x888db012, 0x48e99805, 0x08d74160, + 0xc8b36977, 0x881e114e, 0x487a3959, 0x4928542c, 0x894c7c3b, + 0xc9e10402, 0x09852c15, 0x49bbf570, 0x89dfdd67, 0xc972a55e, + 0x09168d49, 0x490e1795, 0x896a3f82, 0xc9c747bb, 0x09a36fac, + 0x499db6c9, 0x89f99ede, 0xc954e6e7, 0x0930cef0, 0xcbf03c0d, + 0x0b94141a, 0x4b396c23, 0x8b5d4434, 0xcb639d51, 0x0b07b546, + 0x4baacd7f, 0x8bcee568, 0xcbd67fb4, 0x0bb257a3, 0x4b1f2f9a, + 0x8b7b078d, 0xcb45dee8, 0x0b21f6ff, 0x4b8c8ec6, 0x8be8a6d1, + 0x8abacba4, 0x4adee3b3, 0x0a739b8a, 0xca17b39d, 0x8a296af8, + 0x4a4d42ef, 0x0ae03ad6, 0xca8412c1, 0x8a9c881d, 0x4af8a00a, + 0x0a55d833, 0xca31f024, 0x8a0f2941, 0x4a6b0156, 0x0ac6796f, + 0xcaa25178}, + {0x00000000, 0xd4ea739b, 0xe9d396ed, 0x3d39e576, 0x93a15c00, + 0x474b2f9b, 0x7a72caed, 0xae98b976, 0x2643b900, 0xf2a9ca9b, + 0xcf902fed, 0x1b7a5c76, 0xb5e2e500, 0x6108969b, 0x5c3173ed, + 0x88db0076, 0x4c867201, 0x986c019a, 0xa555e4ec, 0x71bf9777, + 0xdf272e01, 0x0bcd5d9a, 0x36f4b8ec, 0xe21ecb77, 0x6ac5cb01, + 0xbe2fb89a, 0x83165dec, 0x57fc2e77, 0xf9649701, 0x2d8ee49a, + 0x10b701ec, 0xc45d7277, 0x980ce502, 0x4ce69699, 0x71df73ef, + 0xa5350074, 0x0badb902, 0xdf47ca99, 0xe27e2fef, 0x36945c74, + 0xbe4f5c02, 0x6aa52f99, 0x579ccaef, 0x8376b974, 0x2dee0002, + 0xf9047399, 0xc43d96ef, 0x10d7e574, 0xd48a9703, 0x0060e498, + 0x3d5901ee, 0xe9b37275, 0x472bcb03, 0x93c1b898, 0xaef85dee, + 0x7a122e75, 0xf2c92e03, 0x26235d98, 0x1b1ab8ee, 0xcff0cb75, + 0x61687203, 0xb5820198, 0x88bbe4ee, 0x5c519775, 0x3019ca05, + 0xe4f3b99e, 0xd9ca5ce8, 0x0d202f73, 0xa3b89605, 0x7752e59e, + 0x4a6b00e8, 0x9e817373, 0x165a7305, 0xc2b0009e, 0xff89e5e8, + 0x2b639673, 0x85fb2f05, 0x51115c9e, 0x6c28b9e8, 0xb8c2ca73, + 0x7c9fb804, 0xa875cb9f, 0x954c2ee9, 0x41a65d72, 0xef3ee404, + 0x3bd4979f, 0x06ed72e9, 0xd2070172, 0x5adc0104, 0x8e36729f, + 0xb30f97e9, 0x67e5e472, 0xc97d5d04, 0x1d972e9f, 0x20aecbe9, + 0xf444b872, 0xa8152f07, 0x7cff5c9c, 0x41c6b9ea, 0x952cca71, + 0x3bb47307, 0xef5e009c, 0xd267e5ea, 0x068d9671, 0x8e569607, + 0x5abce59c, 0x678500ea, 0xb36f7371, 0x1df7ca07, 0xc91db99c, + 0xf4245cea, 0x20ce2f71, 0xe4935d06, 0x30792e9d, 0x0d40cbeb, + 0xd9aab870, 0x77320106, 0xa3d8729d, 0x9ee197eb, 0x4a0be470, + 0xc2d0e406, 0x163a979d, 0x2b0372eb, 0xffe90170, 0x5171b806, + 0x859bcb9d, 0xb8a22eeb, 0x6c485d70, 0x6032940b, 0xb4d8e790, + 0x89e102e6, 0x5d0b717d, 0xf393c80b, 0x2779bb90, 0x1a405ee6, + 0xceaa2d7d, 0x46712d0b, 0x929b5e90, 0xafa2bbe6, 0x7b48c87d, + 0xd5d0710b, 0x013a0290, 0x3c03e7e6, 0xe8e9947d, 0x2cb4e60a, + 0xf85e9591, 0xc56770e7, 0x118d037c, 0xbf15ba0a, 0x6bffc991, + 0x56c62ce7, 0x822c5f7c, 0x0af75f0a, 0xde1d2c91, 0xe324c9e7, + 0x37ceba7c, 0x9956030a, 0x4dbc7091, 0x708595e7, 0xa46fe67c, + 0xf83e7109, 0x2cd40292, 0x11ede7e4, 0xc507947f, 0x6b9f2d09, + 0xbf755e92, 0x824cbbe4, 0x56a6c87f, 0xde7dc809, 0x0a97bb92, + 0x37ae5ee4, 0xe3442d7f, 0x4ddc9409, 0x9936e792, 0xa40f02e4, + 0x70e5717f, 0xb4b80308, 0x60527093, 0x5d6b95e5, 0x8981e67e, + 0x27195f08, 0xf3f32c93, 0xcecac9e5, 0x1a20ba7e, 0x92fbba08, + 0x4611c993, 0x7b282ce5, 0xafc25f7e, 0x015ae608, 0xd5b09593, + 0xe88970e5, 0x3c63037e, 0x502b5e0e, 0x84c12d95, 0xb9f8c8e3, + 0x6d12bb78, 0xc38a020e, 0x17607195, 0x2a5994e3, 0xfeb3e778, + 0x7668e70e, 0xa2829495, 0x9fbb71e3, 0x4b510278, 0xe5c9bb0e, + 0x3123c895, 0x0c1a2de3, 0xd8f05e78, 0x1cad2c0f, 0xc8475f94, + 0xf57ebae2, 0x2194c979, 0x8f0c700f, 0x5be60394, 0x66dfe6e2, + 0xb2359579, 0x3aee950f, 0xee04e694, 0xd33d03e2, 0x07d77079, + 0xa94fc90f, 0x7da5ba94, 0x409c5fe2, 0x94762c79, 0xc827bb0c, + 0x1ccdc897, 0x21f42de1, 0xf51e5e7a, 0x5b86e70c, 0x8f6c9497, + 0xb25571e1, 0x66bf027a, 0xee64020c, 0x3a8e7197, 0x07b794e1, + 0xd35de77a, 0x7dc55e0c, 0xa92f2d97, 0x9416c8e1, 0x40fcbb7a, + 0x84a1c90d, 0x504bba96, 0x6d725fe0, 0xb9982c7b, 0x1700950d, + 0xc3eae696, 0xfed303e0, 0x2a39707b, 0xa2e2700d, 0x76080396, + 0x4b31e6e0, 0x9fdb957b, 0x31432c0d, 0xe5a95f96, 0xd890bae0, + 0x0c7ac97b}, + {0x00000000, 0x27652581, 0x0fcc3bd9, 0x28a91e58, 0x5f9e0669, + 0x78fb23e8, 0x50523db0, 0x77371831, 0xbe3c0dd2, 0x99592853, + 0xb1f0360b, 0x9695138a, 0xe1a20bbb, 0xc6c72e3a, 0xee6e3062, + 0xc90b15e3, 0x3d7f6b7f, 0x1a1a4efe, 0x32b350a6, 0x15d67527, + 0x62e16d16, 0x45844897, 0x6d2d56cf, 0x4a48734e, 0x834366ad, + 0xa426432c, 0x8c8f5d74, 0xabea78f5, 0xdcdd60c4, 0xfbb84545, + 0xd3115b1d, 0xf4747e9c, 0x7afed6fe, 0x5d9bf37f, 0x7532ed27, + 0x5257c8a6, 0x2560d097, 0x0205f516, 0x2aaceb4e, 0x0dc9cecf, + 0xc4c2db2c, 0xe3a7fead, 0xcb0ee0f5, 0xec6bc574, 0x9b5cdd45, + 0xbc39f8c4, 0x9490e69c, 0xb3f5c31d, 0x4781bd81, 0x60e49800, + 0x484d8658, 0x6f28a3d9, 0x181fbbe8, 0x3f7a9e69, 0x17d38031, + 0x30b6a5b0, 0xf9bdb053, 0xded895d2, 0xf6718b8a, 0xd114ae0b, + 0xa623b63a, 0x814693bb, 0xa9ef8de3, 0x8e8aa862, 0xb5fadc26, + 0x929ff9a7, 0xba36e7ff, 0x9d53c27e, 0xea64da4f, 0xcd01ffce, + 0xe5a8e196, 0xc2cdc417, 0x0bc6d1f4, 0x2ca3f475, 0x040aea2d, + 0x236fcfac, 0x5458d79d, 0x733df21c, 0x5b94ec44, 0x7cf1c9c5, + 0x8885b759, 0xafe092d8, 0x87498c80, 0xa02ca901, 0xd71bb130, + 0xf07e94b1, 0xd8d78ae9, 0xffb2af68, 0x36b9ba8b, 0x11dc9f0a, + 0x39758152, 0x1e10a4d3, 0x6927bce2, 0x4e429963, 0x66eb873b, + 0x418ea2ba, 0xcf040ad8, 0xe8612f59, 0xc0c83101, 0xe7ad1480, + 0x909a0cb1, 0xb7ff2930, 0x9f563768, 0xb83312e9, 0x7138070a, + 0x565d228b, 0x7ef43cd3, 0x59911952, 0x2ea60163, 0x09c324e2, + 0x216a3aba, 0x060f1f3b, 0xf27b61a7, 0xd51e4426, 0xfdb75a7e, + 0xdad27fff, 0xade567ce, 0x8a80424f, 0xa2295c17, 0x854c7996, + 0x4c476c75, 0x6b2249f4, 0x438b57ac, 0x64ee722d, 0x13d96a1c, + 0x34bc4f9d, 0x1c1551c5, 0x3b707444, 0x6af5b94d, 0x4d909ccc, + 0x65398294, 0x425ca715, 0x356bbf24, 0x120e9aa5, 0x3aa784fd, + 0x1dc2a17c, 0xd4c9b49f, 0xf3ac911e, 0xdb058f46, 0xfc60aac7, + 0x8b57b2f6, 0xac329777, 0x849b892f, 0xa3feacae, 0x578ad232, + 0x70eff7b3, 0x5846e9eb, 0x7f23cc6a, 0x0814d45b, 0x2f71f1da, + 0x07d8ef82, 0x20bdca03, 0xe9b6dfe0, 0xced3fa61, 0xe67ae439, + 0xc11fc1b8, 0xb628d989, 0x914dfc08, 0xb9e4e250, 0x9e81c7d1, + 0x100b6fb3, 0x376e4a32, 0x1fc7546a, 0x38a271eb, 0x4f9569da, + 0x68f04c5b, 0x40595203, 0x673c7782, 0xae376261, 0x895247e0, + 0xa1fb59b8, 0x869e7c39, 0xf1a96408, 0xd6cc4189, 0xfe655fd1, + 0xd9007a50, 0x2d7404cc, 0x0a11214d, 0x22b83f15, 0x05dd1a94, + 0x72ea02a5, 0x558f2724, 0x7d26397c, 0x5a431cfd, 0x9348091e, + 0xb42d2c9f, 0x9c8432c7, 0xbbe11746, 0xccd60f77, 0xebb32af6, + 0xc31a34ae, 0xe47f112f, 0xdf0f656b, 0xf86a40ea, 0xd0c35eb2, + 0xf7a67b33, 0x80916302, 0xa7f44683, 0x8f5d58db, 0xa8387d5a, + 0x613368b9, 0x46564d38, 0x6eff5360, 0x499a76e1, 0x3ead6ed0, + 0x19c84b51, 0x31615509, 0x16047088, 0xe2700e14, 0xc5152b95, + 0xedbc35cd, 0xcad9104c, 0xbdee087d, 0x9a8b2dfc, 0xb22233a4, + 0x95471625, 0x5c4c03c6, 0x7b292647, 0x5380381f, 0x74e51d9e, + 0x03d205af, 0x24b7202e, 0x0c1e3e76, 0x2b7b1bf7, 0xa5f1b395, + 0x82949614, 0xaa3d884c, 0x8d58adcd, 0xfa6fb5fc, 0xdd0a907d, + 0xf5a38e25, 0xd2c6aba4, 0x1bcdbe47, 0x3ca89bc6, 0x1401859e, + 0x3364a01f, 0x4453b82e, 0x63369daf, 0x4b9f83f7, 0x6cfaa676, + 0x988ed8ea, 0xbfebfd6b, 0x9742e333, 0xb027c6b2, 0xc710de83, + 0xe075fb02, 0xc8dce55a, 0xefb9c0db, 0x26b2d538, 0x01d7f0b9, + 0x297eeee1, 0x0e1bcb60, 0x792cd351, 0x5e49f6d0, 0x76e0e888, + 0x5185cd09}}; + +#endif + +#endif + +#endif + +local const z_crc_t FAR x2n_table[] = { + 0x40000000, 0x20000000, 0x08000000, 0x00800000, 0x00008000, + 0xedb88320, 0xb1e6b092, 0xa06a2517, 0xed627dae, 0x88d14467, + 0xd7bbfe6a, 0xec447f11, 0x8e7ea170, 0x6427800e, 0x4d47bae0, + 0x09fe548f, 0x83852d0f, 0x30362f1a, 0x7b5a9cc3, 0x31fec169, + 0x9fec022a, 0x6c8dedc4, 0x15d6874d, 0x5fde7a4e, 0xbad90e37, + 0x2e4e5eef, 0x4eaba214, 0xa8a472c0, 0x429a969e, 0x148d302a, + 0xc40ba6d0, 0xc4e22c3c}; diff --git a/lib/zlib/inffast.c b/lib/zlib/inffast.c index 0dbd1dbc0..1fec7f363 100644 --- a/lib/zlib/inffast.c +++ b/lib/zlib/inffast.c @@ -70,7 +70,7 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ code const FAR *dcode; /* local strm->distcode */ unsigned lmask; /* mask for first level of length codes */ unsigned dmask; /* mask for first level of distance codes */ - code here; /* retrieved table entry */ + code const *here; /* retrieved table entry */ unsigned op; /* code bits, operation, extra bits, or */ /* window position, window bytes to copy */ unsigned len; /* match length, unused bytes */ @@ -107,20 +107,20 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ hold += (unsigned long)(*in++) << bits; bits += 8; } - here = lcode[hold & lmask]; + here = lcode + (hold & lmask); dolen: - op = (unsigned)(here.bits); + op = (unsigned)(here->bits); hold >>= op; bits -= op; - op = (unsigned)(here.op); + op = (unsigned)(here->op); if (op == 0) { /* literal */ - Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ? + Tracevv((stderr, here->val >= 0x20 && here->val < 0x7f ? "inflate: literal '%c'\n" : - "inflate: literal 0x%02x\n", here.val)); - *out++ = (unsigned char)(here.val); + "inflate: literal 0x%02x\n", here->val)); + *out++ = (unsigned char)(here->val); } else if (op & 16) { /* length base */ - len = (unsigned)(here.val); + len = (unsigned)(here->val); op &= 15; /* number of extra bits */ if (op) { if (bits < op) { @@ -138,14 +138,14 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ hold += (unsigned long)(*in++) << bits; bits += 8; } - here = dcode[hold & dmask]; + here = dcode + (hold & dmask); dodist: - op = (unsigned)(here.bits); + op = (unsigned)(here->bits); hold >>= op; bits -= op; - op = (unsigned)(here.op); + op = (unsigned)(here->op); if (op & 16) { /* distance base */ - dist = (unsigned)(here.val); + dist = (unsigned)(here->val); op &= 15; /* number of extra bits */ if (bits < op) { hold += (unsigned long)(*in++) << bits; @@ -264,7 +264,7 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ } } else if ((op & 64) == 0) { /* 2nd level distance code */ - here = dcode[here.val + (hold & ((1U << op) - 1))]; + here = dcode + here->val + (hold & ((1U << op) - 1)); goto dodist; } else { @@ -274,7 +274,7 @@ unsigned start; /* inflate()'s starting value for strm->avail_out */ } } else if ((op & 64) == 0) { /* 2nd level length code */ - here = lcode[here.val + (hold & ((1U << op) - 1))]; + here = lcode + here->val + (hold & ((1U << op) - 1)); goto dolen; } else if (op & 32) { /* end-of-block */ diff --git a/lib/zlib/inflate.c b/lib/zlib/inflate.c index ac333e8c2..8acbef44e 100644 --- a/lib/zlib/inflate.c +++ b/lib/zlib/inflate.c @@ -1,5 +1,5 @@ /* inflate.c -- zlib decompression - * Copyright (C) 1995-2016 Mark Adler + * Copyright (C) 1995-2022 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h */ @@ -130,6 +130,7 @@ z_streamp strm; state->mode = HEAD; state->last = 0; state->havedict = 0; + state->flags = -1; state->dmax = 32768U; state->head = Z_NULL; state->hold = 0; @@ -167,6 +168,8 @@ int windowBits; /* extract wrap request from windowBits parameter */ if (windowBits < 0) { + if (windowBits < -15) + return Z_STREAM_ERROR; wrap = 0; windowBits = -windowBits; } @@ -447,10 +450,10 @@ unsigned copy; /* check function to use adler32() for zlib or crc32() for gzip */ #ifdef GUNZIP -# define UPDATE(check, buf, len) \ +# define UPDATE_CHECK(check, buf, len) \ (state->flags ? crc32(check, buf, len) : adler32(check, buf, len)) #else -# define UPDATE(check, buf, len) adler32(check, buf, len) +# define UPDATE_CHECK(check, buf, len) adler32(check, buf, len) #endif /* check macros for header crc */ @@ -670,7 +673,6 @@ int flush; state->mode = FLAGS; break; } - state->flags = 0; /* expect zlib header */ if (state->head != Z_NULL) state->head->done = -1; if (!(state->wrap & 1) || /* check if zlib header allowed */ @@ -697,6 +699,7 @@ int flush; break; } state->dmax = 1U << len; + state->flags = 0; /* indicate zlib header */ Tracev((stderr, "inflate: zlib header ok\n")); strm->adler = state->check = adler32(0L, Z_NULL, 0); state->mode = hold & 0x200 ? DICTID : TYPE; @@ -722,6 +725,7 @@ int flush; CRC2(state->check, hold); INITBITS(); state->mode = TIME; + /* fallthrough */ case TIME: NEEDBITS(32); if (state->head != Z_NULL) @@ -730,6 +734,7 @@ int flush; CRC4(state->check, hold); INITBITS(); state->mode = OS; + /* fallthrough */ case OS: NEEDBITS(16); if (state->head != Z_NULL) { @@ -740,6 +745,7 @@ int flush; CRC2(state->check, hold); INITBITS(); state->mode = EXLEN; + /* fallthrough */ case EXLEN: if (state->flags & 0x0400) { NEEDBITS(16); @@ -753,14 +759,16 @@ int flush; else if (state->head != Z_NULL) state->head->extra = Z_NULL; state->mode = EXTRA; + /* fallthrough */ case EXTRA: if (state->flags & 0x0400) { copy = state->length; if (copy > have) copy = have; if (copy) { if (state->head != Z_NULL && - state->head->extra != Z_NULL) { - len = state->head->extra_len - state->length; + state->head->extra != Z_NULL && + (len = state->head->extra_len - state->length) < + state->head->extra_max) { zmemcpy(state->head->extra + len, next, len + copy > state->head->extra_max ? state->head->extra_max - len : copy); @@ -775,6 +783,7 @@ int flush; } state->length = 0; state->mode = NAME; + /* fallthrough */ case NAME: if (state->flags & 0x0800) { if (have == 0) goto inf_leave; @@ -796,6 +805,7 @@ int flush; state->head->name = Z_NULL; state->length = 0; state->mode = COMMENT; + /* fallthrough */ case COMMENT: if (state->flags & 0x1000) { if (have == 0) goto inf_leave; @@ -816,6 +826,7 @@ int flush; else if (state->head != Z_NULL) state->head->comment = Z_NULL; state->mode = HCRC; + /* fallthrough */ case HCRC: if (state->flags & 0x0200) { NEEDBITS(16); @@ -839,6 +850,7 @@ int flush; strm->adler = state->check = ZSWAP32(hold); INITBITS(); state->mode = DICT; + /* fallthrough */ case DICT: if (state->havedict == 0) { RESTORE(); @@ -846,8 +858,10 @@ int flush; } strm->adler = state->check = adler32(0L, Z_NULL, 0); state->mode = TYPE; + /* fallthrough */ case TYPE: if (flush == Z_BLOCK || flush == Z_TREES) goto inf_leave; + /* fallthrough */ case TYPEDO: if (state->last) { BYTEBITS(); @@ -898,8 +912,10 @@ int flush; INITBITS(); state->mode = COPY_; if (flush == Z_TREES) goto inf_leave; + /* fallthrough */ case COPY_: state->mode = COPY; + /* fallthrough */ case COPY: copy = state->length; if (copy) { @@ -935,6 +951,7 @@ int flush; Tracev((stderr, "inflate: table sizes ok\n")); state->have = 0; state->mode = LENLENS; + /* fallthrough */ case LENLENS: while (state->have < state->ncode) { NEEDBITS(3); @@ -956,6 +973,7 @@ int flush; Tracev((stderr, "inflate: code lengths ok\n")); state->have = 0; state->mode = CODELENS; + /* fallthrough */ case CODELENS: while (state->have < state->nlen + state->ndist) { for (;;) { @@ -1039,8 +1057,10 @@ int flush; Tracev((stderr, "inflate: codes ok\n")); state->mode = LEN_; if (flush == Z_TREES) goto inf_leave; + /* fallthrough */ case LEN_: state->mode = LEN; + /* fallthrough */ case LEN: if (have >= 6 && left >= 258) { RESTORE(); @@ -1090,6 +1110,7 @@ int flush; } state->extra = (unsigned)(here.op) & 15; state->mode = LENEXT; + /* fallthrough */ case LENEXT: if (state->extra) { NEEDBITS(state->extra); @@ -1100,6 +1121,7 @@ int flush; Tracevv((stderr, "inflate: length %u\n", state->length)); state->was = state->length; state->mode = DIST; + /* fallthrough */ case DIST: for (;;) { here = state->distcode[BITS(state->distbits)]; @@ -1127,6 +1149,7 @@ int flush; state->offset = (unsigned)here.val; state->extra = (unsigned)(here.op) & 15; state->mode = DISTEXT; + /* fallthrough */ case DISTEXT: if (state->extra) { NEEDBITS(state->extra); @@ -1143,6 +1166,7 @@ int flush; #endif Tracevv((stderr, "inflate: distance %u\n", state->offset)); state->mode = MATCH; + /* fallthrough */ case MATCH: if (left == 0) goto inf_leave; copy = out - left; @@ -1202,7 +1226,7 @@ int flush; state->total += out; if ((state->wrap & 4) && out) strm->adler = state->check = - UPDATE(state->check, put - out, out); + UPDATE_CHECK(state->check, put - out, out); out = left; if ((state->wrap & 4) && ( #ifdef GUNZIP @@ -1218,10 +1242,11 @@ int flush; } #ifdef GUNZIP state->mode = LENGTH; + /* fallthrough */ case LENGTH: if (state->wrap && state->flags) { NEEDBITS(32); - if (hold != (state->total & 0xffffffffUL)) { + if ((state->wrap & 4) && hold != (state->total & 0xffffffff)) { strm->msg = (char *)"incorrect length check"; state->mode = BAD; break; @@ -1231,6 +1256,7 @@ int flush; } #endif state->mode = DONE; + /* fallthrough */ case DONE: ret = Z_STREAM_END; goto inf_leave; @@ -1240,6 +1266,7 @@ int flush; case MEM: return Z_MEM_ERROR; case SYNC: + /* fallthrough */ default: return Z_STREAM_ERROR; } @@ -1265,7 +1292,7 @@ int flush; state->total += out; if ((state->wrap & 4) && out) strm->adler = state->check = - UPDATE(state->check, strm->next_out - out, out); + UPDATE_CHECK(state->check, strm->next_out - out, out); strm->data_type = (int)state->bits + (state->last ? 64 : 0) + (state->mode == TYPE ? 128 : 0) + (state->mode == LEN_ || state->mode == COPY_ ? 256 : 0); @@ -1401,6 +1428,7 @@ int ZEXPORT inflateSync(strm) z_streamp strm; { unsigned len; /* number of bytes to look at or looked at */ + int flags; /* temporary to save header status */ unsigned long in, out; /* temporary to save total_in and total_out */ unsigned char buf[4]; /* to restore bit buffer to byte string */ struct inflate_state FAR *state; @@ -1433,9 +1461,15 @@ z_streamp strm; /* return no joy or set up to restart inflate() on a new block */ if (state->have != 4) return Z_DATA_ERROR; + if (state->flags == -1) + state->wrap = 0; /* if no header yet, treat as raw */ + else + state->wrap &= ~4; /* no point in computing a check value now */ + flags = state->flags; in = strm->total_in; out = strm->total_out; inflateReset(strm); strm->total_in = in; strm->total_out = out; + state->flags = flags; state->mode = TYPE; return Z_OK; } @@ -1531,7 +1565,7 @@ int check; if (inflateStateCheck(strm)) return Z_STREAM_ERROR; state = (struct inflate_state FAR *)strm->state; - if (check) + if (check && state->wrap) state->wrap |= 4; else state->wrap &= ~4; diff --git a/lib/zlib/inflate.h b/lib/zlib/inflate.h index a46cce6b6..f127b6b1f 100644 --- a/lib/zlib/inflate.h +++ b/lib/zlib/inflate.h @@ -1,5 +1,5 @@ /* inflate.h -- internal inflate state definition - * Copyright (C) 1995-2016 Mark Adler + * Copyright (C) 1995-2019 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h */ @@ -86,7 +86,8 @@ struct inflate_state { int wrap; /* bit 0 true for zlib, bit 1 true for gzip, bit 2 true to validate check value */ int havedict; /* true if dictionary provided */ - int flags; /* gzip header method and flags (0 if zlib) */ + int flags; /* gzip header method and flags, 0 if zlib, or + -1 if raw or no header yet */ unsigned dmax; /* zlib header max distance (INFLATE_STRICT) */ unsigned long check; /* protected copy of check value */ unsigned long total; /* protected copy of output count */ diff --git a/lib/zlib/inftrees.c b/lib/zlib/inftrees.c index 2ea08fc13..57d2793be 100644 --- a/lib/zlib/inftrees.c +++ b/lib/zlib/inftrees.c @@ -1,5 +1,5 @@ /* inftrees.c -- generate Huffman trees for efficient decoding - * Copyright (C) 1995-2017 Mark Adler + * Copyright (C) 1995-2022 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h */ @@ -9,7 +9,7 @@ #define MAXBITS 15 const char inflate_copyright[] = - " inflate 1.2.11 Copyright 1995-2017 Mark Adler "; + " inflate 1.2.13 Copyright 1995-2022 Mark Adler "; /* If you use the zlib library in a product, an acknowledgment is welcome in the documentation of your product. If for some reason you cannot @@ -62,7 +62,7 @@ unsigned short FAR *work; 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0}; static const unsigned short lext[31] = { /* Length codes 257..285 extra */ 16, 16, 16, 16, 16, 16, 16, 16, 17, 17, 17, 17, 18, 18, 18, 18, - 19, 19, 19, 19, 20, 20, 20, 20, 21, 21, 21, 21, 16, 77, 202}; + 19, 19, 19, 19, 20, 20, 20, 20, 21, 21, 21, 21, 16, 194, 65}; static const unsigned short dbase[32] = { /* Distance codes 0..29 base */ 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193, 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145, diff --git a/lib/zlib/inftrees.h b/lib/zlib/inftrees.h index baa53a0b1..f53665311 100644 --- a/lib/zlib/inftrees.h +++ b/lib/zlib/inftrees.h @@ -38,7 +38,7 @@ typedef struct { /* Maximum size of the dynamic table. The maximum number of code structures is 1444, which is the sum of 852 for literal/length codes and 592 for distance codes. These values were found by exhaustive searches using the program - examples/enough.c found in the zlib distribtution. The arguments to that + examples/enough.c found in the zlib distribution. The arguments to that program are the number of symbols, the initial root table size, and the maximum bit length of a code. "enough 286 9 15" for literal/length codes returns returns 852, and "enough 30 6 15" for distance codes returns 592. diff --git a/lib/zlib/zconf.h b/lib/zlib/zconf.h index 5e1d68a00..bf977d3e7 100644 --- a/lib/zlib/zconf.h +++ b/lib/zlib/zconf.h @@ -38,6 +38,9 @@ # define crc32 z_crc32 # define crc32_combine z_crc32_combine # define crc32_combine64 z_crc32_combine64 +# define crc32_combine_gen z_crc32_combine_gen +# define crc32_combine_gen64 z_crc32_combine_gen64 +# define crc32_combine_op z_crc32_combine_op # define crc32_z z_crc32_z # define deflate z_deflate # define deflateBound z_deflateBound @@ -349,6 +352,9 @@ # ifdef FAR # undef FAR # endif +# ifndef WIN32_LEAN_AND_MEAN +# define WIN32_LEAN_AND_MEAN +# endif # include <windows.h> /* No need for _export, use ZLIB.DEF instead. */ /* For complete Windows compatibility, use WINAPI, not __stdcall. */ @@ -467,11 +473,18 @@ typedef uLong FAR uLongf; # undef _LARGEFILE64_SOURCE #endif -#if defined(__WATCOMC__) && !defined(Z_HAVE_UNISTD_H) -# define Z_HAVE_UNISTD_H +#ifndef Z_HAVE_UNISTD_H +# ifdef __WATCOMC__ +# define Z_HAVE_UNISTD_H +# endif +#endif +#ifndef Z_HAVE_UNISTD_H +# if defined(_LARGEFILE64_SOURCE) && !defined(_WIN32) +# define Z_HAVE_UNISTD_H +# endif #endif #ifndef Z_SOLO -# if defined(Z_HAVE_UNISTD_H) || defined(_LARGEFILE64_SOURCE) +# if defined(Z_HAVE_UNISTD_H) # include <unistd.h> /* for SEEK_*, off_t, and _LFS64_LARGEFILE */ # ifdef VMS # include <unixio.h> /* for off_t */ diff --git a/lib/zlib/zlib.h b/lib/zlib/zlib.h index f09cdaf1e..953cb5012 100644 --- a/lib/zlib/zlib.h +++ b/lib/zlib/zlib.h @@ -1,7 +1,7 @@ /* zlib.h -- interface of the 'zlib' general purpose compression library - version 1.2.11, January 15th, 2017 + version 1.2.13, October 13th, 2022 - Copyright (C) 1995-2017 Jean-loup Gailly and Mark Adler + Copyright (C) 1995-2022 Jean-loup Gailly and Mark Adler This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages @@ -37,11 +37,11 @@ extern "C" { #endif -#define ZLIB_VERSION "1.2.11" -#define ZLIB_VERNUM 0x12b0 +#define ZLIB_VERSION "1.2.13" +#define ZLIB_VERNUM 0x12d0 #define ZLIB_VER_MAJOR 1 #define ZLIB_VER_MINOR 2 -#define ZLIB_VER_REVISION 11 +#define ZLIB_VER_REVISION 13 #define ZLIB_VER_SUBREVISION 0 /* @@ -276,7 +276,7 @@ ZEXTERN int ZEXPORT deflate OF((z_streamp strm, int flush)); == 0), or after each call of deflate(). If deflate returns Z_OK and with zero avail_out, it must be called again after making room in the output buffer because there might be more output pending. See deflatePending(), - which can be used if desired to determine whether or not there is more ouput + which can be used if desired to determine whether or not there is more output in that case. Normally the parameter flush is set to Z_NO_FLUSH, which allows deflate to @@ -543,8 +543,7 @@ ZEXTERN int ZEXPORT deflateInit2 OF((z_streamp strm, int strategy)); This is another version of deflateInit with more compression options. The - fields next_in, zalloc, zfree and opaque must be initialized before by the - caller. + fields zalloc, zfree and opaque must be initialized before by the caller. The method parameter is the compression method. It must be Z_DEFLATED in this version of the library. @@ -661,7 +660,7 @@ ZEXTERN int ZEXPORT deflateGetDictionary OF((z_streamp strm, to dictionary. dictionary must have enough space, where 32768 bytes is always enough. If deflateGetDictionary() is called with dictionary equal to Z_NULL, then only the dictionary length is returned, and nothing is copied. - Similary, if dictLength is Z_NULL, then it is not set. + Similarly, if dictLength is Z_NULL, then it is not set. deflateGetDictionary() may return a length less than the window size, even when more than the window size in input has been provided. It may return up @@ -712,11 +711,12 @@ ZEXTERN int ZEXPORT deflateParams OF((z_streamp strm, used to switch between compression and straight copy of the input data, or to switch to a different kind of input data requiring a different strategy. If the compression approach (which is a function of the level) or the - strategy is changed, and if any input has been consumed in a previous - deflate() call, then the input available so far is compressed with the old - level and strategy using deflate(strm, Z_BLOCK). There are three approaches - for the compression levels 0, 1..3, and 4..9 respectively. The new level - and strategy will take effect at the next call of deflate(). + strategy is changed, and if there have been any deflate() calls since the + state was initialized or reset, then the input available so far is + compressed with the old level and strategy using deflate(strm, Z_BLOCK). + There are three approaches for the compression levels 0, 1..3, and 4..9 + respectively. The new level and strategy will take effect at the next call + of deflate(). If a deflate(strm, Z_BLOCK) is performed by deflateParams(), and it does not have enough output space to complete, then the parameter change will not @@ -865,9 +865,11 @@ ZEXTERN int ZEXPORT inflateInit2 OF((z_streamp strm, detection, or add 16 to decode only the gzip format (the zlib format will return a Z_DATA_ERROR). If a gzip stream is being decoded, strm->adler is a CRC-32 instead of an Adler-32. Unlike the gunzip utility and gzread() (see - below), inflate() will not automatically decode concatenated gzip streams. - inflate() will return Z_STREAM_END at the end of the gzip stream. The state - would need to be reset to continue decoding a subsequent gzip stream. + below), inflate() will *not* automatically decode concatenated gzip members. + inflate() will return Z_STREAM_END at the end of the gzip member. The state + would need to be reset to continue decoding a subsequent gzip member. This + *must* be done if there is more data after a gzip member, in order for the + decompression to be compliant with the gzip standard (RFC 1952). inflateInit2 returns Z_OK if success, Z_MEM_ERROR if there was not enough memory, Z_VERSION_ERROR if the zlib library version is incompatible with the @@ -913,7 +915,7 @@ ZEXTERN int ZEXPORT inflateGetDictionary OF((z_streamp strm, to dictionary. dictionary must have enough space, where 32768 bytes is always enough. If inflateGetDictionary() is called with dictionary equal to Z_NULL, then only the dictionary length is returned, and nothing is copied. - Similary, if dictLength is Z_NULL, then it is not set. + Similarly, if dictLength is Z_NULL, then it is not set. inflateGetDictionary returns Z_OK on success, or Z_STREAM_ERROR if the stream state is inconsistent. @@ -1302,14 +1304,14 @@ typedef struct gzFile_s *gzFile; /* semi-opaque gzip file descriptor */ /* ZEXTERN gzFile ZEXPORT gzopen OF((const char *path, const char *mode)); - Opens a gzip (.gz) file for reading or writing. The mode parameter is as - in fopen ("rb" or "wb") but can also include a compression level ("wb9") or - a strategy: 'f' for filtered data as in "wb6f", 'h' for Huffman-only - compression as in "wb1h", 'R' for run-length encoding as in "wb1R", or 'F' - for fixed code compression as in "wb9F". (See the description of - deflateInit2 for more information about the strategy parameter.) 'T' will - request transparent writing or appending with no compression and not using - the gzip format. + Open the gzip (.gz) file at path for reading and decompressing, or + compressing and writing. The mode parameter is as in fopen ("rb" or "wb") + but can also include a compression level ("wb9") or a strategy: 'f' for + filtered data as in "wb6f", 'h' for Huffman-only compression as in "wb1h", + 'R' for run-length encoding as in "wb1R", or 'F' for fixed code compression + as in "wb9F". (See the description of deflateInit2 for more information + about the strategy parameter.) 'T' will request transparent writing or + appending with no compression and not using the gzip format. "a" can be used instead of "w" to request that the gzip stream that will be written be appended to the file. "+" will result in an error, since @@ -1339,9 +1341,9 @@ ZEXTERN gzFile ZEXPORT gzopen OF((const char *path, const char *mode)); ZEXTERN gzFile ZEXPORT gzdopen OF((int fd, const char *mode)); /* - gzdopen associates a gzFile with the file descriptor fd. File descriptors - are obtained from calls like open, dup, creat, pipe or fileno (if the file - has been previously opened with fopen). The mode parameter is as in gzopen. + Associate a gzFile with the file descriptor fd. File descriptors are + obtained from calls like open, dup, creat, pipe or fileno (if the file has + been previously opened with fopen). The mode parameter is as in gzopen. The next call of gzclose on the returned gzFile will also close the file descriptor fd, just like fclose(fdopen(fd, mode)) closes the file descriptor @@ -1362,13 +1364,13 @@ ZEXTERN gzFile ZEXPORT gzdopen OF((int fd, const char *mode)); ZEXTERN int ZEXPORT gzbuffer OF((gzFile file, unsigned size)); /* - Set the internal buffer size used by this library's functions. The - default buffer size is 8192 bytes. This function must be called after - gzopen() or gzdopen(), and before any other calls that read or write the - file. The buffer memory allocation is always deferred to the first read or - write. Three times that size in buffer space is allocated. A larger buffer - size of, for example, 64K or 128K bytes will noticeably increase the speed - of decompression (reading). + Set the internal buffer size used by this library's functions for file to + size. The default buffer size is 8192 bytes. This function must be called + after gzopen() or gzdopen(), and before any other calls that read or write + the file. The buffer memory allocation is always deferred to the first read + or write. Three times that size in buffer space is allocated. A larger + buffer size of, for example, 64K or 128K bytes will noticeably increase the + speed of decompression (reading). The new buffer size also affects the maximum length for gzprintf(). @@ -1378,9 +1380,9 @@ ZEXTERN int ZEXPORT gzbuffer OF((gzFile file, unsigned size)); ZEXTERN int ZEXPORT gzsetparams OF((gzFile file, int level, int strategy)); /* - Dynamically update the compression level or strategy. See the description - of deflateInit2 for the meaning of these parameters. Previously provided - data is flushed before the parameter change. + Dynamically update the compression level and strategy for file. See the + description of deflateInit2 for the meaning of these parameters. Previously + provided data is flushed before applying the parameter changes. gzsetparams returns Z_OK if success, Z_STREAM_ERROR if the file was not opened for writing, Z_ERRNO if there is an error writing the flushed data, @@ -1389,7 +1391,7 @@ ZEXTERN int ZEXPORT gzsetparams OF((gzFile file, int level, int strategy)); ZEXTERN int ZEXPORT gzread OF((gzFile file, voidp buf, unsigned len)); /* - Reads the given number of uncompressed bytes from the compressed file. If + Read and decompress up to len uncompressed bytes from file into buf. If the input file is not in gzip format, gzread copies the given number of bytes into the buffer directly from the file. @@ -1420,11 +1422,11 @@ ZEXTERN int ZEXPORT gzread OF((gzFile file, voidp buf, unsigned len)); ZEXTERN z_size_t ZEXPORT gzfread OF((voidp buf, z_size_t size, z_size_t nitems, gzFile file)); /* - Read up to nitems items of size size from file to buf, otherwise operating - as gzread() does. This duplicates the interface of stdio's fread(), with - size_t request and return types. If the library defines size_t, then - z_size_t is identical to size_t. If not, then z_size_t is an unsigned - integer type that can contain a pointer. + Read and decompress up to nitems items of size size from file into buf, + otherwise operating as gzread() does. This duplicates the interface of + stdio's fread(), with size_t request and return types. If the library + defines size_t, then z_size_t is identical to size_t. If not, then z_size_t + is an unsigned integer type that can contain a pointer. gzfread() returns the number of full items read of size size, or zero if the end of the file was reached and a full item could not be read, or if @@ -1435,26 +1437,24 @@ ZEXTERN z_size_t ZEXPORT gzfread OF((voidp buf, z_size_t size, z_size_t nitems, In the event that the end of file is reached and only a partial item is available at the end, i.e. the remaining uncompressed data length is not a - multiple of size, then the final partial item is nevetheless read into buf + multiple of size, then the final partial item is nevertheless read into buf and the end-of-file flag is set. The length of the partial item read is not provided, but could be inferred from the result of gztell(). This behavior is the same as the behavior of fread() implementations in common libraries, but it prevents the direct use of gzfread() to read a concurrently written - file, reseting and retrying on end-of-file, when size is not 1. + file, resetting and retrying on end-of-file, when size is not 1. */ -ZEXTERN int ZEXPORT gzwrite OF((gzFile file, - voidpc buf, unsigned len)); +ZEXTERN int ZEXPORT gzwrite OF((gzFile file, voidpc buf, unsigned len)); /* - Writes the given number of uncompressed bytes into the compressed file. - gzwrite returns the number of uncompressed bytes written or 0 in case of - error. + Compress and write the len uncompressed bytes at buf to file. gzwrite + returns the number of uncompressed bytes written or 0 in case of error. */ ZEXTERN z_size_t ZEXPORT gzfwrite OF((voidpc buf, z_size_t size, z_size_t nitems, gzFile file)); /* - gzfwrite() writes nitems items of size size from buf to file, duplicating + Compress and write nitems items of size size from buf to file, duplicating the interface of stdio's fwrite(), with size_t request and return types. If the library defines size_t, then z_size_t is identical to size_t. If not, then z_size_t is an unsigned integer type that can contain a pointer. @@ -1467,22 +1467,22 @@ ZEXTERN z_size_t ZEXPORT gzfwrite OF((voidpc buf, z_size_t size, ZEXTERN int ZEXPORTVA gzprintf Z_ARG((gzFile file, const char *format, ...)); /* - Converts, formats, and writes the arguments to the compressed file under - control of the format string, as in fprintf. gzprintf returns the number of + Convert, format, compress, and write the arguments (...) to file under + control of the string format, as in fprintf. gzprintf returns the number of uncompressed bytes actually written, or a negative zlib error code in case of error. The number of uncompressed bytes written is limited to 8191, or one less than the buffer size given to gzbuffer(). The caller should assure that this limit is not exceeded. If it is exceeded, then gzprintf() will return an error (0) with nothing written. In this case, there may also be a buffer overflow with unpredictable consequences, which is possible only if - zlib was compiled with the insecure functions sprintf() or vsprintf() + zlib was compiled with the insecure functions sprintf() or vsprintf(), because the secure snprintf() or vsnprintf() functions were not available. This can be determined using zlibCompileFlags(). */ ZEXTERN int ZEXPORT gzputs OF((gzFile file, const char *s)); /* - Writes the given null-terminated string to the compressed file, excluding + Compress and write the given null-terminated string s to file, excluding the terminating null character. gzputs returns the number of characters written, or -1 in case of error. @@ -1490,11 +1490,12 @@ ZEXTERN int ZEXPORT gzputs OF((gzFile file, const char *s)); ZEXTERN char * ZEXPORT gzgets OF((gzFile file, char *buf, int len)); /* - Reads bytes from the compressed file until len-1 characters are read, or a - newline character is read and transferred to buf, or an end-of-file - condition is encountered. If any characters are read or if len == 1, the - string is terminated with a null character. If no characters are read due - to an end-of-file or len < 1, then the buffer is left untouched. + Read and decompress bytes from file into buf, until len-1 characters are + read, or until a newline character is read and transferred to buf, or an + end-of-file condition is encountered. If any characters are read or if len + is one, the string is terminated with a null character. If no characters + are read due to an end-of-file or len is less than one, then the buffer is + left untouched. gzgets returns buf which is a null-terminated string, or it returns NULL for end-of-file or in case of error. If there was an error, the contents at @@ -1503,13 +1504,13 @@ ZEXTERN char * ZEXPORT gzgets OF((gzFile file, char *buf, int len)); ZEXTERN int ZEXPORT gzputc OF((gzFile file, int c)); /* - Writes c, converted to an unsigned char, into the compressed file. gzputc + Compress and write c, converted to an unsigned char, into file. gzputc returns the value that was written, or -1 in case of error. */ ZEXTERN int ZEXPORT gzgetc OF((gzFile file)); /* - Reads one byte from the compressed file. gzgetc returns this byte or -1 + Read and decompress one byte from file. gzgetc returns this byte or -1 in case of end of file or error. This is implemented as a macro for speed. As such, it does not do all of the checking the other functions do. I.e. it does not check to see if file is NULL, nor whether the structure file @@ -1518,8 +1519,8 @@ ZEXTERN int ZEXPORT gzgetc OF((gzFile file)); ZEXTERN int ZEXPORT gzungetc OF((int c, gzFile file)); /* - Push one character back onto the stream to be read as the first character - on the next read. At least one character of push-back is allowed. + Push c back onto the stream for file to be read as the first character on + the next read. At least one character of push-back is always allowed. gzungetc() returns the character pushed, or -1 on failure. gzungetc() will fail if c is -1, and may fail if a character has been pushed but not read yet. If gzungetc is used immediately after gzopen or gzdopen, at least the @@ -1530,9 +1531,9 @@ ZEXTERN int ZEXPORT gzungetc OF((int c, gzFile file)); ZEXTERN int ZEXPORT gzflush OF((gzFile file, int flush)); /* - Flushes all pending output into the compressed file. The parameter flush - is as in the deflate() function. The return value is the zlib error number - (see function gzerror below). gzflush is only permitted when writing. + Flush all pending output to file. The parameter flush is as in the + deflate() function. The return value is the zlib error number (see function + gzerror below). gzflush is only permitted when writing. If the flush parameter is Z_FINISH, the remaining data is written and the gzip stream is completed in the output. If gzwrite() is called again, a new @@ -1547,8 +1548,8 @@ ZEXTERN int ZEXPORT gzflush OF((gzFile file, int flush)); ZEXTERN z_off_t ZEXPORT gzseek OF((gzFile file, z_off_t offset, int whence)); - Sets the starting position for the next gzread or gzwrite on the given - compressed file. The offset represents a number of bytes in the + Set the starting position to offset relative to whence for the next gzread + or gzwrite on file. The offset represents a number of bytes in the uncompressed data stream. The whence parameter is defined as in lseek(2); the value SEEK_END is not supported. @@ -1565,18 +1566,18 @@ ZEXTERN z_off_t ZEXPORT gzseek OF((gzFile file, ZEXTERN int ZEXPORT gzrewind OF((gzFile file)); /* - Rewinds the given file. This function is supported only for reading. + Rewind file. This function is supported only for reading. - gzrewind(file) is equivalent to (int)gzseek(file, 0L, SEEK_SET) + gzrewind(file) is equivalent to (int)gzseek(file, 0L, SEEK_SET). */ /* ZEXTERN z_off_t ZEXPORT gztell OF((gzFile file)); - Returns the starting position for the next gzread or gzwrite on the given - compressed file. This position represents a number of bytes in the - uncompressed data stream, and is zero when starting, even if appending or - reading a gzip stream from the middle of a file using gzdopen(). + Return the starting position for the next gzread or gzwrite on file. + This position represents a number of bytes in the uncompressed data stream, + and is zero when starting, even if appending or reading a gzip stream from + the middle of a file using gzdopen(). gztell(file) is equivalent to gzseek(file, 0L, SEEK_CUR) */ @@ -1584,22 +1585,22 @@ ZEXTERN z_off_t ZEXPORT gztell OF((gzFile file)); /* ZEXTERN z_off_t ZEXPORT gzoffset OF((gzFile file)); - Returns the current offset in the file being read or written. This offset - includes the count of bytes that precede the gzip stream, for example when - appending or when using gzdopen() for reading. When reading, the offset - does not include as yet unused buffered input. This information can be used - for a progress indicator. On error, gzoffset() returns -1. + Return the current compressed (actual) read or write offset of file. This + offset includes the count of bytes that precede the gzip stream, for example + when appending or when using gzdopen() for reading. When reading, the + offset does not include as yet unused buffered input. This information can + be used for a progress indicator. On error, gzoffset() returns -1. */ ZEXTERN int ZEXPORT gzeof OF((gzFile file)); /* - Returns true (1) if the end-of-file indicator has been set while reading, - false (0) otherwise. Note that the end-of-file indicator is set only if the - read tried to go past the end of the input, but came up short. Therefore, - just like feof(), gzeof() may return false even if there is no more data to - read, in the event that the last read request was for the exact number of - bytes remaining in the input file. This will happen if the input file size - is an exact multiple of the buffer size. + Return true (1) if the end-of-file indicator for file has been set while + reading, false (0) otherwise. Note that the end-of-file indicator is set + only if the read tried to go past the end of the input, but came up short. + Therefore, just like feof(), gzeof() may return false even if there is no + more data to read, in the event that the last read request was for the exact + number of bytes remaining in the input file. This will happen if the input + file size is an exact multiple of the buffer size. If gzeof() returns true, then the read functions will return no more data, unless the end-of-file indicator is reset by gzclearerr() and the input file @@ -1608,7 +1609,7 @@ ZEXTERN int ZEXPORT gzeof OF((gzFile file)); ZEXTERN int ZEXPORT gzdirect OF((gzFile file)); /* - Returns true (1) if file is being copied directly while reading, or false + Return true (1) if file is being copied directly while reading, or false (0) if file is a gzip stream being decompressed. If the input file is empty, gzdirect() will return true, since the input @@ -1629,8 +1630,8 @@ ZEXTERN int ZEXPORT gzdirect OF((gzFile file)); ZEXTERN int ZEXPORT gzclose OF((gzFile file)); /* - Flushes all pending output if necessary, closes the compressed file and - deallocates the (de)compression state. Note that once file is closed, you + Flush all pending output for file, if necessary, close file and + deallocate the (de)compression state. Note that once file is closed, you cannot call gzerror with file, since its structures have been deallocated. gzclose must not be called more than once on the same file, just as free must not be called more than once on the same allocation. @@ -1654,10 +1655,10 @@ ZEXTERN int ZEXPORT gzclose_w OF((gzFile file)); ZEXTERN const char * ZEXPORT gzerror OF((gzFile file, int *errnum)); /* - Returns the error message for the last error which occurred on the given - compressed file. errnum is set to zlib error number. If an error occurred - in the file system and not in the compression library, errnum is set to - Z_ERRNO and the application may consult errno to get the exact error code. + Return the error message for the last error which occurred on file. + errnum is set to zlib error number. If an error occurred in the file system + and not in the compression library, errnum is set to Z_ERRNO and the + application may consult errno to get the exact error code. The application must not modify the returned string. Future calls to this function may invalidate the previously returned string. If file is @@ -1670,7 +1671,7 @@ ZEXTERN const char * ZEXPORT gzerror OF((gzFile file, int *errnum)); ZEXTERN void ZEXPORT gzclearerr OF((gzFile file)); /* - Clears the error and end-of-file flags for file. This is analogous to the + Clear the error and end-of-file flags for file. This is analogous to the clearerr() function in stdio. This is useful for continuing to read a gzip file that is being written concurrently. */ @@ -1688,8 +1689,9 @@ ZEXTERN void ZEXPORT gzclearerr OF((gzFile file)); ZEXTERN uLong ZEXPORT adler32 OF((uLong adler, const Bytef *buf, uInt len)); /* Update a running Adler-32 checksum with the bytes buf[0..len-1] and - return the updated checksum. If buf is Z_NULL, this function returns the - required initial value for the checksum. + return the updated checksum. An Adler-32 value is in the range of a 32-bit + unsigned integer. If buf is Z_NULL, this function returns the required + initial value for the checksum. An Adler-32 checksum is almost as reliable as a CRC-32 but can be computed much faster. @@ -1722,12 +1724,13 @@ ZEXTERN uLong ZEXPORT adler32_combine OF((uLong adler1, uLong adler2, negative, the result has no meaning or utility. */ -ZEXTERN uLong ZEXPORT crc32 OF((uLong crc, const Bytef *buf, uInt len)); +ZEXTERN uLong ZEXPORT crc32 OF((uLong crc, const Bytef *buf, uInt len)); /* Update a running CRC-32 with the bytes buf[0..len-1] and return the - updated CRC-32. If buf is Z_NULL, this function returns the required - initial value for the crc. Pre- and post-conditioning (one's complement) is - performed within this function so it shouldn't be done by the application. + updated CRC-32. A CRC-32 value is in the range of a 32-bit unsigned integer. + If buf is Z_NULL, this function returns the required initial value for the + crc. Pre- and post-conditioning (one's complement) is performed within this + function so it shouldn't be done by the application. Usage example: @@ -1739,7 +1742,7 @@ ZEXTERN uLong ZEXPORT crc32 OF((uLong crc, const Bytef *buf, uInt len)); if (crc != original_crc) error(); */ -ZEXTERN uLong ZEXPORT crc32_z OF((uLong adler, const Bytef *buf, +ZEXTERN uLong ZEXPORT crc32_z OF((uLong crc, const Bytef *buf, z_size_t len)); /* Same as crc32(), but with a size_t length. @@ -1755,6 +1758,20 @@ ZEXTERN uLong ZEXPORT crc32_combine OF((uLong crc1, uLong crc2, z_off_t len2)); len2. */ +/* +ZEXTERN uLong ZEXPORT crc32_combine_gen OF((z_off_t len2)); + + Return the operator corresponding to length len2, to be used with + crc32_combine_op(). +*/ + +ZEXTERN uLong ZEXPORT crc32_combine_op OF((uLong crc1, uLong crc2, uLong op)); +/* + Give the same result as crc32_combine(), using op in place of len2. op is + is generated from len2 by crc32_combine_gen(). This will be faster than + crc32_combine() if the generated op is used more than once. +*/ + /* various hacks, don't look :) */ @@ -1842,6 +1859,7 @@ ZEXTERN int ZEXPORT gzgetc_ OF((gzFile file)); /* backward compatibility */ ZEXTERN z_off64_t ZEXPORT gzoffset64 OF((gzFile)); ZEXTERN uLong ZEXPORT adler32_combine64 OF((uLong, uLong, z_off64_t)); ZEXTERN uLong ZEXPORT crc32_combine64 OF((uLong, uLong, z_off64_t)); + ZEXTERN uLong ZEXPORT crc32_combine_gen64 OF((z_off64_t)); #endif #if !defined(ZLIB_INTERNAL) && defined(Z_WANT64) @@ -1852,6 +1870,7 @@ ZEXTERN int ZEXPORT gzgetc_ OF((gzFile file)); /* backward compatibility */ # define z_gzoffset z_gzoffset64 # define z_adler32_combine z_adler32_combine64 # define z_crc32_combine z_crc32_combine64 +# define z_crc32_combine_gen z_crc32_combine_gen64 # else # define gzopen gzopen64 # define gzseek gzseek64 @@ -1859,6 +1878,7 @@ ZEXTERN int ZEXPORT gzgetc_ OF((gzFile file)); /* backward compatibility */ # define gzoffset gzoffset64 # define adler32_combine adler32_combine64 # define crc32_combine crc32_combine64 +# define crc32_combine_gen crc32_combine_gen64 # endif # ifndef Z_LARGE64 ZEXTERN gzFile ZEXPORT gzopen64 OF((const char *, const char *)); @@ -1867,6 +1887,7 @@ ZEXTERN int ZEXPORT gzgetc_ OF((gzFile file)); /* backward compatibility */ ZEXTERN z_off_t ZEXPORT gzoffset64 OF((gzFile)); ZEXTERN uLong ZEXPORT adler32_combine64 OF((uLong, uLong, z_off_t)); ZEXTERN uLong ZEXPORT crc32_combine64 OF((uLong, uLong, z_off_t)); + ZEXTERN uLong ZEXPORT crc32_combine_gen64 OF((z_off_t)); # endif #else ZEXTERN gzFile ZEXPORT gzopen OF((const char *, const char *)); @@ -1875,12 +1896,14 @@ ZEXTERN int ZEXPORT gzgetc_ OF((gzFile file)); /* backward compatibility */ ZEXTERN z_off_t ZEXPORT gzoffset OF((gzFile)); ZEXTERN uLong ZEXPORT adler32_combine OF((uLong, uLong, z_off_t)); ZEXTERN uLong ZEXPORT crc32_combine OF((uLong, uLong, z_off_t)); + ZEXTERN uLong ZEXPORT crc32_combine_gen OF((z_off_t)); #endif #else /* Z_SOLO */ ZEXTERN uLong ZEXPORT adler32_combine OF((uLong, uLong, z_off_t)); ZEXTERN uLong ZEXPORT crc32_combine OF((uLong, uLong, z_off_t)); + ZEXTERN uLong ZEXPORT crc32_combine_gen OF((z_off_t)); #endif /* !Z_SOLO */ @@ -1890,10 +1913,10 @@ ZEXTERN int ZEXPORT inflateSyncPoint OF((z_streamp)); ZEXTERN const z_crc_t FAR * ZEXPORT get_crc_table OF((void)); ZEXTERN int ZEXPORT inflateUndermine OF((z_streamp, int)); ZEXTERN int ZEXPORT inflateValidate OF((z_streamp, int)); -ZEXTERN unsigned long ZEXPORT inflateCodesUsed OF ((z_streamp)); +ZEXTERN unsigned long ZEXPORT inflateCodesUsed OF((z_streamp)); ZEXTERN int ZEXPORT inflateResetKeep OF((z_streamp)); ZEXTERN int ZEXPORT deflateResetKeep OF((z_streamp)); -#if (defined(_WIN32) || defined(__CYGWIN__)) && !defined(Z_SOLO) +#if defined(_WIN32) && !defined(Z_SOLO) ZEXTERN gzFile ZEXPORT gzopen_w OF((const wchar_t *path, const char *mode)); #endif diff --git a/lib/zlib/zutil.c b/lib/zlib/zutil.c index a76c6b0c7..9543ae825 100644 --- a/lib/zlib/zutil.c +++ b/lib/zlib/zutil.c @@ -61,9 +61,11 @@ uLong ZEXPORT zlibCompileFlags() #ifdef ZLIB_DEBUG flags += 1 << 8; #endif + /* #if defined(ASMV) || defined(ASMINF) flags += 1 << 9; #endif + */ #ifdef ZLIB_WINAPI flags += 1 << 10; #endif @@ -119,7 +121,7 @@ uLong ZEXPORT zlibCompileFlags() # endif int ZLIB_INTERNAL z_verbose = verbose; -void ZLIB_INTERNAL z_error (m) +void ZLIB_INTERNAL z_error(m) char *m; { fprintf(stderr, "%s\n", m); @@ -136,8 +138,8 @@ const char * ZEXPORT zError(err) return ERR_MSG(err); } -#if defined(_WIN32_WCE) - /* The Microsoft C Run-Time Library for Windows CE doesn't have +#if defined(_WIN32_WCE) && _WIN32_WCE < 0x800 + /* The older Microsoft C Run-Time Library for Windows CE doesn't have * errno. We define it as a global variable to simplify porting. * Its value is always 0 and should not be used. */ @@ -214,7 +216,7 @@ local ptr_table table[MAX_PTR]; * a protected system like OS/2. Use Microsoft C instead. */ -voidpf ZLIB_INTERNAL zcalloc (voidpf opaque, unsigned items, unsigned size) +voidpf ZLIB_INTERNAL zcalloc(voidpf opaque, unsigned items, unsigned size) { voidpf buf; ulg bsize = (ulg)items*size; @@ -240,7 +242,7 @@ voidpf ZLIB_INTERNAL zcalloc (voidpf opaque, unsigned items, unsigned size) return buf; } -void ZLIB_INTERNAL zcfree (voidpf opaque, voidpf ptr) +void ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr) { int n; @@ -277,13 +279,13 @@ void ZLIB_INTERNAL zcfree (voidpf opaque, voidpf ptr) # define _hfree hfree #endif -voidpf ZLIB_INTERNAL zcalloc (voidpf opaque, uInt items, uInt size) +voidpf ZLIB_INTERNAL zcalloc(voidpf opaque, uInt items, uInt size) { (void)opaque; return _halloc((long)items, size); } -void ZLIB_INTERNAL zcfree (voidpf opaque, voidpf ptr) +void ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr) { (void)opaque; _hfree(ptr); @@ -302,7 +304,7 @@ extern voidp calloc OF((uInt items, uInt size)); extern void free OF((voidpf ptr)); #endif -voidpf ZLIB_INTERNAL zcalloc (opaque, items, size) +voidpf ZLIB_INTERNAL zcalloc(opaque, items, size) voidpf opaque; unsigned items; unsigned size; @@ -312,7 +314,7 @@ voidpf ZLIB_INTERNAL zcalloc (opaque, items, size) (voidpf)calloc(items, size); } -void ZLIB_INTERNAL zcfree (opaque, ptr) +void ZLIB_INTERNAL zcfree(opaque, ptr) voidpf opaque; voidpf ptr; { diff --git a/lib/zlib/zutil.h b/lib/zlib/zutil.h index b079ea6a8..0bc7f4ecd 100644 --- a/lib/zlib/zutil.h +++ b/lib/zlib/zutil.h @@ -1,5 +1,5 @@ /* zutil.h -- internal interface and configuration of the compression library - * Copyright (C) 1995-2016 Jean-loup Gailly, Mark Adler + * Copyright (C) 1995-2022 Jean-loup Gailly, Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h */ @@ -29,10 +29,6 @@ # include <stdlib.h> #endif -#ifdef Z_SOLO - typedef long ptrdiff_t; /* guess -- will be caught if guess is wrong */ -#endif - #ifndef local # define local static #endif @@ -46,6 +42,17 @@ typedef unsigned short ush; typedef ush FAR ushf; typedef unsigned long ulg; +#if !defined(Z_U8) && !defined(Z_SOLO) && defined(STDC) +# include <limits.h> +# if (ULONG_MAX == 0xffffffffffffffff) +# define Z_U8 unsigned long +# elif (ULLONG_MAX == 0xffffffffffffffff) +# define Z_U8 unsigned long long +# elif (UINT_MAX == 0xffffffffffffffff) +# define Z_U8 unsigned +# endif +#endif + extern z_const char * const z_errmsg[10]; /* indexed by 2-zlib_error */ /* (size given to avoid silly warnings with Visual C++) */ @@ -170,10 +177,6 @@ extern z_const char * const z_errmsg[10]; /* indexed by 2-zlib_error */ #if (defined(_MSC_VER) && (_MSC_VER > 600)) && !defined __INTERIX # if defined(_WIN32_WCE) # define fdopen(fd,mode) NULL /* No fdopen() */ -# ifndef _PTRDIFF_T_DEFINED - typedef int ptrdiff_t; -# define _PTRDIFF_T_DEFINED -# endif # else # define fdopen(fd,type) _fdopen(fd,type) # endif @@ -190,6 +193,7 @@ extern z_const char * const z_errmsg[10]; /* indexed by 2-zlib_error */ (!defined(_LARGEFILE64_SOURCE) || _LFS64_LARGEFILE-0 == 0) ZEXTERN uLong ZEXPORT adler32_combine64 OF((uLong, uLong, z_off_t)); ZEXTERN uLong ZEXPORT crc32_combine64 OF((uLong, uLong, z_off_t)); + ZEXTERN uLong ZEXPORT crc32_combine_gen64 OF((z_off_t)); #endif /* common defaults */ diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index a58caf565..426e34494 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -238,6 +238,20 @@ check_$(1): $(check_$(1)_cmd) endef +# SELECT_OPENSSL_API_VERSION selects the OpenSSL API version to be used to +# build the host tools by checking the version of OpenSSL located under +# the path defined by the OPENSSL_DIR variable. It receives no parameters. +define SELECT_OPENSSL_API_VERSION + # Set default value for USING_OPENSSL3 macro to 0 + $(eval USING_OPENSSL3 = 0) + # Obtain the OpenSSL version for the build located under OPENSSL_DIR + $(eval OPENSSL_INFO := $(shell LD_LIBRARY_PATH=${OPENSSL_DIR}:${OPENSSL_DIR}/lib ${OPENSSL_BIN_PATH}/openssl version)) + $(eval OPENSSL_CURRENT_VER = $(word 2, ${OPENSSL_INFO})) + $(eval OPENSSL_CURRENT_VER_MAJOR = $(firstword $(subst ., ,$(OPENSSL_CURRENT_VER)))) + # If OpenSSL version is 3.x, then set USING_OPENSSL3 flag to 1 + $(if $(filter 3,$(OPENSSL_CURRENT_VER_MAJOR)), $(eval USING_OPENSSL3 = 1)) +endef + ################################################################################ # Generic image processing filters ################################################################################ @@ -499,7 +513,8 @@ ifdef MAKE_BUILD_STRINGS $(call MAKE_BUILD_STRINGS, $(BUILD_DIR)/build_message.o) else @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP); \ - const char version_string[] = "${VERSION_STRING}";' | \ + const char version_string[] = "${VERSION_STRING}"; \ + const char version[] = "${VERSION}";' | \ $$(CC) $$(TF_CFLAGS) $$(CFLAGS) -xc -c - -o $(BUILD_DIR)/build_message.o endif ifneq ($(findstring armlink,$(notdir $(LD))),) diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index fab6bf6da..683d7ac9f 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -160,6 +160,10 @@ ENABLE_FEAT_PAN := 0 # Flag to enable access to the Random Number Generator registers ENABLE_FEAT_RNG := 0 +# Flag to enable support for EL3 trapping of reads of the RNDR and RNDRRS +# registers, by setting SCR_EL3.TRNDR. +ENABLE_FEAT_RNG_TRAP := 0 + # Flag to enable Speculation Barrier Instruction ENABLE_FEAT_SB := 0 @@ -212,9 +216,9 @@ GENERATE_COT := 0 # default, they are for Secure EL1. GICV2_G0_FOR_EL3 := 0 -# Route External Aborts to EL3. Disabled by default; External Aborts are handled +# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled # by lower ELs. -HANDLE_EA_EL3_FIRST := 0 +HANDLE_EA_EL3_FIRST_NS := 0 # Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. # The default value is sha256. @@ -266,7 +270,7 @@ SAVE_KEYS := 0 # Software Delegated Exception support SDEI_SUPPORT := 0 -# True Random Number firmware Interface +# True Random Number firmware Interface support TRNG_SUPPORT := 0 # SMCCC PCI support @@ -373,6 +377,9 @@ ifeq (${ARCH},aarch32) endif ENABLE_SVE_FOR_SWD := 0 +# Default SVE vector length to maximum architected value +SVE_VECTOR_LEN := 2048 + # SME defaults to disabled ENABLE_SME_FOR_NS := 0 ENABLE_SME_FOR_SWD := 0 @@ -406,15 +413,22 @@ SUPPORT_STACK_MEMTAG := no # Select workaround for AT speculative behaviour. ERRATA_SPECULATIVE_AT := 0 -# Trap RAS error record access from lower EL -RAS_TRAP_LOWER_EL_ERR_ACCESS := 0 +# Trap RAS error record access from Non secure +RAS_TRAP_NS_ERR_REC_ACCESS := 0 # Build option to create cot descriptors using fconf COT_DESC_IN_DTB := 0 -# Build option to provide openssl directory path +# Build option to provide OpenSSL directory path OPENSSL_DIR := /usr +# Select the openssl binary provided in OPENSSL_DIR variable +ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") + OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps +else + OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin +endif + # Build option to use the SP804 timer instead of the generic one USE_SP804_TIMER := 0 @@ -466,3 +480,7 @@ PLAT_RSS_NOT_SUPPORTED := 0 # Dynamic Root of Trust for Measurement support DRTM_SUPPORT := 0 + +# Check platform if cache management operations should be performed. +# Disabled by default. +CONDITIONAL_CMO := 0 diff --git a/make_helpers/tbbr/tbbr_tools.mk b/make_helpers/tbbr/tbbr_tools.mk index 0a280b4ed..5ef2d852e 100644 --- a/make_helpers/tbbr/tbbr_tools.mk +++ b/make_helpers/tbbr/tbbr_tools.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -25,6 +25,9 @@ # KEY_SIZE # ROT_KEY # PROT_KEY +# PLAT_KEY +# SWD_ROT_KEY +# CORE_SWD_KEY # TRUSTED_WORLD_KEY # NON_TRUSTED_WORLD_KEY # SCP_BL2_KEY @@ -46,10 +49,18 @@ $(eval $(call CERT_ADD_CMD_OPT,${TFW_NVCTR_VAL},--tfw-nvctr)) $(eval $(call CERT_ADD_CMD_OPT,${NTFW_NVCTR_VAL},--ntfw-nvctr)) # Add Trusted Key certificate to the fiptool and cert_create command line options +ifneq (${COT},cca) $(eval $(call TOOL_ADD_PAYLOAD,${TRUSTED_KEY_CERT},--trusted-key-cert)) +else +$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/cca.crt,--cca-cert)) +$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/core-swd.crt,--core-swd-cert)) +$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/plat-key.crt,--plat-key-cert)) +endif # Add fwu certificate to the fiptool and cert_create command line options +ifneq (${COT},cca) $(eval $(call TOOL_ADD_PAYLOAD,${FWU_CERT},--fwu-cert,,FWU_)) +endif # Add the keys to the cert_create command line options (private keys are NOT # packed in the FIP). Developers can use their own keys by specifying the proper @@ -63,6 +74,9 @@ $(if ${HASH_ALG},$(eval $(call CERT_ADD_CMD_OPT,${HASH_ALG},--hash-alg,FWU_))) $(if ${ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key))) $(if ${ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key,FWU_))) $(if ${PROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${PROT_KEY},--prot-key))) +$(if ${PLAT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${PLAT_KEY},--plat-key))) +$(if ${SWD_ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${SWD_ROT_KEY},--swd-rot-key))) +$(if ${CORE_SWD_KEY},$(eval $(call CERT_ADD_CMD_OPT,${CORE_SWD_KEY},--core-swd-key))) $(if ${TRUSTED_WORLD_KEY},$(eval $(call CERT_ADD_CMD_OPT,${TRUSTED_WORLD_KEY},--trusted-world-key))) $(if ${NON_TRUSTED_WORLD_KEY},$(eval $(call CERT_ADD_CMD_OPT,${NON_TRUSTED_WORLD_KEY},--non-trusted-world-key))) @@ -70,25 +84,31 @@ $(if ${NON_TRUSTED_WORLD_KEY},$(eval $(call CERT_ADD_CMD_OPT,${NON_TRUSTED_WORLD # Add the BL2 CoT (image cert) ifeq (${NEED_BL2},yes) ifeq (${BL2_AT_EL3}, 0) +ifneq (${COT},cca) $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert)) endif endif +endif # Add the SCP_BL2 CoT (key cert + img cert) ifneq (${SCP_BL2},) +ifneq (${COT},cca) $(if ${SCP_BL2_KEY},$(eval $(call CERT_ADD_CMD_OPT,${SCP_BL2_KEY},--scp-fw-key))) $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/scp_fw_content.crt,--scp-fw-cert)) $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/scp_fw_key.crt,--scp-fw-key-cert)) endif +endif ifeq (${ARCH},aarch64) ifeq (${NEED_BL31},yes) # Add the BL31 CoT (key cert + img cert) $(if ${BL31_KEY},$(eval $(call CERT_ADD_CMD_OPT,${BL31_KEY},--soc-fw-key))) +ifneq (${COT},cca) $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/soc_fw_content.crt,--soc-fw-cert)) $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/soc_fw_key.crt,--soc-fw-key-cert)) endif endif +endif # Add the BL32 CoT (key cert + img cert) ifeq (${NEED_BL32},yes) @@ -102,7 +122,9 @@ ifneq (${BL33},) $(if ${BL33_KEY},$(eval $(call CERT_ADD_CMD_OPT,${BL33_KEY},--nt-fw-key))) $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/nt_fw_content.crt,--nt-fw-cert)) ifneq (${COT},dualroot) - $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/nt_fw_key.crt,--nt-fw-key-cert)) + ifneq (${COT},cca) + $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/nt_fw_key.crt,--nt-fw-key-cert)) + endif endif endif @@ -112,4 +134,7 @@ ifneq (${SP_LAYOUT_FILE},) ifeq (${COT},dualroot) $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/plat_sp_content.crt,--plat-sp-cert)) endif +ifeq (${COT},cca) + $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/plat_sp_content.crt,--plat-sp-cert)) +endif endif diff --git a/make_helpers/windows.mk b/make_helpers/windows.mk index 26ea88ef0..b6d6f0b77 100644 --- a/make_helpers/windows.mk +++ b/make_helpers/windows.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -81,8 +81,9 @@ BUILD_STRING ?= development build # by defining the MAKE_BUILD_STRINGS macro. BUILT_TIME_DATE_STRING = const char build_message[] = "Built : "${BUILD_MESSAGE_TIMESTAMP}; VERSION_STRING_MESSAGE = const char version_string[] = "${VERSION_STRING}"; +VERSION_MESSAGE = const char version[] = "${VERSION}"; define MAKE_BUILD_STRINGS - @echo $$(BUILT_TIME_DATE_STRING) $$(VERSION_STRING_MESSAGE) | \ + @echo $$(BUILT_TIME_DATE_STRING) $$(VERSION_STRING_MESSAGE) $$(VERSION_MESSAGE) | \ $$(CC) $$(TF_CFLAGS) $$(CFLAGS) -x c -c - -o $1 endef diff --git a/package-lock.json b/package-lock.json index 34e7dbd9f..a3e0ff92a 100644 --- a/package-lock.json +++ b/package-lock.json @@ -1,12 +1,12 @@ { "name": "trusted-firmware-a", - "version": "2.7.0", + "version": "2.8.0", "lockfileVersion": 2, "requires": true, "packages": { "": { "name": "trusted-firmware-a", - "version": "2.7.0", + "version": "2.8.0", "hasInstallScript": true, "license": "BSD-3-Clause", "devDependencies": { @@ -24,29 +24,38 @@ } }, "node_modules/@babel/code-frame": { - "version": "7.12.13", - "resolved": "https://registry.npmjs.org/@babel/code-frame/-/code-frame-7.12.13.tgz", - "integrity": "sha512-HV1Cm0Q3ZrpCR93tkWOYiuYIgLxZXZFVG2VgK+MBWjUqZTundupbfx2aXarXuw5Ko5aMcjtJgbSs4vUGBS5v6g==", + "version": "7.18.6", + "resolved": "https://registry.npmjs.org/@babel/code-frame/-/code-frame-7.18.6.tgz", + "integrity": "sha512-TDCmlK5eOvH+eH7cdAFlNXeVJqWIQ7gW9tY1GJIpUtFb6CmjVyq2VM3u71bOyR8CRihcCgMUYoDNyLXao3+70Q==", "dev": true, "dependencies": { - "@babel/highlight": "^7.12.13" + "@babel/highlight": "^7.18.6" + }, + "engines": { + "node": ">=6.9.0" } }, "node_modules/@babel/helper-validator-identifier": { - "version": "7.14.0", - "resolved": "https://registry.npmjs.org/@babel/helper-validator-identifier/-/helper-validator-identifier-7.14.0.tgz", - "integrity": "sha512-V3ts7zMSu5lfiwWDVWzRDGIN+lnCEUdaXgtVHJgLb1rGaA6jMrtB9EmE7L18foXJIE8Un/A/h6NJfGQp/e1J4A==", - "dev": true + "version": "7.19.1", + "resolved": "https://registry.npmjs.org/@babel/helper-validator-identifier/-/helper-validator-identifier-7.19.1.tgz", + "integrity": "sha512-awrNfaMtnHUr653GgGEs++LlAvW6w+DcPrOliSMXWCKo597CwL5Acf/wWdNkf/tfEQE3mjkeD1YOVZOUV/od1w==", + "dev": true, + "engines": { + "node": ">=6.9.0" + } }, "node_modules/@babel/highlight": { - "version": "7.14.0", - "resolved": "https://registry.npmjs.org/@babel/highlight/-/highlight-7.14.0.tgz", - "integrity": "sha512-YSCOwxvTYEIMSGaBQb5kDDsCopDdiUGsqpatp3fOlI4+2HQSkTmEVWnVuySdAC5EWCqSWWTv0ib63RjR7dTBdg==", + "version": "7.18.6", + "resolved": "https://registry.npmjs.org/@babel/highlight/-/highlight-7.18.6.tgz", + "integrity": "sha512-u7stbOuYjaPezCuLj29hNW1v64M2Md2qupEKP1fHc7WdOA3DgLh37suiSrZYY7haUB7iBeQZ9P1uiRF359do3g==", "dev": true, "dependencies": { - "@babel/helper-validator-identifier": "^7.14.0", + "@babel/helper-validator-identifier": "^7.18.6", "chalk": "^2.0.0", "js-tokens": "^4.0.0" + }, + "engines": { + "node": ">=6.9.0" } }, "node_modules/@babel/highlight/node_modules/ansi-styles": { @@ -87,13 +96,13 @@ "node_modules/@babel/highlight/node_modules/color-name": { "version": "1.1.3", "resolved": "https://registry.npmjs.org/color-name/-/color-name-1.1.3.tgz", - "integrity": "sha1-p9BVi9icQveV3UIyj3QIMcpTvCU=", + "integrity": "sha512-72fSenhMw2HZMTVHeCA9KCmpEIbzWiQsjN+BHcBbS9vr1mtt+vJjPdksIBNUmKAW8TFUDPJK5SUU3QhE9NEXDw==", "dev": true }, "node_modules/@babel/highlight/node_modules/has-flag": { "version": "3.0.0", "resolved": "https://registry.npmjs.org/has-flag/-/has-flag-3.0.0.tgz", - "integrity": "sha1-tdRU3CGZriJWmfNGfloH87lVuv0=", + "integrity": "sha512-sKJf1+ceQBr4SMkvQnBDNDtf4TXpVhVGateu0t918bl30FnbE2m4vNLX+VWe/dpjlb+HugGYzW7uQXH98HPEYw==", "dev": true, "engines": { "node": ">=4" @@ -112,16 +121,16 @@ } }, "node_modules/@commitlint/cli": { - "version": "16.1.0", - "resolved": "https://registry.npmjs.org/@commitlint/cli/-/cli-16.1.0.tgz", - "integrity": "sha512-x5L1knvA3isRWBRVQx+Q6D45pA9139a2aZQYpxkljMG0dj4UHZkCnsYWpnGalxPxASI7nrI0KedKfS2YeQ55cQ==", + "version": "16.3.0", + "resolved": "https://registry.npmjs.org/@commitlint/cli/-/cli-16.3.0.tgz", + "integrity": "sha512-P+kvONlfsuTMnxSwWE1H+ZcPMY3STFaHb2kAacsqoIkNx66O0T7sTpBxpxkMrFPyhkJiLJnJWMhk4bbvYD3BMA==", "dev": true, "dependencies": { - "@commitlint/format": "^16.0.0", - "@commitlint/lint": "^16.0.0", - "@commitlint/load": "^16.1.0", - "@commitlint/read": "^16.0.0", - "@commitlint/types": "^16.0.0", + "@commitlint/format": "^16.2.1", + "@commitlint/lint": "^16.2.4", + "@commitlint/load": "^16.3.0", + "@commitlint/read": "^16.2.1", + "@commitlint/types": "^16.2.1", "lodash": "^4.17.19", "resolve-from": "5.0.0", "resolve-global": "1.0.0", @@ -135,9 +144,9 @@ } }, "node_modules/@commitlint/config-conventional": { - "version": "16.0.0", - "resolved": "https://registry.npmjs.org/@commitlint/config-conventional/-/config-conventional-16.0.0.tgz", - "integrity": "sha512-mN7J8KlKFn0kROd+q9PB01sfDx/8K/R25yITspL1No8PB4oj9M1p77xWjP80hPydqZG9OvQq+anXK3ZWeR7s3g==", + "version": "16.2.4", + "resolved": "https://registry.npmjs.org/@commitlint/config-conventional/-/config-conventional-16.2.4.tgz", + "integrity": "sha512-av2UQJa3CuE5P0dzxj/o/B9XVALqYzEViHrMXtDrW9iuflrqCStWBAioijppj9URyz6ONpohJKAtSdgAOE0gkA==", "dev": true, "dependencies": { "conventional-changelog-conventionalcommits": "^4.3.1" @@ -147,12 +156,12 @@ } }, "node_modules/@commitlint/config-validator": { - "version": "16.1.0", - "resolved": "https://registry.npmjs.org/@commitlint/config-validator/-/config-validator-16.1.0.tgz", - "integrity": "sha512-2cHeZPNTuf1JWbMqyA46MkExor5HMSgv8JrdmzEakUbJHUreh35/wN00FJf57qGs134exQW2thiSQ1IJUsVx2Q==", + "version": "16.2.1", + "resolved": "https://registry.npmjs.org/@commitlint/config-validator/-/config-validator-16.2.1.tgz", + "integrity": "sha512-hogSe0WGg7CKmp4IfNbdNES3Rq3UEI4XRPB8JL4EPgo/ORq5nrGTVzxJh78omibNuB8Ho4501Czb1Er1MoDWpw==", "dev": true, "dependencies": { - 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"dev": true, - "peer": true + "dev": true }, "import-fresh": { "version": "3.3.0", @@ -6034,7 +5748,7 @@ "inflight": { "version": "1.0.6", "resolved": "https://registry.npmjs.org/inflight/-/inflight-1.0.6.tgz", - "integrity": "sha1-Sb1jMdfQLQwJvJEKEHW6gWW1bfk=", + "integrity": "sha512-k92I/b08q4wvFscXCLvqfsHCrjrF7yiXsQuIVvVE7N82W3+aqpzuUdBbfhWcy/FZR3/4IgflMgKLOsvPDrGCJA==", "dev": true, "requires": { "once": "^1.3.0", @@ -6054,11 +5768,10 @@ "dev": true }, "inquirer": { - "version": "8.2.0", - "resolved": "https://registry.npmjs.org/inquirer/-/inquirer-8.2.0.tgz", - "integrity": "sha512-0crLweprevJ02tTuA6ThpoAERAGyVILC4sS74uib58Xf/zSr1/ZWtmm7D5CI+bSQEaA04f0K7idaHpQbSWgiVQ==", + "version": "8.2.4", + "resolved": "https://registry.npmjs.org/inquirer/-/inquirer-8.2.4.tgz", + "integrity": "sha512-nn4F01dxU8VeKfq192IjLsxu0/OmMZ4Lg3xKAns148rCaXP6ntAoEkVYZThWjwON8AlzdZZi6oqnhNbxUG9hVg==", "dev": true, - "peer": true, "requires": { "ansi-escapes": "^4.2.1", "chalk": "^4.1.1", @@ -6070,22 +5783,23 @@ "mute-stream": "0.0.8", "ora": "^5.4.1", "run-async": "^2.4.0", - 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"integrity": "sha1-RQ1Nyfpw3nMnYvvS1KKJgUGaDM8=", + "integrity": "sha512-EPD5q1uXyFxJpCrLnCc1nHnq3gOa6DZBocAIiI2TaSCA7VCJ1UJDMagCzIkXNsUYfD1daK//LTEQ8xiIbrHtcw==", + "dev": true + }, + "v8-compile-cache-lib": { + "version": "3.0.1", + "resolved": "https://registry.npmjs.org/v8-compile-cache-lib/-/v8-compile-cache-lib-3.0.1.tgz", + "integrity": "sha512-wa7YjyUGfNZngI/vtK0UHAN+lgDCxBPCylVXGp0zu59Fz5aiGtNXaq3DhIov063MorB+VfufLh3JlF2KdTK3xg==", "dev": true }, "validate-npm-package-license": { @@ -7224,17 +6962,16 @@ "wcwidth": { "version": "1.0.1", "resolved": "https://registry.npmjs.org/wcwidth/-/wcwidth-1.0.1.tgz", - "integrity": "sha1-8LDc+RW8X/FSivrbLA4XtTLaL+g=", + "integrity": "sha512-XHPEwS0q6TaxcvG85+8EYkbiCux2XtWG2mkc47Ng2A77BQu9+DqIOJldST4HgPkuea7dvKSj5VgX3P1d4rW8Tg==", "dev": true, - "peer": true, "requires": { "defaults": "^1.0.3" } }, "which": { - "version": "1.3.1", - "resolved": "https://registry.npmjs.org/which/-/which-1.3.1.tgz", - "integrity": "sha512-HxJdYWq1MTIQbJ3nw0cqssHoTNU267KlrDuGZ1WYlxDStUtKUhOaJmh112/TZmHxxUfuJqPXSOm7tDyas0OSIQ==", + "version": "2.0.2", + "resolved": "https://registry.npmjs.org/which/-/which-2.0.2.tgz", + "integrity": "sha512-BLI3Tl1TW3Pvl70l3yq3Y64i+awpwXqsGBYWkkqMtnbXgrMD+yj7rhW0kuEDxzJaYXGjEW5ogapKNMEKNMjibA==", "dev": true, "requires": { "isexe": "^2.0.0" @@ -7249,7 +6986,7 @@ "wordwrap": { "version": "1.0.0", "resolved": "https://registry.npmjs.org/wordwrap/-/wordwrap-1.0.0.tgz", - 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"string-width": "^4.2.0", + "string-width": "^4.2.3", "y18n": "^5.0.5", - "yargs-parser": "^20.2.2" + "yargs-parser": "^21.0.0" + }, + "dependencies": { + "yargs-parser": { + "version": "21.1.1", + "resolved": "https://registry.npmjs.org/yargs-parser/-/yargs-parser-21.1.1.tgz", + "integrity": "sha512-tVpsJW7DdjecAiFpbIB1e3qxIQsE6NoPc5/eTdrbbIC4h0LVsWhnoa3g+m2HclBIujHzsxZ4VJVA+GUuc2/LBw==", + "dev": true + } } }, "yargs-parser": { diff --git a/package.json b/package.json index 0284e6f58..8d4dd54d9 100644 --- a/package.json +++ b/package.json @@ -1,6 +1,6 @@ { "name": "trusted-firmware-a", - "version": "2.7.0", + "version": "2.8.0", "license": "BSD-3-Clause", "private": true, "scripts": { diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk index 084532ce2..a14a0d8c0 100644 --- a/plat/arm/board/arm_fpga/platform.mk +++ b/plat/arm/board/arm_fpga/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2021, Arm Limited. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -71,9 +71,9 @@ else lib/cpus/aarch64/cortex_a65.S \ lib/cpus/aarch64/cortex_a65ae.S \ lib/cpus/aarch64/cortex_a510.S \ - lib/cpus/aarch64/cortex_a710.S \ - lib/cpus/aarch64/cortex_makalu.S \ - lib/cpus/aarch64/cortex_makalu_elp_arm.S \ + lib/cpus/aarch64/cortex_a710.S \ + lib/cpus/aarch64/cortex_a715.S \ + lib/cpus/aarch64/cortex_x3.S \ lib/cpus/aarch64/cortex_a78c.S # AArch64/AArch32 cores diff --git a/plat/arm/board/common/board_arm_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c index 66cc3e949..714c444e7 100644 --- a/plat/arm/board/common/board_arm_trusted_boot.c +++ b/plat/arm/board/common/board_arm_trusted_boot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,18 +13,20 @@ #include <drivers/delay_timer.h> #include <lib/cassert.h> #include <lib/fconf/fconf.h> -#include <plat/arm/common/plat_arm.h> -#include <plat/arm/common/fconf_nv_cntr_getter.h> #include <plat/common/common_def.h> #include <plat/common/platform.h> -#include <platform_def.h> - -#if defined(ARM_COT_tbbr) -#include <tools_share/tbbr_oid.h> +#if defined(ARM_COT_cca) +#include <tools_share/cca_oid.h> #elif defined(ARM_COT_dualroot) #include <tools_share/dualroot_oid.h> +#elif defined(ARM_COT_tbbr) +#include <tools_share/tbbr_oid.h> #endif +#include <plat/arm/common/fconf_nv_cntr_getter.h> +#include <plat/arm/common/plat_arm.h> +#include <platform_def.h> + #if !ARM_CRYPTOCELL_INTEG #if !ARM_ROTPK_LOCATION_ID #error "ARM_ROTPK_LOCATION_ID not defined" @@ -181,6 +183,40 @@ int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, return 1; } } + +#elif defined(ARM_COT_cca) + +int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + /* + * Return the right root of trust key hash based on the cookie value: + * - NULL means the primary ROTPK. + * - Otherwise, interpret cookie as the OID of the certificate + * extension containing the key. + */ + if (cookie == NULL) { + return get_rotpk_info(key_ptr, key_len, flags); + } else if (strcmp(cookie, PROT_PK_OID) == 0) { + extern unsigned char arm_protpk_hash[]; + extern unsigned char arm_protpk_hash_end[]; + *key_ptr = arm_protpk_hash; + *key_len = arm_protpk_hash_end - arm_protpk_hash; + *flags = ROTPK_IS_HASH; + return 0; + } else if (strcmp(cookie, SWD_ROT_PK_OID) == 0) { + extern unsigned char arm_swd_rotpk_hash[]; + extern unsigned char arm_swd_rotpk_hash_end[]; + *key_ptr = arm_swd_rotpk_hash; + *key_len = arm_swd_rotpk_hash_end - arm_swd_rotpk_hash; + *flags = ROTPK_IS_HASH; + return 0; + } else { + /* Invalid key ID. */ + return 1; + } +} + #endif /* diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk index 5cdf1bf39..1d0eb136e 100644 --- a/plat/arm/board/common/board_common.mk +++ b/plat/arm/board/common/board_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -38,6 +38,10 @@ endif $(eval $(call add_define,ARM_ROTPK_LOCATION_ID)) +ifeq (${ENABLE_RME}, 1) +COT := cca +endif + # Force generation of the new hash if ROT_KEY is specified ifdef ROT_KEY HASH_PREREQUISITES = $(ROT_KEY) FORCE @@ -49,8 +53,8 @@ $(ARM_ROTPK_HASH) : $(HASH_PREREQUISITES) ifndef ROT_KEY $(error Cannot generate hash: no ROT_KEY defined) endif - openssl ${CRYPTO_ALG} -in $< -pubout -outform DER | openssl dgst \ - -sha256 -binary > $@ + ${OPENSSL_BIN_PATH}/openssl ${CRYPTO_ALG} -in $< -pubout -outform DER | \ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ # Certificate NV-Counters. Use values corresponding to tied off values in # ARM development platforms @@ -88,4 +92,29 @@ $(BUILD_PLAT)/bl1/arm_dev_protpk.o: $(ARM_PROTPK_HASH) $(BUILD_PLAT)/bl2/arm_dev_protpk.o: $(ARM_PROTPK_HASH) endif +ifeq (${COT},cca) +# Platform and Secure World Root of Trust key files. +ARM_PROT_KEY := plat/arm/board/common/protpk/arm_protprivk_rsa.pem +ARM_PROTPK_HASH := plat/arm/board/common/protpk/arm_protpk_rsa_sha256.bin +ARM_SWD_ROT_KEY := plat/arm/board/common/swd_rotpk/arm_swd_rotprivk_rsa.pem +ARM_SWD_ROTPK_HASH := plat/arm/board/common/swd_rotpk/arm_swd_rotpk_rsa_sha256.bin + +# Provide the private keys to cert_create tool. It needs them to sign the images. +PROT_KEY := ${ARM_PROT_KEY} +SWD_ROT_KEY := ${ARM_SWD_ROT_KEY} + +$(eval $(call add_define_val,ARM_PROTPK_HASH,'"$(ARM_PROTPK_HASH)"')) +$(eval $(call add_define_val,ARM_SWD_ROTPK_HASH,'"$(ARM_SWD_ROTPK_HASH)"')) + +BL1_SOURCES += plat/arm/board/common/protpk/arm_dev_protpk.S \ + plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S +BL2_SOURCES += plat/arm/board/common/protpk/arm_dev_protpk.S \ + plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S + +$(BUILD_PLAT)/bl1/arm_dev_protpk.o: $(ARM_PROTPK_HASH) +$(BUILD_PLAT)/bl1/arm_dev_swd_rotpk.o: $(ARM_SWD_ROTPK_HASH) +$(BUILD_PLAT)/bl2/arm_dev_protpk.o: $(ARM_PROTPK_HASH) +$(BUILD_PLAT)/bl2/arm_dev_swd_rotpk.o: $(ARM_SWD_ROTPK_HASH) +endif + endif diff --git a/plat/arm/board/common/swd_rotpk/README b/plat/arm/board/common/swd_rotpk/README new file mode 100644 index 000000000..b628a5fd8 --- /dev/null +++ b/plat/arm/board/common/swd_rotpk/README @@ -0,0 +1,14 @@ +This directory contains some development keys to be used as the secure world +root-of-trust key used in the CCA chain of trust. + +* swd_rotprivk_rsa.pem is a 2K RSA private key in PEM format. It has been + generated using the openssl command line tool: + + openssl genrsa 2048 > arm_swd_rotprivk_rsa.pem + +* swd_rotpk_rsa_sha256.bin is the SHA-256 hash of the DER-encoded public key + associated with the above private key. It has been generated using the openssl + command line tool: + + openssl rsa -in arm_swd_rotprivk_rsa.pem -pubout -outform DER | \ + openssl dgst -sha256 -binary > arm_swd_rotpk_rsa_sha256.bin diff --git a/plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S b/plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S new file mode 100644 index 000000000..ae4f9d271 --- /dev/null +++ b/plat/arm/board/common/swd_rotpk/arm_dev_swd_rotpk.S @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global arm_swd_rotpk_hash + .global arm_swd_rotpk_hash_end + + .section .rodata.arm_swd_rotpk_hash, "a" + +arm_swd_rotpk_hash: + /* DER header. */ + .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 + .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 + /* Key hash. */ + .incbin ARM_SWD_ROTPK_HASH +arm_swd_rotpk_hash_end: diff --git a/plat/arm/board/common/swd_rotpk/arm_swd_rotpk_rsa_sha256.bin b/plat/arm/board/common/swd_rotpk/arm_swd_rotpk_rsa_sha256.bin new file mode 100644 index 000000000..b2f3e60a4 --- /dev/null +++ b/plat/arm/board/common/swd_rotpk/arm_swd_rotpk_rsa_sha256.bin @@ -0,0 +1 @@ +0¾âà ’æœÈË“(ì¨0ŠwIÓÕ éã¡gk
\ No newline at end of file diff --git a/plat/arm/board/common/swd_rotpk/arm_swd_rotprivk_rsa.pem b/plat/arm/board/common/swd_rotpk/arm_swd_rotprivk_rsa.pem new file mode 100644 index 000000000..0de655d4a --- /dev/null +++ b/plat/arm/board/common/swd_rotpk/arm_swd_rotprivk_rsa.pem @@ -0,0 +1,27 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIEpQIBAAKCAQEA8igTd5QdZd181kz9vINr7Au34Rr/pQ1jpesfLlc1ZXCNAI9y +/rhQlpw00y8rwOfgZsf18gPwGWWGhDJMsXI7OPem7BEUr8xKumuJuCiOdJh1STcR +/JoFvz8wJPyycj/DOERRGsz+RvFBs6cLjSZHNQdzKDW+DE5vVJpmNWBVkoK7MCRD +Wh/PMZVSoq9PeJOzayYcsipKvifT1+Wo9y2MG5zTDxi28rLr/FBm0CpTepBcRe8L +pmgS7XJKhCQYxdDSzxi/0t/qXAwWuME4jv2HbNxsUZjahiBYpA0BafXanSuxVHly +qpD0BmKAu7PpgKrEnUcPuHpZ2W+a05lNk6zjewIDAQABAoIBAG3twYCcTYgrtvs1 +8k38vyZl33CiKAGOhXkRtpL75fKJ2IizljmKBJOKj/R6ynsFCHrANadLIFj3HMyw +ZN59A+OFkVJDIsf3jsj3/ooKZzkI6N120YSBizBZiAqSaJOy3HWTldn7y0b7SJ88 +quLFyLeLDTzowMCnbqTSfqmmdNJQAn+Q+7RX5sZGyBQUF2pRAA67cOYzc3a5MZ5E +zBOs2u8VboC3ulEq876XWQbcXpRh/ap3eplQ1kAdyy64IPp2WbxqyXW0IQAQqaqh +6oj19ME6mVD5wtELcYscJCDb7pA6WJtPp6nz/og2ifCJE/75T5RJ6fc6eBFMcofQ +STIClGECgYEA/ZC0GX1HTKEKK3c1TiS3Zy0DS5ZoN5KFK7Sp1ZAjPE63iAr1a3z9 +Kepb+L8TBSw50tVD74MF5ChEid/ghF5BrVC3/YJkiiNpM1F51SMLGFeiDPRzJcx5 +KJkSflX7Q36BAXqj85Yz5AjgTPKcBqQRVZ6pNZN1HY99MloMg22WPRECgYEA9HtU +FXmnTplXaNnihdq+vL5Z4/KDM+1f1E95y1PB8vkLI+o1szVNFP+BYz+w42lKtHW+ +c+z40AhFBGZQ0QCx83NOyObCReFjEbP8Nz71BsHe6GyMk9tSPIpzu9XB49Rs+9EO +DAvFM5y2j5bH+lXE0pSyS3oBf51L9ZCPhp/vB8sCgYEAydwB1Gzsbu+hFfs/v2bx +brzh67HgY6VMSP/5WF/3/RG5gB8hQ6HsNQsyjrMmZC7SFarb+3e2H+2CqrREm3wi +EuS4pKPCgEoyfL03HVtZgNZ61o9gf83pAk3h8Bto/VFfSBsnHEsOIlKCph9Z4NuK +RTwa/uDWEmNhyszvO03pldECgYEA2zB7GWnhc1mNgabfLY0JtuSeaPzzXqnyYcID +eyUT3QglUcTY8lvWSP4ufdILgEfVP2fVIdAS30iawDAPQuLxqEf4Gayx/r7s+GE6 +vjlGqxFEDXPMsX9QApFK49voop/AOiCbDHe9DOHy11ei4TDmbrn8BClVkJlxEa/S +ziszvfMCgYEA2V0zXziooI0toaOJEWZlAYhEONS5SG2z28HMLNgbdMcueGNhseaR +NBGgPcu3EQhbL/hD0tBs09u6gjy1WD1i0HYnm1K1YQ1flzfbjUa3BqZETMbNhugd +CM9yv0GEL/udZyOmO401aYl+QGXZX/WwlLQOe7WqQXOXJvW73oSqy7M= +-----END RSA PRIVATE KEY----- diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts index 21a6073a3..4543671a9 100644 --- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts +++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -82,4 +82,8 @@ device_type = "memory"; reg = <0x0 0x6000000 0x2000000>; /* Trusted DRAM */ }; + +#if MEASURED_BOOT +#include "event_log.dtsi" +#endif }; diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts index cf4ef2d02..6fd334d8e 100644 --- a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts +++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,6 +47,9 @@ soc_fw_cfg_uuid = "9979814b-0376-fb46-8c8e-8d267f7859e0"; tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021"; nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9"; + cca_cert_uuid = "36d83d85-761d-4daf-96f1-cd99d6569b00"; + core_swd_cert_uuid = "52222d31-820f-494d-8bbc-ea6825d3c35a"; + plat_cert_uuid = "d43cd902-5b9f-412e-8ac6-92b6d18be60d"; t_key_cert_uuid = "827ee890-f860-e411-a1b4-777a21b4f94c"; scp_fw_key_uuid = "024221a1-f860-e411-8d9b-f33c0e15a014"; soc_fw_key_uuid = "8ab8becc-f960-e411-9ad0-eb4822d8dcf8"; diff --git a/plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts b/plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts new file mode 100644 index 000000000..1587c72b0 --- /dev/null +++ b/plat/arm/board/fvp/fdts/fvp_tsp_sp_manifest.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/dts-v1/; + +#define AFF 00 + +#include "fvp-defs.dtsi" +#undef POST +#define POST \ + }; + +#define S_EL0 (0x1) +#define S_EL1 (0x2) + +/* For consumption by EL3 SPMC. */ +/ { + compatible = "arm,ffa-manifest-1.0"; + #address-cells = <2>; + #size-cells = <1>; + + ffa-version = <0x00010001>; /* 31:16 - Major, 15:0 - Minor */ + id = <0x8001>; + uuid = <0x6b43b460 0x74a24b78 0xade24502 0x40682886>; + messaging-method = <0x3>; /* Direct Messaging Only */ + exception-level = <S_EL1>; + execution-state = <0>; + execution-ctx-count = <8>; + gp-register-num = <0>; + /* Subscribe to CPU_OFF, CPU_SUSPEND and CPU_SUSPEND_RESUME PM Msgs */ + power-management-messages = <0x7>; +}; diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c index fd15b70d3..e938e2419 100644 --- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c +++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c @@ -6,6 +6,7 @@ #include <stdint.h> +#include <common/tbbr/tbbr_img_def.h> #include <drivers/measured_boot/event_log/event_log.h> #include <drivers/measured_boot/rss/rss_measured_boot.h> #include <tools_share/tbbr_oid.h> @@ -31,6 +32,17 @@ const event_log_metadata_t fvp_event_log_metadata[] = { { TOS_FW_CONFIG_ID, EVLOG_TOS_FW_CONFIG_STRING, PCR_0 }, { RMM_IMAGE_ID, EVLOG_RMM_STRING, PCR_0}, +#if defined(SPD_spmd) + { SP_PKG1_ID, EVLOG_SP1_STRING, PCR_0 }, + { SP_PKG2_ID, EVLOG_SP2_STRING, PCR_0 }, + { SP_PKG3_ID, EVLOG_SP3_STRING, PCR_0 }, + { SP_PKG4_ID, EVLOG_SP4_STRING, PCR_0 }, + { SP_PKG5_ID, EVLOG_SP5_STRING, PCR_0 }, + { SP_PKG6_ID, EVLOG_SP6_STRING, PCR_0 }, + { SP_PKG7_ID, EVLOG_SP7_STRING, PCR_0 }, + { SP_PKG8_ID, EVLOG_SP8_STRING, PCR_0 }, +#endif + { CRITICAL_DATA_ID, EVLOG_CRITICAL_DATA_STRING, PCR_1 }, { EVLOG_INVALID_ID, NULL, (unsigned int)(-1) } /* Terminator */ diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index a7028f6cf..f8463f14c 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -17,6 +17,9 @@ #include <lib/xlat_tables/xlat_tables_compat.h> #include <platform_def.h> #include <services/arm_arch_svc.h> +#if ENABLE_RME +#include <services/rmm_core_manifest.h> +#endif #if SPM_MM #include <services/spm_mm_partition.h> #endif @@ -169,6 +172,7 @@ const mmap_region_t plat_arm_mmap[] = { #endif #if ENABLE_RME ARM_MAP_GPT_L1_DRAM, + ARM_MAP_EL3_RMM_SHARED_MEM, #endif {0} }; @@ -512,3 +516,29 @@ int32_t plat_get_soc_revision(void) return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); } + +#if ENABLE_RME +/* + * Get a pointer to the RMM-EL3 Shared buffer and return it + * through the pointer passed as parameter. + * + * This function returns the size of the shared buffer. + */ +size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared) +{ + *shared = (uintptr_t)RMM_SHARED_BASE; + + return (size_t)RMM_SHARED_SIZE; +} + +int plat_rmmd_load_manifest(rmm_manifest_t *manifest) +{ + assert(manifest != NULL); + + manifest->version = RMMD_MANIFEST_VERSION; + manifest->plat_data = (uintptr_t)NULL; + + return 0; +} + +#endif diff --git a/plat/arm/board/fvp/fvp_drtm_addr.c b/plat/arm/board/fvp/fvp_drtm_addr.c new file mode 100644 index 000000000..eeaa3425b --- /dev/null +++ b/plat/arm/board/fvp/fvp_drtm_addr.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <stdint.h> + +#include <plat/common/platform.h> +#include <platform_def.h> + +/******************************************************************************* + * Check passed region is within Non-Secure region of DRAM + ******************************************************************************/ +int plat_drtm_validate_ns_region(uintptr_t region_start, + size_t region_size) +{ + uintptr_t region_end = region_start + region_size - 1; + + if (region_start >= region_end) { + return -1; + } else if ((region_start >= ARM_NS_DRAM1_BASE) && + (region_start < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE)) && + (region_end >= ARM_NS_DRAM1_BASE) && + (region_end < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { + return 0; + } else if ((region_start >= ARM_DRAM2_BASE) && + (region_start < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE)) && + (region_end >= ARM_DRAM2_BASE) && + (region_end < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { + return 0; + } + + return -1; +} diff --git a/plat/arm/board/fvp/fvp_drtm_dma_prot.c b/plat/arm/board/fvp/fvp_drtm_dma_prot.c new file mode 100644 index 000000000..38ff7fe38 --- /dev/null +++ b/plat/arm/board/fvp/fvp_drtm_dma_prot.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <stddef.h> + +#include <drivers/arm/smmu_v3.h> +#include <lib/utils_def.h> +#include <plat/arm/common/arm_config.h> +#include <plat/common/platform.h> + +#include <platform_def.h> + +/** + * Array mentioning number of SMMUs supported by FVP + */ +static const uintptr_t fvp_smmus[] = { + PLAT_FVP_SMMUV3_BASE, +}; + +bool plat_has_non_host_platforms(void) +{ + /* FVP base platforms typically have GPU, as per FVP Reference guide */ + return true; +} + +bool plat_has_unmanaged_dma_peripherals(void) +{ + /* + * FVP Reference guide does not show devices that are described as + * DMA-capable but not managed by an SMMU in the FVP documentation. + * However, the SMMU seems to have only been introduced in the RevC + * revision. + */ + return (arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) == 0; +} + +unsigned int plat_get_total_smmus(void) +{ + if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) { + return ARRAY_SIZE(fvp_smmus); + } else { + return 0; + } +} + +void plat_enumerate_smmus(const uintptr_t **smmus_out, + size_t *smmu_count_out) +{ + if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) { + *smmus_out = fvp_smmus; + *smmu_count_out = ARRAY_SIZE(fvp_smmus); + } else { + *smmus_out = NULL; + *smmu_count_out = 0; + } +} + +/* DRTM DMA Protection Features */ +static const plat_drtm_dma_prot_features_t dma_prot_features = { + .max_num_mem_prot_regions = 0, /* No protection regions are present */ + .dma_protection_support = 0x1 /* Complete DMA protection only */ +}; + +const plat_drtm_dma_prot_features_t *plat_drtm_get_dma_prot_features(void) +{ + return &dma_prot_features; +} + +uint64_t plat_drtm_dma_prot_get_max_table_bytes(void) +{ + return 0U; +} diff --git a/plat/arm/board/fvp/fvp_drtm_err.c b/plat/arm/board/fvp/fvp_drtm_err.c new file mode 100644 index 000000000..95259fa82 --- /dev/null +++ b/plat/arm/board/fvp/fvp_drtm_err.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <plat/common/platform.h> + +int plat_set_drtm_error(uint64_t error_code) +{ + /* TODO: Set DRTM error in NV-storage */ + return 0; +} + +int plat_get_drtm_error(uint64_t *error_code) +{ + /* TODO: Get DRTM error from NV-storage */ + *error_code = 0; + return 0; +} diff --git a/plat/arm/board/fvp/fvp_drtm_measurement.c b/plat/arm/board/fvp/fvp_drtm_measurement.c new file mode 100644 index 000000000..4fbedd8bc --- /dev/null +++ b/plat/arm/board/fvp/fvp_drtm_measurement.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#include <drivers/measured_boot/event_log/event_log.h> +#include <plat/common/platform.h> + +#include <platform_def.h> + +/* DRTM TPM Features */ +static const plat_drtm_tpm_features_t tpm_features = { + /* No TPM-based hashing supported. */ + .tpm_based_hash_support = false, + + /* Set to decided algorithm by Event Log driver */ + .firmware_hash_algorithm = TPM_ALG_ID + +}; + +const plat_drtm_tpm_features_t *plat_drtm_get_tpm_features(void) +{ + return &tpm_features; +} diff --git a/plat/arm/board/fvp/fvp_drtm_stub.c b/plat/arm/board/fvp/fvp_drtm_stub.c new file mode 100644 index 000000000..e2bc5169a --- /dev/null +++ b/plat/arm/board/fvp/fvp_drtm_stub.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#include <stdint.h> + +#include <services/drtm_svc.h> + +/* + * This file contains DRTM platform functions which don't really do anything on + * FVP but are needed for DRTM to function. + */ + +uint64_t plat_drtm_get_min_size_normal_world_dce(void) +{ + return 0ULL; +} + +uint64_t plat_drtm_get_imp_def_dlme_region_size(void) +{ + return 0ULL; +} + +uint64_t plat_drtm_get_tcb_hash_features(void) +{ + return 0ULL; +} + +uint64_t plat_drtm_get_tcb_hash_table_size(void) +{ + return 0ULL; +} diff --git a/plat/arm/board/fvp/fvp_err.c b/plat/arm/board/fvp/fvp_err.c index 1f9f0dd14..244659ab7 100644 --- a/plat/arm/board/fvp/fvp_err.c +++ b/plat/arm/board/fvp/fvp_err.c @@ -29,3 +29,15 @@ __dead2 void plat_arm_error_handler(int err) for (;;) wfi(); } + +void __dead2 plat_arm_system_reset(void) +{ + /* Write the System Configuration Control Register */ + mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, + V2M_CFGCTRL_START | + V2M_CFGCTRL_RW | + V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); + wfi(); + ERROR("FVP System Reset: operation not handled.\n"); + panic(); +} diff --git a/plat/arm/board/fvp/fvp_gicv3.c b/plat/arm/board/fvp/fvp_gicv3.c index 8f3e7b702..e780f21f2 100644 --- a/plat/arm/board/fvp/fvp_gicv3.c +++ b/plat/arm/board/fvp/fvp_gicv3.c @@ -7,6 +7,7 @@ #include <assert.h> #include <platform_def.h> +#include <common/debug.h> #include <common/interrupt_props.h> #include <drivers/arm/gicv3.h> #include <fconf_hw_config_getter.h> diff --git a/plat/arm/board/fvp/fvp_plat_attest_token.c b/plat/arm/board/fvp/fvp_plat_attest_token.c index 5463f3374..4dd37a4eb 100644 --- a/plat/arm/board/fvp/fvp_plat_attest_token.c +++ b/plat/arm/board/fvp/fvp_plat_attest_token.c @@ -10,298 +10,92 @@ /* Using hardcoded token values for AEM FVP */ static uint8_t platform_token[] = { - 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0x98, 0x18, 0xB5, 0x16, 0x9C, 0x21, 0x78, 0xB7, - 0x92, 0xF8, 0x26, 0x82, 0x76, 0x2F, 0x26, 0x45, - 0x21, 0x6D, 0x0C, 0x21, 0x06, 0xF4, 0xB5, 0xE3, - 0xA8, 0x07, 0xD1, 0xD6, 0x8C, 0x73, 0xA5, 0xC8, - 0x16, 0xD8, 0x30, 0x68, 0xC0, 0xA4, 0x77, 0xE2, - 0x1E, 0xD2, 0x17, 0x86, 0xC3, 0x68, 0x82, 0xDD, - 0x21, 0x1B, 0xA3, 0xE2, 0xC7, 0xF7, 0x06, 0x33, - 0xB0, 0x3A + 0xD2, 0x84, 0x40, 0xA0, 0x59, 0x02, 0x46, 0xA9, + 0x19, 0x01, 0x09, 0x78, 0x1C, 0x68, 0x74, 0x74, + 0x70, 0x3A, 0x2F, 0x2F, 0x61, 0x72, 0x6D, 0x2E, + 0x63, 0x6F, 0x6D, 0x2F, 0x43, 0x43, 0x41, 0x2D, + 0x53, 0x53, 0x44, 0x2F, 0x31, 0x2E, 0x30, 0x2E, + 0x30, 0x0A, 0x58, 0x20, 0x07, 0x06, 0x05, 0x04, + 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, + 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, + 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, + 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, 0x5C, 0x58, + 0x40, 0x7F, 0x45, 0x4C, 0x46, 0x02, 0x01, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x3E, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x50, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xA0, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x38, + 0x00, 0x09, 0x00, 0x40, 0x00, 0x1C, 0x00, 0x1B, + 0x00, 0x19, 0x01, 0x00, 0x58, 0x21, 0x01, 0x07, + 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, + 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, + 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, + 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, + 0x09, 0x61, 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, + 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, + 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, + 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, + 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, 0x5B, + 0x19, 0x30, 0x03, 0x19, 0x09, 0x62, 0x67, 0x73, + 0x68, 0x61, 0x2D, 0x32, 0x35, 0x36, 0x19, 0x09, + 0x5F, 0x84, 0xA5, 0x01, 0x62, 0x42, 0x4C, 0x05, + 0x58, 0x20, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, + 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, + 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, + 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, + 0x19, 0x18, 0x04, 0x65, 0x33, 0x2E, 0x34, 0x2E, + 0x32, 0x02, 0x58, 0x20, 0x07, 0x06, 0x05, 0x04, + 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, + 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, + 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, + 0x1B, 0x1A, 0x19, 0x18, 0x06, 0x67, 0x73, 0x68, + 0x61, 0x2D, 0x32, 0x35, 0x36, 0xA4, 0x01, 0x62, + 0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06, 0x05, + 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, + 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, + 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, + 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63, 0x31, + 0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06, 0x05, + 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, + 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, + 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, + 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01, 0x62, + 0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06, 0x05, + 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, + 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, + 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, + 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65, 0x31, + 0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20, 0x07, + 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, + 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, + 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, + 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, + 0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20, 0x07, + 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, + 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, + 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, + 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, + 0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06, 0x05, + 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, + 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, + 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, + 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, 0x60, + 0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76, 0x65, + 0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x40, 0x84, + 0x32, 0x12, 0x5B, 0x92, 0x6B, 0x20, 0xD8, 0x14, + 0xC1, 0xC1, 0x8C, 0x3C, 0x73, 0xB8, 0x29, 0x0F, + 0x42, 0xBC, 0x0B, 0x25, 0x87, 0x5C, 0x4F, 0xA4, + 0xFA, 0xD9, 0xDE, 0xC1, 0x2B, 0x20, 0xED, 0xDF, + 0x1C, 0xDD, 0x1A, 0x09, 0xBD, 0xA0, 0x25, 0x48, + 0xC6, 0xBB, 0x99, 0xA1, 0x30, 0x4F, 0x2C, 0xDC, + 0x89, 0xE8, 0xB7, 0xFF, 0x32, 0xE9, 0x3F, 0xBB, + 0xC6, 0xBF, 0x9D, 0x38, 0x68, 0xE1, 0xB2, }; -int plat_get_cca_attest_token(uintptr_t buf, size_t *len, - uintptr_t hash, size_t hash_size) +int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len, + uintptr_t hash, size_t hash_size) { (void)hash; (void)hash_size; diff --git a/plat/arm/board/fvp/fvp_realm_attest_key.c b/plat/arm/board/fvp/fvp_realm_attest_key.c index b32f557f5..1af1f0d3f 100644 --- a/plat/arm/board/fvp/fvp_realm_attest_key.c +++ b/plat/arm/board/fvp/fvp_realm_attest_key.c @@ -19,7 +19,8 @@ static uint8_t sample_attest_priv_key[] = { 0xEB, 0x1A, 0x41, 0x85, 0xBD, 0x11, 0x7F, 0x68 }; -int plat_get_cca_realm_attest_key(uintptr_t buf, size_t *len, unsigned int type) +int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len, + unsigned int type) { assert(type == ATTEST_KEY_CURVE_ECC_SECP384R1); diff --git a/plat/arm/board/fvp/include/fvp_critical_data.h b/plat/arm/board/fvp/include/fvp_critical_data.h index 3010d2180..04bd5b2ed 100644 --- a/plat/arm/board/fvp/include/fvp_critical_data.h +++ b/plat/arm/board/fvp/include/fvp_critical_data.h @@ -1,8 +1,10 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#ifndef FVP_CRITICAL_DATA_H +#define FVP_CRITICAL_DATA_H #include <common/nv_cntr_ids.h> #include <lib/utils_def.h> @@ -17,3 +19,5 @@ struct fvp_critical_data { /* platform NV counters */ unsigned int nv_ctr[MAX_NV_CTR_IDS]; }; + +#endif /* FVP_CRITICAL_DATA_H */ diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 82bd7c8a5..1ef6c87a2 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -127,11 +127,7 @@ #if defined(IMAGE_BL31) # if SPM_MM # define PLAT_ARM_MMAP_ENTRIES 10 -# if ENABLE_RME -# define MAX_XLAT_TABLES 11 -# else -# define MAX_XLAT_TABLES 9 -# endif +# define MAX_XLAT_TABLES 9 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 # elif SPMC_AT_EL3 @@ -141,13 +137,15 @@ # define PLAT_ARM_MMAP_ENTRIES 9 # if USE_DEBUGFS # if ENABLE_RME -# define MAX_XLAT_TABLES 10 +# define MAX_XLAT_TABLES 9 # else # define MAX_XLAT_TABLES 8 # endif # else # if ENABLE_RME -# define MAX_XLAT_TABLES 9 +# define MAX_XLAT_TABLES 8 +# elif DRTM_SUPPORT +# define MAX_XLAT_TABLES 8 # else # define MAX_XLAT_TABLES 7 # endif @@ -197,6 +195,9 @@ # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) #elif CRYPTO_SUPPORT # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) +#elif ARM_BL31_IN_DRAM +/* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) #else # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) #endif @@ -248,9 +249,17 @@ #elif defined(IMAGE_BL2U) # define PLATFORM_STACK_SIZE UL(0x400) #elif defined(IMAGE_BL31) +# if DRTM_SUPPORT +# define PLATFORM_STACK_SIZE UL(0x1000) +# else # define PLATFORM_STACK_SIZE UL(0x800) +# endif /* DRTM_SUPPORT */ #elif defined(IMAGE_BL32) -# define PLATFORM_STACK_SIZE UL(0x440) +# if SPMC_AT_EL3 +# define PLATFORM_STACK_SIZE UL(0x1000) +# else +# define PLATFORM_STACK_SIZE UL(0x440) +# endif /* SPMC_AT_EL3 */ #elif defined(IMAGE_RMM) # define PLATFORM_STACK_SIZE UL(0x440) #endif @@ -394,4 +403,14 @@ */ #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) +/* + * Maximum size of Event Log buffer used for DRTM + */ +#define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) + +/* + * Number of MMAP entries used by DRTM implementation + */ +#define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES + #endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 54c5e7545..51ba03524 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -132,17 +132,18 @@ else lib/cpus/aarch64/neoverse_n2.S \ lib/cpus/aarch64/neoverse_e1.S \ lib/cpus/aarch64/neoverse_v1.S \ - lib/cpus/aarch64/neoverse_demeter.S \ + lib/cpus/aarch64/neoverse_v2.S \ lib/cpus/aarch64/cortex_a78_ae.S \ lib/cpus/aarch64/cortex_a510.S \ - lib/cpus/aarch64/cortex_a710.S \ - lib/cpus/aarch64/cortex_makalu.S \ - lib/cpus/aarch64/cortex_makalu_elp_arm.S \ + lib/cpus/aarch64/cortex_a710.S \ + lib/cpus/aarch64/cortex_a715.S \ + lib/cpus/aarch64/cortex_x3.S \ lib/cpus/aarch64/cortex_a65.S \ lib/cpus/aarch64/cortex_a65ae.S \ lib/cpus/aarch64/cortex_a78c.S \ lib/cpus/aarch64/cortex_hayes.S \ lib/cpus/aarch64/cortex_hunter.S \ + lib/cpus/aarch64/cortex_hunter_elp_arm.S \ lib/cpus/aarch64/cortex_x2.S \ lib/cpus/aarch64/neoverse_poseidon.S endif @@ -341,10 +342,6 @@ ifeq ($(filter 1,${BL2_AT_EL3} ${ARM_XLAT_TABLES_LIB_V1}),) endif endif -ifeq (${ENABLE_RME},1) - BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC -endif - ifeq (${ALLOW_RO_XLAT_TABLES}, 1) ifeq (${ARCH},aarch32) BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES @@ -375,6 +372,10 @@ ifeq (${MEASURED_BOOT},1) $(info Including ${RSS_MEASURED_BOOT_MK}) include ${RSS_MEASURED_BOOT_MK} + ifneq (${MBOOT_RSS_HASH_ALG}, sha256) + $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) + endif + BL1_SOURCES += ${MEASURED_BOOT_SOURCES} BL2_SOURCES += ${MEASURED_BOOT_SOURCES} endif @@ -391,12 +392,44 @@ BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ plat/arm/board/fvp/fvp_bl2_measured_boot.c \ lib/psa/measured_boot.c +# Note that attestation code does not depend on measured boot interfaces per se, +# but the two features go together - attestation without boot measurements is +# pretty much pointless... +BL31_SOURCES += lib/psa/delegated_attestation.c + PLAT_INCLUDES += -Iinclude/lib/psa # RSS is not supported on FVP right now. Thus, we use the mocked version -# of PSA Measured Boot APIs. They return with success and hard-coded data. +# of the provided PSA APIs. They return with success and hard-coded data. PLAT_RSS_NOT_SUPPORTED := 1 +# Even though RSS is not supported on FVP (see above), we support overriding +# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building +# the code to detect any build regressions. The resulting firmware will not be +# functional. +ifneq (${PLAT_RSS_NOT_SUPPORTED},1) + $(warning "RSS is not supported on FVP. The firmware will not be functional.") + include drivers/arm/rss/rss_comms.mk + BL1_SOURCES += ${RSS_COMMS_SOURCES} + BL2_SOURCES += ${RSS_COMMS_SOURCES} + BL31_SOURCES += ${RSS_COMMS_SOURCES} \ + lib/psa/delegated_attestation.c + + BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 + BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 + BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 +endif + +endif + +ifeq (${DRTM_SUPPORT}, 1) +BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ + plat/arm/board/fvp/fvp_drtm_dma_prot.c \ + plat/arm/board/fvp/fvp_drtm_err.c \ + plat/arm/board/fvp/fvp_drtm_measurement.c \ + plat/arm/board/fvp/fvp_drtm_stub.c \ + plat/arm/common/arm_dyn_cfg.c \ + plat/arm/board/fvp/fvp_err.c endif ifeq (${TRUSTED_BOARD_BOOT}, 1) diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 3265b0b72..409d7a60f 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -196,12 +196,6 @@ # define PLATFORM_STACK_SIZE UL(0x440) #endif -/* - * Since free SRAM space is scant, enable the ASSERTION message size - * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). - */ -#define PLAT_LOG_LEVEL_ASSERT 40 - /* CCI related constants */ #define PLAT_ARM_CCI_BASE UL(0x2c090000) #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 diff --git a/plat/arm/board/morello/morello_bl2_setup.c b/plat/arm/board/morello/morello_bl2_setup.c index 0d4b6d00f..da1f7ae10 100644 --- a/plat/arm/board/morello/morello_bl2_setup.c +++ b/plat/arm/board/morello/morello_bl2_setup.c @@ -1,27 +1,226 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <common/debug.h> +#include <drivers/arm/css/sds.h> +#include <lib/mmio.h> #include <lib/utils.h> #include <plat/arm/common/plat_arm.h> -void bl2_platform_setup(void) -{ +#include "morello_def.h" +#include <platform_def.h> + +#ifdef TARGET_PLATFORM_FVP +/* + * Platform information structure stored in SDS. + * This structure holds information about platform's DDR + * size + * - Local DDR size in bytes, DDR memory in main board + */ +struct morello_plat_info { + uint64_t local_ddr_size; +} __packed; +#else +/* + * Platform information structure stored in SDS. + * This structure holds information about platform's DDR + * size which is an information about multichip setup + * - Local DDR size in bytes, DDR memory in main board + * - Remote DDR size in bytes, DDR memory in remote board + * - remote_chip_count + * - multichip mode + * - scc configuration + */ +struct morello_plat_info { + uint64_t local_ddr_size; + uint64_t remote_ddr_size; + uint8_t remote_chip_count; + bool multichip_mode; + uint32_t scc_config; +} __packed; +#endif + +/* Compile time assertion to ensure the size of structure is 18 bytes */ +CASSERT(sizeof(struct morello_plat_info) == MORELLO_SDS_PLATFORM_INFO_SIZE, + assert_invalid_plat_info_size); + #ifdef TARGET_PLATFORM_SOC - /* - * Morello platform supports RDIMMs with ECC capability. To use the ECC - * capability, the entire DDR memory space has to be zeroed out before - * enabling the ECC bits in DMC-Bing. - * Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF during BL2 stage, - * as BL33 binary cannot be copied to DDR memory before enabling ECC. - * Rest of the DDR memory space is zeroed out during BL31 stage. - */ +/* + * Morello platform supports RDIMMs with ECC capability. To use the ECC + * capability, the entire DDR memory space has to be zeroed out before + * enabling the ECC bits in DMC-Bing. Zeroing out several gigabytes of + * memory from SCP is quite time consuming so the following function + * is added to zero out the DDR memory from application processor which is + * much faster compared to SCP. + */ + +static void dmc_ecc_setup(struct morello_plat_info *plat_info) +{ + uint64_t dram2_size; + uint32_t val; + uint64_t tag_mem_base; + uint64_t usable_mem_size; + + INFO("Total DIMM size: %uGB\n", + (uint32_t)(plat_info->local_ddr_size / 0x40000000)); + + assert(plat_info->local_ddr_size > ARM_DRAM1_SIZE); + dram2_size = plat_info->local_ddr_size - ARM_DRAM1_SIZE; + INFO("Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF\n"); zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); + + INFO("Zeroing DDR memory range 0x%llx - 0x%llx\n", + ARM_DRAM2_BASE, ARM_DRAM2_BASE + dram2_size); + zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); + flush_dcache_range(ARM_DRAM2_BASE, dram2_size); + + /* Clear previous ECC errors while zeroing out the memory */ + val = mmio_read_32(MORELLO_DMC0_ERR2STATUS_REG); + mmio_write_32(MORELLO_DMC0_ERR2STATUS_REG, val); + + val = mmio_read_32(MORELLO_DMC1_ERR2STATUS_REG); + mmio_write_32(MORELLO_DMC1_ERR2STATUS_REG, val); + + /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ + mmio_write_32(MORELLO_DMC0_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_CONFIG); + mmio_write_32(MORELLO_DMC1_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_CONFIG); + + while ((mmio_read_32(MORELLO_DMC0_MEMC_STATUS_REG) & + MORELLO_DMC_MEMC_STATUS_MASK) != + MORELLO_DMC_MEMC_CMD_CONFIG) { + continue; + } + + while ((mmio_read_32(MORELLO_DMC1_MEMC_STATUS_REG) & + MORELLO_DMC_MEMC_STATUS_MASK) != + MORELLO_DMC_MEMC_CMD_CONFIG) { + continue; + } + + /* Configure Bing client/server mode based on SCC configuration */ + if (plat_info->scc_config & MORELLO_SCC_CLIENT_MODE_MASK) { + INFO("Configuring DMC Bing in client mode\n"); + usable_mem_size = plat_info->local_ddr_size - + (plat_info->local_ddr_size / 128ULL); + + /* Linear DDR address */ + tag_mem_base = usable_mem_size; + tag_mem_base = tag_mem_base / 4; + + /* Reverse translation */ + if (tag_mem_base < ARM_DRAM1_BASE) { + tag_mem_base += ARM_DRAM1_BASE; + } else { + tag_mem_base = tag_mem_base - ARM_DRAM1_BASE + + ARM_DRAM2_BASE; + } + + mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x1); + mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x1); + mmio_write_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x1); + mmio_write_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x1); + + if (plat_info->scc_config & MORELLO_SCC_C1_TAG_CACHE_EN_MASK) { + mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x2); + mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x2); + INFO("C1 Tag Cache Enabled\n"); + } + + if (plat_info->scc_config & MORELLO_SCC_C2_TAG_CACHE_EN_MASK) { + mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x4); + mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x4); + INFO("C2 Tag Cache Enabled\n"); + } + + mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL, + (uint32_t)tag_mem_base); + mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL, + (uint32_t)tag_mem_base); + mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL2, + (uint32_t)(tag_mem_base >> 32)); + mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL2, + (uint32_t)(tag_mem_base >> 32)); + + mmio_setbits_32(MORELLO_DMC0_MEM_ACCESS_CTL, + MORELLO_DMC_MEM_ACCESS_DIS); + mmio_setbits_32(MORELLO_DMC1_MEM_ACCESS_CTL, + MORELLO_DMC_MEM_ACCESS_DIS); + + INFO("Tag base set to 0x%lx\n", tag_mem_base); + plat_info->local_ddr_size = usable_mem_size; + } else { + INFO("Configuring DMC Bing in server mode\n"); + mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x0); + mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x0); + } + + INFO("Enabling ECC on DMCs\n"); + /* Enable ECC in DMCs */ + mmio_setbits_32(MORELLO_DMC0_ERR0CTLR0_REG, + MORELLO_DMC_ERR0CTLR0_ECC_EN); + mmio_setbits_32(MORELLO_DMC1_ERR0CTLR0_REG, + MORELLO_DMC_ERR0CTLR0_ECC_EN); + + /* Set DMCs to READY state */ + mmio_write_32(MORELLO_DMC0_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_READY); + mmio_write_32(MORELLO_DMC1_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_READY); + + while ((mmio_read_32(MORELLO_DMC0_MEMC_STATUS_REG) & + MORELLO_DMC_MEMC_STATUS_MASK) != + MORELLO_DMC_MEMC_CMD_READY) { + continue; + } + + while ((mmio_read_32(MORELLO_DMC1_MEMC_STATUS_REG) & + MORELLO_DMC_MEMC_STATUS_MASK) != + MORELLO_DMC_MEMC_CMD_READY) { + continue; + } +} +#endif + +void bl2_platform_setup(void) +{ + int ret; + struct morello_plat_info plat_info; + + ret = sds_init(); + if (ret != SDS_OK) { + ERROR("SDS initialization failed. ret:%d\n", ret); + panic(); + } + + ret = sds_struct_read(MORELLO_SDS_PLATFORM_INFO_STRUCT_ID, + MORELLO_SDS_PLATFORM_INFO_OFFSET, + &plat_info, + MORELLO_SDS_PLATFORM_INFO_SIZE, + SDS_ACCESS_MODE_NON_CACHED); + if (ret != SDS_OK) { + ERROR("Error getting platform info from SDS. ret:%d\n", ret); + panic(); + } + + /* Validate plat_info SDS */ +#ifdef TARGET_PLATFORM_FVP + if (plat_info.local_ddr_size == 0U) { +#else + if ((plat_info.local_ddr_size == 0U) + || (plat_info.local_ddr_size > MORELLO_MAX_DDR_CAPACITY) + || (plat_info.remote_ddr_size > MORELLO_MAX_DDR_CAPACITY) + || (plat_info.remote_chip_count > MORELLO_MAX_REMOTE_CHIP_COUNT) + ) { +#endif + ERROR("platform info SDS is corrupted\n"); + panic(); + } + +#ifdef TARGET_PLATFORM_SOC + dmc_ecc_setup(&plat_info); #endif arm_bl2_platform_setup(); } diff --git a/plat/arm/board/morello/morello_bl31_setup.c b/plat/arm/board/morello/morello_bl31_setup.c index e41851810..a04421200 100644 --- a/plat/arm/board/morello/morello_bl31_setup.c +++ b/plat/arm/board/morello/morello_bl31_setup.c @@ -1,54 +1,16 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#include <common/debug.h> #include <drivers/arm/css/css_mhu_doorbell.h> #include <drivers/arm/css/scmi.h> -#include <drivers/arm/css/sds.h> -#include <lib/cassert.h> -#include <lib/utils.h> #include <plat/arm/common/plat_arm.h> #include "morello_def.h" #include <platform_def.h> -#ifdef TARGET_PLATFORM_FVP -/* - * Platform information structure stored in SDS. - * This structure holds information about platform's DDR - * size - * - Local DDR size in bytes, DDR memory in main board - */ -struct morello_plat_info { - uint64_t local_ddr_size; -} __packed; -#else -/* - * Platform information structure stored in SDS. - * This structure holds information about platform's DDR - * size which is an information about multichip setup - * - Local DDR size in bytes, DDR memory in main board - * - Remote DDR size in bytes, DDR memory in remote board - * - remote_chip_count - * - multichip mode - * - scc configuration - */ -struct morello_plat_info { - uint64_t local_ddr_size; - uint64_t remote_ddr_size; - uint8_t remote_chip_count; - bool multichip_mode; - uint32_t scc_config; -} __packed; -#endif - -/* Compile time assertion to ensure the size of structure is 18 bytes */ -CASSERT(sizeof(struct morello_plat_info) == MORELLO_SDS_PLATFORM_INFO_SIZE, - assert_invalid_plat_info_size); - static scmi_channel_plat_info_t morello_scmi_plat_info = { .scmi_mbx_mem = MORELLO_SCMI_PAYLOAD_BASE, .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, @@ -67,177 +29,7 @@ const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) return css_scmi_override_pm_ops(ops); } -#ifdef TARGET_PLATFORM_SOC -/* - * Morello platform supports RDIMMs with ECC capability. To use the ECC - * capability, the entire DDR memory space has to be zeroed out before - * enabling the ECC bits in DMC-Bing. Zeroing out several gigabytes of - * memory from SCP is quite time consuming so the following function - * is added to zero out the DDR memory from application processor which is - * much faster compared to SCP. - */ - -static void dmc_ecc_setup(struct morello_plat_info *plat_info) -{ - uint64_t dram2_size; - uint32_t val; - uint64_t tag_mem_base; - uint64_t usable_mem_size; - - INFO("Total DIMM size: %uGB\n", - (uint32_t)(plat_info->local_ddr_size / 0x40000000)); - - assert(plat_info->local_ddr_size > ARM_DRAM1_SIZE); - dram2_size = plat_info->local_ddr_size - ARM_DRAM1_SIZE; - - INFO("Zeroing DDR memory range 0x%llx - 0x%llx\n", - ARM_DRAM2_BASE, ARM_DRAM2_BASE + dram2_size); - zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); - flush_dcache_range(ARM_DRAM2_BASE, dram2_size); - - /* Clear previous ECC errors while zeroing out the memory */ - val = mmio_read_32(MORELLO_DMC0_ERR2STATUS_REG); - mmio_write_32(MORELLO_DMC0_ERR2STATUS_REG, val); - - val = mmio_read_32(MORELLO_DMC1_ERR2STATUS_REG); - mmio_write_32(MORELLO_DMC1_ERR2STATUS_REG, val); - - /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ - mmio_write_32(MORELLO_DMC0_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_CONFIG); - mmio_write_32(MORELLO_DMC1_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_CONFIG); - - while ((mmio_read_32(MORELLO_DMC0_MEMC_STATUS_REG) & - MORELLO_DMC_MEMC_STATUS_MASK) != - MORELLO_DMC_MEMC_CMD_CONFIG) { - continue; - } - - while ((mmio_read_32(MORELLO_DMC1_MEMC_STATUS_REG) & - MORELLO_DMC_MEMC_STATUS_MASK) != - MORELLO_DMC_MEMC_CMD_CONFIG) { - continue; - } - - /* Configure Bing client/server mode based on SCC configuration */ - if (plat_info->scc_config & MORELLO_SCC_CLIENT_MODE_MASK) { - INFO("Configuring DMC Bing in client mode\n"); - usable_mem_size = plat_info->local_ddr_size - - (plat_info->local_ddr_size / 128ULL); - - /* Linear DDR address */ - tag_mem_base = usable_mem_size; - tag_mem_base = tag_mem_base / 4; - - /* Reverse translation */ - if (tag_mem_base < ARM_DRAM1_BASE) { - tag_mem_base += ARM_DRAM1_BASE; - } else { - tag_mem_base = tag_mem_base - ARM_DRAM1_BASE + - ARM_DRAM2_BASE; - } - - mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x1); - mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x1); - mmio_write_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x1); - mmio_write_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x1); - - if (plat_info->scc_config & MORELLO_SCC_C1_TAG_CACHE_EN_MASK) { - mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x2); - mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x2); - INFO("C1 Tag Cache Enabled\n"); - } - - if (plat_info->scc_config & MORELLO_SCC_C2_TAG_CACHE_EN_MASK) { - mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x4); - mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x4); - INFO("C2 Tag Cache Enabled\n"); - } - - mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL, - (uint32_t)tag_mem_base); - mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL, - (uint32_t)tag_mem_base); - mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL2, - (uint32_t)(tag_mem_base >> 32)); - mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL2, - (uint32_t)(tag_mem_base >> 32)); - - mmio_setbits_32(MORELLO_DMC0_MEM_ACCESS_CTL, - MORELLO_DMC_MEM_ACCESS_DIS); - mmio_setbits_32(MORELLO_DMC1_MEM_ACCESS_CTL, - MORELLO_DMC_MEM_ACCESS_DIS); - - INFO("Tag base set to 0x%lx\n", tag_mem_base); - plat_info->local_ddr_size = usable_mem_size; - } else { - INFO("Configuring DMC Bing in server mode\n"); - mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x0); - mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x0); - } - - INFO("Enabling ECC on DMCs\n"); - /* Enable ECC in DMCs */ - mmio_setbits_32(MORELLO_DMC0_ERR0CTLR0_REG, - MORELLO_DMC_ERR0CTLR0_ECC_EN); - mmio_setbits_32(MORELLO_DMC1_ERR0CTLR0_REG, - MORELLO_DMC_ERR0CTLR0_ECC_EN); - - /* Set DMCs to READY state */ - mmio_write_32(MORELLO_DMC0_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_READY); - mmio_write_32(MORELLO_DMC1_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_READY); - - while ((mmio_read_32(MORELLO_DMC0_MEMC_STATUS_REG) & - MORELLO_DMC_MEMC_STATUS_MASK) != - MORELLO_DMC_MEMC_CMD_READY) { - continue; - } - - while ((mmio_read_32(MORELLO_DMC1_MEMC_STATUS_REG) & - MORELLO_DMC_MEMC_STATUS_MASK) != - MORELLO_DMC_MEMC_CMD_READY) { - continue; - } -} -#endif - void bl31_platform_setup(void) { - int ret; - struct morello_plat_info plat_info; - - ret = sds_init(); - if (ret != SDS_OK) { - ERROR("SDS initialization failed. ret:%d\n", ret); - panic(); - } - - ret = sds_struct_read(MORELLO_SDS_PLATFORM_INFO_STRUCT_ID, - MORELLO_SDS_PLATFORM_INFO_OFFSET, - &plat_info, - MORELLO_SDS_PLATFORM_INFO_SIZE, - SDS_ACCESS_MODE_NON_CACHED); - if (ret != SDS_OK) { - ERROR("Error getting platform info from SDS. ret:%d\n", ret); - panic(); - } - - /* Validate plat_info SDS */ -#ifdef TARGET_PLATFORM_FVP - if (plat_info.local_ddr_size == 0U) { -#else - if ((plat_info.local_ddr_size == 0U) - || (plat_info.local_ddr_size > MORELLO_MAX_DDR_CAPACITY) - || (plat_info.remote_ddr_size > MORELLO_MAX_DDR_CAPACITY) - || (plat_info.remote_chip_count > MORELLO_MAX_REMOTE_CHIP_COUNT) - ) { -#endif - ERROR("platform info SDS is corrupted\n"); - panic(); - } - arm_bl31_platform_setup(); - -#ifdef TARGET_PLATFORM_SOC - dmc_ecc_setup(&plat_info); -#endif } diff --git a/plat/arm/board/morello/morello_plat.c b/plat/arm/board/morello/morello_plat.c index 42e5171ca..1da0ff96a 100644 --- a/plat/arm/board/morello/morello_plat.c +++ b/plat/arm/board/morello/morello_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,7 +15,7 @@ * Table of regions to map using the MMU. * Replace or extend the below regions as required */ -#if IMAGE_BL1 || IMAGE_BL31 +#if IMAGE_BL1 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, MORELLO_MAP_DEVICE, @@ -25,12 +25,23 @@ const mmap_region_t plat_arm_mmap[] = { {0} }; #endif + +#if IMAGE_BL31 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + MORELLO_MAP_DEVICE, + MORELLO_MAP_NS_SRAM, + {0} +}; +#endif + #if IMAGE_BL2 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, MORELLO_MAP_DEVICE, MORELLO_MAP_NS_SRAM, ARM_MAP_DRAM1, + ARM_MAP_DRAM2, #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3 ARM_MAP_BL1_RW, #endif diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk index 86047e39f..156b7ea2c 100644 --- a/plat/arm/board/morello/platform.mk +++ b/plat/arm/board/morello/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2020-2021, Arm Limited. All rights reserved. +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -83,6 +83,8 @@ override CTX_INCLUDE_AARCH32_REGS := 0 override ARM_PLAT_MT := 1 +override ARM_BL31_IN_DRAM := 1 + # Errata workarounds: ERRATA_N1_1868343 := 1 diff --git a/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts b/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts index f61e30bc5..700b900ef 100644 --- a/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts +++ b/plat/arm/board/n1sdp/fdts/n1sdp_fw_config.dts @@ -15,7 +15,11 @@ max-size = <0x200>; id = <TB_FW_CONFIG_ID>; }; - + tos_fw-config { + load-address = <0x0 0x4001600>; + max-size = <0x1000>; + id = <TOS_FW_CONFIG_ID>; + }; nt_fw-config { load-address = <0x0 0xFEF00000>; max-size = <0x0100000>; diff --git a/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts b/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts new file mode 100644 index 000000000..ed870803c --- /dev/null +++ b/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/dts-v1/; + +/ { + compatible = "arm,ffa-core-manifest-1.0"; + #address-cells = <2>; + #size-cells = <1>; + + /* + * BL32 image details needed by SPMC + * + * Note: + * binary_size: size of BL32 + TOS_FW_CONFIG + */ + + attribute { + spmc_id = <0x8000>; + maj_ver = <0x1>; + min_ver = <0x0>; + exec_state = <0x0>; + load_address = <0x0 0x08000000>; + entrypoint = <0x0 0x08000000>; + binary_size = <0x2000000>; + }; + +}; diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index c9b81bafa..b3799a7b2 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h @@ -15,8 +15,9 @@ #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 -#define PLAT_ARM_RUN_UART_BASE 0x2A410000 -#define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000 +/* IOFPGA UART0 */ +#define PLAT_ARM_RUN_UART_BASE 0x1C090000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000 #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 @@ -91,7 +92,7 @@ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size * plus a little space for growth. */ -#define PLAT_ARM_MAX_BL1_RW_SIZE 0xE000 +#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 /* * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page @@ -110,12 +111,16 @@ * little space for growth. */ #if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL2_SIZE 0x20000 +# define PLAT_ARM_MAX_BL2_SIZE 0x22000 #else # define PLAT_ARM_MAX_BL2_SIZE 0x14000 #endif -#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) +#define PLAT_ARM_MAX_BL31_SIZE UL(0x40000) + +#define PLAT_ARM_SPMC_BASE U(0x08000000) +#define PLAT_ARM_SPMC_SIZE UL(0x02000000) /* 32 MB */ + /******************************************************************************* * N1SDP topology related constants diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk index 740fb2988..9c0cc022c 100644 --- a/plat/arm/board/n1sdp/platform.mk +++ b/plat/arm/board/n1sdp/platform.mk @@ -68,6 +68,13 @@ $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) # Add the NT_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG})) +N1SDP_SPMC_MANIFEST_DTS := ${N1SDP_BASE}/fdts/${PLAT}_optee_spmc_manifest.dts +FDT_SOURCES += ${N1SDP_SPMC_MANIFEST_DTS} +N1SDP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_optee_spmc_manifest.dtb + +# Add the TOS_FW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${N1SDP_TOS_FW_CONFIG},--tos-fw-config,${N1SDP_TOS_FW_CONFIG})) + # Setting to 0 as no NVCTR in N1SDP N1SDP_FW_NVCTR_VAL := 0 TFW_NVCTR_VAL := ${N1SDP_FW_NVCTR_VAL} diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h index a9b30a41d..69bfd7bcf 100644 --- a/plat/arm/board/rde1edge/include/platform_def.h +++ b/plat/arm/board/rde1edge/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, Arm Limited. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,12 +26,15 @@ #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 +/* Maximum number of address bits used per chip */ +#define CSS_SGI_ADDR_BITS_PER_CHIP U(36) + /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ #ifdef __aarch64__ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) #else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h index a61b0d555..de0190272 100644 --- a/plat/arm/board/rdn1edge/include/platform_def.h +++ b/plat/arm/board/rdn1edge/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,12 +30,17 @@ /* Virtual address used by dynamic mem_protect for chunk_base */ #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) +/* Maximum number of address bits used per chip */ +#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) + /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ #ifdef __aarch64__ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) +#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ + CSS_SGI_CHIP_COUNT) +#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ + CSS_SGI_CHIP_COUNT) #else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk index 22ab312ee..95753aafc 100644 --- a/plat/arm/board/rdn1edge/platform.mk +++ b/plat/arm/board/rdn1edge/platform.mk @@ -4,6 +4,8 @@ # SPDX-License-Identifier: BSD-3-Clause # +$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected) + # GIC-600 configuration GICV3_IMPL_GIC600_MULTICHIP := 1 diff --git a/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts b/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts index bbc36fc14..dd70141de 100644 --- a/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts +++ b/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020 - 2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,5 +18,26 @@ platform-id = <0x0>; config-id = <0x0>; multi-chip-mode = <0x0>; + /* + * First cell pair: Count of isolated CPUs in the list. + * Rest of the cells: MPID list of the isolated CPUs. + */ + isolated-cpu-list = <0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0>; }; }; diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h index e4015f75b..347401626 100644 --- a/plat/arm/board/rdn2/include/platform_def.h +++ b/plat/arm/board/rdn2/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,15 +69,16 @@ */ #ifdef __aarch64__ #if (CSS_SGI_PLATFORM_VARIANT == 2) +#define CSS_SGI_ADDR_BITS_PER_CHIP U(46) /* 64TB */ +#else +#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) /* 4TB */ +#endif + #define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ CSS_SGI_CHIP_COUNT) #define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ CSS_SGI_CHIP_COUNT) #else -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) -#endif -#else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #endif @@ -95,4 +96,8 @@ #define PLAT_ARM_GICR_BASE UL(0x301C0000) #endif +/* Interrupt priority level for shutdown/reboot */ +#define PLAT_REBOOT_PRI GIC_HIGHEST_SEC_PRIORITY +#define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI) + #endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk index b882dc823..7492fe5ce 100644 --- a/plat/arm/board/rdn2/platform.mk +++ b/plat/arm/board/rdn2/platform.mk @@ -1,4 +1,4 @@ -# Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -18,12 +18,16 @@ endif # RD-N2 platform uses GIC-700 which is based on GICv4.1 GIC_ENABLE_V4_EXTN := 1 +GIC_EXT_INTID := 1 #Enable GIC Multichip Extension only for Multichip Platforms ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2) GICV3_IMPL_GIC600_MULTICHIP := 1 endif +override CSS_SYSTEM_GRACEFUL_RESET := 1 +override EL3_EXCEPTION_HANDLING := 1 + include plat/arm/css/sgi/sgi-common.mk RDN2_BASE = plat/arm/board/rdn2 @@ -31,7 +35,7 @@ RDN2_BASE = plat/arm/board/rdn2 PLAT_INCLUDES += -I${RDN2_BASE}/include/ SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S \ - lib/cpus/aarch64/neoverse_demeter.S + lib/cpus/aarch64/neoverse_v2.S PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c diff --git a/plat/arm/board/rdn2/rdn2_plat.c b/plat/arm/board/rdn2/rdn2_plat.c index 8cf192972..2506f9da0 100644 --- a/plat/arm/board/rdn2/rdn2_plat.c +++ b/plat/arm/board/rdn2/rdn2_plat.c @@ -47,15 +47,15 @@ static struct gic600_multichip_data rdn2mc_multichip_data __init = { #endif }, .spi_ids = { - {32, 479}, + {32, 511}, #if CSS_SGI_CHIP_COUNT > 1 - {0, 0}, + {512, 991}, #endif #if CSS_SGI_CHIP_COUNT > 2 - {0, 0}, + {4096, 4575}, #endif #if CSS_SGI_CHIP_COUNT > 3 - {0, 0}, + {4576, 5055}, #endif } }; diff --git a/plat/arm/board/rdv1/include/platform_def.h b/plat/arm/board/rdv1/include/platform_def.h index 5b98b4e8c..620fa3e2d 100644 --- a/plat/arm/board/rdv1/include/platform_def.h +++ b/plat/arm/board/rdv1/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,12 +46,15 @@ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) +/* Maximum number of address bits used per chip */ +#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) + /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ #ifdef __aarch64__ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) #else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) diff --git a/plat/arm/board/rdv1mc/include/platform_def.h b/plat/arm/board/rdv1mc/include/platform_def.h index 12ce8063a..367090488 100644 --- a/plat/arm/board/rdv1mc/include/platform_def.h +++ b/plat/arm/board/rdv1mc/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,6 +46,9 @@ /* Virtual address used by dynamic mem_protect for chunk_base */ #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000) +/* Remote chip address offset (4TB per chip) */ +#define CSS_SGI_ADDR_BITS_PER_CHIP U(42) + /* Physical and virtual address space limits for MMU in AARCH64 mode */ #define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \ CSS_SGI_CHIP_COUNT) diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h index 72d5f7cf0..82a38c549 100644 --- a/plat/arm/board/sgi575/include/platform_def.h +++ b/plat/arm/board/sgi575/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,12 +27,15 @@ #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 +/* Maximum number of address bits used per chip */ +#define CSS_SGI_ADDR_BITS_PER_CHIP U(36) + /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ #ifdef __aarch64__ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) #else #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk index 0761b77ef..2f2bf73b4 100644 --- a/plat/arm/board/sgi575/platform.mk +++ b/plat/arm/board/sgi575/platform.mk @@ -4,6 +4,8 @@ # SPDX-License-Identifier: BSD-3-Clause # +$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected) + include plat/arm/css/sgi/sgi-common.mk SGI575_BASE = plat/arm/board/sgi575 diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h index 745d91cab..bc4f25449 100644 --- a/plat/arm/board/tc/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -101,7 +101,7 @@ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size * plus a little space for growth. */ -#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 +#define PLAT_ARM_MAX_BL1_RW_SIZE 0xD000 /* * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page @@ -117,20 +117,19 @@ /* * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a - * little space for growth. + * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT + * and MEASURED_BOOT is enabled. */ -#if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL2_SIZE 0x20000 -#else -# define PLAT_ARM_MAX_BL2_SIZE 0x14000 -#endif +# define PLAT_ARM_MAX_BL2_SIZE 0x26000 + /* * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is * calculated using the current BL31 PROGBITS debug size plus the sizes of - * BL2 and BL1-RW + * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and + * MEASURED_BOOT is enabled. */ -#define PLAT_ARM_MAX_BL31_SIZE 0x3F000 +#define PLAT_ARM_MAX_BL31_SIZE 0x47000 /* * Size of cacheable stacks @@ -159,6 +158,13 @@ # define PLATFORM_STACK_SIZE 0x440 #endif +/* + * In the current implementation the RoT Service request that requires the + * biggest message buffer is the RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The + * maximum required buffer size is calculated based on the platform-specific + * needs of this request. + */ +#define PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE 0x500 #define TC_DEVICE_BASE 0x21000000 #define TC_DEVICE_SIZE 0x5f000000 @@ -177,8 +183,14 @@ #define PLAT_ARM_NSTIMER_FRAME_ID 0 +#if (TARGET_PLATFORM >= 2) +#define PLAT_ARM_TRUSTED_ROM_BASE 0x1000 +#else #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 -#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ +#endif + +/* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ +#define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) #define PLAT_ARM_NSRAM_BASE 0x06000000 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ @@ -214,9 +226,14 @@ #define PLAT_MAX_CPUS_PER_CLUSTER U(8) #define PLAT_MAX_PE_PER_CPU U(1) +/* Message Handling Unit (MHU) base addresses */ #define PLAT_CSS_MHU_BASE UL(0x45400000) #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE +/* TC2: AP<->RSS MHUs */ +#define PLAT_RSS_AP_SND_MHU_BASE UL(0x2A840000) +#define PLAT_RSS_AP_RCV_MHU_BASE UL(0x2A850000) + #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index 3acd88e78..37ba2295c 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -1,14 +1,21 @@ -# Copyright (c) 2021, Arm Limited. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include common/fdt_wrappers.mk -ifeq ($(filter ${TARGET_PLATFORM}, 0 1),) - $(error TARGET_PLATFORM must be 0 or 1) +ifeq ($(TARGET_PLATFORM), 0) +$(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \ +Some of the features might not work as expected) endif +ifeq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0) + $(error TARGET_PLATFORM must be less than or equal to 2) +endif + +$(eval $(call add_define,TARGET_PLATFORM)) + CSS_LOAD_SCP_IMAGES := 1 CSS_USE_SCMI_SDS_DRIVER := 1 @@ -19,7 +26,7 @@ SDEI_SUPPORT := 0 EL3_EXCEPTION_HANDLING := 0 -HANDLE_EA_EL3_FIRST := 0 +HANDLE_EA_EL3_FIRST_NS := 0 # System coherency is managed in hardware HW_ASSISTED_COHERENCY := 1 @@ -61,19 +68,25 @@ TC_BASE = plat/arm/board/tc PLAT_INCLUDES += -I${TC_BASE}/include/ -# Common CPU libraries -TC_CPU_SOURCES := lib/cpus/aarch64/cortex_a510.S - # CPU libraries for TARGET_PLATFORM=0 ifeq (${TARGET_PLATFORM}, 0) -TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a710.S \ +TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \ + lib/cpus/aarch64/cortex_a710.S \ lib/cpus/aarch64/cortex_x2.S endif # CPU libraries for TARGET_PLATFORM=1 ifeq (${TARGET_PLATFORM}, 1) -TC_CPU_SOURCES += lib/cpus/aarch64/cortex_makalu.S \ - lib/cpus/aarch64/cortex_makalu_elp_arm.S +TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \ + lib/cpus/aarch64/cortex_a715.S \ + lib/cpus/aarch64/cortex_x3.S +endif + +# CPU libraries for TARGET_PLATFORM=2 +ifeq (${TARGET_PLATFORM}, 2) +TC_CPU_SOURCES += lib/cpus/aarch64/cortex_hayes.S \ + lib/cpus/aarch64/cortex_hunter.S \ + lib/cpus/aarch64/cortex_hunter_elp_arm.S endif INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c @@ -87,7 +100,6 @@ BL1_SOURCES += ${INTERCONNECT_SOURCES} \ ${TC_BASE}/tc_err.c \ drivers/arm/sbsa/sbsa.c - BL2_SOURCES += ${TC_BASE}/tc_security.c \ ${TC_BASE}/tc_err.c \ ${TC_BASE}/tc_trusted_boot.c \ @@ -155,6 +167,32 @@ override ENABLE_AMU_FCONF := 1 override ENABLE_MPMM := 1 override ENABLE_MPMM_FCONF := 1 +# Include Measured Boot makefile before any Crypto library makefile. +# Crypto library makefile may need default definitions of Measured Boot build +# flags present in Measured Boot makefile. +ifeq (${MEASURED_BOOT},1) + MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk + $(info Including ${MEASURED_BOOT_MK}) + include ${MEASURED_BOOT_MK} + $(info Including rss_comms.mk) + include drivers/arm/rss/rss_comms.mk + + BL1_SOURCES += ${MEASURED_BOOT_SOURCES} \ + plat/arm/board/tc/tc_common_measured_boot.c \ + plat/arm/board/tc/tc_bl1_measured_boot.c \ + lib/psa/measured_boot.c \ + ${RSS_COMMS_SOURCES} + + BL2_SOURCES += ${MEASURED_BOOT_SOURCES} \ + plat/arm/board/tc/tc_common_measured_boot.c \ + plat/arm/board/tc/tc_bl2_measured_boot.c \ + lib/psa/measured_boot.c \ + ${RSS_COMMS_SOURCES} + +PLAT_INCLUDES += -Iinclude/lib/psa + +endif + include plat/arm/common/arm_common.mk include plat/arm/css/common/css_common.mk include plat/arm/soc/common/soc_css.mk diff --git a/plat/arm/board/tc/tc_bl1_measured_boot.c b/plat/arm/board/tc/tc_bl1_measured_boot.c new file mode 100644 index 000000000..0d29c5114 --- /dev/null +++ b/plat/arm/board/tc/tc_bl1_measured_boot.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <drivers/arm/rss_comms.h> +#include <drivers/measured_boot/rss/rss_measured_boot.h> +#include <lib/psa/measured_boot.h> + +#include <plat/arm/common/plat_arm.h> +#include <platform_def.h> + +/* Table with platform specific image IDs and metadata. Intentionally not a + * const struct, some members might set by bootloaders during trusted boot. + */ +struct rss_mboot_metadata tc_rss_mboot_metadata[] = { + { + .id = FW_CONFIG_ID, + .slot = U(6), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_FW_CONFIG_STRING, + .lock_measurement = true }, + { + .id = TB_FW_CONFIG_ID, + .slot = U(7), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_TB_FW_CONFIG_STRING, + .lock_measurement = true }, + { + .id = BL2_IMAGE_ID, + .slot = U(8), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_BL2_STRING, + .lock_measurement = true }, + + { + .id = RSS_MBOOT_INVALID_ID } +}; + +void bl1_plat_mboot_init(void) +{ + /* Initialize the communication channel between AP and RSS */ + (void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, + PLAT_RSS_AP_RCV_MHU_BASE); + + rss_measured_boot_init(); +} + +void bl1_plat_mboot_finish(void) +{ + /* Nothing to do. */ +} diff --git a/plat/arm/board/tc/tc_bl2_measured_boot.c b/plat/arm/board/tc/tc_bl2_measured_boot.c new file mode 100644 index 000000000..7ea2c2ec4 --- /dev/null +++ b/plat/arm/board/tc/tc_bl2_measured_boot.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <drivers/arm/rss_comms.h> +#include <drivers/measured_boot/rss/rss_measured_boot.h> +#include <lib/psa/measured_boot.h> + +#include <plat/common/common_def.h> +#include <platform_def.h> + +/* TC specific table with image IDs and metadata. Intentionally not a + * const struct, some members might set by bootloaders during trusted boot. + */ +struct rss_mboot_metadata tc_rss_mboot_metadata[] = { + { + .id = BL31_IMAGE_ID, + .slot = U(9), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_BL31_STRING, + .lock_measurement = true }, + { + .id = HW_CONFIG_ID, + .slot = U(10), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_HW_CONFIG_STRING, + .lock_measurement = true }, + { + .id = SOC_FW_CONFIG_ID, + .slot = U(11), + .signer_id_size = SIGNER_ID_MIN_SIZE, + .sw_type = RSS_MBOOT_SOC_FW_CONFIG_STRING, + .lock_measurement = true }, + { + .id = RSS_MBOOT_INVALID_ID } +}; + +void bl2_plat_mboot_init(void) +{ + /* Initialize the communication channel between AP and RSS */ + (void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, + PLAT_RSS_AP_RCV_MHU_BASE); + + rss_measured_boot_init(); +} + +void bl2_plat_mboot_finish(void) +{ + /* Nothing to do. */ +} diff --git a/plat/arm/board/tc/tc_common_measured_boot.c b/plat/arm/board/tc/tc_common_measured_boot.c new file mode 100644 index 000000000..fe718995a --- /dev/null +++ b/plat/arm/board/tc/tc_common_measured_boot.c @@ -0,0 +1,35 @@ + +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <stdint.h> + +#include <common/desc_image_load.h> +#include <drivers/measured_boot/rss/rss_measured_boot.h> + +extern struct rss_mboot_metadata tc_rss_mboot_metadata[]; + +struct rss_mboot_metadata *plat_rss_mboot_get_metadata(void) +{ + return tc_rss_mboot_metadata; +} + +int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data) +{ + int err; + + /* Calculate image hash and record data in RSS */ + err = rss_mboot_measure_and_record(image_data->image_base, + image_data->image_size, + image_id); + if (err != 0) { + ERROR("%s%s image id %u (%i)\n", + "Failed to ", "record in RSS", image_id, err); + } + + return err; +} diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c index a9668e117..77db023fd 100644 --- a/plat/arm/board/tc/tc_plat.c +++ b/plat/arm/board/tc/tc_plat.c @@ -135,7 +135,7 @@ const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( } #endif /* SPM_MM && defined(IMAGE_BL31) */ -#if TRUSTED_BOARD_BOOT +#if TRUSTED_BOARD_BOOT || MEASURED_BOOT int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) { assert(heap_addr != NULL); diff --git a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c index 78360b06c..18f1a3798 100644 --- a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c +++ b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c @@ -20,71 +20,72 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { #ifdef SCP_BL2_BASE /* Fill SCP_BL2 related information if it exists */ - { - .image_id = SCP_BL2_IMAGE_ID, + { + .image_id = SCP_BL2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #endif /* SCP_BL2_BASE */ /* Fill BL32 related information */ - { - .image_id = BL32_IMAGE_ID, + { + .image_id = BL32_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL32_BASE, - .ep_info.spsr = SPSR_MODE32(MODE32_mon, SPSR_T_ARM, - SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL32_BASE, + .ep_info.spsr = SPSR_MODE32(MODE32_mon, SPSR_T_ARM, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = BL33_IMAGE_ID, - }, + .next_handoff_image_id = BL33_IMAGE_ID, + }, /* Fill HW_CONFIG related information if it exists */ - { - .image_id = HW_CONFIG_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + { + .image_id = HW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, + NON_SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* Fill BL33 related information */ - { - .image_id = BL33_IMAGE_ID, + { + .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), #ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, + .ep_info.pc = PRELOADED_BL33_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), #else - .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, + .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, - .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE - - PLAT_ARM_NS_IMAGE_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, + .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE + - PLAT_ARM_NS_IMAGE_BASE, #endif /* PRELOADED_BL33_BASE */ - .next_handoff_image_id = INVALID_IMAGE_ID, - } + .next_handoff_image_id = INVALID_IMAGE_ID, + } }; REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c index 0666e57fa..3d7b3613e 100644 --- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c +++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c @@ -20,203 +20,207 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { #ifdef SCP_BL2_BASE /* Fill SCP_BL2 related information if it exists */ - { - .image_id = SCP_BL2_IMAGE_ID, + { + .image_id = SCP_BL2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #endif /* SCP_BL2_BASE */ #ifdef EL3_PAYLOAD_BASE /* Fill EL3 payload related information (BL31 is EL3 payload)*/ - { - .image_id = BL31_IMAGE_ID, + { + .image_id = BL31_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #else /* EL3_PAYLOAD_BASE */ /* Fill BL31 related information */ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), #if DEBUG - .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL, + .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL, #endif - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, # if defined(BL32_BASE) - .next_handoff_image_id = BL32_IMAGE_ID, + .next_handoff_image_id = BL32_IMAGE_ID, # elif ENABLE_RME - .next_handoff_image_id = RMM_IMAGE_ID, + .next_handoff_image_id = RMM_IMAGE_ID, # else - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, # endif - }, + }, /* Fill HW_CONFIG related information */ - { - .image_id = HW_CONFIG_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + { + .image_id = HW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, + NON_SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* Fill SOC_FW_CONFIG related information */ - { - .image_id = SOC_FW_CONFIG_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + { + .image_id = SOC_FW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, # if ENABLE_RME /* Fill RMM related information */ - { - .image_id = RMM_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, EP_REALM | EXECUTABLE), - .ep_info.pc = RMM_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = RMM_BASE, - .image_info.image_max_size = RMM_LIMIT - RMM_BASE, - .next_handoff_image_id = BL33_IMAGE_ID, - }, + { + .image_id = RMM_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, EP_REALM | EXECUTABLE), + .ep_info.pc = RMM_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = RMM_BASE, + .image_info.image_max_size = RMM_LIMIT - RMM_BASE, + .next_handoff_image_id = BL33_IMAGE_ID, + }, # endif # ifdef BL32_BASE /* Fill BL32 related information */ - { - .image_id = BL32_IMAGE_ID, + { + .image_id = BL32_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), - .ep_info.pc = BL32_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, # if ENABLE_RME - .next_handoff_image_id = RMM_IMAGE_ID, + .next_handoff_image_id = RMM_IMAGE_ID, # else - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, # endif - }, + }, /* * Fill BL32 external 1 related information. - * A typical use for extra1 image is with OP-TEE where it is the pager image. + * A typical use for extra1 image is with OP-TEE where it is the pager + * image. */ - { - .image_id = BL32_EXTRA1_IMAGE_ID, + { + .image_id = BL32_EXTRA1_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* * Fill BL32 external 2 related information. - * A typical use for extra2 image is with OP-TEE where it is the paged image. + * A typical use for extra2 image is with OP-TEE where it is the paged + * image. */ - { - .image_id = BL32_EXTRA2_IMAGE_ID, + { + .image_id = BL32_EXTRA2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), #ifdef SPD_opteed - .image_info.image_base = ARM_OPTEE_PAGEABLE_LOAD_BASE, - .image_info.image_max_size = ARM_OPTEE_PAGEABLE_LOAD_SIZE, + .image_info.image_base = ARM_OPTEE_PAGEABLE_LOAD_BASE, + .image_info.image_max_size = ARM_OPTEE_PAGEABLE_LOAD_SIZE, #endif - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* Fill TOS_FW_CONFIG related information */ - { - .image_id = TOS_FW_CONFIG_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + { + .image_id = TOS_FW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, # endif /* BL32_BASE */ /* Fill BL33 related information */ - { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), # ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, + .ep_info.pc = PRELOADED_BL33_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), # else - .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, + .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, - .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE - - PLAT_ARM_NS_IMAGE_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE, + .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE + - PLAT_ARM_NS_IMAGE_BASE, # endif /* PRELOADED_BL33_BASE */ - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* Fill NT_FW_CONFIG related information */ - { - .image_id = NT_FW_CONFIG_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - } + { + .image_id = NT_FW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, + NON_SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + } #endif /* EL3_PAYLOAD_BASE */ }; diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index 7a9e04d0c..70002362d 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -11,6 +11,7 @@ #include <arch.h> #include <bl1/bl1.h> #include <common/bl_common.h> +#include <common/debug.h> #include <lib/fconf/fconf.h> #include <lib/fconf/fconf_dyn_cfg_getter.h> #include <lib/utils.h> diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index a6f7df5f4..cf403b161 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -164,6 +164,14 @@ void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_confi bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +#if ENABLE_RME + /* + * Populate entry point information for RMM. + * Only PC needs to be set as other fields are determined by RMMD. + */ + rmm_image_ep_info.pc = RMM_BASE; +#endif /* ENABLE_RME */ + #else /* RESET_TO_BL31 */ /* diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 946b7329f..fc681149e 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -237,3 +237,7 @@ int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) } #endif +const mmap_region_t *plat_get_addr_mmap(void) +{ + return plat_arm_mmap; +} diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 6d7aa2df5..7162ce984 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -73,6 +73,14 @@ ARM_BL31_IN_DRAM := 0 $(eval $(call assert_boolean,ARM_BL31_IN_DRAM)) $(eval $(call add_define,ARM_BL31_IN_DRAM)) +# As per CCA security model, all root firmware must execute from on-chip secure +# memory. This means we must not run BL31 from TZC-protected DRAM. +ifeq (${ARM_BL31_IN_DRAM},1) + ifeq (${ENABLE_RME},1) + $(error "BL31 must not run from DRAM on RME-systems. Please set ARM_BL31_IN_DRAM to 0") + endif +endif + # Process ARM_PLAT_MT flag ARM_PLAT_MT := 0 $(eval $(call assert_boolean,ARM_PLAT_MT)) @@ -106,7 +114,7 @@ ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) endif endif -# Arm Ethos-N NPU SiP service +# Arm(R) Ethos(TM)-N NPU SiP service ARM_ETHOSN_NPU_DRIVER := 0 $(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER)) $(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER)) @@ -187,8 +195,10 @@ endif # Enable CRC instructions via extension for ARMv8-A CPUs. # For ARMv8.1-A, and onwards CRC instructions are default enabled. # Enable HW computed CRC support unconditionally in BL2 component. -ifeq (${ARM_ARCH_MINOR},0) - BL2_CPPFLAGS += -march=armv8-a+crc +ifeq (${ARM_ARCH_MAJOR},8) + ifeq (${ARM_ARCH_MINOR},0) + BL2_CPPFLAGS += -march=armv8-a+crc + endif endif ifeq ($(PSA_FWU_SUPPORT),1) @@ -355,6 +365,10 @@ BL31_SOURCES += plat/common/plat_spmd_manifest.c \ BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} endif +ifeq (${DRTM_SUPPORT},1) +BL31_SOURCES += plat/arm/common/arm_err.c +endif + ifneq (${TRUSTED_BOARD_BOOT},0) # Include common TBB sources @@ -373,6 +387,8 @@ ifneq (${TRUSTED_BOARD_BOOT},0) endif else ifeq (${COT},dualroot) AUTH_SOURCES += drivers/auth/dualroot/cot.c + else ifeq (${COT},cca) + AUTH_SOURCES += drivers/auth/cca/cot.c else $(error Unknown chain of trust ${COT}) endif @@ -396,20 +412,31 @@ endif # Include Measured Boot makefile before any Crypto library makefile. # Crypto library makefile may need default definitions of Measured Boot build # flags present in Measured Boot makefile. -ifeq (${MEASURED_BOOT},1) +ifneq ($(filter 1,${MEASURED_BOOT} ${DRTM_SUPPORT}),) MEASURED_BOOT_MK := drivers/measured_boot/event_log/event_log.mk $(info Including ${MEASURED_BOOT_MK}) include ${MEASURED_BOOT_MK} - BL1_SOURCES += ${EVENT_LOG_SOURCES} - BL2_SOURCES += ${EVENT_LOG_SOURCES} + ifneq (${MBOOT_EL_HASH_ALG}, sha256) + $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) + endif + + ifeq (${MEASURED_BOOT},1) + BL1_SOURCES += ${EVENT_LOG_SOURCES} + BL2_SOURCES += ${EVENT_LOG_SOURCES} + endif + + ifeq (${DRTM_SUPPORT},1) + BL31_SOURCES += ${EVENT_LOG_SOURCES} + endif endif -ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT}),) +ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT} ${DRTM_SUPPORT}),) CRYPTO_SOURCES := drivers/auth/crypto_mod.c \ lib/fconf/fconf_tbbr_getter.c BL1_SOURCES += ${CRYPTO_SOURCES} BL2_SOURCES += ${CRYPTO_SOURCES} + BL31_SOURCES += drivers/auth/crypto_mod.c # We expect to locate the *.mk files under the directories specified below ifeq (${ARM_CRYPTOCELL_INTEG},0) diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c index 83e3f9aa2..c88621e37 100644 --- a/plat/arm/common/arm_dyn_cfg.c +++ b/plat/arm/common/arm_dyn_cfg.c @@ -45,7 +45,7 @@ int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size) assert(heap_addr != NULL); assert(heap_size != NULL); -#if defined(IMAGE_BL1) || BL2_AT_EL3 +#if defined(IMAGE_BL1) || BL2_AT_EL3 || defined(IMAGE_BL31) /* If in BL1 or BL2_AT_EL3 define a heap */ static unsigned char heap[TF_MBEDTLS_HEAP_SIZE]; @@ -131,6 +131,7 @@ void arm_bl2_dyn_cfg_init(void) bl_mem_params_node_t *cfg_mem_params = NULL; uintptr_t image_base; uint32_t image_size; + unsigned int error_config_id = MAX_IMAGE_IDS; const unsigned int config_ids[] = { HW_CONFIG_ID, SOC_FW_CONFIG_ID, @@ -142,17 +143,17 @@ void arm_bl2_dyn_cfg_init(void) /* Iterate through all the fw config IDs */ for (i = 0; i < ARRAY_SIZE(config_ids); i++) { - /* Get the config load address and size from TB_FW_CONFIG */ + /* Get the config load address and size */ cfg_mem_params = get_bl_mem_params_node(config_ids[i]); if (cfg_mem_params == NULL) { - VERBOSE("%sHW_CONFIG in bl_mem_params_node\n", - "Couldn't find "); + VERBOSE("%sconfig_id = %d in bl_mem_params_node\n", + "Couldn't find ", config_ids[i]); continue; } dtb_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, config_ids[i]); if (dtb_info == NULL) { - VERBOSE("%sconfig_id %d load info in TB_FW_CONFIG\n", + VERBOSE("%sconfig_id %d load info in FW_CONFIG\n", "Couldn't find ", config_ids[i]); continue; } @@ -168,17 +169,32 @@ void arm_bl2_dyn_cfg_init(void) if (config_ids[i] != HW_CONFIG_ID) { if (check_uptr_overflow(image_base, image_size)) { + VERBOSE("%s=%d as its %s is overflowing uptr\n", + "skip loading of firmware config", + config_ids[i], + "load-address"); + error_config_id = config_ids[i]; continue; } #ifdef BL31_BASE /* Ensure the configs don't overlap with BL31 */ if ((image_base >= BL31_BASE) && (image_base <= BL31_LIMIT)) { + VERBOSE("%s=%d as its %s is overlapping BL31\n", + "skip loading of firmware config", + config_ids[i], + "load-address"); + error_config_id = config_ids[i]; continue; } #endif /* Ensure the configs are loaded in a valid address */ if (image_base < ARM_BL_RAM_BASE) { + VERBOSE("%s=%d as its %s is invalid\n", + "skip loading of firmware config", + config_ids[i], + "load-address"); + error_config_id = config_ids[i]; continue; } #ifdef BL32_BASE @@ -188,6 +204,11 @@ void arm_bl2_dyn_cfg_init(void) */ if ((image_base >= BL32_BASE) && (image_base <= BL32_LIMIT)) { + VERBOSE("%s=%d as its %s is overlapping BL32\n", + "skip loading of firmware config", + config_ids[i], + "load-address"); + error_config_id = config_ids[i]; continue; } #endif @@ -202,4 +223,9 @@ void arm_bl2_dyn_cfg_init(void) */ cfg_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; } + + if (error_config_id != MAX_IMAGE_IDS) { + ERROR("Invalid config file %u\n", error_config_id); + panic(); + } } diff --git a/plat/arm/common/arm_dyn_cfg_helpers.c b/plat/arm/common/arm_dyn_cfg_helpers.c index 6a2a6f89a..e88ea657f 100644 --- a/plat/arm/common/arm_dyn_cfg_helpers.c +++ b/plat/arm/common/arm_dyn_cfg_helpers.c @@ -6,6 +6,7 @@ #include <assert.h> +#include <common/debug.h> #if MEASURED_BOOT #include <common/desc_image_load.h> #endif diff --git a/plat/arm/common/arm_err.c b/plat/arm/common/arm_err.c index f80ba78c7..fa36e8d3a 100644 --- a/plat/arm/common/arm_err.c +++ b/plat/arm/common/arm_err.c @@ -13,3 +13,8 @@ void __dead2 plat_error_handler(int err) { plat_arm_error_handler(err); } + +void __dead2 plat_system_reset(void) +{ + plat_arm_system_reset(); +} diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index 4a3a22ec0..469e22ade 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -7,6 +7,7 @@ #include <assert.h> #include <platform_def.h> +#include <common/debug.h> #include <common/interrupt_props.h> #include <drivers/arm/gicv3.h> #include <lib/utils.h> diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c index aea2f38d4..6c323312c 100644 --- a/plat/arm/common/fconf/arm_fconf_io.c +++ b/plat/arm/common/fconf/arm_fconf_io.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, ARM Limited. All rights reserved. + * Copyright (c) 2019-2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -72,6 +72,9 @@ const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = { #if TRUSTED_BOARD_BOOT [TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT}, #if !ARM_IO_IN_DTB + [CCA_CONTENT_CERT_ID] = {UUID_CCA_CONTENT_CERT}, + [CORE_SWD_KEY_CERT_ID] = {UUID_CORE_SWD_KEY_CERT}, + [PLAT_KEY_CERT_ID] = {UUID_PLAT_KEY_CERT}, [TRUSTED_KEY_CERT_ID] = {UUID_TRUSTED_KEY_CERT}, [SCP_FW_KEY_CERT_ID] = {UUID_SCP_FW_KEY_CERT}, [SOC_FW_KEY_CERT_ID] = {UUID_SOC_FW_KEY_CERT}, @@ -196,6 +199,21 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { open_fip }, #if !ARM_IO_IN_DTB + [CCA_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[CCA_CONTENT_CERT_ID], + open_fip + }, + [CORE_SWD_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[CORE_SWD_KEY_CERT_ID], + open_fip + }, + [PLAT_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&arm_uuid_spec[PLAT_KEY_CERT_ID], + open_fip + }, [TRUSTED_KEY_CERT_ID] = { &fip_dev_handle, (uintptr_t)&arm_uuid_spec[TRUSTED_KEY_CERT_ID], @@ -260,7 +278,7 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { #ifdef IMAGE_BL2 #if TRUSTED_BOARD_BOOT -#define FCONF_ARM_IO_UUID_NUMBER U(21) +#define FCONF_ARM_IO_UUID_NUMBER U(24) #else #define FCONF_ARM_IO_UUID_NUMBER U(10) #endif @@ -286,6 +304,9 @@ static const struct policies_load_info load_info[FCONF_ARM_IO_UUID_NUMBER] = { {TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"}, {NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"}, #if TRUSTED_BOARD_BOOT + {CCA_CONTENT_CERT_ID, "cca_cert_uuid"}, + {CORE_SWD_KEY_CERT_ID, "core_swd_cert_uuid"}, + {PLAT_KEY_CERT_ID, "plat_cert_uuid"}, {TRUSTED_KEY_CERT_ID, "t_key_cert_uuid"}, {SCP_FW_KEY_CERT_ID, "scp_fw_key_uuid"}, {SOC_FW_KEY_CERT_ID, "soc_fw_key_uuid"}, diff --git a/plat/arm/common/fconf/fconf_ethosn_getter.c b/plat/arm/common/fconf/fconf_ethosn_getter.c index 0af1a20fb..0b48a9816 100644 --- a/plat/arm/common/fconf/fconf_ethosn_getter.c +++ b/plat/arm/common/fconf/fconf_ethosn_getter.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,107 +12,341 @@ #include <libfdt.h> #include <plat/arm/common/fconf_ethosn_getter.h> -struct ethosn_config_t ethosn_config = {.num_cores = 0}; +struct ethosn_config_t ethosn_config = {0}; -static uint8_t fdt_node_get_status(const void *fdt, int node) +struct ethosn_sub_allocator_t { + const char *name; + size_t name_len; + uint32_t stream_id; +}; + +static bool fdt_node_is_enabled(const void *fdt, int node) { int len; - uint8_t status = ETHOSN_STATUS_DISABLED; const char *node_status; node_status = fdt_getprop(fdt, node, "status", &len); if (node_status == NULL || (len == 5 && /* Includes null character */ strncmp(node_status, "okay", 4U) == 0)) { - status = ETHOSN_STATUS_ENABLED; + return true; + } + + return false; +} + +static bool fdt_node_has_reserved_memory(const void *fdt, int dev_node) +{ + return fdt_get_property(fdt, dev_node, "memory-region", NULL) != NULL; +} + +static int fdt_node_get_iommus_stream_id(const void *fdt, int node, uint32_t *stream_id) +{ + int err; + uint32_t iommus_array[2] = {0U}; + + err = fdt_read_uint32_array(fdt, node, "iommus", 2U, iommus_array); + if (err) { + return err; + } + + *stream_id = iommus_array[1]; + return 0; +} + +static int fdt_node_populate_sub_allocators(const void *fdt, + int alloc_node, + struct ethosn_sub_allocator_t *sub_allocators, + size_t num_allocs) +{ + int sub_node; + size_t i; + int err = -FDT_ERR_NOTFOUND; + uint32_t found_sub_allocators = 0U; + + fdt_for_each_subnode(sub_node, fdt, alloc_node) { + const char *node_name; + + if (!fdt_node_is_enabled(fdt, sub_node)) { + /* Ignore disabled node */ + continue; + } + + if (fdt_node_check_compatible(fdt, sub_node, "ethosn-memory") != 0) { + continue; + } + + node_name = fdt_get_name(fdt, sub_node, NULL); + for (i = 0U; i < num_allocs; ++i) { + if (strncmp(node_name, sub_allocators[i].name, + sub_allocators[i].name_len) != 0) { + continue; + } + + err = fdt_node_get_iommus_stream_id(fdt, sub_node, + &sub_allocators[i].stream_id); + if (err) { + ERROR("FCONF: Failed to get stream ID from sub-allocator %s\n", + node_name); + return err; + } + + ++found_sub_allocators; + /* Nothing more to do for this node */ + break; + } + + /* Check that at least one of the sub-allocators matched */ + if (i == num_allocs) { + ERROR("FCONF: Unknown sub-allocator %s\n", node_name); + return -FDT_ERR_BADSTRUCTURE; + } + } + + if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) { + ERROR("FCONF: Failed to parse sub-allocators\n"); + return -FDT_ERR_BADSTRUCTURE; + } + + if (err == -FDT_ERR_NOTFOUND) { + ERROR("FCONF: No matching sub-allocator found\n"); + return err; + } + + if (found_sub_allocators != num_allocs) { + ERROR("FCONF: Not all sub-allocators were found\n"); + return -FDT_ERR_BADSTRUCTURE; + } + + return 0; +} + +static int fdt_node_populate_main_allocator(const void *fdt, + int alloc_node, + struct ethosn_main_allocator_t *allocator) +{ + int err; + struct ethosn_sub_allocator_t sub_allocators[] = { + {.name = "firmware", .name_len = 8U}, + {.name = "working_data", .name_len = 12U} + }; + + err = fdt_node_populate_sub_allocators(fdt, alloc_node, sub_allocators, + ARRAY_SIZE(sub_allocators)); + if (err) { + return err; + } + + allocator->firmware.stream_id = sub_allocators[0].stream_id; + allocator->working_data.stream_id = sub_allocators[1].stream_id; + + return 0; +} + +static int fdt_node_populate_asset_allocator(const void *fdt, + int alloc_node, + struct ethosn_asset_allocator_t *allocator) +{ + int err; + struct ethosn_sub_allocator_t sub_allocators[] = { + {.name = "command_stream", .name_len = 14U}, + {.name = "weight_data", .name_len = 11U}, + {.name = "buffer_data", .name_len = 11U}, + {.name = "intermediate_data", .name_len = 17U} + }; + + err = fdt_node_populate_sub_allocators(fdt, alloc_node, sub_allocators, + ARRAY_SIZE(sub_allocators)); + if (err) { + return err; } - return status; + + allocator->command_stream.stream_id = sub_allocators[0].stream_id; + allocator->weight_data.stream_id = sub_allocators[1].stream_id; + allocator->buffer_data.stream_id = sub_allocators[2].stream_id; + allocator->intermediate_data.stream_id = sub_allocators[3].stream_id; + return 0; +} + +static int fdt_node_populate_core(const void *fdt, + int device_node, + int core_node, + bool has_reserved_memory, + uint32_t core_index, + struct ethosn_core_t *core) +{ + int err; + int sub_node; + uintptr_t core_addr; + + err = fdt_get_reg_props_by_index(fdt, device_node, core_index, + &core_addr, NULL); + if (err < 0) { + ERROR("FCONF: Failed to read reg property for NPU core %u\n", + core_index); + return err; + } + + err = -FDT_ERR_NOTFOUND; + fdt_for_each_subnode(sub_node, fdt, core_node) { + + if (!fdt_node_is_enabled(fdt, sub_node)) { + continue; + } + + if (fdt_node_check_compatible(fdt, + sub_node, + "ethosn-main_allocator") != 0) { + continue; + } + + if (has_reserved_memory) { + ERROR("FCONF: Main allocator not supported when using reserved memory\n"); + return -FDT_ERR_BADSTRUCTURE; + } + + if (err != -FDT_ERR_NOTFOUND) { + ERROR("FCONF: NPU core 0x%lx has more than one main allocator\n", + core_addr); + return -FDT_ERR_BADSTRUCTURE; + } + + err = fdt_node_populate_main_allocator(fdt, sub_node, &core->main_allocator); + if (err) { + ERROR("FCONF: Failed to parse main allocator for NPU core 0x%lx\n", + core_addr); + return err; + } + } + + if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) { + ERROR("FCONF: Failed to parse core sub nodes\n"); + return -FDT_ERR_BADSTRUCTURE; + } + + if (!has_reserved_memory && err) { + ERROR("FCONF: Main allocator not found for NPU core 0x%lx\n", + core_addr); + return err; + } + + core->addr = core_addr; + + return 0; } int fconf_populate_ethosn_config(uintptr_t config) { int ethosn_node; + uint32_t dev_count = 0U; const void *hw_conf_dtb = (const void *)config; - /* Find offset to node with 'ethosn' compatible property */ - INFO("Probing Arm Ethos-N NPU\n"); - uint32_t total_core_count = 0U; + INFO("Probing Arm(R) Ethos(TM)-N NPU\n"); fdt_for_each_compatible_node(hw_conf_dtb, ethosn_node, "ethosn") { + struct ethosn_device_t *dev = ðosn_config.devices[dev_count]; + uint32_t dev_asset_alloc_count = 0U; + uint32_t dev_core_count = 0U; + bool has_reserved_memory; int sub_node; - uint8_t ethosn_status; - uint32_t device_core_count = 0U; - /* If the Arm Ethos-N NPU is disabled the core check can be skipped */ - ethosn_status = fdt_node_get_status(hw_conf_dtb, ethosn_node); - if (ethosn_status == ETHOSN_STATUS_DISABLED) { + if (!fdt_node_is_enabled(hw_conf_dtb, ethosn_node)) { continue; } + if (dev_count >= ETHOSN_DEV_NUM_MAX) { + ERROR("FCONF: Reached max number of NPUs\n"); + return -FDT_ERR_BADSTRUCTURE; + } + + has_reserved_memory = fdt_node_has_reserved_memory(hw_conf_dtb, ethosn_node); fdt_for_each_subnode(sub_node, hw_conf_dtb, ethosn_node) { int err; - uintptr_t core_addr; - uint8_t core_status; - if (total_core_count >= ETHOSN_CORE_NUM_MAX) { - ERROR("FCONF: Reached max number of Arm Ethos-N NPU cores\n"); - return -FDT_ERR_BADSTRUCTURE; + if (!fdt_node_is_enabled(hw_conf_dtb, sub_node)) { + /* Ignore disabled sub node */ + continue; } - /* Check that the sub node is "ethosn-core" compatible */ if (fdt_node_check_compatible(hw_conf_dtb, sub_node, - "ethosn-core") != 0) { - /* Ignore incompatible sub node */ - continue; - } + "ethosn-core") == 0) { - core_status = fdt_node_get_status(hw_conf_dtb, sub_node); - if (core_status == ETHOSN_STATUS_DISABLED) { - continue; - } + if (dev_core_count >= ETHOSN_DEV_CORE_NUM_MAX) { + ERROR("FCONF: Reached max number of NPU cores for NPU %u\n", + dev_count); + return -FDT_ERR_BADSTRUCTURE; + } - err = fdt_get_reg_props_by_index(hw_conf_dtb, - ethosn_node, - device_core_count, - &core_addr, - NULL); - if (err < 0) { - ERROR( - "FCONF: Failed to read reg property for Arm Ethos-N NPU core %u\n", - device_core_count); - return err; - } + err = fdt_node_populate_core(hw_conf_dtb, + ethosn_node, + sub_node, + has_reserved_memory, + dev_core_count, + &(dev->cores[dev_core_count])); + if (err) { + return err; + } + ++dev_core_count; + } else if (fdt_node_check_compatible(hw_conf_dtb, + sub_node, + "ethosn-asset_allocator") == 0) { + + if (dev_asset_alloc_count >= + ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX) { + ERROR("FCONF: Reached max number of asset allocators for NPU %u\n", + dev_count); + return -FDT_ERR_BADSTRUCTURE; + } + + if (has_reserved_memory) { + ERROR("FCONF: Asset allocator not supported when using reserved memory\n"); + return -FDT_ERR_BADSTRUCTURE; + } - INFO("NPU core probed at address 0x%lx\n", core_addr); - ethosn_config.core[total_core_count].addr = core_addr; - total_core_count++; - device_core_count++; + err = fdt_node_populate_asset_allocator(hw_conf_dtb, + sub_node, + &(dev->asset_allocators[dev_asset_alloc_count])); + if (err) { + ERROR("FCONF: Failed to parse asset allocator for NPU %u\n", + dev_count); + return err; + } + ++dev_asset_alloc_count; + } } if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) { - ERROR("FCONF: Failed to parse sub nodes\n"); + ERROR("FCONF: Failed to parse sub nodes for NPU %u\n", + dev_count); + return -FDT_ERR_BADSTRUCTURE; + } + + if (dev_core_count == 0U) { + ERROR("FCONF: NPU %u must have at least one enabled core\n", + dev_count); return -FDT_ERR_BADSTRUCTURE; } - if (device_core_count == 0U) { - ERROR( - "FCONF: Enabled Arm Ethos-N NPU device must have at least one enabled core\n"); + if (!has_reserved_memory && dev_asset_alloc_count == 0U) { + ERROR("FCONF: NPU %u must have at least one asset allocator\n", + dev_count); return -FDT_ERR_BADSTRUCTURE; } + + dev->num_cores = dev_core_count; + dev->num_allocators = dev_asset_alloc_count; + dev->has_reserved_memory = has_reserved_memory; + ++dev_count; } - if (total_core_count == 0U) { + if (dev_count == 0U) { ERROR("FCONF: Can't find 'ethosn' compatible node in dtb\n"); return -FDT_ERR_BADSTRUCTURE; } - ethosn_config.num_cores = total_core_count; - - INFO("%d NPU core%s probed\n", - ethosn_config.num_cores, - ethosn_config.num_cores > 1 ? "s" : ""); + ethosn_config.num_devices = dev_count; return 0; } diff --git a/plat/arm/common/trp/arm_trp.mk b/plat/arm/common/trp/arm_trp.mk index 997111f99..204c14ac1 100644 --- a/plat/arm/common/trp/arm_trp.mk +++ b/plat/arm/common/trp/arm_trp.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -8,3 +8,5 @@ RMM_SOURCES += plat/arm/common/trp/arm_trp_setup.c \ plat/arm/common/arm_topology.c \ plat/common/aarch64/platform_mp_stack.S + +INCLUDES += -Iinclude/services/trp diff --git a/plat/arm/common/trp/arm_trp_setup.c b/plat/arm/common/trp/arm_trp_setup.c index 8e4829344..59b4c06e9 100644 --- a/plat/arm/common/trp/arm_trp_setup.c +++ b/plat/arm/common/trp/arm_trp_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,33 +8,65 @@ #include <common/debug.h> #include <drivers/arm/pl011.h> #include <drivers/console.h> +#include <services/rmm_core_manifest.h> +#include <services/rmmd_svc.h> +#include <services/trp/platform_trp.h> +#include <trp_helpers.h> + #include <plat/arm/common/plat_arm.h> #include <platform_def.h> /******************************************************************************* + * Received from boot manifest and populated here + ******************************************************************************/ +extern uint32_t trp_boot_manifest_version; + +/******************************************************************************* * Initialize the UART ******************************************************************************/ static console_t arm_trp_runtime_console; -void arm_trp_early_platform_setup(void) +static int arm_trp_process_manifest(rmm_manifest_t *manifest) +{ + /* Verify the Boot Manifest Version. Only the Major is considered */ + if (RMMD_MANIFEST_VERSION_MAJOR != + RMMD_GET_MANIFEST_VERSION_MAJOR(manifest->version)) { + return E_RMM_BOOT_MANIFEST_VERSION_NOT_SUPPORTED; + } + + trp_boot_manifest_version = manifest->version; + flush_dcache_range((uintptr_t)manifest, sizeof(rmm_manifest_t)); + + return 0; +} + +void arm_trp_early_platform_setup(rmm_manifest_t *manifest) { + int rc; + + rc = arm_trp_process_manifest(manifest); + if (rc != 0) { + trp_boot_abort(rc); + } + /* * Initialize a different console than already in use to display * messages from trp */ - int rc = console_pl011_register(PLAT_ARM_TRP_UART_BASE, - PLAT_ARM_TRP_UART_CLK_IN_HZ, - ARM_CONSOLE_BAUDRATE, - &arm_trp_runtime_console); + rc = console_pl011_register(PLAT_ARM_TRP_UART_BASE, + PLAT_ARM_TRP_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE, + &arm_trp_runtime_console); if (rc == 0) { panic(); } console_set_scope(&arm_trp_runtime_console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); + } -void trp_early_platform_setup(void) +void trp_early_platform_setup(rmm_manifest_t *manifest) { - arm_trp_early_platform_setup(); + arm_trp_early_platform_setup(manifest); } diff --git a/plat/arm/css/common/css_common.mk b/plat/arm/css/common/css_common.mk index 2fbbe4560..1e4851cd4 100644 --- a/plat/arm/css/common/css_common.mk +++ b/plat/arm/css/common/css_common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -35,6 +35,7 @@ BL31_SOURCES += drivers/arm/css/mhu/css_mhu_doorbell.c \ drivers/arm/css/scmi/scmi_common.c \ drivers/arm/css/scmi/scmi_pwr_dmn_proto.c \ drivers/arm/css/scmi/scmi_sys_pwr_proto.c \ + drivers/delay_timer/delay_timer.c \ drivers/arm/css/scp/css_pm_scmi.c endif @@ -88,3 +89,9 @@ CSS_NON_SECURE_UART := 0 $(eval $(call assert_boolean,CSS_NON_SECURE_UART)) $(eval $(call add_define,CSS_NON_SECURE_UART)) +# Process CSS_SYSTEM_GRACEFUL_RESET flag +# This build option can be used on CSS platforms that require all the CPUs +# to execute the CPU specific power down sequence to complete a warm reboot +# sequence in which only the CPUs are power cycled. +CSS_SYSTEM_GRACEFUL_RESET := 0 +$(eval $(call add_define,CSS_SYSTEM_GRACEFUL_RESET)) diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c index 926b8ec7c..9b2639c35 100644 --- a/plat/arm/css/common/css_pm.c +++ b/plat/arm/css/common/css_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,10 +9,14 @@ #include <platform_def.h> #include <arch_helpers.h> +#include <bl31/interrupt_mgmt.h> #include <common/debug.h> #include <drivers/arm/css/css_scp.h> #include <lib/cassert.h> #include <plat/arm/common/plat_arm.h> + +#include <plat/common/platform.h> + #include <plat/arm/css/common/css_pm.h> /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ @@ -110,6 +114,9 @@ void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state) /* Enable the gic cpu interface */ plat_arm_gic_cpuif_enable(); + + /* Setup the CPU power down request interrupt for secondary core(s) */ + css_setup_cpu_pwr_down_intr(); } /******************************************************************************* @@ -331,6 +338,52 @@ static int css_translate_power_state_by_mpidr(u_register_t mpidr, return arm_validate_power_state(power_state, output_state); } +/* + * Setup the SGI interrupt that will be used trigger the execution of power + * down sequence for all the secondary cores. This interrupt is setup to be + * handled in EL3 context at a priority defined by the platform. + */ +void css_setup_cpu_pwr_down_intr(void) +{ +#if CSS_SYSTEM_GRACEFUL_RESET + plat_ic_set_interrupt_type(CSS_CPU_PWR_DOWN_REQ_INTR, INTR_TYPE_EL3); + plat_ic_set_interrupt_priority(CSS_CPU_PWR_DOWN_REQ_INTR, + PLAT_REBOOT_PRI); + plat_ic_enable_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR); +#endif +} + +/* + * For a graceful shutdown/reboot, each CPU in the system should do their power + * down sequence. On a PSCI shutdown/reboot request, only one CPU gets an + * opportunity to do the powerdown sequence. To achieve graceful reset, of all + * cores in the system, the CPU gets the opportunity raise warm reboot SGI to + * rest of the CPUs which are online. Add handler for the reboot SGI where the + * rest of the CPU execute the powerdown sequence. + */ +int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags, + void *handle, void *cookie) +{ + assert(intr_raw == CSS_CPU_PWR_DOWN_REQ_INTR); + + /* Deactivate warm reboot SGI */ + plat_ic_end_of_interrupt(CSS_CPU_PWR_DOWN_REQ_INTR); + + /* + * Disable GIC CPU interface to prevent pending interrupt from waking + * up the AP from WFI. + */ + plat_arm_gic_cpuif_disable(); + plat_arm_gic_redistif_off(); + + psci_pwrdown_cpu(PLAT_MAX_PWR_LVL); + + dmbsy(); + + wfi(); + return 0; +} + /******************************************************************************* * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard * platform will take care of registering the handlers with PSCI. diff --git a/plat/arm/css/common/sp_min/css_sp_min.mk b/plat/arm/css/common/sp_min/css_sp_min.mk index 6523a164b..ae489fdf8 100644 --- a/plat/arm/css/common/sp_min/css_sp_min.mk +++ b/plat/arm/css/common/sp_min/css_sp_min.mk @@ -15,6 +15,7 @@ BL32_SOURCES += drivers/arm/css/mhu/css_mhu.c \ else BL32_SOURCES += drivers/arm/css/mhu/css_mhu_doorbell.c \ drivers/arm/css/scp/css_pm_scmi.c \ + drivers/delay_timer/delay_timer.c \ drivers/arm/css/scmi/scmi_common.c \ drivers/arm/css/scmi/scmi_pwr_dmn_proto.c \ drivers/arm/css/scmi/scmi_sys_pwr_proto.c diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index c9c8c0463..c1fadc654 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,10 +19,11 @@ CSS_SGI_MAX_CPUS_PER_CLUSTER * \ CSS_SGI_MAX_PE_PER_CPU) -#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ +#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ -/* Remote chip address offset (4TB per chip) */ -#define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) ((ULL(1) << 42) * (n)) +/* Remote chip address offset */ +#define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) \ + ((ULL(1) << CSS_SGI_ADDR_BITS_PER_CHIP) * (n)) /* * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the @@ -35,8 +36,8 @@ # if SPM_MM # define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) -# define PLAT_SP_IMAGE_MMAP_REGIONS 9 -# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 11 +# define PLAT_SP_IMAGE_MMAP_REGIONS 10 +# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 # else # define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) @@ -67,7 +68,7 @@ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size * plus a little space for growth. */ -#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 +#define PLAT_ARM_MAX_BL1_RW_SIZE (64 * 1024) /* 64 KB */ /* * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page @@ -98,10 +99,16 @@ /* * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is - * calculated using the current BL31 PROGBITS debug size plus the sizes of - * BL2 and BL1-RW + * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2 + * and BL1-RW. CSS_SGI_BL31_SIZE - is tuned with respect to the actual BL31 + * PROGBITS size which is around 64-68KB at the time this change is being made. + * A buffer of ~35KB is added to account for future expansion of the image, + * making it a total of 100KB. */ -#define PLAT_ARM_MAX_BL31_SIZE 0x3B000 +#define CSS_SGI_BL31_SIZE (100 * 1024) /* 100 KB */ +#define PLAT_ARM_MAX_BL31_SIZE (CSS_SGI_BL31_SIZE + \ + PLAT_ARM_MAX_BL2_SIZE + \ + PLAT_ARM_MAX_BL1_RW_SIZE) /* * Size of cacheable stacks @@ -130,6 +137,21 @@ # define PLATFORM_STACK_SIZE 0x440 #endif +/* PL011 UART related constants */ +#define SOC_CSS_SEC_UART_BASE UL(0x2A410000) +#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000) +#define SOC_CSS_UART_SIZE UL(0x10000) +#define SOC_CSS_UART_CLK_IN_HZ UL(7372800) + +/* UART related constants */ +#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ + +#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ + +#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ #define PLAT_ARM_NSTIMER_FRAME_ID 0 @@ -258,4 +280,21 @@ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \ ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} +#if SPM_MM + +/* + * Stand-alone MM logs would be routed via secure UART. Define page table + * entry for secure UART which would be common to all platforms. + */ +#define SOC_PLATFORM_SECURE_UART MAP_REGION_FLAT( \ + SOC_CSS_SEC_UART_BASE, \ + SOC_CSS_UART_SIZE, \ + MT_DEVICE | MT_RW | \ + MT_SECURE | MT_USER) + +#endif + +/* SDS ID for unusable CPU MPID list structure */ +#define SDS_ISOLATED_CPU_LIST_ID U(128) + #endif /* SGI_BASE_PLATFORM_DEF_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def.h b/plat/arm/css/sgi/include/sgi_soc_css_def.h new file mode 100644 index 000000000..f78b45a28 --- /dev/null +++ b/plat/arm/css/sgi/include/sgi_soc_css_def.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SGI_SOC_CSS_DEF_H +#define SGI_SOC_CSS_DEF_H + +#include <lib/utils_def.h> +#include <plat/arm/board/common/v2m_def.h> +#include <plat/arm/soc/common/soc_css_def.h> +#include <plat/common/common_def.h> + +/* + * Definitions common to all ARM CSSv1-based development platforms + */ + +/* Platform ID address */ +#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x7ffe00e0) + +/* Platform ID related accessors */ +#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f +#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 +#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 + +#ifndef __ASSEMBLER__ + +#include <lib/mmio.h> + +#define BOARD_CSS_GET_PLAT_TYPE(addr) \ + ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ + >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) + +#endif /* __ASSEMBLER__ */ + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/* Reserve the last block of flash for PSCI MEM PROTECT flag */ +#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE +#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +#endif /* SGI_SOC_CSS_DEF_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h index 639b687f1..acf31ebba 100644 --- a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h +++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,17 +24,10 @@ #define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000) -/* PL011 UART related constants */ -#define SOC_CSS_UART1_BASE UL(0x0ef80000) -#define SOC_CSS_UART0_BASE UL(0x0ef70000) - /* Memory controller */ #define SOC_MEMCNTRL_BASE UL(0x10000000) #define SOC_MEMCNTRL_SIZE UL(0x10000000) -#define SOC_CSS_UART0_CLK_IN_HZ UL(7372800) -#define SOC_CSS_UART1_CLK_IN_HZ UL(7372800) - /* SoC NIC-400 Global Programmers View (GPV) */ #define SOC_CSS_NIC400_BASE UL(0x0ED00000) @@ -206,17 +199,4 @@ #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) -/* UART related constants */ -#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE -#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ - -#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE -#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ - -#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE -#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ - -#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE -#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ - #endif /* SGI_SOC_CSS_DEF_V2_H */ diff --git a/plat/arm/css/sgi/include/sgi_soc_platform_def.h b/plat/arm/css/sgi/include/sgi_soc_platform_def.h index 405d62f12..3b8d9c664 100644 --- a/plat/arm/css/sgi/include/sgi_soc_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_soc_platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +7,10 @@ #ifndef SGI_SOC_PLATFORM_DEF_H #define SGI_SOC_PLATFORM_DEF_H -#include <sgi_base_platform_def.h> -#include <plat/arm/board/common/board_css_def.h> #include <plat/arm/board/common/v2m_def.h> #include <plat/arm/soc/common/soc_css_def.h> +#include <sgi_base_platform_def.h> +#include <sgi_soc_css_def.h> /* Map the System registers to access from S-EL0 */ #define CSS_SYSTEMREG_DEVICE_BASE (0x1C010000) diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h index 41467f7de..223ac3ecc 100644 --- a/plat/arm/css/sgi/include/sgi_variant.h +++ b/plat/arm/css/sgi/include/sgi_variant.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,9 +23,9 @@ /* SID Version values for RD-N2 variants */ #define RD_N2_CFG1_SID_VER_PART_NUM 0x07B6 -/* SID Version values for RD-Edmunds */ -#define RD_EDMUNDS_SID_VER_PART_NUM 0x07F2 -#define RD_EDMUNDS_CONFIG_ID 0x1 +/* SID Version values for RD-V2 */ +#define RD_V2_SID_VER_PART_NUM 0x07F2 +#define RD_V2_CONFIG_ID 0x1 /* Structure containing SGI platform variant information */ typedef struct sgi_platform_info { diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk index 76c8025ba..282a5f080 100644 --- a/plat/arm/css/sgi/sgi-common.mk +++ b/plat/arm/css/sgi/sgi-common.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -14,7 +14,7 @@ SDEI_SUPPORT := 0 EL3_EXCEPTION_HANDLING := 0 -HANDLE_EA_EL3_FIRST := 0 +HANDLE_EA_EL3_FIRST_NS := 0 CSS_SGI_CHIP_COUNT := 1 @@ -44,7 +44,8 @@ PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/aarch64/sgi_helper.S BL1_SOURCES += ${INTERCONNECT_SOURCES} \ drivers/arm/sbsa/sbsa.c -BL2_SOURCES += ${CSS_ENT_BASE}/sgi_image_load.c +BL2_SOURCES += ${CSS_ENT_BASE}/sgi_image_load.c \ + drivers/arm/css/sds/sds.c BL31_SOURCES += ${INTERCONNECT_SOURCES} \ ${ENT_GIC_SOURCES} \ @@ -68,7 +69,6 @@ $(eval $(call add_define,CSS_SGI_PLATFORM_VARIANT)) override CSS_LOAD_SCP_IMAGES := 0 override NEED_BL2U := no -override ARM_BL31_IN_DRAM := 1 override ARM_PLAT_MT := 1 override PSCI_EXTENDED_STATE_ID := 1 override ARM_RECOM_STATE_ID_ENC := 1 diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c index 99f2f2002..27cf18346 100644 --- a/plat/arm/css/sgi/sgi_bl31_setup.c +++ b/plat/arm/css/sgi/sgi_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,8 +13,11 @@ #include <drivers/arm/css/css_mhu_doorbell.h> #include <drivers/arm/css/scmi.h> #include <plat/arm/common/plat_arm.h> + #include <plat/common/platform.h> +#include <plat/arm/css/common/css_pm.h> + #include <sgi_ras.h> #include <sgi_variant.h> @@ -76,7 +79,7 @@ scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id) if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM || sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM || sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM || - sgi_plat_info.platform_id == RD_EDMUNDS_SID_VER_PART_NUM || + sgi_plat_info.platform_id == RD_V2_SID_VER_PART_NUM || sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) { if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info)) panic(); @@ -105,6 +108,15 @@ void sgi_bl31_common_platform_setup(void) #if RAS_EXTENSION sgi_ras_intr_handler_setup(); #endif + + /* Configure the warm reboot SGI for primary core */ + css_setup_cpu_pwr_down_intr(); + +#if CSS_SYSTEM_GRACEFUL_RESET + /* Register priority level handlers for reboot */ + ehf_register_priority_handler(PLAT_REBOOT_PRI, + css_reboot_interrupt_handler); +#endif } const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) diff --git a/plat/arm/css/sgi/sgi_image_load.c b/plat/arm/css/sgi/sgi_image_load.c index 09f3b728d..ac4bfd292 100644 --- a/plat/arm/css/sgi/sgi_image_load.c +++ b/plat/arm/css/sgi/sgi_image_load.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,16 +9,68 @@ #include <arch_helpers.h> #include <common/debug.h> #include <common/desc_image_load.h> +#include <drivers/arm/css/sds.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> +#include <platform_def.h> +#include <sgi_base_platform_def.h> #include <sgi_variant.h> +/* + * Information about the isolated CPUs obtained from SDS. + */ +struct isolated_cpu_mpid_list { + uint64_t num_entries; /* Number of entries in the list */ + uint64_t mpid_list[PLATFORM_CORE_COUNT]; /* List of isolated CPU MPIDs */ +}; + +/* Function to read isolated CPU MPID list from SDS. */ +void plat_arm_sgi_get_isolated_cpu_list(struct isolated_cpu_mpid_list *list) +{ + int ret; + + ret = sds_init(); + if (ret != SDS_OK) { + ERROR("SDS initialization failed, error: %d\n", ret); + panic(); + } + + ret = sds_struct_read(SDS_ISOLATED_CPU_LIST_ID, 0, &list->num_entries, + sizeof(list->num_entries), SDS_ACCESS_MODE_CACHED); + if (ret != SDS_OK) { + INFO("SDS CPU num elements read failed, error: %d\n", ret); + list->num_entries = 0; + return; + } + + if (list->num_entries > PLATFORM_CORE_COUNT) { + ERROR("Isolated CPU list count %ld greater than max" + " number supported %d\n", + list->num_entries, PLATFORM_CORE_COUNT); + panic(); + } else if (list->num_entries == 0) { + INFO("SDS isolated CPU list is empty\n"); + return; + } + + ret = sds_struct_read(SDS_ISOLATED_CPU_LIST_ID, + sizeof(list->num_entries), + &list->mpid_list, + sizeof(list->mpid_list[0]) * list->num_entries, + SDS_ACCESS_MODE_CACHED); + if (ret != SDS_OK) { + ERROR("SDS CPU list read failed. error: %d\n", ret); + panic(); + } +} + /******************************************************************************* * This function inserts Platform information via device tree nodes as, * system-id { * platform-id = <0>; * config-id = <0>; + * isolated-cpu-list = <0> * } ******************************************************************************/ static int plat_sgi_append_config_node(void) @@ -27,6 +79,7 @@ static int plat_sgi_append_config_node(void) void *fdt; int nodeoffset, err; unsigned int platid = 0, platcfg = 0; + struct isolated_cpu_mpid_list cpu_mpid_list = {0}; mem_params = get_bl_mem_params_node(NT_FW_CONFIG_ID); if (mem_params == NULL) { @@ -69,6 +122,18 @@ static int plat_sgi_append_config_node(void) return -1; } + plat_arm_sgi_get_isolated_cpu_list(&cpu_mpid_list); + if (cpu_mpid_list.num_entries > 0) { + err = fdt_setprop(fdt, nodeoffset, "isolated-cpu-list", + &cpu_mpid_list, + (sizeof(cpu_mpid_list.num_entries) * + (cpu_mpid_list.num_entries + 1))); + if (err < 0) { + ERROR("Failed to set isolated-cpu-list, error: %d\n", + err); + } + } + flush_dcache_range((uintptr_t)fdt, mem_params->image_info.image_size); return 0; diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c index 20c52e9c5..a0199c348 100644 --- a/plat/arm/css/sgi/sgi_plat.c +++ b/plat/arm/css/sgi/sgi_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -89,6 +89,7 @@ const mmap_region_t plat_arm_mmap[] = { const mmap_region_t plat_arm_secure_partition_mmap[] = { PLAT_ARM_SECURE_MAP_SYSTEMREG, PLAT_ARM_SECURE_MAP_NOR2, + SOC_PLATFORM_SECURE_UART, PLAT_ARM_SECURE_MAP_DEVICE, ARM_SP_IMAGE_MMAP, ARM_SP_IMAGE_NS_BUF_MMAP, diff --git a/plat/arm/css/sgi/sgi_plat_v2.c b/plat/arm/css/sgi/sgi_plat_v2.c index 1a2a96629..cef5345cd 100644 --- a/plat/arm/css/sgi/sgi_plat_v2.c +++ b/plat/arm/css/sgi/sgi_plat_v2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -83,6 +83,7 @@ const mmap_region_t plat_arm_mmap[] = { const mmap_region_t plat_arm_secure_partition_mmap[] = { PLAT_ARM_SECURE_MAP_SYSTEMREG, PLAT_ARM_SECURE_MAP_NOR2, + SOC_PLATFORM_SECURE_UART, SOC_PLATFORM_PERIPH_MAP_DEVICE_USER, ARM_SP_IMAGE_MMAP, ARM_SP_IMAGE_NS_BUF_MMAP, diff --git a/plat/brcm/board/common/cmn_plat_def.h b/plat/brcm/board/common/cmn_plat_def.h index 8aa7fd453..79d9a29d5 100644 --- a/plat/brcm/board/common/cmn_plat_def.h +++ b/plat/brcm/board/common/cmn_plat_def.h @@ -8,6 +8,7 @@ #define CMN_PLAT_DEF_H #include <bcm_elog.h> +#include <platform_def.h> #ifndef GET_LOG_LEVEL #define GET_LOG_LEVEL() LOG_LEVEL @@ -57,9 +58,6 @@ } \ } while (0) -/* Print file and line number on assert */ -#define PLAT_LOG_LEVEL_ASSERT LOG_LEVEL_INFO - /* * The number of regions like RO(code), coherent and data required by * different BL stages which need to be mapped in the MMU. diff --git a/plat/brcm/common/brcm_bl2_mem_params_desc.c b/plat/brcm/common/brcm_bl2_mem_params_desc.c index f711354bc..aed99d914 100644 --- a/plat/brcm/common/brcm_bl2_mem_params_desc.c +++ b/plat/brcm/common/brcm_bl2_mem_params_desc.c @@ -22,84 +22,84 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { #ifdef SCP_BL2_BASE /* Fill SCP_BL2 related information if it exists */ { - .image_id = SCP_BL2_IMAGE_ID, + .image_id = SCP_BL2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = PLAT_MAX_SCP_BL2_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = PLAT_MAX_SCP_BL2_SIZE, - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, }, #endif /* SCP_BL2_BASE */ /* Fill BL31 related information */ { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), #if DEBUG - .ep_info.args.arg3 = BRCM_BL31_PLAT_PARAM_VAL, + .ep_info.args.arg3 = BRCM_BL31_PLAT_PARAM_VAL, #endif - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, #ifdef BL32_BASE - .next_handoff_image_id = BL32_IMAGE_ID, + .next_handoff_image_id = BL32_IMAGE_ID, #else - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, #endif }, #ifdef BL32_BASE /* Fill BL32 related information */ { - .image_id = BL32_IMAGE_ID, + .image_id = BL32_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), - .ep_info.pc = BL32_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, }, #endif /* BL32_BASE */ /* Fill BL33 related information */ { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), #ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, + .ep_info.pc = PRELOADED_BL33_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), #else - .ep_info.pc = PLAT_BRCM_NS_IMAGE_OFFSET, + .ep_info.pc = PLAT_BRCM_NS_IMAGE_OFFSET, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_BRCM_NS_IMAGE_OFFSET, - .image_info.image_max_size = BRCM_DRAM1_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_BRCM_NS_IMAGE_OFFSET, + .image_info.image_max_size = BRCM_DRAM1_SIZE, #endif /* PRELOADED_BL33_BASE */ - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, } }; diff --git a/plat/common/aarch32/platform_helpers.S b/plat/common/aarch32/platform_helpers.S index 5b9cb5914..75cc456c4 100644 --- a/plat/common/aarch32/platform_helpers.S +++ b/plat/common/aarch32/platform_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,8 @@ #include <asm_macros.S> .weak plat_report_exception + .weak plat_report_prefetch_abort + .weak plat_report_data_abort .weak plat_reset_handler .weak plat_disable_acp .weak bl1_plat_prepare_exit @@ -28,6 +30,24 @@ endfunc plat_report_exception * each platform. * ----------------------------------------------------- */ +func plat_report_prefetch_abort + bx lr +endfunc plat_report_prefetch_abort + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_report_data_abort + bx lr +endfunc plat_report_data_abort + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ func plat_reset_handler bx lr endfunc plat_reset_handler diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c index e807660d8..8ce1d6c76 100644 --- a/plat/common/aarch64/plat_common.c +++ b/plat/common/aarch64/plat_common.c @@ -9,6 +9,7 @@ #include <stdint.h> #include <arch_helpers.h> +#include <common/debug.h> #include <drivers/console.h> #if RAS_EXTENSION #include <lib/extensions/ras.h> @@ -66,17 +67,15 @@ int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) } #endif -#if !ENABLE_BACKTRACE -static const char *get_el_str(unsigned int el) +const char *get_el_str(unsigned int el) { if (el == MODE_EL3) { return "EL3"; } else if (el == MODE_EL2) { return "EL2"; } - return "S-EL1"; + return "EL1"; } -#endif /* !ENABLE_BACKTRACE */ /* RAS functions common to AArch64 ARM platforms */ void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, @@ -94,7 +93,7 @@ void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *co ERROR("Unhandled External Abort received on 0x%lx from %s\n", read_mpidr_el1(), get_el_str(level)); ERROR("exception reason=%u syndrome=0x%" PRIx64 "\n", ea_reason, syndrome); -#if HANDLE_EA_EL3_FIRST +#if HANDLE_EA_EL3_FIRST_NS /* Skip backtrace for lower EL */ if (level != MODE_EL3) { console_flush(); diff --git a/plat/common/plat_gicv2.c b/plat/common/plat_gicv2.c index 4c76f1bd1..0f988dc74 100644 --- a/plat/common/plat_gicv2.c +++ b/plat/common/plat_gicv2.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -34,6 +35,8 @@ #pragma weak plat_ic_set_interrupt_priority #pragma weak plat_ic_set_interrupt_type #pragma weak plat_ic_raise_el3_sgi +#pragma weak plat_ic_raise_ns_sgi +#pragma weak plat_ic_raise_s_el1_sgi #pragma weak plat_ic_set_spi_routing /* @@ -247,12 +250,44 @@ void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) /* Verify that this is a secure SGI */ assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); - gicv2_raise_sgi(sgi_num, id); + gicv2_raise_sgi(sgi_num, false, id); #else assert(false); #endif } +void plat_ic_raise_ns_sgi(int sgi_num, u_register_t target) +{ + int id; + + /* Target must be a valid MPIDR in the system */ + id = plat_core_pos_by_mpidr(target); + assert(id >= 0); + + /* Verify that this is a non-secure SGI */ + assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_NS); + + gicv2_raise_sgi(sgi_num, true, id); +} + +void plat_ic_raise_s_el1_sgi(int sgi_num, u_register_t target) +{ +#if GICV2_G0_FOR_EL3 + assert(false); +#else + int id; + + /* Target must be a valid MPIDR in the system */ + id = plat_core_pos_by_mpidr(target); + assert(id >= 0); + + /* Verify that this is a secure EL1 SGI */ + assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_S_EL1); + + gicv2_raise_sgi(sgi_num, false, id); +#endif +} + void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, u_register_t mpidr) { diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c index 4a8a7eefe..e1420bb90 100644 --- a/plat/common/plat_gicv3.c +++ b/plat/common/plat_gicv3.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +10,7 @@ #include <arch_helpers.h> #include <common/bl_common.h> +#include <common/debug.h> #include <bl31/interrupt_mgmt.h> #include <drivers/arm/gic_common.h> #include <drivers/arm/gicv3.h> @@ -39,6 +41,8 @@ #pragma weak plat_ic_set_interrupt_priority #pragma weak plat_ic_set_interrupt_type #pragma weak plat_ic_raise_el3_sgi +#pragma weak plat_ic_raise_ns_sgi +#pragma weak plat_ic_raise_s_el1_sgi #pragma weak plat_ic_set_spi_routing #pragma weak plat_ic_set_interrupt_pending #pragma weak plat_ic_clear_interrupt_pending @@ -242,7 +246,31 @@ void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) == INTR_TYPE_EL3); - gicv3_raise_secure_g0_sgi((unsigned int)sgi_num, target); + gicv3_raise_sgi((unsigned int)sgi_num, GICV3_G0, target); +} + +void plat_ic_raise_ns_sgi(int sgi_num, u_register_t target) +{ + /* Target must be a valid MPIDR in the system */ + assert(plat_core_pos_by_mpidr(target) >= 0); + + /* Verify that this is a non-secure SGI */ + assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) == + INTR_TYPE_NS); + + gicv3_raise_sgi((unsigned int)sgi_num, GICV3_G1NS, target); +} + +void plat_ic_raise_s_el1_sgi(int sgi_num, u_register_t target) +{ + /* Target must be a valid MPIDR in the system */ + assert(plat_core_pos_by_mpidr(target) >= 0); + + /* Verify that this is a secure EL1 SGI */ + assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) == + INTR_TYPE_S_EL1); + + gicv3_raise_sgi((unsigned int)sgi_num, GICV3_G1S, target); } void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, diff --git a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c index 4e013a0f3..d0297035b 100644 --- a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c +++ b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c @@ -21,144 +21,146 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { #ifdef SCP_BL2_BASE /* Fill SCP_BL2 related information if it exists */ - { - .image_id = SCP_BL2_IMAGE_ID, + { + .image_id = SCP_BL2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = SCP_BL2_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = SCP_BL2_SIZE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #endif /* SCP_BL2_BASE */ #ifdef EL3_PAYLOAD_BASE /* Fill EL3 payload related information (BL31 is EL3 payload)*/ - { - .image_id = BL31_IMAGE_ID, + { + .image_id = BL31_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #else /* EL3_PAYLOAD_BASE */ /* Fill BL31 related information */ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), #if DEBUG - .ep_info.args.arg1 = HIKEY_BL31_PLAT_PARAM_VAL, + .ep_info.args.arg1 = HIKEY_BL31_PLAT_PARAM_VAL, #endif - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, # ifdef BL32_BASE - .next_handoff_image_id = BL32_IMAGE_ID, + .next_handoff_image_id = BL32_IMAGE_ID, # else - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, # endif - }, + }, # ifdef BL32_BASE /* Fill BL32 related information */ - { - .image_id = BL32_IMAGE_ID, + { + .image_id = BL32_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), - .ep_info.pc = BL32_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = BL33_IMAGE_ID, - }, + .next_handoff_image_id = BL33_IMAGE_ID, + }, /* * Fill BL32 external 1 related information. - * A typical use for extra1 image is with OP-TEE where it is the pager image. + * A typical use for extra1 image is with OP-TEE where it is the pager + * image. */ - { - .image_id = BL32_EXTRA1_IMAGE_ID, + { + .image_id = BL32_EXTRA1_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* * Fill BL32 external 2 related information. - * A typical use for extra2 image is with OP-TEE where it is the paged image. + * A typical use for extra2 image is with OP-TEE where it is the paged + * image. */ - { - .image_id = BL32_EXTRA2_IMAGE_ID, + { + .image_id = BL32_EXTRA2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), #ifdef SPD_opteed - .image_info.image_base = HIKEY_OPTEE_PAGEABLE_LOAD_BASE, - .image_info.image_max_size = HIKEY_OPTEE_PAGEABLE_LOAD_SIZE, + .image_info.image_base = HIKEY_OPTEE_PAGEABLE_LOAD_BASE, + .image_info.image_max_size = HIKEY_OPTEE_PAGEABLE_LOAD_SIZE, #endif - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, # endif /* BL32_BASE */ /* Fill BL33 related information */ - { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), # ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, + .ep_info.pc = PRELOADED_BL33_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), # else - .ep_info.pc = HIKEY_NS_IMAGE_OFFSET, + .ep_info.pc = HIKEY_NS_IMAGE_OFFSET, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = HIKEY_NS_IMAGE_OFFSET, - .image_info.image_max_size = 0x200000 /* 2MB */, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = HIKEY_NS_IMAGE_OFFSET, + .image_info.image_max_size = 0x200000 /* 2MB */, # endif /* PRELOADED_BL33_BASE */ - .next_handoff_image_id = INVALID_IMAGE_ID, - } + .next_handoff_image_id = INVALID_IMAGE_ID, + } #endif /* EL3_PAYLOAD_BASE */ }; diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk index 3e1771c66..2bfc58281 100644 --- a/plat/hisilicon/hikey/platform.mk +++ b/plat/hisilicon/hikey/platform.mk @@ -154,12 +154,12 @@ $(BUILD_PLAT)/bl2/hikey_rotpk.o: $(ROTPK_HASH) certificates: $(ROT_KEY) $(ROT_KEY): | $(BUILD_PLAT) @echo " OPENSSL $@" - $(Q)openssl genrsa 2048 > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null $(ROTPK_HASH): $(ROT_KEY) @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null endif # Enable workarounds for selected Cortex-A53 errata. diff --git a/plat/hisilicon/hikey960/aarch64/hikey960_common.c b/plat/hisilicon/hikey960/aarch64/hikey960_common.c index 612a7f21b..c70286fb2 100644 --- a/plat/hisilicon/hikey960/aarch64/hikey960_common.c +++ b/plat/hisilicon/hikey960/aarch64/hikey960_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ #include <common/bl_common.h> #include <common/debug.h> #include <lib/mmio.h> -#include <lib/xlat_tables/xlat_tables.h> +#include <lib/xlat_tables/xlat_tables_v2.h> #include <plat/common/platform.h> #include "../hikey960_def.h" @@ -69,7 +69,6 @@ static const mmap_region_t hikey960_mmap[] = { #ifdef IMAGE_BL31 static const mmap_region_t hikey960_mmap[] = { MAP_DEVICE, - MAP_TSP_MEM, {0} }; #endif diff --git a/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c b/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c index ba236d22f..e42785a97 100644 --- a/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c +++ b/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,144 +21,162 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { #ifdef SCP_BL2_BASE /* Fill SCP_BL2 related information if it exists */ - { - .image_id = SCP_BL2_IMAGE_ID, + { + .image_id = SCP_BL2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = SCP_BL2_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = SCP_BL2_SIZE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #endif /* SCP_BL2_BASE */ #ifdef EL3_PAYLOAD_BASE /* Fill EL3 payload related information (BL31 is EL3 payload)*/ - { - .image_id = BL31_IMAGE_ID, + { + .image_id = BL31_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #else /* EL3_PAYLOAD_BASE */ /* Fill BL31 related information */ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), #if DEBUG - .ep_info.args.arg1 = HIKEY960_BL31_PLAT_PARAM_VAL, + .ep_info.args.arg1 = HIKEY960_BL31_PLAT_PARAM_VAL, #endif - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, # ifdef BL32_BASE - .next_handoff_image_id = BL32_IMAGE_ID, + .next_handoff_image_id = BL32_IMAGE_ID, # else - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, # endif - }, + }, # ifdef BL32_BASE /* Fill BL32 related information */ - { - .image_id = BL32_IMAGE_ID, + { + .image_id = BL32_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), - .ep_info.pc = BL32_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = BL33_IMAGE_ID, - }, + .next_handoff_image_id = BL33_IMAGE_ID, + }, /* * Fill BL32 external 1 related information. - * A typical use for extra1 image is with OP-TEE where it is the pager image. + * A typical use for extra1 image is with OP-TEE where it is the pager + * image. */ - { - .image_id = BL32_EXTRA1_IMAGE_ID, + { + .image_id = BL32_EXTRA1_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* * Fill BL32 external 2 related information. - * A typical use for extra2 image is with OP-TEE where it is the paged image. + * A typical use for extra2 image is with OP-TEE where it is the paged + * image. */ - { - .image_id = BL32_EXTRA2_IMAGE_ID, + { + .image_id = BL32_EXTRA2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), #ifdef SPD_opteed - .image_info.image_base = HIKEY960_OPTEE_PAGEABLE_LOAD_BASE, - .image_info.image_max_size = HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE, + .image_info.image_base = HIKEY960_OPTEE_PAGEABLE_LOAD_BASE, + .image_info.image_max_size = HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE, #endif - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + +#ifdef SPD_spmd + /* Fill TOS_FW_CONFIG related information */ + { + .image_id = TOS_FW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = DDR_SEC_CONFIG_BASE, + .image_info.image_max_size = DDR_SEC_CONFIG_SIZE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +#endif + # endif /* BL32_BASE */ /* Fill BL33 related information */ - { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), # ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, + .ep_info.pc = PRELOADED_BL33_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), # else - .ep_info.pc = NS_BL1U_BASE, + .ep_info.pc = NS_BL1U_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = NS_BL1U_BASE, - .image_info.image_max_size = 0x200000 /* 2MB */, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = NS_BL1U_BASE, + .image_info.image_max_size = 0x200000 /* 2MB */, # endif /* PRELOADED_BL33_BASE */ - .next_handoff_image_id = INVALID_IMAGE_ID, - } + .next_handoff_image_id = INVALID_IMAGE_ID, + } #endif /* EL3_PAYLOAD_BASE */ }; diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c index c1c2a8c59..733485385 100644 --- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -31,6 +31,9 @@ #define BL2_RW_BASE (BL_CODE_END) +/* BL2 platform parameters passed to BL31 */ +static plat_params_from_bl2_t plat_params_from_bl2; + static meminfo_t bl2_el3_tzram_layout; static console_t console; extern int load_lpm3(void); @@ -217,6 +220,11 @@ int hikey960_bl2_handle_post_image_load(unsigned int image_id) assert(bl_mem_params); switch (image_id) { + case BL31_IMAGE_ID: + /* Pass BL2 platform parameter to BL31 */ + bl_mem_params->ep_info.args.arg1 = (uint64_t) &plat_params_from_bl2; + break; + #ifdef __aarch64__ case BL32_IMAGE_ID: #ifdef SPD_opteed @@ -307,6 +315,8 @@ void bl2_el3_plat_arch_setup(void) void bl2_platform_setup(void) { + int ret; + /* disable WDT0 */ if (mmio_read_32(WDT0_REG_BASE + WDT_LOCK_OFFSET) == WDT_LOCKED) { mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, WDT_UNLOCK); @@ -322,4 +332,13 @@ void bl2_platform_setup(void) hikey960_gpio_init(); hikey960_init_ufs(); hikey960_io_setup(); + + /* Read serial number from storage */ + plat_params_from_bl2.fastboot_serno = 0; + ret = hikey960_load_serialno(&plat_params_from_bl2.fastboot_serno); + if (ret != 0) { + ERROR("BL2: could not read serial number\n"); + } + INFO("BL2: fastboot_serno %lx\n", plat_params_from_bl2.fastboot_serno); + flush_dcache_range((uintptr_t)&plat_params_from_bl2, sizeof(plat_params_from_bl2_t)); } diff --git a/plat/hisilicon/hikey960/hikey960_bl31_setup.c b/plat/hisilicon/hikey960/hikey960_bl31_setup.c index f5f8ffed0..0debe1ee6 100644 --- a/plat/hisilicon/hikey960/hikey960_bl31_setup.c +++ b/plat/hisilicon/hikey960/hikey960_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,9 @@ #include <drivers/console.h> #include <drivers/generic_delay_timer.h> #include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> #include <plat/common/platform.h> +#include <services/el3_spmc_ffa_memory.h> #include <hi3660.h> #include <hisi_ipc.h> @@ -31,6 +33,9 @@ static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; static console_t console; +/* fastboot serial number consumed by Kinibi SPD/LP for gpd.tee.deviceID. */ +uint64_t fastboot_serno; + /****************************************************************************** * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 * interrupts. @@ -71,6 +76,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, { unsigned int id, uart_base; void *from_bl2; + plat_params_from_bl2_t *plat_params_from_bl2 = (plat_params_from_bl2_t *) arg1; from_bl2 = (void *) arg0; @@ -89,6 +95,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map)); cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); + /* Fastboot serial number passed from BL2 as a platform parameter */ + fastboot_serno = plat_params_from_bl2->fastboot_serno; + INFO("BL31: fastboot_serno %lx\n", fastboot_serno); + /* * Check params passed from BL2 should not be NULL, */ @@ -119,6 +129,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { +#if SPMC_AT_EL3 + mmap_add_region(DDR2_SEC_BASE, DDR2_SEC_BASE, DDR2_SEC_SIZE, + MT_MEMORY | MT_RW | MT_SECURE); +#endif + hikey960_init_mmu_el3(BL31_BASE, BL31_LIMIT - BL31_BASE, BL_CODE_BASE, @@ -156,6 +171,48 @@ static void hikey960_iomcu_dma_init(void) } } +#if SPMC_AT_EL3 +/* + * On the hikey960 platform when using the EL3 SPMC implementation allocate the + * datastore for tracking shared memory descriptors in the RAM2 DRAM section + * to ensure sufficient storage can be allocated. + * Provide an implementation of the accessor method to allow the datastore + * details to be retrieved by the SPMC. + * The SPMC will take care of initializing the memory region. + */ + +#define SPMC_SHARED_MEMORY_OBJ_SIZE (512 * 1024) + +__section("ram2_region") uint8_t plat_spmc_shmem_datastore[SPMC_SHARED_MEMORY_OBJ_SIZE]; + +int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) +{ + *datastore = plat_spmc_shmem_datastore; + *size = SPMC_SHARED_MEMORY_OBJ_SIZE; + return 0; +} + +/* + * Add dummy implementations of memory management related platform hooks. + * These can be used to implement platform specific functionality to support + * a memory sharing/lending operation. + * + * Note: The hooks must be located as part of the initial share request and + * final reclaim to prevent order dependencies with operations that may take + * place in the normal world without visibility of the SPMC. + */ +int plat_spmc_shmem_begin(struct ffa_mtd *desc) +{ + return 0; +} + +int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) +{ + return 0; +} + +#endif + void bl31_platform_setup(void) { /* Initialize the GIC driver, cpu and distributor interfaces */ diff --git a/plat/hisilicon/hikey960/hikey960_def.h b/plat/hisilicon/hikey960/hikey960_def.h index 9651d7891..e103cf465 100644 --- a/plat/hisilicon/hikey960/hikey960_def.h +++ b/plat/hisilicon/hikey960/hikey960_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,15 +21,21 @@ #define HIKEY960_DRAM_ID 1 /* - * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several + * DDR for TEE (80MB from 0x3E00000-0x43000FFF) is divided into several * regions: - * - Secure DDR (default is the top 16MB) used by OP-TEE + * - SPMC manifest (4KB at the top) used by SPMC_AT_EL3 and the TEE + * - Datastore for SPMC_AT_EL3 (4MB at the top) used by BL31 + * - Secure DDR (default is the top 60MB) used by OP-TEE * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature * - Non-secure DDR (8MB) reserved for OP-TEE's future use */ -#define DDR_SEC_SIZE 0x01000000 +#define DDR_SEC_SIZE 0x03C00000 /* reserve 60MB secure memory */ #define DDR_SEC_BASE 0x3F000000 +#define DDR2_SEC_SIZE 0x00400000 /* SPMC_AT_EL3: 4MB for BL31 RAM2 */ +#define DDR2_SEC_BASE 0x42C00000 +#define DDR_SEC_CONFIG_SIZE 0x00001000 /* SPMC_AT_EL3: SPMC manifest */ +#define DDR_SEC_CONFIG_BASE 0x43000000 #define DDR_SDP_SIZE 0x00400000 #define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \ @@ -50,4 +56,27 @@ #define HIKEY960_UFS_DATA_BASE 0x10000000 #define HIKEY960_UFS_DATA_SIZE 0x0A000000 /* 160MB */ +#if defined(SPMC_AT_EL3) +/* + * Number of Secure Partitions supported. + * SPMC at EL3, uses this count to configure the maximum number of supported + * secure partitions. + */ +#define SECURE_PARTITION_COUNT 1 + +/* + * Number of Nwld Partitions supported. + * SPMC at EL3, uses this count to configure the maximum number of supported + * nwld partitions. + */ +#define NS_PARTITION_COUNT 1 +/* + * Number of Logical Partitions supported. + * SPMC at EL3, uses this count to configure the maximum number of supported + * logical partitions. + */ +#define MAX_EL3_LP_DESCS_COUNT 1 + +#endif /* SPMC_AT_EL3 */ + #endif /* HIKEY960_DEF_H */ diff --git a/plat/hisilicon/hikey960/hikey960_el3_spmc_logical_sp.c b/plat/hisilicon/hikey960/hikey960_el3_spmc_logical_sp.c new file mode 100644 index 000000000..b9e4f864c --- /dev/null +++ b/plat/hisilicon/hikey960/hikey960_el3_spmc_logical_sp.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <services/el3_spmc_logical_sp.h> +#include <services/ffa_svc.h> +#include <smccc_helpers.h> + +#define LP_PARTITION_ID 0xC001 +#define LP_UUID {0x47a3bf57, 0xe98e43ad, 0xb7db524f, 0x1588f4e3} + +/* Our Logical SP currently only supports receipt of direct messaging. */ +#define PARTITION_PROPERTIES FFA_PARTITION_DIRECT_REQ_RECV + +static int32_t sp_init(void) +{ + INFO("LSP: Init function called.\n"); + return 0; +} + +static uint64_t handle_ffa_direct_request(uint32_t smc_fid, bool secure_origin, + uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, + void *handle, uint64_t flags) +{ + uint64_t ret; + + /* Determine if we have a 64 or 32 direct request. */ + if (smc_fid == FFA_MSG_SEND_DIRECT_REQ_SMC32) { + ret = FFA_MSG_SEND_DIRECT_RESP_SMC32; + } else if (smc_fid == FFA_MSG_SEND_DIRECT_REQ_SMC64) { + ret = FFA_MSG_SEND_DIRECT_RESP_SMC64; + } else { + panic(); /* Unknown SMC. */ + } + /* + * Handle the incoming request. For testing purposes we echo the + * incoming message. + */ + INFO("Logical Partition: Received Direct Request from %s world!\n", + secure_origin ? "Secure" : "Normal"); + + /* + * Logical SP's must always send a direct response so we can populate + * our response directly. + */ + SMC_RET8(handle, ret, 0, 0, x4, 0, 0, 0, 0); +} + +/* Register logical partition */ +DECLARE_LOGICAL_PARTITION( + my_logical_partition, + sp_init, /* Init Function */ + LP_PARTITION_ID, /* FF-A Partition ID */ + LP_UUID, /* UUID */ + PARTITION_PROPERTIES, /* Partition Properties. */ + handle_ffa_direct_request /* Callback for direct requests. */ +); diff --git a/plat/hisilicon/hikey960/hikey960_image_load.c b/plat/hisilicon/hikey960/hikey960_image_load.c index 57cb1b228..9a5b74ee1 100644 --- a/plat/hisilicon/hikey960/hikey960_image_load.c +++ b/plat/hisilicon/hikey960/hikey960_image_load.c @@ -1,9 +1,10 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <assert.h> #include <common/bl_common.h> #include <common/desc_image_load.h> #include <plat/common/platform.h> @@ -25,10 +26,30 @@ bl_load_info_t *plat_get_bl_image_load_info(void) return get_bl_load_info_from_mem_params_desc(); } + +/******************************************************************************* + * ARM helper function to return the list of executable images. Since the default + * descriptors are allocated within BL2 RW memory, this prevents BL31/BL32 + * overlay of BL2 memory. Hence this function also copies the descriptors to a + * pre-allocated memory indicated by ARM_BL2_MEM_DESC_BASE. + ******************************************************************************/ +struct bl_params *hikey960_get_next_bl_params(void) +{ + bl_params_t *next_bl_params; + + next_bl_params = get_next_bl_params_from_mem_params_desc(); + assert(next_bl_params != NULL); + + populate_next_bl_params_config(next_bl_params); + + return next_bl_params; +} + + /******************************************************************************* * This function returns the list of executable images. ******************************************************************************/ bl_params_t *plat_get_next_bl_params(void) { - return get_next_bl_params_from_mem_params_desc(); + return hikey960_get_next_bl_params(); } diff --git a/plat/hisilicon/hikey960/hikey960_io_storage.c b/plat/hisilicon/hikey960/hikey960_io_storage.c index e1c5845fb..475e41676 100644 --- a/plat/hisilicon/hikey960/hikey960_io_storage.c +++ b/plat/hisilicon/hikey960/hikey960_io_storage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,6 +23,9 @@ #include <lib/semihosting.h> #include <tools_share/firmware_image_package.h> +#include "hikey960_def.h" +#include "hikey960_private.h" + struct plat_io_policy { uintptr_t *dev_handle; uintptr_t image_spec; @@ -45,6 +48,12 @@ static const io_block_spec_t ufs_gpt_spec = { (PLAT_PARTITION_MAX_ENTRIES / 4 + 2), }; +/* Fastboot serial number stored within first UFS device blocks */ +static const io_block_spec_t ufs_fastboot_spec = { + .offset = UFS_BASE, + .length = 1 << 20, +}; + static const io_block_dev_spec_t ufs_dev_spec = { /* It's used as temp buffer in block driver. */ .buffer = { @@ -78,6 +87,12 @@ static const io_uuid_spec_t bl32_extra2_uuid_spec = { .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, }; +#ifdef SPD_spmd +static const io_uuid_spec_t bl32_tos_fw_spec = { + .uuid = UUID_TOS_FW_CONFIG, +}; +#endif + static const io_uuid_spec_t bl33_uuid_spec = { .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, }; @@ -151,6 +166,15 @@ static const struct plat_io_policy policies[] = { (uintptr_t)&bl32_extra2_uuid_spec, check_fip }, + +#ifdef SPD_spmd + [TOS_FW_CONFIG_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_tos_fw_spec, + check_fip + }, +#endif + [BL33_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl33_uuid_spec, @@ -241,6 +265,54 @@ static int check_fip(const uintptr_t spec) return result; } +int hikey960_load_serialno(uint64_t *serno) +{ + int result; + size_t len = 0; + uintptr_t local_handle; + uint64_t buf[HIKEY960_SERIAL_NUMBER_SIZE / sizeof(uint64_t)]; + + if (serno == NULL) { + return -1; + } + + result = io_dev_init(ufs_dev_handle, (uintptr_t)NULL); + if (result != 0) { + return result; + } + + result = io_open(ufs_dev_handle, + (uintptr_t)&ufs_fastboot_spec, &local_handle); + if (result != 0) { + return result; + } + + result = io_seek(local_handle, IO_SEEK_SET, + HIKEY960_SERIAL_NUMBER_LBA * UFS_BLOCK_SIZE); + if (result != 0) { + goto closing; + } + + result = io_read(local_handle, (uintptr_t)buf, + HIKEY960_SERIAL_NUMBER_SIZE, &len); + if (result != 0) { + goto closing; + } + + if (len != HIKEY960_SERIAL_NUMBER_SIZE) { + result = -1; + goto closing; + } + + /* UEFI fastboot app stores a 16 bytes blob */ + /* We extract only relevant 8 bytes serial number */ + *serno = buf[1]; + +closing: + io_close(local_handle); + return result; +} + void hikey960_io_setup(void) { int result; diff --git a/plat/hisilicon/hikey960/hikey960_private.h b/plat/hisilicon/hikey960/hikey960_private.h index 54bf50134..742725c69 100644 --- a/plat/hisilicon/hikey960/hikey960_private.h +++ b/plat/hisilicon/hikey960/hikey960_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,10 @@ #include <common/bl_common.h> +/* Fastboot serial number */ +#define HIKEY960_SERIAL_NUMBER_LBA (UFS_BASE + 20) +#define HIKEY960_SERIAL_NUMBER_SIZE 16 + /* * Function and variable prototypes */ @@ -27,6 +31,7 @@ void hikey960_init_mmu_el3(unsigned long total_base, void hikey960_io_setup(void); int hikey960_read_boardid(unsigned int *id); int hikey960_set_fip_addr(unsigned int image_id, const char *name); +int hikey960_load_serialno(uint64_t *serno); void hikey960_clk_init(void); void hikey960_pmu_init(void); void hikey960_regulator_enable(void); @@ -39,4 +44,12 @@ void clr_retention_ticks(unsigned int val); void clr_ex(void); void nop(void); +/******************************************************************************* + * Struct for parameters received from BL2 + ******************************************************************************/ +typedef struct plat_params_from_bl2 { + /* Fastboot serial number gathered from UFS */ + uint64_t fastboot_serno; +} plat_params_from_bl2_t; + #endif /* HIKEY960_PRIVATE_H */ diff --git a/plat/hisilicon/hikey960/include/plat.ld.S b/plat/hisilicon/hikey960/include/plat.ld.S new file mode 100644 index 000000000..0cc25cdac --- /dev/null +++ b/plat/hisilicon/hikey960/include/plat.ld.S @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLAT_LD_S +#define PLAT_LD_S + +#include <lib/xlat_tables/xlat_tables_defs.h> + +MEMORY { + RAM2 (rw): ORIGIN = DDR2_SEC_BASE, LENGTH = DDR2_SEC_SIZE +} + +SECTIONS +{ + ram2_region (NOLOAD) : { + *(ram2_region) + }>RAM2 +} + +#endif /* PLAT_LD_S */ diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h index 215eebe1b..10eff011b 100644 --- a/plat/hisilicon/hikey960/include/platform_def.h +++ b/plat/hisilicon/hikey960/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -114,15 +114,23 @@ /* * Platform specific page table and MMU setup constants */ -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) -#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || defined(IMAGE_BL32) +#if defined(IMAGE_BL1) || defined(IMAGE_BL32) #define MAX_XLAT_TABLES 3 #endif -#ifdef IMAGE_BL2 -#define MAX_XLAT_TABLES 4 +#if defined(IMAGE_BL2) +#define MAX_XLAT_TABLES 5 +#endif + +#if defined(IMAGE_BL31) +#if defined(SPMC_AT_EL3) +#define MAX_XLAT_TABLES 17 +#else +#define MAX_XLAT_TABLES 5 +#endif #endif #define MAX_MMAP_REGIONS 16 diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk index 608fe0937..4c3c8178b 100644 --- a/plat/hisilicon/hikey960/platform.mk +++ b/plat/hisilicon/hikey960/platform.mk @@ -46,11 +46,12 @@ PLAT_INCLUDES := -Iplat/hisilicon/hikey960/include PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ - lib/xlat_tables/aarch64/xlat_tables.c \ - lib/xlat_tables/xlat_tables_common.c \ plat/hisilicon/hikey960/aarch64/hikey960_common.c \ plat/hisilicon/hikey960/hikey960_boardid.c +include lib/xlat_tables_v2/xlat_tables.mk +PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} + HIKEY960_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/v2/gicv2_helpers.c \ @@ -146,12 +147,12 @@ $(BUILD_PLAT)/bl2/hikey960_rotpk.o: $(ROTPK_HASH) certificates: $(ROT_KEY) $(ROT_KEY): | $(BUILD_PLAT) @echo " OPENSSL $@" - $(Q)openssl genrsa 2048 > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null $(ROTPK_HASH): $(ROT_KEY) @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null endif # Enable workarounds for selected Cortex-A53 errata. @@ -160,3 +161,22 @@ ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 FIP_ALIGN := 512 + +# SPM dispatcher +ifeq (${SPD},spmd) +ifeq (${SPMC_AT_EL3},1) +# include device tree helper library +include lib/libfdt/libfdt.mk +BL31_SOURCES += common/fdt_wrappers.c \ + ${LIBFDT_SRCS} \ + common/uuid.c + +# Add support for platform supplied linker script for BL31 build +$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) +endif + +ifeq ($(PLAT_SP_MANIFEST_DTS),) + $(error "Error: A SP manifest is required for the SPMC.") +endif +FDT_SOURCES += ${PLAT_SP_MANIFEST_DTS} +endif diff --git a/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c b/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c index f683d750d..9bda02e4b 100644 --- a/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c +++ b/plat/hisilicon/poplar/bl2_plat_mem_params_desc.c @@ -22,143 +22,145 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { #ifdef SCP_BL2_BASE /* Fill SCP_BL2 related information if it exists */ { - .image_id = SCP_BL2_IMAGE_ID, + .image_id = SCP_BL2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = SCP_BL2_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = SCP_BL2_SIZE, - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, }, #endif /* SCP_BL2_BASE */ #ifdef EL3_PAYLOAD_BASE /* Fill EL3 payload related information (BL31 is EL3 payload)*/ { - .image_id = BL31_IMAGE_ID, + .image_id = BL31_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, }, #else /* EL3_PAYLOAD_BASE */ /* Fill BL31 related information */ { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), #if DEBUG - .ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL, + .ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL, #endif - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, # ifdef BL32_BASE - .next_handoff_image_id = BL32_IMAGE_ID, + .next_handoff_image_id = BL32_IMAGE_ID, # else - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, # endif }, # ifdef BL32_BASE /* Fill BL32 related information */ { - .image_id = BL32_IMAGE_ID, + .image_id = BL32_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), - .ep_info.pc = BL32_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, }, /* * Fill BL32 external 1 related information. - * A typical use for extra1 image is with OP-TEE where it is the pager image. + * A typical use for extra1 image is with OP-TEE where it is the pager + * image. */ { - .image_id = BL32_EXTRA1_IMAGE_ID, + .image_id = BL32_EXTRA1_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, }, /* * Fill BL32 external 2 related information. - * A typical use for extra2 image is with OP-TEE where it is the paged image. + * A typical use for extra2 image is with OP-TEE where it is the paged + * image. */ { - .image_id = BL32_EXTRA2_IMAGE_ID, + .image_id = BL32_EXTRA2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), #ifdef SPD_opteed - .image_info.image_base = POPLAR_OPTEE_PAGEABLE_LOAD_BASE, - .image_info.image_max_size = POPLAR_OPTEE_PAGEABLE_LOAD_SIZE, + .image_info.image_base = POPLAR_OPTEE_PAGEABLE_LOAD_BASE, + .image_info.image_max_size = POPLAR_OPTEE_PAGEABLE_LOAD_SIZE, #endif - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, }, # endif /* BL32_BASE */ /* Fill BL33 related information */ { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), # ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, + .ep_info.pc = PRELOADED_BL33_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), # else - .ep_info.pc = PLAT_POPLAR_NS_IMAGE_OFFSET, + .ep_info.pc = PLAT_POPLAR_NS_IMAGE_OFFSET, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = PLAT_POPLAR_NS_IMAGE_OFFSET, - .image_info.image_max_size = DDR_BASE + DDR_SIZE - + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_POPLAR_NS_IMAGE_OFFSET, + .image_info.image_max_size = DDR_BASE + DDR_SIZE - PLAT_POPLAR_NS_IMAGE_OFFSET, # endif /* PRELOADED_BL33_BASE */ - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, } #endif /* EL3_PAYLOAD_BASE */ }; diff --git a/plat/imx/common/imx_sip_svc.c b/plat/imx/common/imx_sip_svc.c index fd54820cf..11d02f3f5 100644 --- a/plat/imx/common/imx_sip_svc.c +++ b/plat/imx/common/imx_sip_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -34,6 +34,13 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid, SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); break; #endif +#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) + case IMX_SIP_DDR_DVFS: + return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); + case IMX_SIP_GPC: + SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); + break; +#endif #if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx)) case IMX_SIP_SRTC: return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); @@ -53,6 +60,11 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid, SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle)); break; #endif +#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) + case IMX_SIP_HAB: + SMC_RET1(handle, imx_hab_handler(smc_fid, x1, x2, x3, x4)); + break; +#endif case IMX_SIP_BUILDINFO: SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4)); default: diff --git a/plat/imx/common/include/imx_sip_svc.h b/plat/imx/common/include/imx_sip_svc.h index 6c7a760c6..1f459858b 100644 --- a/plat/imx/common/include/imx_sip_svc.h +++ b/plat/imx/common/include/imx_sip_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,8 @@ #define __IMX_SIP_SVC_H__ /* SMC function IDs for SiP Service queries */ +#define IMX_SIP_GPC 0xC2000000 + #define IMX_SIP_CPUFREQ 0xC2000001 #define IMX_SIP_SET_CPUFREQ 0x00 @@ -17,12 +19,25 @@ #define IMX_SIP_BUILDINFO 0xC2000003 #define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00 +#define IMX_SIP_DDR_DVFS 0xc2000004 + #define IMX_SIP_SRC 0xC2000005 #define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10 #define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11 #define IMX_SIP_GET_SOC_INFO 0xC2000006 +#define IMX_SIP_HAB 0xC2000007 +#define IMX_SIP_HAB_AUTH_IMG 0x00 +#define IMX_SIP_HAB_ENTRY 0x01 +#define IMX_SIP_HAB_EXIT 0x02 +#define IMX_SIP_HAB_REPORT_EVENT 0x03 +#define IMX_SIP_HAB_REPORT_STATUS 0x04 +#define IMX_SIP_HAB_FAILSAFE 0x05 +#define IMX_SIP_HAB_CHECK_TARGET 0x06 +#define IMX_SIP_HAB_GET_VERSION 0x07 +#define IMX_SIP_HAB_AUTH_IMG_NO_DCD 0x08 + #define IMX_SIP_WAKEUP_SRC 0xC2000009 #define IMX_SIP_WAKEUP_SRC_SCU 0x1 #define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2 @@ -41,12 +56,24 @@ int imx_kernel_entry_handler(uint32_t smc_fid, u_register_t x1, int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3); #endif +#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) +int dram_dvfs_handler(uint32_t smc_fid, void *handle, + u_register_t x1, u_register_t x2, u_register_t x3); + +int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3); +#endif #if defined(PLAT_imx8mm) || defined(PLAT_imx8mq) int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3, void *handle); #endif +#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) +int imx_hab_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3, u_register_t x4); +#endif + #if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx)) int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3); diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk index fdde9a9da..f4f5bfc0c 100644 --- a/plat/imx/imx7/common/imx7.mk +++ b/plat/imx/imx7/common/imx7.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -80,13 +80,13 @@ certificates: $(ROT_KEY) $(ROT_KEY): | $(BUILD_PLAT) @echo " OPENSSL $@" @if [ ! -f $(ROT_KEY) ]; then \ - openssl genrsa 2048 > $@ 2>/dev/null; \ + ${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \ fi $(ROTPK_HASH): $(ROT_KEY) @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null endif # Add the build options to pack BLx images and kernel device tree diff --git a/plat/imx/imx8m/ddr/clock.c b/plat/imx/imx8m/ddr/clock.c new file mode 100644 index 000000000..7fb5730dc --- /dev/null +++ b/plat/imx/imx8m/ddr/clock.c @@ -0,0 +1,136 @@ +/* + * Copyright 2018-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> + +#include <lib/mmio.h> +#include <platform_def.h> + +#define IMX_CCM_IP_BASE (IMX_CCM_BASE + 0xa000) +#define DRAM_SEL_CFG (IMX_CCM_BASE + 0x9800) +#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x00) +#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x04) +#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x08) +#define PLL_FREQ_800M U(0x00ece580) +#define PLL_FREQ_400M U(0x00ec6984) +#define PLL_FREQ_167M U(0x00f5a406) + +void ddr_pll_bypass_100mts(void) +{ + /* change the clock source of dram_alt_clk_root to source 2 --100MHz */ + mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0), (0x7 << 24) | (0x7 << 16)); + mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0), (0x2 << 24)); + + /* change the clock source of dram_apb_clk_root to source 2 --40MHz/2 */ + mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16)); + mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x2 << 24) | (0x1 << 16)); + + /* configure pll bypass mode */ + mmio_write_32(DRAM_SEL_CFG + 0x4, BIT(24)); +} + +void ddr_pll_bypass_400mts(void) +{ + /* change the clock source of dram_alt_clk_root to source 1 --400MHz */ + mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0), (0x7 << 24) | (0x7 << 16)); + mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0), (0x1 << 24) | (0x1 << 16)); + + /* change the clock source of dram_apb_clk_root to source 3 --160MHz/2 */ + mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16)); + mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x3 << 24) | (0x1 << 16)); + + /* configure pll bypass mode */ + mmio_write_32(DRAM_SEL_CFG + 0x4, BIT(24)); +} + +void ddr_pll_unbypass(void) +{ + mmio_write_32(DRAM_SEL_CFG + 0x8, BIT(24)); + mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16)); + /* to source 4 --800MHz/5 */ + mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4 << 24) | (0x4 << 16)); +} + +#if defined(PLAT_imx8mq) +void dram_pll_init(unsigned int drate) +{ + /* bypass the PLL */ + mmio_setbits_32(HW_DRAM_PLL_CFG0, 0x30); + + switch (drate) { + case 3200: + mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_800M); + break; + case 1600: + mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_400M); + break; + case 667: + mmio_write_32(HW_DRAM_PLL_CFG2, PLL_FREQ_167M); + break; + default: + break; + } + + /* unbypass the PLL */ + mmio_clrbits_32(HW_DRAM_PLL_CFG0, 0x30); + while (!(mmio_read_32(HW_DRAM_PLL_CFG0) & (1 << 31))) { + ; + } +} +#else +void dram_pll_init(unsigned int drate) +{ + /* bypass the PLL */ + mmio_setbits_32(DRAM_PLL_CTRL, (1 << 16)); + mmio_clrbits_32(DRAM_PLL_CTRL, (1 << 9)); + + switch (drate) { + case 2400: + mmio_write_32(DRAM_PLL_CTRL + 0x4, (300 << 12) | (3 << 4) | 2); + break; + case 1600: + mmio_write_32(DRAM_PLL_CTRL + 0x4, (400 << 12) | (3 << 4) | 3); + break; + case 1066: + mmio_write_32(DRAM_PLL_CTRL + 0x4, (266 << 12) | (3 << 4) | 3); + break; + case 667: + mmio_write_32(DRAM_PLL_CTRL + 0x4, (334 << 12) | (3 << 4) | 4); + break; + default: + break; + } + + mmio_setbits_32(DRAM_PLL_CTRL, BIT(9)); + /* wait for PLL locked */ + while (!(mmio_read_32(DRAM_PLL_CTRL) & BIT(31))) { + ; + } + + /* unbypass the PLL */ + mmio_clrbits_32(DRAM_PLL_CTRL, BIT(16)); +} +#endif + +/* change the dram clock frequency */ +void dram_clock_switch(unsigned int target_drate, bool bypass_mode) +{ + if (bypass_mode) { + switch (target_drate) { + case 400: + ddr_pll_bypass_400mts(); + break; + case 100: + ddr_pll_bypass_100mts(); + break; + default: + ddr_pll_unbypass(); + break; + } + } else { + dram_pll_init(target_drate); + } +} diff --git a/plat/imx/imx8m/ddr/ddr4_dvfs.c b/plat/imx/imx8m/ddr/ddr4_dvfs.c new file mode 100644 index 000000000..cdc7dc2dd --- /dev/null +++ b/plat/imx/imx8m/ddr/ddr4_dvfs.c @@ -0,0 +1,241 @@ +/* + * Copyright 2018-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <drivers/delay_timer.h> +#include <lib/mmio.h> + +#include <dram.h> + +void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, uint32_t rank) +{ + uint32_t val, mr_mirror, data_mirror; + + /* + * 1. Poll MRSTAT.mr_wr_busy until it is 0 to make sure + * that there is no outstanding MR transAction. + */ + while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) { + ; + } + + /* + * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank + * and (for MRWs) MRCTRL1.mr_data to define the MR transaction. + */ + val = mmio_read_32(DDRC_DIMMCTL(0)); + if ((val & 0x2) && (rank == 0x2)) { + mr_mirror = (mr & 0x4) | ((mr & 0x1) << 1) | ((mr & 0x2) >> 1); /* BA0, BA1 swap */ + data_mirror = (data & 0x1607) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | + ((data & 0x20) << 1) | ((data & 0x40) >> 1) | ((data & 0x80) << 1) | + ((data & 0x100) >> 1) | ((data & 0x800) << 2) | ((data & 0x2000) >> 2) ; + } else { + mr_mirror = mr; + data_mirror = data; + } + + mmio_write_32(DDRC_MRCTRL0(0), mr_type | (mr_mirror << 12) | (rank << 4)); + mmio_write_32(DDRC_MRCTRL1(0), data_mirror); + + /* + * 3. In a separate APB transaction, write the MRCTRL0.mr_wr to 1. + * This bit is self-clearing, and triggers the MR transaction. + * The uMCTL2 then asserts the MRSTAT.mr_wr_busy while it performs + * the MR transaction to SDRAM, and no further accesses can be + * initiated until it is deasserted. + */ + mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); + + while (mmio_read_32(DDRC_MRSTAT(0))) { + ; + } +} + +void dram_cfg_all_mr(struct dram_info *info, uint32_t pstate) +{ + uint32_t num_rank = info->num_rank; + /* + * 15. Perform MRS commands as required to re-program + * timing registers in the SDRAM for the new frequency + * (in particular, CL, CWL and WR may need to be changed). + */ + + for (int i = 1; i <= num_rank; i++) { + for (int j = 0; j < 6; j++) { + ddr4_mr_write(j, info->mr_table[pstate][j], 0, i); + } + ddr4_mr_write(6, info->mr_table[pstate][7], 0, i); + } +} + +void sw_pstate(uint32_t pstate, uint32_t drate) +{ + uint32_t val; + + mmio_write_32(DDRC_SWCTL(0), 0x0); + + /* + * Update any registers which may be required to + * change for the new frequency. + */ + mmio_write_32(DDRC_MSTR2(0), pstate); + mmio_setbits_32(DDRC_MSTR(0), (0x1 << 29)); + + /* + * Toggle RFSHCTL3.refresh_update_level to allow the + * new refresh-related register values to propagate + * to the refresh logic. + */ + val = mmio_read_32(DDRC_RFSHCTL3(0)); + if (val & 0x2) { + mmio_write_32(DDRC_RFSHCTL3(0), val & 0xFFFFFFFD); + } else { + mmio_write_32(DDRC_RFSHCTL3(0), val | 0x2); + } + + /* + * 19. If required, trigger the initialization in the PHY. + * If using the gen2 multiPHY, PLL initialization should + * be triggered at this point. See the PHY databook for + * details about the frequency change procedure. + */ + mmio_write_32(DDRC_DFIMISC(0), 0x00000000 | (pstate << 8)); + mmio_write_32(DDRC_DFIMISC(0), 0x00000020 | (pstate << 8)); + + /* wait DFISTAT.dfi_init_complete to 0 */ + while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) { + ; + } + + /* change the clock to the target frequency */ + dram_clock_switch(drate, false); + + mmio_write_32(DDRC_DFIMISC(0), 0x00000000 | (pstate << 8)); + + /* wait DFISTAT.dfi_init_complete to 1 */ + while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { + ; + } + + /* + * When changing frequencies the controller may violate the JEDEC + * requirement that no more than 16 refreshes should be issued within + * 2*tREFI. These extra refreshes are not expected to cause a problem + * in the SDRAM. This issue can be avoided by waiting for at least 2*tREFI + * before exiting self-refresh in step 19. + */ + udelay(14); + + /* 14. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */ + mmio_clrbits_32(DDRC_PWRCTL(0), (1 << 5)); + + while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) == 0x23) { + ; + } +} + +void ddr4_swffc(struct dram_info *info, unsigned int pstate) +{ + uint32_t drate = info->timing_info->fsp_table[pstate]; + + /* + * 1. set SWCTL.sw_done to disable quasi-dynamic register + * programming outside reset. + */ + mmio_write_32(DDRC_SWCTL(0), 0x0); + + /* + * 2. Write 0 to PCTRL_n.port_en. This blocks AXI port(s) + * from taking any transaction (blocks traffic on AXI ports). + */ + mmio_write_32(DDRC_PCTRL_0(0), 0x0); + + /* + * 3. Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. + * Wait until all AXI ports are idle (the uMCTL2 core has to + * be idle). + */ + while (mmio_read_32(DDRC_PSTAT(0)) & 0x10001) { + ; + } + + /* + * 4. Write 0 to SBRCTL.scrub_en. Disable SBR, required only if + * SBR instantiated. + * 5. Poll SBRSTAT.scrub_busy=0. + * 6. Set DERATEEN.derate_enable = 0, if DERATEEN.derate_eanble = 1 + * and the read latency (RL) value needs to change after the frequency + * change (LPDDR2/3/4 only). + * 7. Set DBG1.dis_hif=1 so that no new commands will be accepted by the uMCTL2. + */ + mmio_setbits_32(DDRC_DBG1(0), (0x1 << 1)); + + /* + * 8. Poll DBGCAM.dbg_wr_q_empty and DBGCAM.dbg_rd_q_empty to ensure + * that write and read data buffers are empty. + */ + while ((mmio_read_32(DDRC_DBGCAM(0)) & 0x06000000) != 0x06000000) { + ; + } + + /* + * 9. For DDR4, update MR6 with the new tDLLK value via the Mode + * Register Write signals + * 10. Set DFILPCFG0.dfi_lp_en_sr = 0, if DFILPCFG0.dfi_lp_en_sr = 1, + * and wait until DFISTAT.dfi_lp_ack + * 11. If DFI PHY Master interface is active in uMCTL2, then disable it + * 12. Wait until STAT.operating_mode[1:0]!=11 indicating that the + * controller is not in self-refresh mode. + */ + while ((mmio_read_32(DDRC_STAT(0)) & 0x3) == 0x3) { + ; + } + + /* + * 13. Assert PWRCTL.selfref_sw for the DWC_ddr_umctl2 core to enter + * the self-refresh mode. + */ + mmio_setbits_32(DDRC_PWRCTL(0), (1 << 5)); + + /* + * 14. Wait until STAT.operating_mode[1:0]==11 indicating that the + * controller core is in self-refresh mode. + */ + while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) != 0x23) { + ; + } + + sw_pstate(pstate, drate); + dram_cfg_all_mr(info, pstate); + + /* 23. Enable HIF commands by setting DBG1.dis_hif=0. */ + mmio_clrbits_32(DDRC_DBG1(0), (0x1 << 1)); + + /* + * 24. Reset DERATEEN.derate_enable = 1 if DERATEEN.derate_enable + * has been set to 0 in step 6. + * 25. If DFI PHY Master interface was active before step 11 then + * enable it back by programming DFIPHYMSTR.phymstr_en = 1'b1. + * 26. Write 1 to PCTRL_n.port_en. AXI port(s) are no longer blocked + * from taking transactions (Re-enable traffic on AXI ports) + */ + mmio_write_32(DDRC_PCTRL_0(0), 0x1); + + /* + * 27. Write 1 to SBRCTL.scrub_en. Enable SBR if desired, only + * required if SBR instantiated. + */ + + /* + * set SWCTL.sw_done to enable quasi-dynamic register programming + * outside reset. + */ + mmio_write_32(DDRC_SWCTL(0), 0x1); + + /* wait SWSTAT.sw_done_ack to 1 */ + while (!(mmio_read_32(DDRC_SWSTAT(0)) & 0x1)) { + ; + } +} diff --git a/plat/imx/imx8m/ddr/dram.c b/plat/imx/imx8m/ddr/dram.c new file mode 100644 index 000000000..8ea9ba192 --- /dev/null +++ b/plat/imx/imx8m/ddr/dram.c @@ -0,0 +1,263 @@ +/* + * Copyright 2019-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <bl31/interrupt_mgmt.h> +#include <common/runtime_svc.h> +#include <lib/mmio.h> +#include <lib/spinlock.h> +#include <plat/common/platform.h> + +#include <dram.h> + +#define IMX_SIP_DDR_DVFS_GET_FREQ_COUNT 0x10 +#define IMX_SIP_DDR_DVFS_GET_FREQ_INFO 0x11 + +struct dram_info dram_info; + +/* lock used for DDR DVFS */ +spinlock_t dfs_lock; + +static volatile uint32_t wfe_done; +static volatile bool wait_ddrc_hwffc_done = true; +static unsigned int dev_fsp = 0x1; + +static uint32_t fsp_init_reg[3][4] = { + { DDRC_INIT3(0), DDRC_INIT4(0), DDRC_INIT6(0), DDRC_INIT7(0) }, + { DDRC_FREQ1_INIT3(0), DDRC_FREQ1_INIT4(0), DDRC_FREQ1_INIT6(0), DDRC_FREQ1_INIT7(0) }, + { DDRC_FREQ2_INIT3(0), DDRC_FREQ2_INIT4(0), DDRC_FREQ2_INIT6(0), DDRC_FREQ2_INIT7(0) }, +}; + +static void get_mr_values(uint32_t (*mr_value)[8]) +{ + uint32_t init_val; + unsigned int i, fsp_index; + + for (fsp_index = 0U; fsp_index < 3U; fsp_index++) { + for (i = 0U; i < 4U; i++) { + init_val = mmio_read_32(fsp_init_reg[fsp_index][i]); + mr_value[fsp_index][2*i] = init_val >> 16; + mr_value[fsp_index][2*i + 1] = init_val & 0xFFFF; + } + } +} + +/* Restore the ddrc configs */ +void dram_umctl2_init(struct dram_timing_info *timing) +{ + struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg; + unsigned int i; + + for (i = 0U; i < timing->ddrc_cfg_num; i++) { + mmio_write_32(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } + + /* set the default fsp to P0 */ + mmio_write_32(DDRC_MSTR2(0), 0x0); +} + +/* Restore the dram PHY config */ +void dram_phy_init(struct dram_timing_info *timing) +{ + struct dram_cfg_param *cfg = timing->ddrphy_cfg; + unsigned int i; + + /* Restore the PHY init config */ + cfg = timing->ddrphy_cfg; + for (i = 0U; i < timing->ddrphy_cfg_num; i++) { + dwc_ddrphy_apb_wr(cfg->reg, cfg->val); + cfg++; + } + + /* Restore the DDR PHY CSRs */ + cfg = timing->ddrphy_trained_csr; + for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) { + dwc_ddrphy_apb_wr(cfg->reg, cfg->val); + cfg++; + } + + /* Load the PIE image */ + cfg = timing->ddrphy_pie; + for (i = 0U; i < timing->ddrphy_pie_num; i++) { + dwc_ddrphy_apb_wr(cfg->reg, cfg->val); + cfg++; + } +} + +/* EL3 SGI-8 IPI handler for DDR Dynamic frequency scaling */ +static uint64_t waiting_dvfs(uint32_t id, uint32_t flags, + void *handle, void *cookie) +{ + uint64_t mpidr = read_mpidr_el1(); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + uint32_t irq; + + irq = plat_ic_acknowledge_interrupt(); + if (irq < 1022U) { + plat_ic_end_of_interrupt(irq); + } + + /* set the WFE done status */ + spin_lock(&dfs_lock); + wfe_done |= (1 << cpu_id * 8); + dsb(); + spin_unlock(&dfs_lock); + + while (1) { + /* ddr frequency change done */ + if (!wait_ddrc_hwffc_done) + break; + + wfe(); + } + + return 0; +} + +void dram_info_init(unsigned long dram_timing_base) +{ + uint32_t ddrc_mstr, current_fsp; + unsigned int idx = 0; + uint32_t flags = 0; + uint32_t rc; + unsigned int i; + + /* Get the dram type & rank */ + ddrc_mstr = mmio_read_32(DDRC_MSTR(0)); + + dram_info.dram_type = ddrc_mstr & DDR_TYPE_MASK; + dram_info.num_rank = (ddrc_mstr >> 24) & ACTIVE_RANK_MASK; + + /* Get current fsp info */ + current_fsp = mmio_read_32(DDRC_DFIMISC(0)) & 0xf; + dram_info.boot_fsp = current_fsp; + dram_info.current_fsp = current_fsp; + + get_mr_values(dram_info.mr_table); + + dram_info.timing_info = (struct dram_timing_info *)dram_timing_base; + + /* get the num of supported fsp */ + for (i = 0U; i < 4U; ++i) { + if (!dram_info.timing_info->fsp_table[i]) { + break; + } + idx = i; + } + dram_info.num_fsp = i; + + /* check if has bypass mode support */ + if (dram_info.timing_info->fsp_table[idx] < 666) { + dram_info.bypass_mode = true; + } else { + dram_info.bypass_mode = false; + } + + /* Register the EL3 handler for DDR DVFS */ + set_interrupt_rm_flag(flags, NON_SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_EL3, waiting_dvfs, flags); + if (rc != 0) { + panic(); + } +} + + +/* + * For each freq return the following info: + * + * r1: data rate + * r2: 1 + dram_core parent + * r3: 1 + dram_alt parent index + * r4: 1 + dram_apb parent index + * + * The parent indices can be used by an OS who manages source clocks to enabled + * them ahead of the switch. + * + * A parent value of "0" means "don't care". + * + * Current implementation of freq switch is hardcoded in + * plat/imx/common/imx8m/clock.c but in theory this can be enhanced to support + * a wide variety of rates. + */ +int dram_dvfs_get_freq_info(void *handle, u_register_t index) +{ + switch (index) { + case 0: + SMC_RET4(handle, dram_info.timing_info->fsp_table[0], + 1, 0, 5); + case 1: + if (!dram_info.bypass_mode) { + SMC_RET4(handle, dram_info.timing_info->fsp_table[1], + 1, 0, 0); + } + SMC_RET4(handle, dram_info.timing_info->fsp_table[1], + 2, 2, 4); + case 2: + if (!dram_info.bypass_mode) { + SMC_RET4(handle, dram_info.timing_info->fsp_table[2], + 1, 0, 0); + } + SMC_RET4(handle, dram_info.timing_info->fsp_table[2], + 2, 3, 3); + case 3: + SMC_RET4(handle, dram_info.timing_info->fsp_table[3], + 1, 0, 0); + default: + SMC_RET1(handle, -3); + } +} + +int dram_dvfs_handler(uint32_t smc_fid, void *handle, + u_register_t x1, u_register_t x2, u_register_t x3) +{ + uint64_t mpidr = read_mpidr_el1(); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + unsigned int fsp_index = x1; + uint32_t online_cores = x2; + + if (x1 == IMX_SIP_DDR_DVFS_GET_FREQ_COUNT) { + SMC_RET1(handle, dram_info.num_fsp); + } else if (x1 == IMX_SIP_DDR_DVFS_GET_FREQ_INFO) { + return dram_dvfs_get_freq_info(handle, x2); + } else if (x1 < 4) { + wait_ddrc_hwffc_done = true; + dsb(); + + /* trigger the SGI IPI to info other cores */ + for (int i = 0; i < PLATFORM_CORE_COUNT; i++) { + if (cpu_id != i && (online_cores & (0x1 << (i * 8)))) { + plat_ic_raise_el3_sgi(0x8, i); + } + } + + /* make sure all the core in WFE */ + online_cores &= ~(0x1 << (cpu_id * 8)); + while (1) { + if (online_cores == wfe_done) { + break; + } + } + + /* flush the L1/L2 cache */ + dcsw_op_all(DCCSW); + + if (dram_info.dram_type == DDRC_LPDDR4) { + lpddr4_swffc(&dram_info, dev_fsp, fsp_index); + dev_fsp = (~dev_fsp) & 0x1; + } else if (dram_info.dram_type == DDRC_DDR4) { + ddr4_swffc(&dram_info, fsp_index); + } + + dram_info.current_fsp = fsp_index; + wait_ddrc_hwffc_done = false; + wfe_done = 0; + dsb(); + sev(); + isb(); + } + + SMC_RET1(handle, 0); +} diff --git a/plat/imx/imx8m/ddr/dram_retention.c b/plat/imx/imx8m/ddr/dram_retention.c new file mode 100644 index 000000000..7d4f8230e --- /dev/null +++ b/plat/imx/imx8m/ddr/dram_retention.c @@ -0,0 +1,203 @@ +/* + * Copyright 2018-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> +#include <lib/mmio.h> + +#include <dram.h> +#include <platform_def.h> + +#define SRC_DDR1_RCR (IMX_SRC_BASE + 0x1000) +#define SRC_DDR2_RCR (IMX_SRC_BASE + 0x1004) + +#define PU_PGC_UP_TRG 0xf8 +#define PU_PGC_DN_TRG 0x104 +#define GPC_PU_PWRHSK (IMX_GPC_BASE + 0x01FC) +#define CCM_SRC_CTRL_OFFSET (IMX_CCM_BASE + 0x800) +#define CCM_CCGR_OFFSET (IMX_CCM_BASE + 0x4000) +#define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * (n)) +#define CCM_CCGR(n) (CCM_CCGR_OFFSET + 0x10 * (n)) + +#define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) + +#define DBGCAM_EMPTY 0x36000000 + +void dram_enter_retention(void) +{ + /* Wait DBGCAM to be empty */ + while (mmio_read_32(DDRC_DBGCAM(0)) != DBGCAM_EMPTY) { + ; + } + + /* Block AXI ports from taking anymore transactions */ + mmio_write_32(DDRC_PCTRL_0(0), 0x0); + /* Wait until all AXI ports are idle */ + while (mmio_read_32(DDRC_PSTAT(0)) & 0x10001) { + ; + } + + /* Enter self refresh */ + mmio_write_32(DDRC_PWRCTL(0), 0xaa); + + /* LPDDR4 & DDR4/DDR3L need to check different status */ + if (dram_info.dram_type == DDRC_LPDDR4) { + while (0x223 != (mmio_read_32(DDRC_STAT(0)) & 0x33f)) { + ; + } + } else { + while (0x23 != (mmio_read_32(DDRC_STAT(0)) & 0x3f)) { + ; + } + } + + mmio_write_32(DDRC_DFIMISC(0), 0x0); + mmio_write_32(DDRC_SWCTL(0), 0x0); + mmio_write_32(DDRC_DFIMISC(0), 0x1f00); + mmio_write_32(DDRC_DFIMISC(0), 0x1f20); + + while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) { + ; + } + + mmio_write_32(DDRC_DFIMISC(0), 0x1f00); + /* wait DFISTAT.dfi_init_complete to 1 */ + while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { + ; + } + + mmio_write_32(DDRC_SWCTL(0), 0x1); + + /* should check PhyInLP3 pub reg */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + if (!(dwc_ddrphy_apb_rd(0x90028) & 0x1)) { + INFO("PhyInLP3 = 1\n"); + } + dwc_ddrphy_apb_wr(0xd0000, 0x1); + +#if defined(PLAT_imx8mq) + /* pwrdnreqn_async adbm/adbs of ddr */ + mmio_clrbits_32(GPC_PU_PWRHSK, BIT(1)); + while (mmio_read_32(GPC_PU_PWRHSK) & BIT(18)) { + ; + } + mmio_setbits_32(GPC_PU_PWRHSK, BIT(1)); +#else + /* pwrdnreqn_async adbm/adbs of ddr */ + mmio_clrbits_32(GPC_PU_PWRHSK, BIT(2)); + while (mmio_read_32(GPC_PU_PWRHSK) & BIT(20)) { + ; + } + mmio_setbits_32(GPC_PU_PWRHSK, BIT(2)); +#endif + /* remove PowerOk */ + mmio_write_32(SRC_DDR1_RCR, 0x8F000008); + + mmio_write_32(CCM_CCGR(5), 0); + mmio_write_32(CCM_SRC_CTRL(15), 2); + + /* enable the phy iso */ + mmio_setbits_32(IMX_GPC_BASE + 0xd40, 1); + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, BIT(5)); + + VERBOSE("dram enter retention\n"); +} + +void dram_exit_retention(void) +{ + VERBOSE("dram exit retention\n"); + /* assert all reset */ +#if defined(PLAT_imx8mq) + mmio_write_32(SRC_DDR2_RCR, 0x8F000003); + mmio_write_32(SRC_DDR1_RCR, 0x8F00000F); + mmio_write_32(SRC_DDR2_RCR, 0x8F000000); +#else + mmio_write_32(SRC_DDR1_RCR, 0x8F00001F); + mmio_write_32(SRC_DDR1_RCR, 0x8F00000F); +#endif + mmio_write_32(CCM_CCGR(5), 2); + mmio_write_32(CCM_SRC_CTRL(15), 2); + + /* disable iso */ + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, BIT(5)); + mmio_write_32(SRC_DDR1_RCR, 0x8F000006); + + /* wait dram pll locked */ + while (!(mmio_read_32(DRAM_PLL_CTRL) & BIT(31))) { + ; + } + + /* ddrc re-init */ + dram_umctl2_init(dram_info.timing_info); + + /* + * Skips the DRAM init routine and starts up in selfrefresh mode + * Program INIT0.skip_dram_init = 2'b11 + */ + mmio_setbits_32(DDRC_INIT0(0), 0xc0000000); + /* Keeps the controller in self-refresh mode */ + mmio_write_32(DDRC_PWRCTL(0), 0xaa); + mmio_write_32(DDRC_DBG1(0), 0x0); + mmio_write_32(SRC_DDR1_RCR, 0x8F000004); + mmio_write_32(SRC_DDR1_RCR, 0x8F000000); + + /* before write Dynamic reg, sw_done should be 0 */ + mmio_write_32(DDRC_SWCTL(0), 0x0); + +#if !PLAT_imx8mn + if (dram_info.dram_type == DDRC_LPDDR4) { + mmio_write_32(DDRC_DDR_SS_GPR0, 0x01); /*LPDDR4 mode */ + } +#endif /* !PLAT_imx8mn */ + + mmio_write_32(DDRC_DFIMISC(0), 0x0); + + /* dram phy re-init */ + dram_phy_init(dram_info.timing_info); + + /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + while (dwc_ddrphy_apb_rd(0x20097)) { + ; + } + dwc_ddrphy_apb_wr(0xd0000, 0x1); + + /* before write Dynamic reg, sw_done should be 0 */ + mmio_write_32(DDRC_SWCTL(0), 0x0); + mmio_write_32(DDRC_DFIMISC(0), 0x20); + /* wait DFISTAT.dfi_init_complete to 1 */ + while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { + ; + } + + /* clear DFIMISC.dfi_init_start */ + mmio_write_32(DDRC_DFIMISC(0), 0x0); + /* set DFIMISC.dfi_init_complete_en */ + mmio_write_32(DDRC_DFIMISC(0), 0x1); + + /* set SWCTL.sw_done to enable quasi-dynamic register programming */ + mmio_write_32(DDRC_SWCTL(0), 0x1); + /* wait SWSTAT.sw_done_ack to 1 */ + while (!(mmio_read_32(DDRC_SWSTAT(0)) & 0x1)) { + ; + } + + mmio_write_32(DDRC_PWRCTL(0), 0x88); + /* wait STAT to normal state */ + while (0x1 != (mmio_read_32(DDRC_STAT(0)) & 0x7)) { + ; + } + + mmio_write_32(DDRC_PCTRL_0(0), 0x1); + /* dis_auto-refresh is set to 0 */ + mmio_write_32(DDRC_RFSHCTL3(0), 0x0); + + /* should check PhyInLP3 pub reg */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + if (!(dwc_ddrphy_apb_rd(0x90028) & 0x1)) { + VERBOSE("PHYInLP3 = 0\n"); + } + dwc_ddrphy_apb_wr(0xd0000, 0x1); +} diff --git a/plat/imx/imx8m/ddr/lpddr4_dvfs.c b/plat/imx/imx8m/ddr/lpddr4_dvfs.c new file mode 100644 index 000000000..2b4f300c7 --- /dev/null +++ b/plat/imx/imx8m/ddr/lpddr4_dvfs.c @@ -0,0 +1,292 @@ +/* + * Copyright 2018-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/mmio.h> + +#include <dram.h> + +static void lpddr4_mr_write(uint32_t mr_rank, uint32_t mr_addr, uint32_t mr_data) +{ + /* + * 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there + * is no outstanding MR transaction. No + * writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1. + */ + while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) + ; + + /* + * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, + * MRCTRL0.mr_rank and (for MRWs) + * MRCTRL1.mr_data to define the MR transaction. + */ + mmio_write_32(DDRC_MRCTRL0(0), (mr_rank << 4)); + mmio_write_32(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); + mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); +} + +void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, + unsigned int fsp_index) + +{ + uint32_t mr, emr, emr2, emr3; + uint32_t mr11, mr12, mr22, mr14; + uint32_t val; + uint32_t derate_backup[3]; + uint32_t (*mr_data)[8]; + + /* 1. program targetd UMCTL2_REGS_FREQ1/2/3,already done, skip it. */ + + /* 2. MR13.FSP-WR=1, MRW to update MR registers */ + mr_data = info->mr_table; + mr = mr_data[fsp_index][0]; + emr = mr_data[fsp_index][1]; + emr2 = mr_data[fsp_index][2]; + emr3 = mr_data[fsp_index][3]; + mr11 = mr_data[fsp_index][4]; + mr12 = mr_data[fsp_index][5]; + mr22 = mr_data[fsp_index][6]; + mr14 = mr_data[fsp_index][7]; + + val = (init_fsp == 1) ? 0x2 << 6 : 0x1 << 6; + emr3 = (emr3 & 0x003f) | val | 0x0d00; + + /* 12. set PWRCTL.selfref_en=0 */ + mmio_clrbits_32(DDRC_PWRCTL(0), 0xf); + + /* It is more safe to config it here */ + mmio_clrbits_32(DDRC_DFIPHYMSTR(0), 0x1); + + lpddr4_mr_write(3, 13, emr3); + lpddr4_mr_write(3, 1, mr); + lpddr4_mr_write(3, 2, emr); + lpddr4_mr_write(3, 3, emr2); + lpddr4_mr_write(3, 11, mr11); + lpddr4_mr_write(3, 12, mr12); + lpddr4_mr_write(3, 14, mr14); + lpddr4_mr_write(3, 22, mr22); + + do { + val = mmio_read_32(DDRC_MRSTAT(0)); + } while (val & 0x1); + + /* 3. disable AXI ports */ + mmio_write_32(DDRC_PCTRL_0(0), 0x0); + + /* 4.Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. */ + do { + val = mmio_read_32(DDRC_PSTAT(0)); + } while (val != 0); + + /* 6.disable SBRCTL.scrub_en, skip if never enable it */ + /* 7.poll SBRSTAT.scrub_busy Q2: should skip phy master if never enable it */ + /* Disable phy master */ +#ifdef DFILP_SPT + /* 8. disable DFI LP */ + /* DFILPCFG0.dfi_lp_en_sr */ + val = mmio_read_32(DDRC_DFILPCFG0(0)); + if (val & 0x100) { + mmio_write_32(DDRC_DFILPCFG0(0), 0x0); + do { + val = mmio_read_32(DDRC_DFISTAT(0)); // dfi_lp_ack + val2 = mmio_read_32(DDRC_STAT(0)); // operating_mode + } while (((val & 0x2) == 0x2) && ((val2 & 0x7) == 3)); + } +#endif + /* 9. wait until in normal or power down states */ + do { + /* operating_mode */ + val = mmio_read_32(DDRC_STAT(0)); + } while (((val & 0x7) != 1) && ((val & 0x7) != 2)); + + /* 10. Disable automatic derating: derate_enable */ + val = mmio_read_32(DDRC_DERATEEN(0)); + derate_backup[0] = val; + mmio_clrbits_32(DDRC_DERATEEN(0), 0x1); + + val = mmio_read_32(DDRC_FREQ1_DERATEEN(0)); + derate_backup[1] = val; + mmio_clrbits_32(DDRC_FREQ1_DERATEEN(0), 0x1); + + val = mmio_read_32(DDRC_FREQ2_DERATEEN(0)); + derate_backup[2] = val; + mmio_clrbits_32(DDRC_FREQ2_DERATEEN(0), 0x1); + + /* 11. disable automatic ZQ calibration */ + mmio_setbits_32(DDRC_ZQCTL0(0), BIT(31)); + mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31)); + mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31)); + + /* 12. set PWRCTL.selfref_en=0 */ + mmio_clrbits_32(DDRC_PWRCTL(0), 0x1); + + /* 13.Poll STAT.operating_mode is in "Normal" (001) or "Power-down" (010) */ + do { + val = mmio_read_32(DDRC_STAT(0)); + } while (((val & 0x7) != 1) && ((val & 0x7) != 2)); + + /* 14-15. trigger SW SR */ + /* bit 5: selfref_sw, bit 6: stay_in_selfref */ + mmio_setbits_32(DDRC_PWRCTL(0), 0x60); + + /* 16. Poll STAT.selfref_state in "Self Refresh 1" */ + do { + val = mmio_read_32(DDRC_STAT(0)); + } while ((val & 0x300) != 0x100); + + /* 17. disable dq */ + mmio_setbits_32(DDRC_DBG1(0), 0x1); + + /* 18. Poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty */ + do { + val = mmio_read_32(DDRC_DBGCAM(0)); + val &= 0x30000000; + } while (val != 0x30000000); + + /* 19. change MR13.FSP-OP to new FSP and MR13.VRCG to high current */ + emr3 = (((~init_fsp) & 0x1) << 7) | (0x1 << 3) | (emr3 & 0x0077) | 0x0d00; + lpddr4_mr_write(3, 13, emr3); + + /* 20. enter SR Power Down */ + mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x20); + + /* 21. Poll STAT.selfref_state is in "SR Power down" */ + do { + val = mmio_read_32(DDRC_STAT(0)); + } while ((val & 0x300) != 0x200); + + /* 22. set dfi_init_complete_en = 0 */ + + /* 23. switch clock */ + /* set SWCTL.dw_done to 0 */ + mmio_write_32(DDRC_SWCTL(0), 0x0000); + + /* 24. program frequency mode=1(bit 29), target_frequency=target_freq (bit 29) */ + mmio_write_32(DDRC_MSTR2(0), fsp_index); + + /* 25. DBICTL for FSP-OP[1], skip it if never enable it */ + + /* 26.trigger initialization in the PHY */ + + /* Q3: if refresh level is updated, then should program */ + /* as updating refresh, need to toggle refresh_update_level signal */ + val = mmio_read_32(DDRC_RFSHCTL3(0)); + val = val ^ 0x2; + mmio_write_32(DDRC_RFSHCTL3(0), val); + + /* Q4: only for legacy PHY, so here can skipped */ + + /* dfi_frequency -> 0x1x */ + val = mmio_read_32(DDRC_DFIMISC(0)); + val &= 0xFE; + val |= (fsp_index << 8); + mmio_write_32(DDRC_DFIMISC(0), val); + /* dfi_init_start */ + val |= 0x20; + mmio_write_32(DDRC_DFIMISC(0), val); + + /* polling dfi_init_complete de-assert */ + do { + val = mmio_read_32(DDRC_DFISTAT(0)); + } while ((val & 0x1) == 0x1); + + /* change the clock frequency */ + dram_clock_switch(info->timing_info->fsp_table[fsp_index], info->bypass_mode); + + /* dfi_init_start de-assert */ + mmio_clrbits_32(DDRC_DFIMISC(0), 0x20); + + /* polling dfi_init_complete re-assert */ + do { + val = mmio_read_32(DDRC_DFISTAT(0)); + } while ((val & 0x1) == 0x0); + + /* 27. set ZQCTL0.dis_srx_zqcl = 1 */ + if (fsp_index == 0) { + mmio_setbits_32(DDRC_ZQCTL0(0), BIT(30)); + } else if (fsp_index == 1) { + mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); + } else { + mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30)); + } + + /* 28,29. exit "self refresh power down" to stay "self refresh 2" */ + /* exit SR power down */ + mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x40); + /* 30. Poll STAT.selfref_state in "Self refresh 2" */ + do { + val = mmio_read_32(DDRC_STAT(0)); + } while ((val & 0x300) != 0x300); + + /* 31. change MR13.VRCG to normal */ + emr3 = (emr3 & 0x00f7) | 0x0d00; + lpddr4_mr_write(3, 13, emr3); + + /* enable PHY master */ + mmio_write_32(DDRC_DFIPHYMSTR(0), 0x1); + + /* 32. issue ZQ if required: zq_calib_short, bit 4 */ + /* polling zq_calib_short_busy */ + mmio_setbits_32(DDRC_DBGCMD(0), 0x10); + + do { + val = mmio_read_32(DDRC_DBGSTAT(0)); + } while ((val & 0x10) != 0x0); + + /* 33. Reset ZQCTL0.dis_srx_zqcl=0 */ + if (fsp_index == 1) + mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); + else if (fsp_index == 2) + mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30)); + else + mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(30)); + + /* set SWCTL.dw_done to 1 and poll SWSTAT.sw_done_ack=1 */ + mmio_write_32(DDRC_SWCTL(0), 0x1); + + /* wait SWSTAT.sw_done_ack to 1 */ + do { + val = mmio_read_32(DDRC_SWSTAT(0)); + } while ((val & 0x1) == 0x0); + + /* 34. set PWRCTL.stay_in_selfreh=0, exit SR */ + mmio_clrbits_32(DDRC_PWRCTL(0), 0x40); + /* wait tXSR */ + + /* 35. Poll STAT.selfref_state in "Idle" */ + do { + val = mmio_read_32(DDRC_STAT(0)); + } while ((val & 0x300) != 0x0); + +#ifdef DFILP_SPT + /* 36. restore dfi_lp.dfi_lp_en_sr */ + mmio_setbits_32(DDRC_DFILPCFG0(0), BIT(8)); +#endif + + /* 37. re-enable CAM: dis_dq */ + mmio_clrbits_32(DDRC_DBG1(0), 0x1); + + /* 38. re-enable automatic SR: selfref_en */ + mmio_setbits_32(DDRC_PWRCTL(0), 0x1); + + /* 39. re-enable automatic ZQ: dis_auto_zq=0 */ + /* disable automatic ZQ calibration */ + if (fsp_index == 1) + mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31)); + else if (fsp_index == 2) + mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31)); + else + mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(31)); + /* 40. re-emable automatic derating: derate_enable */ + mmio_write_32(DDRC_DERATEEN(0), derate_backup[0]); + mmio_write_32(DDRC_FREQ1_DERATEEN(0), derate_backup[1]); + mmio_write_32(DDRC_FREQ2_DERATEEN(0), derate_backup[2]); + + /* 41. write 1 to PCTRL.port_en */ + mmio_write_32(DDRC_PCTRL_0(0), 0x1); + + /* 42. enable SBRCTL.scrub_en, skip if never enable it */ +} diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c index 1e55f058d..e674d7a31 100644 --- a/plat/imx/imx8m/gpc_common.c +++ b/plat/imx/imx8m/gpc_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include <arch.h> #include <arch_helpers.h> #include <common/debug.h> +#include <common/runtime_svc.h> #include <lib/mmio.h> #include <lib/psci/psci.h> @@ -16,10 +17,14 @@ #include <imx8m_psci.h> #include <plat_imx8.h> +#define MAX_PLL_NUM U(10) + static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, }; DEFINE_BAKERY_LOCK(gpc_lock); +#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03 + #pragma weak imx_set_cpu_pwr_off #pragma weak imx_set_cpu_pwr_on #pragma weak imx_set_cpu_lpm @@ -250,3 +255,54 @@ void imx_clear_rbc_count(void) mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | (0x3f << SLPCR_RBC_COUNT_SHIFT)); } + +struct pll_override { + uint32_t reg; + uint32_t override_mask; +}; + +struct pll_override pll[MAX_PLL_NUM] = { + {.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), }, + {.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), }, + {.reg = 0x28, .override_mask = (1 << 12) | (1 << 8), }, + {.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), }, + {.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), }, + {.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), }, + {.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), }, + {.reg = 0x94, .override_mask = 0x5555500, }, + {.reg = 0x104, .override_mask = 0x5555500, }, + {.reg = 0x114, .override_mask = 0x500, }, +}; + +#define PLL_BYPASS BIT(4) +void imx_anamix_override(bool enter) +{ + unsigned int i; + + /* + * bypass all the plls & enable the override bit before + * entering DSM mode. + */ + for (i = 0U; i < MAX_PLL_NUM; i++) { + if (enter) { + mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); + mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); + } else { + mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); + mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); + } + } +} + +int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3) +{ + switch (x1) { + case FSL_SIP_CONFIG_GPC_PM_DOMAIN: + imx_gpc_pm_domain_enable(x2, x3); + break; + default: + return SMC_UNK; + } + + return 0; +} diff --git a/plat/imx/imx8m/imx8m_caam.c b/plat/imx/imx8m/imx8m_caam.c index 644572c5a..a4915506a 100644 --- a/plat/imx/imx8m/imx8m_caam.c +++ b/plat/imx/imx8m/imx8m_caam.c @@ -24,7 +24,7 @@ void imx8m_caam_init(void) /* config CAAM JRaMID set MID to Cortex A */ if (mmio_read_32(CAAM_JR0MID) == HAB_JR0_DID) { - NOTICE("Do not release JR0 to NS as it can be used by HAB"); + NOTICE("Do not release JR0 to NS as it can be used by HAB\n"); } else { mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); } diff --git a/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c b/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c index 8b2fdd626..5d65ef202 100644 --- a/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c +++ b/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c @@ -13,6 +13,7 @@ #endif #include <common/fdt_wrappers.h> #include <libfdt.h> +#include <platform_def.h> #define DTB_PROP_HW_LOG_ADDR "tpm_event_log_addr" #define DTB_PROP_HW_LOG_SIZE "tpm_event_log_size" diff --git a/plat/imx/imx8m/imx8m_psci_common.c b/plat/imx/imx8m/imx8m_psci_common.c index 9dfd311d1..8f545d652 100644 --- a/plat/imx/imx8m/imx8m_psci_common.c +++ b/plat/imx/imx8m/imx8m_psci_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,7 @@ #include <lib/mmio.h> #include <lib/psci/psci.h> +#include <dram.h> #include <gpc.h> #include <imx8m_psci.h> #include <plat_imx8.h> @@ -39,7 +40,7 @@ int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) int imx_pwr_domain_on(u_register_t mpidr) { unsigned int core_id; - uint64_t base_addr = BL31_BASE; + uint64_t base_addr = BL31_START; core_id = MPIDR_AFFLVL0_VAL(mpidr); @@ -101,7 +102,7 @@ void imx_cpu_standby(plat_local_state_t cpu_state) void imx_domain_suspend(const psci_power_state_t *target_state) { - uint64_t base_addr = BL31_BASE; + uint64_t base_addr = BL31_START; uint64_t mpidr = read_mpidr_el1(); unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); @@ -118,8 +119,11 @@ void imx_domain_suspend(const psci_power_state_t *target_state) if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state)); - if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) + if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) { imx_set_sys_lpm(core_id, true); + dram_enter_retention(); + imx_anamix_override(true); + } } void imx_domain_suspend_finish(const psci_power_state_t *target_state) @@ -127,8 +131,11 @@ void imx_domain_suspend_finish(const psci_power_state_t *target_state) uint64_t mpidr = read_mpidr_el1(); unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); - if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) + if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) { + imx_anamix_override(false); + dram_exit_retention(); imx_set_sys_lpm(core_id, false); + } if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) { imx_clear_rbc_count(); @@ -222,8 +229,11 @@ int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie) void __dead2 imx_system_off(void) { - mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV | - SNVS_LPCR_DP_EN | SNVS_LPCR_TOP); + uint32_t val; + + val = mmio_read_32(IMX_SNVS_BASE + SNVS_LPCR); + val |= SNVS_LPCR_SRTC_ENV | SNVS_LPCR_DP_EN | SNVS_LPCR_TOP; + mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, val); while (1) ; diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c index ab59292e5..cc1cb1066 100644 --- a/plat/imx/imx8m/imx8mm/gpc.c +++ b/plat/imx/imx8m/imx8mm/gpc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,332 @@ #include <gpc.h> #include <imx_sip_svc.h> +#define MIPI_PWR_REQ BIT(0) +#define PCIE_PWR_REQ BIT(1) +#define OTG1_PWR_REQ BIT(2) +#define OTG2_PWR_REQ BIT(3) +#define HSIOMIX_PWR_REQ BIT(4) +#define GPU2D_PWR_REQ BIT(6) +#define GPUMIX_PWR_REQ BIT(7) +#define VPUMIX_PWR_REQ BIT(8) +#define GPU3D_PWR_REQ BIT(9) +#define DISPMIX_PWR_REQ BIT(10) +#define VPU_G1_PWR_REQ BIT(11) +#define VPU_G2_PWR_REQ BIT(12) +#define VPU_H1_PWR_REQ BIT(13) + +#define HSIOMIX_ADB400_SYNC (0x3 << 5) +#define DISPMIX_ADB400_SYNC BIT(7) +#define VPUMIX_ADB400_SYNC BIT(8) +#define GPU3D_ADB400_SYNC BIT(9) +#define GPU2D_ADB400_SYNC BIT(10) +#define GPUMIX_ADB400_SYNC BIT(11) +#define HSIOMIX_ADB400_ACK (0x3 << 23) +#define DISPMIX_ADB400_ACK BIT(25) +#define VPUMIX_ADB400_ACK BIT(26) +#define GPU3D_ADB400_ACK BIT(27) +#define GPU2D_ADB400_ACK BIT(28) +#define GPUMIX_ADB400_ACK BIT(29) + +#define MIPI_PGC 0xc00 +#define PCIE_PGC 0xc40 +#define OTG1_PGC 0xc80 +#define OTG2_PGC 0xcc0 +#define HSIOMIX_PGC 0xd00 +#define GPU2D_PGC 0xd80 +#define GPUMIX_PGC 0xdc0 +#define VPUMIX_PGC 0xe00 +#define GPU3D_PGC 0xe40 +#define DISPMIX_PGC 0xe80 +#define VPU_G1_PGC 0xec0 +#define VPU_G2_PGC 0xf00 +#define VPU_H1_PGC 0xf40 + +enum pu_domain_id { + HSIOMIX, + PCIE, + OTG1, + OTG2, + GPUMIX, + VPUMIX, + VPU_G1, + VPU_G2, + VPU_H1, + DISPMIX, + MIPI, + /* below two domain only for ATF internal use */ + GPU2D, + GPU3D, + MAX_DOMAINS, +}; + +/* PU domain */ +static struct imx_pwr_domain pu_domains[] = { + IMX_MIX_DOMAIN(HSIOMIX, false), + IMX_PD_DOMAIN(PCIE, false), + IMX_PD_DOMAIN(OTG1, true), + IMX_PD_DOMAIN(OTG2, true), + IMX_MIX_DOMAIN(GPUMIX, false), + IMX_MIX_DOMAIN(VPUMIX, false), + IMX_PD_DOMAIN(VPU_G1, false), + IMX_PD_DOMAIN(VPU_G2, false), + IMX_PD_DOMAIN(VPU_H1, false), + IMX_MIX_DOMAIN(DISPMIX, false), + IMX_PD_DOMAIN(MIPI, false), + /* below two domain only for ATF internal use */ + IMX_MIX_DOMAIN(GPU2D, false), + IMX_MIX_DOMAIN(GPU3D, false), +}; + +static unsigned int pu_domain_status; + +#define GPU_RCR 0x40 +#define VPU_RCR 0x44 + +#define VPU_CTL_BASE 0x38330000 +#define BLK_SFT_RSTN_CSR 0x0 +#define H1_SFT_RSTN BIT(2) +#define G1_SFT_RSTN BIT(1) +#define G2_SFT_RSTN BIT(0) + +#define DISP_CTL_BASE 0x32e28000 + +void vpu_sft_reset_assert(uint32_t domain_id) +{ + uint32_t val; + + val = mmio_read_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR); + + switch (domain_id) { + case VPU_G1: + val &= ~G1_SFT_RSTN; + mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val); + break; + case VPU_G2: + val &= ~G2_SFT_RSTN; + mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val); + break; + case VPU_H1: + val &= ~H1_SFT_RSTN; + mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val); + break; + default: + break; + } +} + +void vpu_sft_reset_deassert(uint32_t domain_id) +{ + uint32_t val; + + val = mmio_read_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR); + + switch (domain_id) { + case VPU_G1: + val |= G1_SFT_RSTN; + mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val); + break; + case VPU_G2: + val |= G2_SFT_RSTN; + mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val); + break; + case VPU_H1: + val |= H1_SFT_RSTN; + mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val); + break; + default: + break; + } +} + +void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) +{ + if (domain_id >= MAX_DOMAINS) { + return; + } + + struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; + + if (on) { + pu_domain_status |= (1 << domain_id); + + if (domain_id == VPU_G1 || domain_id == VPU_G2 || + domain_id == VPU_H1) { + vpu_sft_reset_assert(domain_id); + } + + /* HSIOMIX has no PU bit, so skip for it */ + if (domain_id != HSIOMIX) { + /* clear the PGC bit */ + mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); + + /* power up the domain */ + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); + + /* wait for power request done */ + while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { + ; + } + } + + if (domain_id == VPU_G1 || domain_id == VPU_G2 || + domain_id == VPU_H1) { + vpu_sft_reset_deassert(domain_id); + /* dealy for a while to make sure reset done */ + udelay(100); + } + + if (domain_id == GPUMIX) { + /* assert reset */ + mmio_write_32(IMX_SRC_BASE + GPU_RCR, 0x1); + + /* power up GPU2D */ + mmio_clrbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1); + + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU2D_PWR_REQ); + + /* wait for power request done */ + while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU2D_PWR_REQ) { + ; + } + + udelay(1); + + /* power up GPU3D */ + mmio_clrbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1); + + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU3D_PWR_REQ); + + /* wait for power request done */ + while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU3D_PWR_REQ) { + ; + } + + udelay(10); + /* release the gpumix reset */ + mmio_write_32(IMX_SRC_BASE + GPU_RCR, 0x0); + udelay(10); + } + + /* vpu sft clock enable */ + if (domain_id == VPUMIX) { + mmio_write_32(IMX_SRC_BASE + VPU_RCR, 0x1); + udelay(5); + mmio_write_32(IMX_SRC_BASE + VPU_RCR, 0x0); + udelay(5); + + /* enable all clock */ + mmio_write_32(VPU_CTL_BASE + 0x4, 0x7); + } + + if (domain_id == DISPMIX) { + /* special setting for DISPMIX */ + mmio_write_32(DISP_CTL_BASE + 0x4, 0x1fff); + mmio_write_32(DISP_CTL_BASE, 0x7f); + mmio_write_32(DISP_CTL_BASE + 0x8, 0x30000); + } + + /* handle the ADB400 sync */ + if (pwr_domain->need_sync) { + /* clear adb power down request */ + mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); + + /* wait for adb power request ack */ + while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { + ; + } + } + + if (domain_id == GPUMIX) { + /* power up GPU2D ADB */ + mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); + + /* wait for adb power request ack */ + while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) { + ; + } + + /* power up GPU3D ADB */ + mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); + + /* wait for adb power request ack */ + while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) { + ; + } + } + } else { + pu_domain_status &= ~(1 << domain_id); + + if (domain_id == OTG1 || domain_id == OTG2) { + return; + } + + /* GPU2D & GPU3D ADB power down */ + if (domain_id == GPUMIX) { + mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); + + /* wait for adb power request ack */ + while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) { + ; + } + + mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); + + /* wait for adb power request ack */ + while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) { + ; + } + } + + /* handle the ADB400 sync */ + if (pwr_domain->need_sync) { + /* set adb power down request */ + mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); + + /* wait for adb power request ack */ + while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { + ; + } + } + + if (domain_id == GPUMIX) { + /* power down GPU2D */ + mmio_setbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1); + + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU2D_PWR_REQ); + + /* wait for power request done */ + while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU2D_PWR_REQ) { + ; + } + + /* power down GPU3D */ + mmio_setbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1); + + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU3D_PWR_REQ); + + /* wait for power request done */ + while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU3D_PWR_REQ) { + ; + } + } + + /* HSIOMIX has no PU bit, so skip for it */ + if (domain_id != HSIOMIX) { + /* set the PGC bit */ + mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); + + /* power down the domain */ + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); + + /* wait for power request done */ + while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) { + ; + } + } + } +} + void imx_gpc_init(void) { unsigned int val; @@ -85,7 +411,4 @@ void imx_gpc_init(void) */ mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); - - /* enable all the power domain by default */ - mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf); } diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c index debede1fd..67bfd3651 100644 --- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c @@ -21,6 +21,7 @@ #include <lib/xlat_tables/xlat_tables_v2.h> #include <plat/common/platform.h> +#include <dram.h> #include <gpc.h> #include <imx_aipstz.h> #include <imx_uart.h> @@ -31,9 +32,22 @@ #define TRUSTY_PARAMS_LEN_BYTES (4096*2) +/* + * Note: DRAM region is mapped with entire size available and uses MT_RW + * attributes. + * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section + * for explanation of this mapping scheme. + */ static const mmap_region_t imx_mmap[] = { MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ + MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */ + MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */ + MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */ + MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */ + MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */ + MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */ + MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */ {0}, }; @@ -130,13 +144,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, imx_csu_init(csu_cfg); - imx8m_caam_init(); - console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE, &console); /* This console is only used for boot stage */ console_set_scope(&console, CONSOLE_FLAG_BOOT); + imx8m_caam_init(); + /* * tell BL3-1 where the non-secure software image is located * and the entry state information. @@ -170,24 +184,30 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl31_tzc380_setup(); } +#define MAP_BL31_TOTAL \ + MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) +#define MAP_BL31_RO \ + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) +#define MAP_COHERENT_MEM \ + MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#define MAP_BL32_TOTAL \ + MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) + void bl31_plat_arch_setup(void) { - mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), - MT_MEMORY | MT_RW | MT_SECURE); - mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), - MT_MEMORY | MT_RO | MT_SECURE); + const mmap_region_t bl_regions[] = { + MAP_BL31_TOTAL, + MAP_BL31_RO, #if USE_COHERENT_MEM - mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, - (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), - MT_DEVICE | MT_RW | MT_SECURE); + MAP_COHERENT_MEM, #endif - /* Map TEE memory */ - mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); - - mmap_add(imx_mmap); - - init_xlat_tables(); + /* Map TEE memory */ + MAP_BL32_TOTAL, + {0} + }; + setup_page_tables(bl_regions, imx_mmap); enable_mmu_el3(0); } @@ -198,6 +218,9 @@ void bl31_platform_setup(void) /* select the CKIL source to 32K OSC */ mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); + /* Init the dram info */ + dram_info_init(SAVED_DRAM_TIMING_BASE); + plat_gic_driver_init(); plat_gic_init(); diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index ed693b9fc..65749f348 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -6,6 +6,8 @@ #include <arch.h> #include <common/tbbr/tbbr_img_def.h> +#include <lib/utils_def.h> +#include <plat/common/common_def.h> #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 @@ -39,9 +41,9 @@ #if defined(NEED_BL2) #define BL2_BASE U(0x920000) -#define BL2_LIMIT U(0x940000) +#define BL2_SIZE SZ_128K +#define BL2_LIMIT (BL2_BASE + BL2_SIZE) #define BL31_BASE U(0x900000) -#define BL31_LIMIT U(0x920000) #define IMX_FIP_BASE U(0x40310000) #define IMX_FIP_SIZE U(0x000300000) #define IMX_FIP_LIMIT U(FIP_BASE + FIP_SIZE) @@ -52,9 +54,11 @@ #define PLAT_IMX8MM_BOOT_MMC_BASE U(0x30B50000) /* SD */ #else #define BL31_BASE U(0x920000) -#define BL31_LIMIT U(0x940000) #endif +#define BL31_SIZE SZ_128K +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + /* non-secure uboot base */ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) #define PLAT_NS_IMAGE_SIZE U(0x00200000) @@ -85,7 +89,7 @@ #define IMX_AIPSTZ4 U(0x32df0000) #define IMX_AIPS_BASE U(0x30000000) -#define IMX_AIPS_SIZE U(0xC00000) +#define IMX_AIPS_SIZE U(0x3000000) #define IMX_GPV_BASE U(0x32000000) #define IMX_GPV_SIZE U(0x800000) #define IMX_AIPS1_BASE U(0x30200000) @@ -105,7 +109,17 @@ #define IMX_DDRC_BASE U(0x3d400000) #define IMX_DDRPHY_BASE U(0x3c000000) #define IMX_DDR_IPS_BASE U(0x3d000000) +#define IMX_DDR_IPS_SIZE U(0x1800000) +#define IMX_VPUMIX_BASE U(0x38330000) +#define IMX_VPUMIX_SIZE U(0x100000) #define IMX_ROM_BASE U(0x0) +#define IMX_ROM_SIZE U(0x40000) +#define IMX_NS_OCRAM_BASE U(0x900000) +#define IMX_NS_OCRAM_SIZE U(0x20000) +#define IMX_CAAM_RAM_BASE U(0x100000) +#define IMX_CAAM_RAM_SIZE U(0x10000) +#define IMX_DRAM_BASE U(0x40000000) +#define IMX_DRAM_SIZE U(0xc0000000) #define GPV_BASE U(0x32000000) #define GPV_SIZE U(0x800000) @@ -140,12 +154,14 @@ #define GPR_TZASC_EN_LOCK BIT(16) #define ANAMIX_MISC_CTL U(0x124) +#define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) #define MAX_CSU_NUM U(64) #define OCRAM_S_BASE U(0x00180000) #define OCRAM_S_SIZE U(0x8000) #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) +#define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE #define COUNTER_FREQUENCY 8000000 /* 8MHz */ diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk index 0cce7ca57..7a42554f5 100644 --- a/plat/imx/imx8m/imx8mm/platform.mk +++ b/plat/imx/imx8m/imx8mm/platform.mk @@ -19,6 +19,12 @@ include drivers/arm/gic/v3/gicv3.mk include lib/libfdt/libfdt.mk +IMX_DRAM_SOURCES := plat/imx/imx8m/ddr/dram.c \ + plat/imx/imx8m/ddr/clock.c \ + plat/imx/imx8m/ddr/dram_retention.c \ + plat/imx/imx8m/ddr/ddr4_dvfs.c \ + plat/imx/imx8m/ddr/lpddr4_dvfs.c + IMX_GIC_SOURCES := ${GICV3_SOURCES} \ plat/common/plat_gicv3.c \ plat/common/plat_psci_common.c \ @@ -26,6 +32,7 @@ IMX_GIC_SOURCES := ${GICV3_SOURCES} \ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ plat/imx/imx8m/gpc_common.c \ + plat/imx/imx8m/imx_hab.c \ plat/imx/imx8m/imx_aipstz.c \ plat/imx/imx8m/imx_rdc.c \ plat/imx/imx8m/imx8m_csu.c \ @@ -43,6 +50,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ ${XLAT_TABLES_LIB_SRCS} \ + ${IMX_DRAM_SOURCES} \ ${IMX_GIC_SOURCES} ifeq (${NEED_BL2},yes) @@ -125,15 +133,16 @@ certificates: $(ROT_KEY) $(ROT_KEY): | $(BUILD_PLAT) @echo " OPENSSL $@" @if [ ! -f $(ROT_KEY) ]; then \ - openssl genrsa 2048 > $@ 2>/dev/null; \ + ${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \ fi $(ROTPK_HASH): $(ROT_KEY) @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null endif +ENABLE_PIE := 1 USE_COHERENT_MEM := 1 RESET_TO_BL31 := 1 A53_DISABLE_NON_TEMPORAL_HINT := 0 @@ -162,6 +171,10 @@ ifeq (${MEASURED_BOOT},1) $(info Including ${MEASURED_BOOT_MK}) include ${MEASURED_BOOT_MK} +ifneq (${MBOOT_EL_HASH_ALG}, sha256) + $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) +endif + BL2_SOURCES += plat/imx/imx8m/imx8m_measured_boot.c \ plat/imx/imx8m/imx8m_dyn_cfg_helpers.c \ ${EVENT_LOG_SOURCES} diff --git a/plat/imx/imx8m/imx8mn/gpc.c b/plat/imx/imx8m/imx8mn/gpc.c index 37d4226a6..4e052972c 100644 --- a/plat/imx/imx8m/imx8mn/gpc.c +++ b/plat/imx/imx8m/imx8mn/gpc.c @@ -1,5 +1,5 @@ /* - * Copyright 2019-2020 NXP + * Copyright 2019-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,6 +21,124 @@ #define CCGR(x) (0x4000 + (x) * 0x10) +#define MIPI_PWR_REQ BIT(0) +#define OTG1_PWR_REQ BIT(2) +#define HSIOMIX_PWR_REQ BIT(4) +#define GPUMIX_PWR_REQ BIT(7) +#define DISPMIX_PWR_REQ BIT(10) + +#define HSIOMIX_ADB400_SYNC BIT(5) +#define DISPMIX_ADB400_SYNC BIT(7) +#define GPUMIX_ADB400_SYNC (0x5 << 9) +#define HSIOMIX_ADB400_ACK BIT(23) +#define DISPMIX_ADB400_ACK BIT(25) +#define GPUMIX_ADB400_ACK (0x5 << 27) + +#define MIPI_PGC 0xc00 +#define OTG1_PGC 0xc80 +#define HSIOMIX_PGC 0xd00 +#define GPUMIX_PGC 0xdc0 +#define DISPMIX_PGC 0xe80 + +enum pu_domain_id { + HSIOMIX, + OTG1 = 2, + GPUMIX = 4, + DISPMIX = 9, + MIPI, +}; + +/* PU domain, add some hole to minimize the uboot change */ +static struct imx_pwr_domain pu_domains[11] = { + [HSIOMIX] = IMX_MIX_DOMAIN(HSIOMIX, false), + [OTG1] = IMX_PD_DOMAIN(OTG1, true), + [GPUMIX] = IMX_MIX_DOMAIN(GPUMIX, false), + [DISPMIX] = IMX_MIX_DOMAIN(DISPMIX, false), + [MIPI] = IMX_PD_DOMAIN(MIPI, true), +}; + +static unsigned int pu_domain_status; + +void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) +{ + if (domain_id > MIPI) { + return; + } + + struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; + + if (on) { + if (pwr_domain->need_sync) { + pu_domain_status |= (1 << domain_id); + } + + /* HSIOMIX has no PU bit, so skip for it */ + if (domain_id != HSIOMIX) { + /* clear the PGC bit */ + mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); + + /* power up the domain */ + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); + + /* wait for power request done */ + while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { + ; + } + } + + if (domain_id == DISPMIX) { + /* de-reset bus_blk clk and + * enable bus_blk clk + */ + mmio_write_32(0x32e28000, 0x100); + mmio_write_32(0x32e28004, 0x100); + } + + /* handle the ADB400 sync */ + if (pwr_domain->need_sync) { + /* clear adb power down request */ + mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); + + /* wait for adb power request ack */ + while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { + ; + } + } + } else { + pu_domain_status &= ~(1 << domain_id); + + if (domain_id == OTG1) { + return; + } + + /* handle the ADB400 sync */ + if (pwr_domain->need_sync) { + + /* set adb power down request */ + mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); + + /* wait for adb power request ack */ + while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { + ; + } + } + + /* HSIOMIX has no PU bit, so skip for it */ + if (domain_id != HSIOMIX) { + /* set the PGC bit */ + mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); + + /* power down the domain */ + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); + + /* wait for power request done */ + while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) { + ; + } + } + } +} + void imx_gpc_init(void) { unsigned int val; @@ -86,9 +204,4 @@ void imx_gpc_init(void) * only need to do it once. */ mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); - - /* enable all the power domain by default */ - for (i = 0; i < 103; i++) - mmio_write_32(IMX_CCM_BASE + CCGR(i), 0x3); - mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x485); } diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c index 8147792c6..eff198dd7 100644 --- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c +++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c @@ -19,6 +19,7 @@ #include <lib/xlat_tables/xlat_tables_v2.h> #include <plat/common/platform.h> +#include <dram.h> #include <gpc.h> #include <imx_aipstz.h> #include <imx_uart.h> @@ -31,7 +32,9 @@ #define TRUSTY_PARAMS_LEN_BYTES (4096*2) static const mmap_region_t imx_mmap[] = { - GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, {0}, + GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, + CAAM_RAM_MAP, NS_OCRAM_MAP, ROM_MAP, DRAM_MAP, + {0}, }; static const struct aipstz_cfg aipstz[] = { @@ -138,13 +141,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); - imx8m_caam_init(); - console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE, &console); /* This console is only used for boot stage */ console_set_scope(&console, CONSOLE_FLAG_BOOT); + imx8m_caam_init(); + /* * tell BL3-1 where the non-secure software image is located * and the entry state information. @@ -178,25 +181,30 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl31_tzc380_setup(); } +#define MAP_BL31_TOTAL \ + MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) +#define MAP_BL31_RO \ + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) +#define MAP_COHERENT_MEM \ + MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#define MAP_BL32_TOTAL \ + MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) + void bl31_plat_arch_setup(void) { - mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), - MT_MEMORY | MT_RW | MT_SECURE); - mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), - MT_MEMORY | MT_RO | MT_SECURE); + const mmap_region_t bl_regions[] = { + MAP_BL31_TOTAL, + MAP_BL31_RO, #if USE_COHERENT_MEM - mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, - (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), - MT_DEVICE | MT_RW | MT_SECURE); + MAP_COHERENT_MEM, #endif + /* Map TEE memory */ + MAP_BL32_TOTAL, + {0} + }; - /* Map TEE memory */ - mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); - - mmap_add(imx_mmap); - - init_xlat_tables(); - + setup_page_tables(bl_regions, imx_mmap); enable_mmu_el3(0); } @@ -207,6 +215,9 @@ void bl31_platform_setup(void) /* select the CKIL source to 32K OSC */ mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); + /* Init the dram info */ + dram_info_init(SAVED_DRAM_TIMING_BASE); + plat_gic_driver_init(); plat_gic_init(); diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h index 8d39ea6a5..c75e25052 100644 --- a/plat/imx/imx8m/imx8mn/include/platform_def.h +++ b/plat/imx/imx8m/imx8mn/include/platform_def.h @@ -8,6 +8,7 @@ #include <lib/utils_def.h> #include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/common_def.h> #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 @@ -40,7 +41,8 @@ #define PLAT_SDEI_SGI_PRIVATE U(9) #define BL31_BASE U(0x960000) -#define BL31_LIMIT U(0x980000) +#define BL31_SIZE SZ_128K +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) /* non-secure uboot base */ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) @@ -70,7 +72,7 @@ #define IMX_AIPSTZ4 U(0x32df0000) #define IMX_AIPS_BASE U(0x30000000) -#define IMX_AIPS_SIZE U(0xC00000) +#define IMX_AIPS_SIZE U(0x3000000) #define IMX_GPV_BASE U(0x32000000) #define IMX_GPV_SIZE U(0x800000) #define IMX_AIPS1_BASE U(0x30200000) @@ -92,6 +94,13 @@ #define IMX_DDR_IPS_BASE U(0x3d000000) #define IMX_DDR_IPS_SIZE U(0x1800000) #define IMX_ROM_BASE U(0x0) +#define IMX_ROM_SIZE U(0x40000) +#define IMX_NS_OCRAM_BASE U(0x900000) +#define IMX_NS_OCRAM_SIZE U(0x60000) +#define IMX_CAAM_RAM_BASE U(0x100000) +#define IMX_CAAM_RAM_SIZE U(0x10000) +#define IMX_DRAM_BASE U(0x40000000) +#define IMX_DRAM_SIZE U(0xc0000000) #define IMX_GIC_BASE PLAT_GICD_BASE #define IMX_GIC_SIZE U(0x200000) @@ -138,5 +147,16 @@ #define AIPS_MAP MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW) /* AIPS map */ #define OCRAM_S_MAP MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW) /* OCRAM_S */ #define DDRC_MAP MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW) /* DDRMIX */ +#define CAAM_RAM_MAP MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW) /* CAMM RAM */ +#define NS_OCRAM_MAP MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW) /* NS OCRAM */ +#define ROM_MAP MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO) /* ROM code */ + +/* + * Note: DRAM region is mapped with entire size available and uses MT_RW + * attributes. + * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section + * for explanation of this mapping scheme. + */ +#define DRAM_MAP MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS) /* DRAM */ #endif /* platform_def.h */ diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk index 54be41b7d..1c0ad4f3b 100644 --- a/plat/imx/imx8m/imx8mn/platform.mk +++ b/plat/imx/imx8m/imx8mn/platform.mk @@ -13,6 +13,13 @@ include lib/xlat_tables_v2/xlat_tables.mk # Include GICv3 driver files include drivers/arm/gic/v3/gicv3.mk +IMX_DRAM_SOURCES := plat/imx/imx8m/ddr/dram.c \ + plat/imx/imx8m/ddr/clock.c \ + plat/imx/imx8m/ddr/dram_retention.c \ + plat/imx/imx8m/ddr/ddr4_dvfs.c \ + plat/imx/imx8m/ddr/lpddr4_dvfs.c + + IMX_GIC_SOURCES := ${GICV3_SOURCES} \ plat/common/plat_gicv3.c \ plat/common/plat_psci_common.c \ @@ -20,6 +27,7 @@ IMX_GIC_SOURCES := ${GICV3_SOURCES} \ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ plat/imx/imx8m/gpc_common.c \ + plat/imx/imx8m/imx_hab.c \ plat/imx/imx8m/imx_aipstz.c \ plat/imx/imx8m/imx_rdc.c \ plat/imx/imx8m/imx8m_caam.c \ @@ -36,9 +44,11 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ drivers/arm/tzc/tzc380.c \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ + ${IMX_DRAM_SOURCES} \ ${IMX_GIC_SOURCES} \ ${XLAT_TABLES_LIB_SRCS} +ENABLE_PIE := 1 USE_COHERENT_MEM := 1 RESET_TO_BL31 := 1 A53_DISABLE_NON_TEMPORAL_HINT := 0 diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c index 3d68b94a3..452e7883c 100644 --- a/plat/imx/imx8m/imx8mp/gpc.c +++ b/plat/imx/imx8m/imx8mp/gpc.c @@ -170,7 +170,7 @@ static void imx_noc_qos(unsigned int domain_id) } } -static void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) +void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) { struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; unsigned int i; diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c index 57e5c5167..4c31fa28d 100644 --- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c +++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c @@ -19,6 +19,7 @@ #include <lib/xlat_tables/xlat_tables_v2.h> #include <plat/common/platform.h> +#include <dram.h> #include <gpc.h> #include <imx_aipstz.h> #include <imx_uart.h> @@ -32,7 +33,9 @@ static const mmap_region_t imx_mmap[] = { GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, - NOC_MAP, {0}, + NOC_MAP, CAAM_RAM_MAP, NS_OCRAM_MAP, + ROM_MAP, DRAM_MAP, + {0}, }; static const struct aipstz_cfg aipstz[] = { @@ -134,13 +137,13 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); - imx8m_caam_init(); - console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE, &console); /* This console is only used for boot stage */ console_set_scope(&console, CONSOLE_FLAG_BOOT); + imx8m_caam_init(); + /* * tell BL3-1 where the non-secure software image is located * and the entry state information. @@ -174,25 +177,30 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl31_tzc380_setup(); } +#define MAP_BL31_TOTAL \ + MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) +#define MAP_BL31_RO \ + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) +#define MAP_COHERENT_MEM \ + MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#define MAP_BL32_TOTAL \ + MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) + void bl31_plat_arch_setup(void) { - mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), - MT_MEMORY | MT_RW | MT_SECURE); - mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), - MT_MEMORY | MT_RO | MT_SECURE); + const mmap_region_t bl_regions[] = { + MAP_BL31_TOTAL, + MAP_BL31_RO, #if USE_COHERENT_MEM - mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, - (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), - MT_DEVICE | MT_RW | MT_SECURE); + MAP_COHERENT_MEM, #endif + /* Map TEE memory */ + MAP_BL32_TOTAL, + {0} + }; - /* Map TEE memory */ - mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); - - mmap_add(imx_mmap); - - init_xlat_tables(); - + setup_page_tables(bl_regions, imx_mmap); enable_mmu_el3(0); } @@ -203,6 +211,9 @@ void bl31_platform_setup(void) /* select the CKIL source to 32K OSC */ mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); + /* Init the dram info */ + dram_info_init(SAVED_DRAM_TIMING_BASE); + plat_gic_driver_init(); plat_gic_init(); diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h index 8807f5d2d..14cb7099f 100644 --- a/plat/imx/imx8m/imx8mp/include/platform_def.h +++ b/plat/imx/imx8m/imx8mp/include/platform_def.h @@ -9,6 +9,7 @@ #include <common/tbbr/tbbr_img_def.h> #include <lib/utils_def.h> #include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/common_def.h> #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 @@ -37,9 +38,9 @@ #if defined(NEED_BL2) #define BL2_BASE U(0x970000) -#define BL2_LIMIT U(0x990000) +#define BL2_SIZE SZ_128K +#define BL2_LIMIT (BL2_BASE + BL2_SIZE) #define BL31_BASE U(0x950000) -#define BL31_LIMIT U(0x970000) #define IMX_FIP_BASE U(0x40310000) #define IMX_FIP_SIZE U(0x000300000) #define IMX_FIP_LIMIT U(FIP_BASE + FIP_SIZE) @@ -50,9 +51,11 @@ #define PLAT_IMX8MP_BOOT_MMC_BASE U(0x30B50000) /* SD */ #else #define BL31_BASE U(0x970000) -#define BL31_LIMIT U(0x990000) #endif +#define BL31_SIZE SZ_128K +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + #define PLAT_PRI_BITS U(3) #define PLAT_SDEI_CRITICAL_PRI 0x10 #define PLAT_SDEI_NORMAL_PRI 0x20 @@ -111,6 +114,13 @@ #define IMX_DDR_IPS_BASE U(0x3d000000) #define IMX_DDR_IPS_SIZE U(0x1800000) #define IMX_ROM_BASE U(0x0) +#define IMX_ROM_SIZE U(0x40000) +#define IMX_NS_OCRAM_BASE U(0x900000) +#define IMX_NS_OCRAM_SIZE U(0x60000) +#define IMX_CAAM_RAM_BASE U(0x100000) +#define IMX_CAAM_RAM_SIZE U(0x10000) +#define IMX_DRAM_BASE U(0x40000000) +#define IMX_DRAM_SIZE U(0xc0000000) #define IMX_GIC_BASE PLAT_GICD_BASE #define IMX_GIC_SIZE U(0x200000) @@ -178,5 +188,16 @@ #define OCRAM_S_MAP MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_MEMORY | MT_RW) /* OCRAM_S */ #define DDRC_MAP MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW) /* DDRMIX */ #define NOC_MAP MAP_REGION_FLAT(IMX_NOC_BASE, IMX_NOC_SIZE, MT_DEVICE | MT_RW) /* NOC QoS */ +#define CAAM_RAM_MAP MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW) /* CAMM RAM */ +#define NS_OCRAM_MAP MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW) /* NS OCRAM */ +#define ROM_MAP MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO) /* ROM code */ + +/* + * Note: DRAM region is mapped with entire size available and uses MT_RW + * attributes. + * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section + * for explanation of this mapping scheme. + */ +#define DRAM_MAP MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS) /* DRAM */ #endif /* platform_def.h */ diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk index 73fbd872b..5414c0a57 100644 --- a/plat/imx/imx8m/imx8mp/platform.mk +++ b/plat/imx/imx8m/imx8mp/platform.mk @@ -15,6 +15,12 @@ include lib/xlat_tables_v2/xlat_tables.mk # Include GICv3 driver files include drivers/arm/gic/v3/gicv3.mk +IMX_DRAM_SOURCES := plat/imx/imx8m/ddr/dram.c \ + plat/imx/imx8m/ddr/clock.c \ + plat/imx/imx8m/ddr/dram_retention.c \ + plat/imx/imx8m/ddr/ddr4_dvfs.c \ + plat/imx/imx8m/ddr/lpddr4_dvfs.c + IMX_GIC_SOURCES := ${GICV3_SOURCES} \ plat/common/plat_gicv3.c \ plat/common/plat_psci_common.c \ @@ -22,6 +28,7 @@ IMX_GIC_SOURCES := ${GICV3_SOURCES} \ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ plat/imx/imx8m/gpc_common.c \ + plat/imx/imx8m/imx_hab.c \ plat/imx/imx8m/imx_aipstz.c \ plat/imx/imx8m/imx_rdc.c \ plat/imx/imx8m/imx8m_caam.c \ @@ -38,6 +45,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ drivers/arm/tzc/tzc380.c \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ + ${IMX_DRAM_SOURCES} \ ${IMX_GIC_SOURCES} \ ${XLAT_TABLES_LIB_SRCS} @@ -122,15 +130,16 @@ certificates: $(ROT_KEY) $(ROT_KEY): | $(BUILD_PLAT) @echo " OPENSSL $@" @if [ ! -f $(ROT_KEY) ]; then \ - openssl genrsa 2048 > $@ 2>/dev/null; \ + ${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \ fi $(ROTPK_HASH): $(ROT_KEY) @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null endif +ENABLE_PIE := 1 USE_COHERENT_MEM := 1 RESET_TO_BL31 := 1 A53_DISABLE_NON_TEMPORAL_HINT := 0 diff --git a/plat/imx/imx8m/imx8mq/gpc.c b/plat/imx/imx8m/imx8mq/gpc.c index 367c9411d..fa83324e1 100644 --- a/plat/imx/imx8m/imx8mq/gpc.c +++ b/plat/imx/imx8m/imx8mq/gpc.c @@ -9,6 +9,7 @@ #include <stdbool.h> #include <common/debug.h> +#include <drivers/delay_timer.h> #include <lib/mmio.h> #include <lib/psci/psci.h> #include <platform_def.h> @@ -176,6 +177,13 @@ void imx_gpc_init(void) mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); - /* enable all the power domain by default */ - mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf); + /* + * for USB OTG, the limitation are: + * 1. before system clock config, the IPG clock run at 12.5MHz, delay time + * should be longer than 82us. + * 2. after system clock config, ipg clock run at 66.5MHz, delay time + * be longer that 15.3 us. + * Add 100us to make sure the USB OTG SRC is clear safely. + */ + udelay(100); } diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c index e998a165c..59c3779ab 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c @@ -132,14 +132,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, imx_aipstz_init(aipstz); - imx8m_caam_init(); - #if DEBUG_CONSOLE static console_t console; console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE, &console); #endif + + imx8m_caam_init(); + /* * tell BL3-1 where the non-secure software image is located * and the entry state information. diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h index a76e89529..1dd22d952 100644 --- a/plat/imx/imx8m/imx8mq/include/platform_def.h +++ b/plat/imx/imx8m/imx8mq/include/platform_def.h @@ -126,7 +126,7 @@ #define OCRAM_S_SIZE U(0x8000) #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) -#define COUNTER_FREQUENCY 8000000 /* 8MHz */ +#define COUNTER_FREQUENCY 8333333 /* 25MHz / 3 */ #define DEBUG_CONSOLE 0 #define IMX_WDOG_B_RESET diff --git a/plat/imx/imx8m/imx_hab.c b/plat/imx/imx8m/imx_hab.c new file mode 100644 index 000000000..222046fb9 --- /dev/null +++ b/plat/imx/imx8m/imx_hab.c @@ -0,0 +1,124 @@ +/* + * Copyright 2017-2020 NXP + * Copyright 2022 Leica Geosystems AG + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/runtime_svc.h> +#include <imx_sip_svc.h> + +#define HAB_CID_ATF U(2) /* TF-A Caller ID */ + +/* HAB Status definitions */ +enum hab_status { + HAB_STS_ANY = 0x00, /* Match any status in report_event() */ + HAB_FAILURE = 0x33, /* Operation failed */ + HAB_WARNING = 0x69, /* Operation completed with warning */ + HAB_SUCCESS = 0xf0 /* Operation completed successfully */ +}; + +/* HAB Configuration definitions */ +enum hab_config { + HAB_CFG_RETURN = 0x33, /* Field Return IC */ + HAB_CFG_OPEN = 0xf0, /* Non-secure IC */ + HAB_CFG_CLOSED = 0xcc /* Secure IC */ +}; + +/* HAB State definitions */ +enum hab_state { + HAB_STATE_INITIAL = 0x33, /* Initializing state (transitory) */ + HAB_STATE_CHECK = 0x55, /* Check state (non-secure) */ + HAB_STATE_NONSECURE = 0x66, /* Non-secure state */ + HAB_STATE_TRUSTED = 0x99, /* Trusted state */ + HAB_STATE_SECURE = 0xaa, /* Secure state */ + HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */ + HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */ + HAB_STATE_NONE = 0xf0 /* No security state machine */ +}; + +/* HAB Verification Target definitions */ +enum hab_target { + HAB_TGT_MEMORY = 0x0f, /* Check memory allowed list */ + HAB_TGT_PERIPHERAL = 0xf0, /* Check peripheral allowed list */ + HAB_TGT_ANY = 0x55 /* Check memory & peripheral allowed list */ +}; + +/* Authenticate Image Loader Callback prototype */ +typedef enum hab_status hab_loader_callback_f_t(void **, size_t *, const void *); + +/* + * HAB Rom VectorTable (RVT) structure. + * This table provides function pointers into the HAB library in ROM for + * use by post-ROM boot sequence components. + * Functions are ordered in the structure below based on the offsets in ROM + * image, and shall not be changed! + * Details on API allocation offsets and function description could be + * found in following documents from NXP: + * - High Assurance Boot Version 4 Application Programming Interface + * Reference Manual (available in CST package) + * - HABv4 RVT Guidelines and Recommendations (AN12263) + */ +struct hab_rvt_api { + uint64_t hdr; + enum hab_status (*entry)(void); + enum hab_status (*exit)(void); + enum hab_status (*check_target)(enum hab_target type, const void *start, size_t bytes); + void* (*authenticate_image)(uint8_t cid, long ivt_offset, void **start, + size_t *bytes, hab_loader_callback_f_t loader); + enum hab_status (*run_dcd)(const uint8_t *dcd); + enum hab_status (*run_csf)(const uint8_t *csf, uint8_t cid, uint32_t srkmask); + enum hab_status (*assert)(long type, const void *data, uint32_t count); + enum hab_status (*report_event)(enum hab_status status, uint32_t index, + uint8_t *event, size_t *bytes); + enum hab_status (*report_status)(enum hab_config *config, enum hab_state *state); + void (*failsafe)(void); + void* (*authenticate_image_no_dcd)(uint8_t cid, long ivt_offset, void **start, + size_t *bytes, hab_loader_callback_f_t loader); + uint32_t (*get_version)(void); + enum hab_status (*authenticate_container)(uint8_t cid, long ivt_offset, void **start, + size_t *bytes, hab_loader_callback_f_t loader, uint32_t srkmask, int skip_dcd); +}; + +struct hab_rvt_api *g_hab_rvt_api = (struct hab_rvt_api *)HAB_RVT_BASE; + +/******************************************************************************* + * Handler for servicing HAB SMC calls + ******************************************************************************/ +int imx_hab_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4) +{ + switch (x1) { + case IMX_SIP_HAB_ENTRY: + return g_hab_rvt_api->entry(); + case IMX_SIP_HAB_EXIT: + return g_hab_rvt_api->exit(); + case IMX_SIP_HAB_CHECK_TARGET: + return g_hab_rvt_api->check_target((enum hab_target)x2, + (const void *)x3, (size_t)x4); + case IMX_SIP_HAB_AUTH_IMG: + return (unsigned long)g_hab_rvt_api->authenticate_image(HAB_CID_ATF, + x2, (void **)x3, (size_t *)x4, NULL); + case IMX_SIP_HAB_REPORT_EVENT: + return g_hab_rvt_api->report_event(HAB_FAILURE, + (uint32_t)x2, (uint8_t *)x3, (size_t *)x4); + case IMX_SIP_HAB_REPORT_STATUS: + return g_hab_rvt_api->report_status((enum hab_config *)x2, + (enum hab_state *)x3); + case IMX_SIP_HAB_FAILSAFE: + g_hab_rvt_api->failsafe(); + break; + case IMX_SIP_HAB_AUTH_IMG_NO_DCD: + return (unsigned long)g_hab_rvt_api->authenticate_image_no_dcd( + HAB_CID_ATF, x2, (void **)x3, (size_t *)x4, NULL); + case IMX_SIP_HAB_GET_VERSION: + return g_hab_rvt_api->get_version(); + default: + return SMC_UNK; + }; + + return SMC_OK; +} diff --git a/plat/imx/imx8m/include/ddrc.h b/plat/imx/imx8m/include/ddrc.h new file mode 100644 index 000000000..55af3ff0c --- /dev/null +++ b/plat/imx/imx8m/include/ddrc.h @@ -0,0 +1,336 @@ +/* + * Copyright 2019-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX_DDRC_H +#define IMX_DDRC_H + +#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) +#define DDRC_DDR_SS_GPR0 0x3d000000 + +/* DWC ddr umctl2 REGs offset*/ +/**********************/ +#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) +#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) +#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) +#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) +#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) +#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) +#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) +#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) +#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24) +#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28) +#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) +#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34) +#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38) +#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c) +#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40) +#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50) +#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54) +#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58) +#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) +#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64) +#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70) +#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74) +#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78) +#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c) +#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80) +#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84) +#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88) +#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c) +#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90) +#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94) +#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98) +#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c) +#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0) +#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4) +#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8) +#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac) +#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0) +#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4) +#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8) +#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc) +#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0) +#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4) +#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8) +#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) +#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0) +#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4) +#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8) +#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc) +#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0) +#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4) +#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8) +#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec) +#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0) +#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4) +#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) +#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104) +#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108) +#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c) +#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110) +#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114) +#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118) +#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c) +#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120) +#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124) +#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128) +#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c) +#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130) +#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134) +#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138) +#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C) +#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140) +#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) + +#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180) +#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184) +#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188) +#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c) +#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190) +#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194) +#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198) +#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c) +#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) +#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4) +#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8) +#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) +#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) +#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8) +#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) + +#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0) +#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) +#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0) +#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4) +#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8) +#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc) +#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200) +#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204) +#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208) +#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c) +#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210) +#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214) +#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218) +#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c) +#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220) +#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224) +#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228) +#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c) + +#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240) +#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244) +#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250) +#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254) +#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c) +#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) +#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c) +#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274) + +#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278) + +#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280) +#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284) +#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288) +#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c) +#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290) +#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294) +#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300) +#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) +#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308) +#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c) +#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310) + +#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) +#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) +#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330) +#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334) +#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338) +#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c) +#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340) +#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344) +#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348) +#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c) +#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350) +#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354) +#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358) +#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c) +#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360) +#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364) +#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368) +#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C) +#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370) +#define DDRC_ADVECCINDEX(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ADVECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_HIFCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) + +#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc) +#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400) +#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404) +#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404) +#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404) +#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404) +#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408) +#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408) +#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408) +#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408) +#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c) +#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410) +#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414) +#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) +#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0) +#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0) +#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0) +#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) +#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) +#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c) +#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0) +#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04) +#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08) +#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24) +#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28) +#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) +#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30) +#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34) + +/* SHADOW registers */ +#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020) +#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024) +#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050) +#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064) +#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) +#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0) +#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8) +#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec) +#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100) +#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) +#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108) +#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c) +#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110) +#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) +#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118) +#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c) +#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120) +#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124) +#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128) +#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c) +#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130) +#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134) +#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138) +#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C) +#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140) +#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144) +#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180) +#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020) +#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024) +#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050) +#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064) +#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc) +#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0) +#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) +#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec) +#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100) +#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104) +#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108) +#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c) +#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110) +#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114) +#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118) +#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c) +#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120) +#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124) +#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128) +#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c) +#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130) +#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134) +#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138) +#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C) +#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140) +#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144) +#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180) +#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190) +#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194) +#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4) +#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8) +#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240) + +#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020) +#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024) +#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050) +#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064) +#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc) +#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0) +#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8) +#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec) +#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100) +#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104) +#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108) +#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c) +#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110) +#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114) +#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118) +#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c) +#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120) +#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124) +#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128) +#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c) +#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130) +#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134) +#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138) +#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C) +#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140) + +#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180) +#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190) +#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194) +#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4) +#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8) +#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240) +#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000)) +#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) +#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) +#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) +#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC) +#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20) +#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24) +#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28) +#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C) +#define DRC_PERF_MON_DPCR_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x30) +#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40) +#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44) +#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48) +#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C) +#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50) +#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54) +#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58) +#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C) +#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60) +#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64) +#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68) +#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C) +#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70) +#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74) +#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) +#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) + +#define dwc_ddrphy_apb_rd(addr) mmio_read_32(IMX_DDRPHY_BASE + 4 * (addr)) +#define dwc_ddrphy_apb_wr(addr, val) mmio_write_32(IMX_DDRPHY_BASE + 4 * (addr), val) + +#endif /*IMX_DDRC_H */ diff --git a/plat/imx/imx8m/include/dram.h b/plat/imx/imx8m/include/dram.h new file mode 100644 index 000000000..ad11a2724 --- /dev/null +++ b/plat/imx/imx8m/include/dram.h @@ -0,0 +1,78 @@ +/* + * Copyright 2019-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRAM_H +#define DRAM_H + +#include <assert.h> + +#include <arch_helpers.h> +#include <lib/utils_def.h> + +#include <ddrc.h> +#include <platform_def.h> + +#define DDRC_LPDDR4 BIT(5) +#define DDRC_DDR4 BIT(4) +#define DDRC_DDR3L BIT(0) +#define DDR_TYPE_MASK U(0x3f) +#define ACTIVE_RANK_MASK U(0x3) + +/* reg & config param */ +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_timing_info { + /* umctl2 config */ + struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; + /* ddrphy config */ + struct dram_cfg_param *ddrphy_cfg; + unsigned int ddrphy_cfg_num; + /* ddr fsp train info */ + struct dram_fsp_msg *fsp_msg; + unsigned int fsp_msg_num; + /* ddr phy trained CSR */ + struct dram_cfg_param *ddrphy_trained_csr; + unsigned int ddrphy_trained_csr_num; + /* ddr phy PIE */ + struct dram_cfg_param *ddrphy_pie; + unsigned int ddrphy_pie_num; + /* initialized fsp table */ + unsigned int fsp_table[4]; +}; + +struct dram_info { + int dram_type; + unsigned int num_rank; + uint32_t num_fsp; + int current_fsp; + int boot_fsp; + bool bypass_mode; + struct dram_timing_info *timing_info; + /* mr, emr, emr2, emr3, mr11, mr12, mr22, mr14 */ + uint32_t mr_table[3][8]; +}; + +extern struct dram_info dram_info; + +void dram_info_init(unsigned long dram_timing_base); +void dram_umctl2_init(struct dram_timing_info *timing); +void dram_phy_init(struct dram_timing_info *timing); + +/* dram retention */ +void dram_enter_retention(void); +void dram_exit_retention(void); + +void dram_clock_switch(unsigned int target_drate, bool bypass_mode); + +/* dram frequency change */ +void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, unsigned int fsp_index); +void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate); + +#endif /* DRAM_H */ diff --git a/plat/imx/imx8m/include/gpc.h b/plat/imx/imx8m/include/gpc.h index 29b8ecf93..a41030e5f 100644 --- a/plat/imx/imx8m/include/gpc.h +++ b/plat/imx/imx8m/include/gpc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,5 +69,7 @@ void imx_set_sys_wakeup(unsigned int last_core, bool pdn); void imx_set_sys_lpm(unsigned last_core, bool retention); void imx_set_rbc_count(void); void imx_clear_rbc_count(void); +void imx_anamix_override(bool enter); +void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on); #endif /*IMX8M_GPC_H */ diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index ccb4e071f..a1e58fcca 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -80,5 +80,4 @@ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 -SIMICS_BUILD := 0 USE_COHERENT_MEM := 1 diff --git a/plat/intel/soc/common/bl2_plat_mem_params_desc.c b/plat/intel/soc/common/bl2_plat_mem_params_desc.c index 4f7566567..187c53ac7 100644 --- a/plat/intel/soc/common/bl2_plat_mem_params_desc.c +++ b/plat/intel/soc/common/bl2_plat_mem_params_desc.c @@ -22,58 +22,58 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { #ifdef SCP_BL2_BASE /* Fill SCP_BL2 related information if it exists */ { - .image_id = SCP_BL2_IMAGE_ID, + .image_id = SCP_BL2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = SCP_BL2_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = SCP_BL2_SIZE, - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, }, #endif /* SCP_BL2_BASE */ #ifdef EL3_PAYLOAD_BASE /* Fill EL3 payload related information (BL31 is EL3 payload)*/ { - .image_id = BL31_IMAGE_ID, + .image_id = BL31_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, }, #else /* EL3_PAYLOAD_BASE */ /* Fill BL31 related information */ { - .image_id = BL31_IMAGE_ID, + .image_id = BL31_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, }, #endif /* EL3_PAYLOAD_BASE */ diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index a31adf707..2b3f144ca 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -17,6 +17,7 @@ #define PLAT_SOCFPGA_STRATIX10 1 #define PLAT_SOCFPGA_AGILEX 2 #define PLAT_SOCFPGA_N5X 3 +#define PLAT_SOCFPGA_EMULATOR 0 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ #define PLAT_CPU_RELEASE_ADDR 0xffd12210 @@ -170,14 +171,12 @@ #define CRASH_CONSOLE_BASE PLAT_UART0_BASE #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE -#ifndef SIMICS_BUILD -#define PLAT_BAUDRATE (115200) -#define PLAT_UART_CLOCK (100000000) - -#else +#if PLAT_SOCFPGA_EMULATOR #define PLAT_BAUDRATE (4800) #define PLAT_UART_CLOCK (76800) - +#else +#define PLAT_BAUDRATE (115200) +#define PLAT_UART_CLOCK (100000000) #endif /******************************************************************************* diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c index eacc4dda1..facee0fbd 100644 --- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c +++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c @@ -979,7 +979,7 @@ int intel_fcs_mac_verify_update_finalize(uint32_t session_id, return INTEL_SIP_SMC_STATUS_REJECTED; } - if (data_size >= src_size) { + if (data_size > src_size) { return INTEL_SIP_SMC_STATUS_REJECTED; } diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 778d4af3c..79817e64c 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c @@ -236,7 +236,7 @@ int mailbox_read_response_async(unsigned int *job_id, uint32_t *header, /* copy response data to input buffer if applicable */ ret_resp_len = MBOX_RESP_LEN(mailbox_resp_ctr.payload->header); - if ((ret_resp_len > 0) && (response == NULL) && resp_len) { + if ((ret_resp_len > 0) && (response != NULL) && (resp_len != NULL)) { if (*resp_len > ret_resp_len) { *resp_len = ret_resp_len; } diff --git a/plat/intel/soc/n5x/platform.mk b/plat/intel/soc/n5x/platform.mk index 953bf0caf..be1ad8c6b 100644 --- a/plat/intel/soc/n5x/platform.mk +++ b/plat/intel/soc/n5x/platform.mk @@ -49,5 +49,4 @@ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 -SIMICS_BUILD := 0 USE_COHERENT_MEM := 1 diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 5c0b42146..b7eb4bd77 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -77,5 +77,4 @@ BL31_SOURCES += \ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 -SIMICS_BUILD := 0 USE_COHERENT_MEM := 1 diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk index d0e86886a..b9c28de1a 100644 --- a/plat/marvell/armada/a3k/common/a3700_common.mk +++ b/plat/marvell/armada/a3k/common/a3700_common.mk @@ -62,7 +62,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ $(PLAT_COMMON_BASE)/a3700_sip_svc.c \ $(MARVELL_DRV) -ifeq ($(HANDLE_EA_EL3_FIRST),1) +ifeq ($(HANDLE_EA_EL3_FIRST_NS),1) BL31_SOURCES += $(PLAT_COMMON_BASE)/a3700_ea.c endif @@ -205,12 +205,12 @@ ifeq ($(MARVELL_SECURE_BOOT),1) @$(ECHO_BLANK_LINE) $(Q)cp $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/wtmi-align.bin $(Q)truncate -s %16 $(BUILD_PLAT)/wtmi-align.bin - $(Q)openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/wtmi-align.bin \ + $(Q)${OPENSSL_BIN_PATH}/openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/wtmi-align.bin \ -out $(BUILD_PLAT)/$(WTMI_ENC_IMG) \ -K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \ -iv `cat $(IMAGESPATH)/iv.txt` -p $(Q)truncate -s %16 $(BUILD_PLAT)/$(BOOT_IMAGE); - $(Q)openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \ + $(Q)${OPENSSL_BIN_PATH}/openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \ -out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \ -K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \ -iv `cat $(IMAGESPATH)/iv.txt` -p diff --git a/plat/marvell/armada/a3k/common/a3700_ea.c b/plat/marvell/armada/a3k/common/a3700_ea.c index bc12845a5..5696b5c46 100644 --- a/plat/marvell/armada/a3k/common/a3700_ea.c +++ b/plat/marvell/armada/a3k/common/a3700_ea.c @@ -16,21 +16,9 @@ #define A53_SERR_INT_AXI_SLVERR_ON_EXTERNAL_ACCESS 0xbf000002 -#if !ENABLE_BACKTRACE -static const char *get_el_str(unsigned int el) -{ - if (el == MODE_EL3) { - return "EL3"; - } else if (el == MODE_EL2) { - return "EL2"; - } - return "S-EL1"; -} -#endif /* !ENABLE_BACKTRACE */ - /* * This source file with custom plat_ea_handler function is compiled only when - * building TF-A with compile option HANDLE_EA_EL3_FIRST=1 + * building TF-A with compile option HANDLE_EA_EL3_FIRST_NS=1 */ void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, void *handle, uint64_t flags) diff --git a/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c b/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c index 8d909dc59..6c558586d 100644 --- a/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c +++ b/plat/marvell/armada/common/aarch64/marvell_bl2_mem_params_desc.c @@ -22,84 +22,84 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { #ifdef SCP_BL2_BASE /* Fill SCP_BL2 related information if it exists */ - { - .image_id = SCP_BL2_IMAGE_ID, + { + .image_id = SCP_BL2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, - VERSION_2, image_info_t, 0), - .image_info.image_base = SCP_BL2_BASE, - .image_info.image_max_size = SCP_BL2_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = SCP_BL2_SIZE, - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #endif /* SCP_BL2_BASE */ #ifdef EL3_PAYLOAD_BASE /* Fill EL3 payload related information (BL31 is EL3 payload)*/ - { - .image_id = BL31_IMAGE_ID, + { + .image_id = BL31_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = EL3_PAYLOAD_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), - .next_handoff_image_id = INVALID_IMAGE_ID, - }, + .next_handoff_image_id = INVALID_IMAGE_ID, + }, #else /* EL3_PAYLOAD_BASE */ /* Fill BL31 related information */ - { - .image_id = BL31_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - .ep_info.pc = BL31_BASE, - .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS), + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), #if DEBUG - .ep_info.args.arg3 = MARVELL_BL31_PLAT_PARAM_VAL, + .ep_info.args.arg3 = MARVELL_BL31_PLAT_PARAM_VAL, #endif - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), - .image_info.image_base = BL31_BASE, - .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, # ifdef BL32_BASE - .next_handoff_image_id = BL32_IMAGE_ID, + .next_handoff_image_id = BL32_IMAGE_ID, # else - .next_handoff_image_id = BL33_IMAGE_ID, + .next_handoff_image_id = BL33_IMAGE_ID, # endif - }, + }, # ifdef BL32_BASE /* Fill BL32 related information */ - { - .image_id = BL32_IMAGE_ID, + { + .image_id = BL32_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), - .ep_info.pc = BL32_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = BL33_IMAGE_ID, - }, + .next_handoff_image_id = BL33_IMAGE_ID, + }, /* * Fill BL32 external 1 related information. @@ -107,17 +107,17 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { * where it is the pager image. */ { - .image_id = BL32_EXTRA1_IMAGE_ID, + .image_id = BL32_EXTRA1_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), - .image_info.image_base = BL32_BASE, - .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, }, /* @@ -126,42 +126,42 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { * where it is the paged image. */ { - .image_id = BL32_EXTRA2_IMAGE_ID, + .image_id = BL32_EXTRA2_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), #ifdef SPD_opteed - .image_info.image_base = MARVELL_OPTEE_PAGEABLE_LOAD_BASE, - .image_info.image_max_size = MARVELL_OPTEE_PAGEABLE_LOAD_SIZE, + .image_info.image_base = MARVELL_OPTEE_PAGEABLE_LOAD_BASE, + .image_info.image_max_size = MARVELL_OPTEE_PAGEABLE_LOAD_SIZE, #endif - .next_handoff_image_id = INVALID_IMAGE_ID, + .next_handoff_image_id = INVALID_IMAGE_ID, }, # endif /* BL32_BASE */ /* Fill BL33 related information */ - { - .image_id = BL33_IMAGE_ID, - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), # ifdef PRELOADED_BL33_BASE - .ep_info.pc = PRELOADED_BL33_BASE, + .ep_info.pc = PRELOADED_BL33_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), # else - .ep_info.pc = MARVELL_DRAM_BASE, + .ep_info.pc = MARVELL_DRAM_BASE, - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0), - .image_info.image_base = MARVELL_DRAM_BASE, - .image_info.image_max_size = MARVELL_DRAM_SIZE, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = MARVELL_DRAM_BASE, + .image_info.image_max_size = MARVELL_DRAM_SIZE, # endif /* PRELOADED_BL33_BASE */ - .next_handoff_image_id = INVALID_IMAGE_ID, - } + .next_handoff_image_id = INVALID_IMAGE_ID, + } #endif /* EL3_PAYLOAD_BASE */ }; diff --git a/plat/mediatek/build_helpers/mtk_build_helpers.mk b/plat/mediatek/build_helpers/mtk_build_helpers.mk index 47d96faed..fc3876e71 100644 --- a/plat/mediatek/build_helpers/mtk_build_helpers.mk +++ b/plat/mediatek/build_helpers/mtk_build_helpers.mk @@ -116,20 +116,23 @@ endef # Include MTK configuration files # MTK makefile variables +ifeq (${COREBOOT},1) +MTK_COMMON_CFG := $(MTK_PLAT)/common/coreboot_config.mk +else +MTK_COMMON_CFG := $(MTK_PLAT)/common/common_config.mk +endif MTK_PLAT := plat/mediatek MTK_PLAT_SOC := ${MTK_PLAT}/${MTK_SOC} -MTK_COMMON_CFG := $(MTK_PLAT)/common/common_config.mk MTK_PLAT_CFG := $(MTK_PLAT_SOC)/plat_config.mk MTK_PROJECT_CFG := $(MTK_PLAT)/project/$(PLAT)/project_config.mk MTK_OPTIONS := $(MTK_PLAT)/build_helpers/options.mk MTK_COND_EVAL := $(MTK_PLAT)/build_helpers/conditional_eval_options.mk # Indicate which BL should be built in command line -ifeq (${NEED_BL31},yes) -MTK_BL := bl31 -endif ifeq (${NEED_BL32},yes) MTK_BL := bl32 +else +MTK_BL := bl31 endif # Include common, platform, board level config include $(MTK_COMMON_CFG) diff --git a/plat/mediatek/build_helpers/options.mk b/plat/mediatek/build_helpers/options.mk index 394a605ee..027964809 100644 --- a/plat/mediatek/build_helpers/options.mk +++ b/plat/mediatek/build_helpers/options.mk @@ -6,12 +6,20 @@ # call add_defined_option to evaluate MTK defined value $(eval $(call add_defined_option,MTK_SIP_KERNEL_BOOT_ENABLE)) -$(eval $(call add_defined_option,PLAT_EXTRA_LD_SCRIPT)) +$(eval $(call add_defined_option,PLAT_EXTRA_RODATA_INCLUDES)) $(eval $(call add_defined_option,MTK_EXTRA_LINKERFILE)) $(eval $(call add_defined_option,MTK_BL31_AS_BL2)) $(eval $(call add_defined_option,MTK_BL33_IS_64BIT)) $(eval $(call add_defined_option,PLAT_XLAT_TABLES_DYNAMIC)) $(eval $(call add_defined_option,MTK_ADAPTED)) +$(eval $(call add_defined_option,MTK_PUBEVENT_ENABLE)) $(eval $(call add_defined_option,MTK_SOC)) $(eval $(call add_defined_option,UART_CLOCK)) $(eval $(call add_defined_option,UART_BAUDRATE)) +$(eval $(call add_defined_option,CONFIG_MTK_MCUSYS)) +$(eval $(call add_defined_option,CONFIG_MTK_PM_SUPPORT)) +$(eval $(call add_defined_option,CONFIG_MTK_CPU_PM_SUPPORT)) +$(eval $(call add_defined_option,CONFIG_MTK_SMP_EN)) +$(eval $(call add_defined_option,CONFIG_MTK_CPU_SUSPEND_EN)) +$(eval $(call add_defined_option,CONFIG_MTK_PM_ARCH)) +$(eval $(call add_defined_option,CONFIG_MTK_CPU_PM_ARCH)) diff --git a/plat/mediatek/common/common_config.mk b/plat/mediatek/common/common_config.mk new file mode 100644 index 000000000..851eb2cc4 --- /dev/null +++ b/plat/mediatek/common/common_config.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# indicate the reset vector address can be programmed +PROGRAMMABLE_RESET_ADDRESS := 1 +MULTI_CONSOLE_API := 1 +COLD_BOOT_SINGLE_CPU := 1 +# Build flag to include AArch32 registers in cpu context save and restore during +# world switch. This flag must be set to 0 for AArch64-only platforms. +CTX_INCLUDE_AARCH32_REGS := 0 +PLAT_XLAT_TABLES_DYNAMIC := 1 +# enable this definition to print irq dump status in tf-a +GIC_DEBUG := 0 +# Enable stack protector. +# Allowed values are "all", "strong", "default" and "none" +ENABLE_STACK_PROTECTOR := strong +# AMU, Kernel will access amuserenr_el0 if PE supported +# Firmware _must_ implement AMU support +ENABLE_AMU := 1 +VENDOR_EXTEND_PUBEVENT_ENABLE := 1 + +# MTK define options +MTK_BL33_IS_64BIT := 0 +MTK_ADAPTED := 1 + +# MTK module config +CONFIG_MTK_INTERRUPT := y +CONFIG_MTK_UART := y + +# UART baudrate +UART_BAUDRATE := 921600 diff --git a/plat/mediatek/common/coreboot_config.mk b/plat/mediatek/common/coreboot_config.mk new file mode 100644 index 000000000..59d18e86d --- /dev/null +++ b/plat/mediatek/common/coreboot_config.mk @@ -0,0 +1,15 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# indicate the reset vector address can be programmed +PROGRAMMABLE_RESET_ADDRESS := 1 +COLD_BOOT_SINGLE_CPU := 1 +# Build flag to include AArch32 registers in cpu context save and restore during +# world switch. This flag must be set to 0 for AArch64-only platforms. +CTX_INCLUDE_AARCH32_REGS := 0 +PLAT_XLAT_TABLES_DYNAMIC := 1 + +VENDOR_EXTEND_PUBEVENT_ENABLE := 1 diff --git a/plat/mediatek/common/custom/oem_svc.c b/plat/mediatek/common/custom/oem_svc.c deleted file mode 100644 index 27ee6aa7b..000000000 --- a/plat/mediatek/common/custom/oem_svc.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <stdint.h> - -#include <arch.h> -#include <arch_helpers.h> -#include <common/debug.h> -#include <common/runtime_svc.h> -#include <plat/common/platform.h> -#include <tools_share/uuid.h> - -#include <oem_svc.h> - -/* OEM Service UUID */ -DEFINE_SVC_UUID2(oem_svc_uid, - 0xd0ad43b9, 0x9b06, 0xe411, 0x91, 0x91, - 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66); - -/* Setup OEM Services */ -static int32_t oem_svc_setup(void) -{ - /* - * Invoke related module setup from here - */ - - return 0; -} - -/******************************************************************************* - * OEM top level handler for servicing SMCs. - ******************************************************************************/ -uintptr_t oem_smc_handler(uint32_t smc_fid, - u_register_t x1, - u_register_t x2, - u_register_t x3, - u_register_t x4, - void *cookie, - void *handle, - u_register_t flags) -{ - WARN("Unimplemented OEM Call: 0x%x\n", smc_fid); - SMC_RET1(handle, SMC_UNK); -} - -/* - * Top-level OEM Service SMC handler. This handler will in turn dispatch - * calls to related SMC handler - */ -uintptr_t oem_svc_smc_handler(uint32_t smc_fid, - u_register_t x1, - u_register_t x2, - u_register_t x3, - u_register_t x4, - void *cookie, - void *handle, - u_register_t flags) -{ - /* - * Dispatch OEM calls to OEM Common handler and return its return value - */ - if (is_oem_fid(smc_fid)) { - return oem_smc_handler(smc_fid, x1, x2, x3, x4, cookie, - handle, flags); - } - - switch (smc_fid) { - case OEM_SVC_CALL_COUNT: - /* - * Return the number of OEM Service Calls. - */ - SMC_RET1(handle, OEM_SVC_NUM_CALLS); - - case OEM_SVC_UID: - /* Return UID to the caller */ - SMC_UUID_RET(handle, oem_svc_uid); - - case OEM_SVC_VERSION: - /* Return the version of current implementation */ - SMC_RET2(handle, OEM_VERSION_MAJOR, OEM_VERSION_MINOR); - - default: - WARN("Unimplemented OEM Service Call: 0x%x\n", smc_fid); - SMC_RET1(handle, SMC_UNK); - } -} - -/* Register OEM Service Calls as runtime service */ -DECLARE_RT_SVC( - oem_svc, - OEN_OEM_START, - OEN_OEM_END, - SMC_TYPE_FAST, - oem_svc_setup, - oem_svc_smc_handler -); diff --git a/plat/mediatek/common/custom/oem_svc.h b/plat/mediatek/common/custom/oem_svc.h deleted file mode 100644 index 76f7c24e5..000000000 --- a/plat/mediatek/common/custom/oem_svc.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef OEM_SVC_H -#define OEM_SVC_H - -/******************************************************************************* - * Defines for runtime services func ids - ******************************************************************************/ -/* - * Number of OEM calls (above) implemented. - */ -#define OEM_SVC_NUM_CALLS 3 - -/******************************************************************************* - * Defines for OEM Service queries - ******************************************************************************/ -/* 0x83000000 - 0x8300FEFF is OEM service calls */ -#define OEM_SVC_CALL_COUNT 0x8300ff00 -#define OEM_SVC_UID 0x8300ff01 -/* 0x8300ff02 is reserved */ -#define OEM_SVC_VERSION 0x8300ff03 -/* 0x8300ff04 - 0x8300FFFF is reserved for future expansion */ - -/* OEM Service Calls version numbers */ -#define OEM_VERSION_MAJOR 0x0 -#define OEM_VERSION_MINOR 0x1 - -/* The macros below are used to identify OEM calls from the SMC function ID */ -/* SMC32 ID range from 0x83000000 to 0x83000FFF */ -/* SMC64 ID range from 0xC3000000 to 0xC3000FFF */ -#define OEM_FID_MASK 0xf000u -#define OEM_FID_VALUE 0u -#define is_oem_fid(_fid) \ - (((_fid) & OEM_FID_MASK) == OEM_FID_VALUE) - -#define OEM_SVC_E_SUCCESS 0 -#define OEM_SVC_E_NOT_SUPPORTED -1 -#define OEM_SVC_E_INVALID_PARAMS -2 - -#endif /* OEM_SVC_H */ diff --git a/plat/mediatek/common/lpm/mt_lp_rm.c b/plat/mediatek/common/lpm/mt_lp_rm.c index f3148fe74..0bafc661b 100644 --- a/plat/mediatek/common/lpm/mt_lp_rm.c +++ b/plat/mediatek/common/lpm/mt_lp_rm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/common/lpm/mt_lp_rm.h b/plat/mediatek/common/lpm/mt_lp_rm.h index 39759f1d2..e93dac3d7 100644 --- a/plat/mediatek/common/lpm/mt_lp_rm.h +++ b/plat/mediatek/common/lpm/mt_lp_rm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/common/lpm/rules.mk b/plat/mediatek/common/lpm/rules.mk new file mode 100644 index 000000000..87a212a83 --- /dev/null +++ b/plat/mediatek/common/lpm/rules.mk @@ -0,0 +1,14 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := lpm +LOCAL_SRCS-y := $(LOCAL_DIR)/mt_lp_rm.c + +PLAT_INCLUDES += -I${LOCAL_DIR} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/common/mtk_bl31_setup.c b/plat/mediatek/common/mtk_bl31_setup.c new file mode 100644 index 000000000..7c9db8bb1 --- /dev/null +++ b/plat/mediatek/common/mtk_bl31_setup.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <arch.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <drivers/generic_delay_timer.h> +#if XLAT_TABLES_LIB_V2 && PLAT_XLAT_TABLES_DYNAMIC +#include <lib/xlat_tables/xlat_tables_v2.h> +#endif +#include <plat/common/platform.h> + +#if COREBOOT +#include <common/desc_image_load.h> + +#include <drivers/ti/uart/uart_16550.h> +#include <lib/coreboot.h> +#include <plat_params.h> +#endif + +/* MTK headers */ +#if MTK_SIP_KERNEL_BOOT_ENABLE +#include <cold_boot.h> +#endif +#include <lib/mtk_init/mtk_init.h> +#include <mtk_mmap_pool.h> + +IMPORT_SYM(uintptr_t, __RW_START__, RW_START); +IMPORT_SYM(uintptr_t, __DATA_START__, DATA_START); + +#if COREBOOT +static entry_point_info_t bl32_ep_info; +static entry_point_info_t bl33_ep_info; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; + assert(next_image_info->h.type == PARAM_EP); + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) { + return next_image_info; + } else { + return NULL; + } +} +#else +#ifndef MTK_BL31_AS_BL2 +static struct mtk_bl31_fw_config bl31_fw_config; +#else +struct mtk_bl31_fw_config bl31_fw_config; +#endif +/* In order to be accessed after MMU enable */ +static struct mtk_bl_param_t bl_param_clone; + +void *get_mtk_bl31_fw_config(int index) +{ + void *arg = NULL; + + switch (index) { + case BOOT_ARG_FROM_BL2: + arg = bl31_fw_config.from_bl2; + break; + case BOOT_ARG_SOC_FW_CONFIG: + arg = bl31_fw_config.soc_fw_config; + break; + case BOOT_ARG_HW_CONFIG: + arg = bl31_fw_config.hw_config; + break; + case BOOT_ARG_RESERVED: + arg = bl31_fw_config.reserved; + break; + default: + WARN("Fail to get boot arg, index:%d", index); + break; + } + return arg; +} +#endif +/***************************************************************************** + * Perform the very early platform specific architectural setup shared between + * ARM standard platforms. This only does basic initialization. Later + * architectural setup (bl31_arch_setup()) does not do anything platform + * specific. + ******************************************************************************/ +void bl31_early_platform_setup2(u_register_t from_bl2, + u_register_t soc_fw_config, + u_register_t hw_config, u_register_t plat_params_from_bl2) + +{ +#if COREBOOT + static console_t console; + + params_early_setup(soc_fw_config); + if (coreboot_serial.type) { + console_16550_register(coreboot_serial.baseaddr, + coreboot_serial.input_hertz, + coreboot_serial.baud, + &console); + } + bl31_params_parse_helper(from_bl2, &bl32_ep_info, &bl33_ep_info); +#else + struct mtk_bl_param_t *p_mtk_bl_param = (struct mtk_bl_param_t *)from_bl2; + + if (p_mtk_bl_param == NULL) { + ERROR("from_bl2 should not be NULL\n"); + panic(); + } + memcpy(&bl_param_clone, p_mtk_bl_param, sizeof(struct mtk_bl_param_t)); + bl31_fw_config.from_bl2 = (void *)&bl_param_clone; + bl31_fw_config.soc_fw_config = (void *)soc_fw_config; + bl31_fw_config.hw_config = (void *)hw_config; + bl31_fw_config.reserved = (void *)plat_params_from_bl2; +#endif + + INFO("MTK BL31 start\n"); + /* Init delay function */ + generic_delay_timer_init(); + /* Initialize module initcall */ + mtk_init_one_level(MTK_INIT_LVL_EARLY_PLAT); +} + +void bl31_plat_arch_setup(void) +{ + const mmap_region_t bl_regions[] = { + MAP_BL_RO, + MAP_BL_RW, +#if USE_COHERENT_MEM + MAP_BL_COHERENT_RAM, +#endif + {0}, + }; + + mtk_xlat_init(bl_regions); + /* Initialize module initcall */ + mtk_init_one_level(MTK_INIT_LVL_ARCH); +} + +/***************************************************************************** + * Perform any BL31 platform setup common to ARM standard platforms + ******************************************************************************/ + +void bl31_platform_setup(void) +{ + mtk_init_one_level(MTK_INIT_LVL_PLAT_SETUP_0); + mtk_init_one_level(MTK_INIT_LVL_PLAT_SETUP_1); +} + +/******************************************************************************* + * Operations before cold CPU leave BL31. + * Switch console to runtime state. + ******************************************************************************/ +void bl31_plat_runtime_setup(void) +{ + mtk_init_one_level(MTK_INIT_LVL_PLAT_RUNTIME); + console_switch_state(CONSOLE_FLAG_RUNTIME); +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_HZ; +} diff --git a/plat/mediatek/common/mtk_plat_common.c b/plat/mediatek/common/mtk_plat_common.c index 142b5c999..76f74a95b 100644 --- a/plat/mediatek/common/mtk_plat_common.c +++ b/plat/mediatek/common/mtk_plat_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,8 +19,6 @@ #include <mtk_sip_svc.h> #include <plat_private.h> -struct atf_arg_t gteearg; - void clean_top_32b_of_param(uint32_t smc_fid, u_register_t *px1, u_register_t *px2, @@ -28,7 +26,7 @@ void clean_top_32b_of_param(uint32_t smc_fid, u_register_t *px4) { /* if parameters from SMC32. Clean top 32 bits */ - if (0 == (smc_fid & SMC_AARCH64_BIT)) { + if (GET_SMC_CC(smc_fid) == SMC_64) { *px1 = *px1 & SMC32_PARAM_MASK; *px2 = *px2 & SMC32_PARAM_MASK; *px3 = *px3 & SMC32_PARAM_MASK; @@ -36,89 +34,6 @@ void clean_top_32b_of_param(uint32_t smc_fid, } } -#if MTK_SIP_KERNEL_BOOT_ENABLE -static struct kernel_info k_info; - -static void save_kernel_info(uint64_t pc, - uint64_t r0, - uint64_t r1, - uint64_t k32_64) -{ - k_info.k32_64 = k32_64; - k_info.pc = pc; - - if (LINUX_KERNEL_32 == k32_64) { - /* for 32 bits kernel */ - k_info.r0 = 0; - /* machtype */ - k_info.r1 = r0; - /* tags */ - k_info.r2 = r1; - } else { - /* for 64 bits kernel */ - k_info.r0 = r0; - k_info.r1 = r1; - } -} - -uint64_t get_kernel_info_pc(void) -{ - return k_info.pc; -} - -uint64_t get_kernel_info_r0(void) -{ - return k_info.r0; -} - -uint64_t get_kernel_info_r1(void) -{ - return k_info.r1; -} - -uint64_t get_kernel_info_r2(void) -{ - return k_info.r2; -} - -void boot_to_kernel(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4) -{ - static uint8_t kernel_boot_once_flag; - /* only support in booting flow */ - if (0 == kernel_boot_once_flag) { - kernel_boot_once_flag = 1; - - console_init(gteearg.atf_log_port, - UART_CLOCK, UART_BAUDRATE); - INFO("save kernel info\n"); - save_kernel_info(x1, x2, x3, x4); - bl31_prepare_kernel_entry(x4); - INFO("el3_exit\n"); - console_uninit(); - } -} -#endif - -uint32_t plat_get_spsr_for_bl33_entry(void) -{ - unsigned int mode; - uint32_t spsr; - unsigned int ee; - unsigned long daif; - - INFO("Secondary bootloader is AArch32\n"); - mode = MODE32_svc; - ee = 0; - /* - * TODO: Choose async. exception bits if HYP mode is not - * implemented according to the values of SCR.{AW, FW} bits - */ - daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; - - spsr = SPSR_MODE32(mode, 0, ee, daif); - return spsr; -} - /***************************************************************************** * plat_is_smccc_feature_available() - This function checks whether SMCCC * feature is availabile for platform. diff --git a/plat/mediatek/common/mtk_plat_common.h b/plat/mediatek/common/mtk_plat_common.h index 919c17358..4c14b9d10 100644 --- a/plat/mediatek/common/mtk_plat_common.h +++ b/plat/mediatek/common/mtk_plat_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,45 +14,11 @@ /******************************************************************************* * Function and variable prototypes ******************************************************************************/ -#define DEVINFO_SIZE 4 -#define LINUX_KERNEL_32 0 #define SMC32_PARAM_MASK (0xFFFFFFFF) #define JEDEC_MTK_BKID U(4) #define JEDEC_MTK_MFID U(0x26) -struct atf_arg_t { - unsigned int atf_magic; - unsigned int tee_support; - unsigned int tee_entry; - unsigned int tee_boot_arg_addr; - unsigned int hwuid[4]; /* HW Unique id for t-base used */ - unsigned int HRID[2]; /* HW random id for t-base used */ - unsigned int atf_log_port; - unsigned int atf_log_baudrate; - unsigned int atf_log_buf_start; - unsigned int atf_log_buf_size; - unsigned int atf_irq_num; - unsigned int devinfo[DEVINFO_SIZE]; - unsigned int atf_aee_debug_buf_start; - unsigned int atf_aee_debug_buf_size; -}; - -struct kernel_info { - uint64_t pc; - uint64_t r0; - uint64_t r1; - uint64_t r2; - uint64_t k32_64; -}; - -struct mtk_bl_param_t { - uint64_t bootarg_loc; - uint64_t bootarg_size; - uint64_t bl33_start_addr; - uint64_t tee_info_addr; -}; - struct mtk_bl31_params { param_header_t h; image_info_t *bl31_image_info; diff --git a/plat/mediatek/common/mtk_sip_svc.h b/plat/mediatek/common/mtk_sip_svc.h deleted file mode 100644 index 74b17b645..000000000 --- a/plat/mediatek/common/mtk_sip_svc.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef MTK_SIP_SVC_H -#define MTK_SIP_SVC_H - -#include <stdint.h> - -/* SMC function IDs for SiP Service queries */ -#define SIP_SVC_CALL_COUNT 0x8200ff00 -#define SIP_SVC_UID 0x8200ff01 -/* 0x8200ff02 is reserved */ -#define SIP_SVC_VERSION 0x8200ff03 - -/* Mediatek SiP Service Calls version numbers */ -#define MTK_SIP_SVC_VERSION_MAJOR 0x0 -#define MTK_SIP_SVC_VERSION_MINOR 0x1 - -#define SMC_AARCH64_BIT 0x40000000 - -/* Number of Mediatek SiP Calls implemented */ -#define MTK_COMMON_SIP_NUM_CALLS 4 - -/* Mediatek SiP Service Calls function IDs */ -#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001 - -/* For MTK SMC from Secure OS */ -/* 0x82000000 - 0x820000FF & 0xC2000000 - 0xC20000FF */ -#define MTK_SIP_KERNEL_BOOT_AARCH32 0x82000200 -#define MTK_SIP_KERNEL_BOOT_AARCH64 0xC2000200 - -/* VCORE */ -#define MTK_SIP_VCORE_CONTROL_ARCH32 0x82000506 -#define MTK_SIP_VCORE_CONTROL_ARCH64 0xC2000506 - -/* APUSYS SMC call */ -#define MTK_SIP_APUSYS_CONTROL_AARCH32 0x8200051E -#define MTK_SIP_APUSYS_CONTROL_AARCH64 0xC200051E - -/* Mediatek SiP Calls error code */ -enum { - MTK_SIP_E_SUCCESS = 0, - MTK_SIP_E_INVALID_PARAM = -1, - MTK_SIP_E_NOT_SUPPORTED = -2, - MTK_SIP_E_INVALID_RANGE = -3, - MTK_SIP_E_PERMISSION_DENY = -4, - MTK_SIP_E_LOCK_FAIL = -5 -}; - -/* - * This function should be implemented in Mediatek SOC directory. It fullfills - * MTK_SIP_SET_AUTHORIZED_SECURE_REG SiP call by checking the sreg with the - * predefined secure register list, if a match was found, set val to sreg. - * - * Return MTK_SIP_E_SUCCESS on success, and MTK_SIP_E_INVALID_PARAM on failure. - */ -uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val); - -#endif /* MTK_SIP_SVC_H */ diff --git a/plat/mediatek/common/mtk_smc_handlers.c b/plat/mediatek/common/mtk_smc_handlers.c new file mode 100644 index 000000000..51a960fc3 --- /dev/null +++ b/plat/mediatek/common/mtk_smc_handlers.c @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#if MTK_SIP_KERNEL_BOOT_ENABLE +#include <cold_boot.h> +#endif +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <lib/mtk_init/mtk_init.h> +#include <mtk_sip_svc.h> + +#define SMC_HANDLER_DEBUG(...) VERBOSE(__VA_ARGS__) +#define SMC_HANDLER_DEBUG_NOT_IMP_MSG "%s[0x%x] smc handler not implemented\n" +#define SMC_HANDLER_DEBUG_START_MSG "%s[0x%x] smc handler start, smc desc. index:%d\n" +#define SMC_HANDLER_DEBUG_END_MSG "%s[0x%x] smc handler end\n" + +/* + * These macros below are used to identify SIP calls from Kernel, + * Hypervisor, or 2ndBootloader + */ +#define SIP_FID_ORI_MASK (0xc000) +#define SIP_FID_ORI_SHIFT (14) +#define SIP_FID_KERNEL (0x0) +#define SIP_FID_KERNEL_VIA_GZ (0x1) +#define SIP_FID_GZ (0x2) + +#define GET_SMC_ORI(_fid) (((_fid) & SIP_FID_ORI_MASK) >> SIP_FID_ORI_SHIFT) +#define GET_SMC_ORI_NUM(_fid) ((_fid) & ~(SIP_FID_ORI_MASK)) + +#define is_from_nsel2(_ori) (_ori == SIP_FID_GZ) +#define is_from_bl33(_ori) \ + ((_ori != SIP_FID_GZ) && (is_el1_2nd_bootloader() == 1)) +#define is_from_nsel1(_ori) \ + (((_ori == SIP_FID_KERNEL) || \ + (_ori == SIP_FID_KERNEL_VIA_GZ)) && \ + (is_el1_2nd_bootloader() == 0)) + +#define is_smc_forbidden(_ori) (_ori == SIP_FID_KERNEL_VIA_GZ) + +#define MASK_32_BIT (0xffffffffU) +#define SMC_ID_EXPAND_AS_SMC_OPERATION(_smc_id, _smc_num) \ + case _smc_id##_AARCH32: \ + { \ + x1 = x1 & MASK_32_BIT; \ + x2 = x2 & MASK_32_BIT; \ + x3 = x3 & MASK_32_BIT; \ + x4 = x4 & MASK_32_BIT; \ + } \ + case _smc_id##_AARCH64: \ + { \ + if (_smc_id##_descriptor_index < 0) { \ + SMC_HANDLER_DEBUG(SMC_HANDLER_DEBUG_NOT_IMP_MSG, #_smc_id, smc_id); \ + break; \ + } \ + if (_smc_id##_descriptor_index >= smc_id_descriptor_max) { \ + SMC_HANDLER_DEBUG("smc descriptor index[%d] exceed max[%d]\n", \ + _smc_id##_descriptor_index, smc_id_descriptor_max); \ + break; \ + } \ + SMC_HANDLER_DEBUG(SMC_HANDLER_DEBUG_START_MSG, #_smc_id, smc_id, \ + _smc_id##_descriptor_index); \ + ret = smc_handler_pool[_smc_id##_descriptor_index].smc_handler(x1,\ + x2, x3, x4, handle, &smc_ret); \ + SMC_HANDLER_DEBUG(SMC_HANDLER_DEBUG_END_MSG, #_smc_id, smc_id); \ + break; \ + } + +#define SMC_ID_EXPAND_AS_DESCRIPTOR_INDEX(_smc_id, _smc_num) \ + short _smc_id##_descriptor_index __section("mtk_plat_ro") = -1; + +MTK_SIP_SMC_FROM_BL33_TABLE(SMC_ID_EXPAND_AS_DESCRIPTOR_INDEX); +MTK_SIP_SMC_FROM_NS_EL1_TABLE(SMC_ID_EXPAND_AS_DESCRIPTOR_INDEX); + +IMPORT_SYM(uintptr_t, __MTK_SMC_POOL_START__, MTK_SMC_POOL_START); +IMPORT_SYM(uintptr_t, __MTK_SMC_POOL_END_UNALIGNED__, MTK_SMC_POOL_END_UNALIGNED); + +static const struct smc_descriptor *smc_handler_pool; +static short smc_id_descriptor_max; + +#if !MTK_SIP_KERNEL_BOOT_ENABLE +/* + * If there is no SMC request needs to be served in 2nd bootloader, + * disable the service path inherently. + */ +bool is_el1_2nd_bootloader(void) +{ + return false; +} +#endif + +static void print_smc_descriptor(const struct smc_descriptor pool[]) +{ + const struct smc_descriptor *p_smc_desc; + + INFO("print smc descriptor pool\n"); + for (p_smc_desc = &pool[0]; + (char *)p_smc_desc < (char *)MTK_SMC_POOL_END_UNALIGNED; + p_smc_desc++) { + INFO("descriptor name:%s\n", p_smc_desc->smc_name); + INFO("descriptor index:%d\n", *p_smc_desc->smc_descriptor_index); + INFO("smc id 32:0x%x, smc id 64:0x%x\n", + p_smc_desc->smc_id_aarch32, p_smc_desc->smc_id_aarch64); + } +} + +static int mtk_smc_handler_init(void) +{ + const struct smc_descriptor *iter; + short index_cnt; + int ret = 0; + + smc_handler_pool = (const struct smc_descriptor *)MTK_SMC_POOL_START; + /* Designate descriptor index point to smc_handler_pool */ + for (index_cnt = 0, iter = &smc_handler_pool[0]; + (char *)iter < (char *)MTK_SMC_POOL_END_UNALIGNED; + iter++, index_cnt++) { + if (index_cnt < 0) { + SMC_HANDLER_DEBUG("smc handler pool index overflow!\n"); + ret = -EPERM; + assert(0); + break; + } + *(iter->smc_descriptor_index) = index_cnt; + } + smc_id_descriptor_max = index_cnt; + print_smc_descriptor(smc_handler_pool); + return ret; +} +MTK_EARLY_PLAT_INIT(mtk_smc_handler_init); + +/* This function handles Mediatek defined SiP Calls from Bootloader */ +static uintptr_t mtk_smc_handler_bl33(uint32_t smc_id, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + uintptr_t ret = MTK_SIP_E_SUCCESS; + struct smccc_res smc_ret = {0}; + + switch (smc_id) { + MTK_SIP_SMC_FROM_BL33_TABLE(SMC_ID_EXPAND_AS_SMC_OPERATION); + default: + INFO("BL33 SMC ID:0x%x not supported\n", smc_id); + ret = SMC_UNK; + break; + } + SMC_RET4(handle, ret, smc_ret.a1, smc_ret.a2, smc_ret.a3); +} + +/* This function handles Mediatek defined SiP Calls from Kernel */ +static uintptr_t mtk_smc_handler_nsel1(uint32_t smc_id, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + uintptr_t ret = MTK_SIP_E_SUCCESS; + struct smccc_res smc_ret = {0}; + + switch (smc_id) { + MTK_SIP_SMC_FROM_NS_EL1_TABLE(SMC_ID_EXPAND_AS_SMC_OPERATION); + default: + INFO("NSEL1 SMC ID:0x%x not supported\n", smc_id); + ret = SMC_UNK; + break; + } + SMC_RET4(handle, ret, smc_ret.a1, smc_ret.a2, smc_ret.a3); +} + +static uintptr_t mtk_smc_handler(uint32_t smc_id, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + uintptr_t ret = SMC_UNK; + uint32_t ns; + uint32_t smc_ori; + uint32_t smc_num; + + /* Get SMC Originator bit 14.15 */ + smc_ori = GET_SMC_ORI(smc_id); + /* Get SMC Number. Clean bit 14.15 */ + smc_num = GET_SMC_ORI_NUM(smc_id); + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + + if (ns && is_smc_forbidden(smc_ori)) { + ERROR("%s: Forbidden SMC call (0x%x)\n", __func__, smc_id); + SMC_RET1(handle, ret); + } + + if (!ns) { + /* SiP SMC service secure world's call */ + INFO("Secure SMC ID:0x%x not supported\n", smc_id); + SMC_RET1(handle, ret); + } + if (is_from_bl33(smc_ori)) { + /* SiP SMC service secure bootloader's call */ + return mtk_smc_handler_bl33(smc_num, x1, x2, x3, x4, + cookie, handle, flags); + } else if (is_from_nsel1(smc_ori)) { + /* SiP SMC service kernel's call */ + return mtk_smc_handler_nsel1(smc_num, x1, x2, x3, x4, + cookie, handle, flags); + } + INFO("SMC ID:0x%x not supported\n", smc_id); + SMC_RET1(handle, ret); +} + +/* Define a runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + mtk_smc_handler, + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + mtk_smc_handler +); diff --git a/plat/mediatek/common/rules.mk b/plat/mediatek/common/rules.mk new file mode 100644 index 000000000..6acc731f2 --- /dev/null +++ b/plat/mediatek/common/rules.mk @@ -0,0 +1,15 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := mtk_common + +LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_bl31_setup.c +LOCAL_SRCS-y += ${LOCAL_DIR}/mtk_smc_handlers.c +LOCAL_SRCS-$(MTK_SIP_KERNEL_BOOT_ENABLE) += ${LOCAL_DIR}/cold_boot.c + +$(eval $(call MAKE_LOCALS,$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/audio/audio.c b/plat/mediatek/drivers/audio/audio.c new file mode 100644 index 000000000..285c56511 --- /dev/null +++ b/plat/mediatek/drivers/audio/audio.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <errno.h> +#include <stdbool.h> + +#include <common/debug.h> + +#include <audio.h> + +#include <mtk_sip_svc.h> + +#define MODULE_TAG "[AUDIO]" + +static u_register_t audio_smc_handler(u_register_t x1, u_register_t x2, + u_register_t x3, u_register_t x4, + void *handle, struct smccc_res *smccc_ret) +{ + uint32_t request_ops; + int ret; + + request_ops = (uint32_t)x1; + + switch (request_ops) { + case MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS: + ret = set_audio_domain_sidebands(); + break; + default: + ERROR("%s: %s: Unsupported request_ops %x\n", + MODULE_TAG, __func__, request_ops); + ret = -EIO; + break; + } + + VERBOSE("%s: %s, request_ops = %x, ret = %d\n", + MODULE_TAG, __func__, request_ops, ret); + return ret; +} +/* Register SiP SMC service */ +DECLARE_SMC_HANDLER(MTK_SIP_AUDIO_CONTROL, audio_smc_handler); diff --git a/plat/mediatek/drivers/audio/audio.h b/plat/mediatek/drivers/audio/audio.h new file mode 100644 index 000000000..1598a92d2 --- /dev/null +++ b/plat/mediatek/drivers/audio/audio.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AUDIO_H +#define AUDIO_H + +#include <stdint.h> +#include <lib/mmio.h> + +enum mtk_audio_smc_call_op { + MTK_AUDIO_SMC_OP_INIT = 0, + MTK_AUDIO_SMC_OP_DRAM_REQUEST, + MTK_AUDIO_SMC_OP_DRAM_RELEASE, + MTK_AUDIO_SMC_OP_SRAM_REQUEST, + MTK_AUDIO_SMC_OP_SRAM_RELEASE, + MTK_AUDIO_SMC_OP_ADSP_REQUEST, + MTK_AUDIO_SMC_OP_ADSP_RELEASE, + MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS, + MTK_AUDIO_SMC_OP_BTCVSD_WRITE, + MTK_AUDIO_SMC_OP_BTCVSD_UPDATE_CTRL_CLEAR, + MTK_AUDIO_SMC_OP_BTCVSD_UPDATE_CTRL_UNDERFLOW, + MTK_AUDIO_SMC_OP_NUM, +}; + +int32_t set_audio_domain_sidebands(void); + +#endif /* AUDIO_H */ diff --git a/plat/mediatek/drivers/audio/mt8188/audio_domain.c b/plat/mediatek/drivers/audio/mt8188/audio_domain.c new file mode 100644 index 000000000..cbafd1990 --- /dev/null +++ b/plat/mediatek/drivers/audio/mt8188/audio_domain.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2022, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <errno.h> +#include <common/debug.h> + +#include <audio.h> +#include <mt_audio_private.h> +#include <mtk_mmap_pool.h> +#include <platform_def.h> +#include <spm_reg.h> + +#define MODULE_TAG "[AUDIO_DOMAIN]" + +int32_t set_audio_domain_sidebands(void) +{ + uint32_t val = mmio_read_32(PWR_STATUS); + + if ((val & BIT(SPM_PWR_STATUS_AUDIO_BIT)) == 0) { + ERROR("%s: %s, pwr_status=0x%x, w/o [%d]AUDIO!\n", + MODULE_TAG, __func__, val, SPM_PWR_STATUS_AUDIO_BIT); + return -EIO; + } + + mmio_write_32(AFE_SE_SECURE_CON, 0x0); + + mmio_write_32(AFE_SECURE_SIDEBAND0, 0x0); + mmio_write_32(AFE_SECURE_SIDEBAND1, 0x0); + mmio_write_32(AFE_SECURE_SIDEBAND2, 0x0); + mmio_write_32(AFE_SECURE_SIDEBAND3, 0x0); + + VERBOSE("%s: %s, SE_SECURE_CON=0x%x, SIDEBAND0/1/2/3=0x%x/0x%x/0x%x/0x%x\n", + MODULE_TAG, __func__, + mmio_read_32(AFE_SE_SECURE_CON), + mmio_read_32(AFE_SECURE_SIDEBAND0), + mmio_read_32(AFE_SECURE_SIDEBAND1), + mmio_read_32(AFE_SECURE_SIDEBAND2), + mmio_read_32(AFE_SECURE_SIDEBAND3)); + + return 0; +} diff --git a/plat/mediatek/drivers/audio/mt8188/mt_audio_private.h b/plat/mediatek/drivers/audio/mt8188/mt_audio_private.h new file mode 100644 index 000000000..bcb1abc07 --- /dev/null +++ b/plat/mediatek/drivers/audio/mt8188/mt_audio_private.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_AUDIO_PRIVATE_H +#define MT_AUDIO_PRIVATE_H + +#include <platform_def.h> + +#define AFE_SE_SECURE_CON (AUDIO_BASE + 0x17a8) +#define AFE_SECURE_SIDEBAND0 (AUDIO_BASE + 0x1908) +#define AFE_SECURE_SIDEBAND1 (AUDIO_BASE + 0x190c) +#define AFE_SECURE_SIDEBAND2 (AUDIO_BASE + 0x1910) +#define AFE_SECURE_SIDEBAND3 (AUDIO_BASE + 0x1914) + +#define SPM_PWR_STATUS_AUDIO_BIT (6) + +#endif /* MT_AUDIO_PRIVATE_H */ diff --git a/plat/mediatek/drivers/audio/mt8188/rules.mk b/plat/mediatek/drivers/audio/mt8188/rules.mk new file mode 100644 index 000000000..82acbfc7b --- /dev/null +++ b/plat/mediatek/drivers/audio/mt8188/rules.mk @@ -0,0 +1,13 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := audio_${MTK_SOC} + +LOCAL_SRCS-y := ${LOCAL_DIR}/audio_domain.c + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/audio/rules.mk b/plat/mediatek/drivers/audio/rules.mk new file mode 100644 index 000000000..8538a643b --- /dev/null +++ b/plat/mediatek/drivers/audio/rules.mk @@ -0,0 +1,19 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := audio + +LOCAL_SRCS-y := ${LOCAL_DIR}/audio.c + +PLAT_INCLUDES += -I${LOCAL_DIR} +PLAT_INCLUDES += -I${LOCAL_DIR}/$(MTK_SOC) + +SUB_RULES-y:= ${LOCAL_DIR}/${MTK_SOC} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) +$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y))) diff --git a/plat/mediatek/common/mtk_cirq.c b/plat/mediatek/drivers/cirq/mt_cirq.c index 9cf714449..60534a2d2 100644 --- a/plat/mediatek/common/mtk_cirq.c +++ b/plat/mediatek/drivers/cirq/mt_cirq.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +9,8 @@ #include <drivers/arm/gic_common.h> #include <lib/mmio.h> +#include <mt_cirq.h> #include <mt_gic_v3.h> -#include <mtk_cirq.h> static struct cirq_events cirq_all_events = { .spi_start = CIRQ_SPI_START, diff --git a/plat/mediatek/common/mtk_cirq.h b/plat/mediatek/drivers/cirq/mt_cirq.h index 6e63bb834..cb9629568 100644 --- a/plat/mediatek/common/mtk_cirq.h +++ b/plat/mediatek/drivers/cirq/mt_cirq.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/drivers/cirq/rules.mk b/plat/mediatek/drivers/cirq/rules.mk new file mode 100644 index 000000000..710eae0f1 --- /dev/null +++ b/plat/mediatek/drivers/cirq/rules.mk @@ -0,0 +1,14 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := cirq +LOCAL_SRCS-y := $(LOCAL_DIR)/mt_cirq.c + +PLAT_INCLUDES += -I${LOCAL_DIR} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c new file mode 100644 index 000000000..313ad470f --- /dev/null +++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.c @@ -0,0 +1,466 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <stdint.h> + +#include <lib/spinlock.h> + +#include <lib/mtk_init/mtk_init.h> +#include <lib/pm/mtk_pm.h> +#include "mt_cpu_pm.h" +#include "mt_cpu_pm_cpc.h" +#include "mt_cpu_pm_mbox.h" +#include <mt_lp_rm.h> +#include "mt_smp.h" +#include <mtk_mmap_pool.h> +#include <platform_def.h> + +/* + * The locker must use the bakery locker when cache turns off. + * Using spin_lock will gain better performance. + */ +#ifdef MT_CPU_PM_USING_BAKERY_LOCK +DEFINE_BAKERY_LOCK(mt_cpu_pm_lock); +#define plat_cpu_pm_lock_init() bakery_lock_init(&mt_cpu_pm_lock) +#define plat_cpu_pm_lock() bakery_lock_get(&mt_cpu_pm_lock) +#define plat_cpu_pm_unlock() bakery_lock_release(&mt_cpu_pm_lock) +#else +spinlock_t mt_cpu_pm_lock; +#define plat_cpu_pm_lock_init() +#define plat_cpu_pm_lock() spin_lock(&mt_cpu_pm_lock) +#define plat_cpu_pm_unlock() spin_unlock(&mt_cpu_pm_lock) +#endif + +enum mt_pwr_node { + MT_PWR_NONMCUSYS = 0, + MT_PWR_MCUSYS_PDN, + MT_PWR_SUSPEND, + MT_PWR_SYSTEM_MEM, + MT_PWR_SYSTEM_PLL, + MT_PWR_SYSTEM_BUS, + MT_PWR_MAX, +}; + +#define CPU_PM_DEPD_INIT BIT(0) +#define CPU_PM_DEPD_READY BIT(1) +#define CPU_PM_PLAT_READY BIT(2) + +#ifdef CPU_PM_TINYSYS_SUPPORT +#define CPU_PM_INIT_READY (CPU_PM_DEPD_INIT | CPU_PM_DEPD_READY) +#define CPU_PM_LP_READY (CPU_PM_INIT_READY | CPU_PM_PLAT_READY) +#else +#define CPU_PM_LP_READY (CPU_PM_PLAT_READY) +#endif + +#if CONFIG_MTK_PM_SUPPORT + +#if CONFIG_MTK_CPU_SUSPEND_EN || CONFIG_MTK_SMP_EN +static void cpupm_cpu_resume_common(const struct mtk_cpupm_pwrstate *state) +{ + CPU_PM_ASSERT(state != NULL); + mtk_cpc_core_on_hint_clr(state->info.cpuid); +} +#endif + +#if CONFIG_MTK_SMP_EN +static int cpupm_cpu_pwr_on_prepare(unsigned int cpu, uintptr_t entry) +{ + struct cpu_pwr_ctrl pwr_ctrl; + + PER_CPU_PWR_CTRL(pwr_ctrl, cpu); + mt_smp_core_bootup_address_set(&pwr_ctrl, entry); + mt_smp_core_init_arch(0, cpu, 1, &pwr_ctrl); + + return mt_smp_power_core_on(cpu, &pwr_ctrl); +} + +static void cpupm_cpu_resume_smp(const struct mtk_cpupm_pwrstate *state) +{ + CPU_PM_ASSERT(state != NULL); + + plat_cpu_pm_lock(); + mmio_clrbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, + GIC_WAKEUP_IGNORE(state->info.cpuid)); + plat_cpu_pm_unlock(); + cpupm_cpu_resume_common(state); +} + +static void cpupm_cpu_suspend_smp(const struct mtk_cpupm_pwrstate *state) +{ + struct cpu_pwr_ctrl pwr_ctrl; + + CPU_PM_ASSERT(state != NULL); + + PER_CPU_PWR_CTRL(pwr_ctrl, state->info.cpuid); + mt_smp_power_core_off(&pwr_ctrl); + mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, + GIC_WAKEUP_IGNORE(state->info.cpuid)); +} + +static void cpupm_smp_init(unsigned int cpu, uintptr_t sec_entrypoint) +{ + unsigned int reg; + struct mtk_cpupm_pwrstate state = { + .info = { + .cpuid = cpu, + .mode = MTK_CPU_PM_SMP, + }, + .pwr = { + .afflv = 0, + .state_id = 0, + }, + }; + + reg = mmio_read_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG); + if ((reg & CPC_MCUSYS_CPC_RESET_PWR_ON_EN) != 0) { + INFO("[%s:%d][CPU_PM] reset pwr on is enabled then clear it!\n", + __func__, __LINE__); + mmio_clrbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_MCUSYS_CPC_RESET_PWR_ON_EN); + } + + cpupm_cpu_pwr_on_prepare(cpu, sec_entrypoint); + cpupm_cpu_resume_smp(&state); +} + +static struct mtk_cpu_smp_ops cpcv3_2_cpu_smp = { + .init = cpupm_smp_init, + .cpu_pwr_on_prepare = cpupm_cpu_pwr_on_prepare, + .cpu_on = cpupm_cpu_resume_smp, + .cpu_off = cpupm_cpu_suspend_smp, +}; + +#endif /* CONFIG_MTK_SMP_EN */ + +#if CONFIG_MTK_CPU_SUSPEND_EN +#define CPUPM_READY_MS (40000) +#define CPUPM_ARCH_TIME_MS(ms) (ms * 1000 * SYS_COUNTER_FREQ_IN_MHZ) +#define CPUPM_BOOTUP_TIME_THR CPUPM_ARCH_TIME_MS(CPUPM_READY_MS) + +static int mt_pwr_nodes[MT_PWR_MAX]; +static int plat_mt_lp_cpu_rc; +static unsigned int cpu_pm_status; +static unsigned int plat_prev_stateid; + +static int mcusys_prepare_suspend(const struct mtk_cpupm_pwrstate *state) +{ + unsigned int stateid = state->pwr.state_id; + + if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) { + goto mt_pwr_mcusysoff_break; + } + + if (!IS_PLAT_SUSPEND_ID(stateid)) { + if (mt_pwr_nodes[MT_PWR_SYSTEM_MEM] != 0) { + stateid = MT_PLAT_PWR_STATE_SYSTEM_MEM; + } else if (mt_pwr_nodes[MT_PWR_SYSTEM_PLL] != 0) { + stateid = MT_PLAT_PWR_STATE_SYSTEM_PLL; + } else if (mt_pwr_nodes[MT_PWR_SYSTEM_BUS] != 0) { + stateid = MT_PLAT_PWR_STATE_SYSTEM_BUS; + } else if (mt_pwr_nodes[MT_PWR_SUSPEND] != 0) { + stateid = MT_PLAT_PWR_STATE_SUSPEND; + } else { + stateid = MT_PLAT_PWR_STATE_MCUSYS; + } + } + + plat_prev_stateid = stateid; + plat_mt_lp_cpu_rc = mt_lp_rm_find_and_run_constraint(0, state->info.cpuid, stateid, NULL); + + if (plat_mt_lp_cpu_rc < 0) { + goto mt_pwr_mcusysoff_reflect; + } + +#ifdef CPU_PM_TINYSYS_SUPPORT + mtk_set_cpu_pm_preffered_cpu(state->info.cpuid); +#endif + return MTK_CPUPM_E_OK; + +mt_pwr_mcusysoff_reflect: + mtk_cpc_mcusys_off_reflect(); +mt_pwr_mcusysoff_break: + plat_mt_lp_cpu_rc = -1; + + return MTK_CPUPM_E_FAIL; +} + +static int mcusys_prepare_resume(const struct mtk_cpupm_pwrstate *state) +{ + if (plat_mt_lp_cpu_rc < 0) { + return MTK_CPUPM_E_FAIL; + } + + mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, state->info.cpuid, plat_prev_stateid); + mtk_cpc_mcusys_off_reflect(); + return MTK_CPUPM_E_OK; +} + +static unsigned int cpupm_do_pstate_off(const mtk_pstate_type psci_state, + const struct mtk_cpupm_pwrstate *state) +{ + unsigned int pstate = MT_CPUPM_PWR_DOMAIN_CORE; + + if (!state || (state->pwr.afflv > PLAT_MAX_PWR_LVL)) { + CPU_PM_ASSERT(0); + } + + switch (state->pwr.state_id) { + case MT_PLAT_PWR_STATE_SYSTEM_MEM: + mt_pwr_nodes[MT_PWR_SYSTEM_MEM] += 1; + break; + case MT_PLAT_PWR_STATE_SYSTEM_PLL: + mt_pwr_nodes[MT_PWR_SYSTEM_PLL] += 1; + break; + case MT_PLAT_PWR_STATE_SYSTEM_BUS: + mt_pwr_nodes[MT_PWR_SYSTEM_BUS] += 1; + break; + case MT_PLAT_PWR_STATE_SUSPEND: + mt_pwr_nodes[MT_PWR_SUSPEND] += 1; + break; + default: + if (!IS_MT_PLAT_PWR_STATE_MCUSYS(state->pwr.state_id) && + !IS_PLAT_SYSTEM_SUSPEND(state->pwr.afflv)) { + plat_cpu_pm_lock(); + mt_pwr_nodes[MT_PWR_NONMCUSYS] += 1; + flush_dcache_range((uintptr_t)&mt_pwr_nodes[MT_PWR_NONMCUSYS], + sizeof(mt_pwr_nodes[MT_PWR_NONMCUSYS])); + plat_cpu_pm_unlock(); + } + break; + } + + if ((mt_pwr_nodes[MT_PWR_NONMCUSYS] == 0) && IS_PLAT_MCUSYSOFF_AFFLV(state->pwr.afflv)) { + /* Prepare to power down mcusys */ + if (mcusys_prepare_suspend(state) == MTK_CPUPM_E_OK) { + mt_pwr_nodes[MT_PWR_MCUSYS_PDN] += 1; + flush_dcache_range((uintptr_t)&mt_pwr_nodes[MT_PWR_MCUSYS_PDN], + sizeof(mt_pwr_nodes[MT_PWR_MCUSYS_PDN])); + pstate |= (MT_CPUPM_PWR_DOMAIN_MCUSYS | MT_CPUPM_PWR_DOMAIN_CLUSTER); + } + } + + if (state->pwr.afflv >= PLAT_MT_CPU_SUSPEND_CLUSTER) { + pstate |= MT_CPUPM_PWR_DOMAIN_CLUSTER; + } + + if (psci_get_pstate_pwrlvl(psci_state) >= PLAT_MT_CPU_SUSPEND_CLUSTER) { + pstate |= MT_CPUPM_PWR_DOMAIN_PERCORE_DSU; + } + + return pstate; +} + +static unsigned int cpupm_do_pstate_on(const mtk_pstate_type psci_state, + const struct mtk_cpupm_pwrstate *state) +{ + unsigned int pstate = MT_CPUPM_PWR_DOMAIN_CORE; + + CPU_PM_ASSERT(state != NULL); + + if (state->pwr.afflv > PLAT_MAX_PWR_LVL) { + CPU_PM_ASSERT(0); + } + + if (mt_pwr_nodes[MT_PWR_MCUSYS_PDN] != 0) { + mt_pwr_nodes[MT_PWR_MCUSYS_PDN] = 0; + flush_dcache_range((uintptr_t)&mt_pwr_nodes[MT_PWR_MCUSYS_PDN], + sizeof(mt_pwr_nodes[MT_PWR_MCUSYS_PDN])); + pstate |= (MT_CPUPM_PWR_DOMAIN_MCUSYS | MT_CPUPM_PWR_DOMAIN_CLUSTER); + mcusys_prepare_resume(state); + } + + if (state->pwr.afflv >= PLAT_MT_CPU_SUSPEND_CLUSTER) { + pstate |= MT_CPUPM_PWR_DOMAIN_CLUSTER; + } + + switch (state->pwr.state_id) { + case MT_PLAT_PWR_STATE_SYSTEM_MEM: + mt_pwr_nodes[MT_PWR_SYSTEM_MEM] -= 1; + CPU_PM_ASSERT(mt_pwr_nodes[MT_PWR_SYSTEM_MEM] >= 0); + break; + case MT_PLAT_PWR_STATE_SYSTEM_PLL: + mt_pwr_nodes[MT_PWR_SYSTEM_PLL] -= 1; + CPU_PM_ASSERT(mt_pwr_nodes[MT_PWR_SYSTEM_PLL] >= 0); + break; + case MT_PLAT_PWR_STATE_SYSTEM_BUS: + mt_pwr_nodes[MT_PWR_SYSTEM_BUS] -= 1; + CPU_PM_ASSERT(mt_pwr_nodes[MT_PWR_SYSTEM_BUS] >= 0); + break; + case MT_PLAT_PWR_STATE_SUSPEND: + mt_pwr_nodes[MT_PWR_SUSPEND] -= 1; + CPU_PM_ASSERT(mt_pwr_nodes[MT_PWR_SUSPEND] >= 0); + break; + default: + if (!IS_MT_PLAT_PWR_STATE_MCUSYS(state->pwr.state_id) && + !IS_PLAT_SYSTEM_SUSPEND(state->pwr.afflv)) { + plat_cpu_pm_lock(); + mt_pwr_nodes[MT_PWR_NONMCUSYS] -= 1; + flush_dcache_range((uintptr_t)&mt_pwr_nodes[MT_PWR_NONMCUSYS], + sizeof(mt_pwr_nodes[MT_PWR_NONMCUSYS])); + plat_cpu_pm_unlock(); + } + break; + } + + if (IS_PLAT_SYSTEM_SUSPEND(state->pwr.afflv) || + (IS_PLAT_SYSTEM_RETENTION(state->pwr.afflv) && (mt_pwr_nodes[MT_PWR_SUSPEND] > 0))) { + mtk_cpc_time_sync(); + } + + if (mt_pwr_nodes[MT_PWR_NONMCUSYS] < 0) { + CPU_PM_ASSERT(0); + } + + pstate |= MT_CPUPM_PWR_DOMAIN_PERCORE_DSU; + + return pstate; +} + +static void cpupm_cpu_resume(const struct mtk_cpupm_pwrstate *state) +{ + cpupm_cpu_resume_common(state); +} + +static void cpupm_mcusys_resume(const struct mtk_cpupm_pwrstate *state) +{ + assert(state != NULL); +} + +static void cpupm_mcusys_suspend(const struct mtk_cpupm_pwrstate *state) +{ + assert(state != NULL); +} + +static unsigned int cpupm_get_pstate(enum mt_cpupm_pwr_domain domain, + const mtk_pstate_type psci_state, + const struct mtk_cpupm_pwrstate *state) +{ + unsigned int pstate = 0; + + if (state == NULL) { + return 0; + } + + if (state->info.mode == MTK_CPU_PM_SMP) { + pstate = MT_CPUPM_PWR_DOMAIN_CORE; + } else { + if (domain == CPUPM_PWR_OFF) { + pstate = cpupm_do_pstate_off(psci_state, state); + } else if (domain == CPUPM_PWR_ON) { + pstate = cpupm_do_pstate_on(psci_state, state); + } else { + INFO("[%s:%d][CPU_PM] unknown pwr domain :%d\n", + __func__, __LINE__, domain); + assert(0); + } + } + return pstate; +} + +static int cpupm_init(void) +{ + int ret = MTK_CPUPM_E_OK; + +#ifdef CPU_PM_TINYSYS_SUPPORT + int status; + + if ((cpu_pm_status & CPU_PM_INIT_READY) == CPU_PM_INIT_READY) { + return MTK_CPUPM_E_OK; + } + + if (!(cpu_pm_status & CPU_PM_DEPD_INIT)) { + status = mtk_lp_depd_condition(CPUPM_MBOX_WAIT_DEV_INIT); + if (status == 0) { + plat_cpu_pm_lock(); + cpu_pm_status |= CPU_PM_DEPD_INIT; + plat_cpu_pm_unlock(); + } + } + + if ((cpu_pm_status & CPU_PM_DEPD_INIT) && !(cpu_pm_status & CPU_PM_DEPD_READY)) { + status = mtk_lp_depd_condition(CPUPM_MBOX_WAIT_TASK_READY); + if (status == 0) { + plat_cpu_pm_lock(); + cpu_pm_status |= CPU_PM_DEPD_READY; + plat_cpu_pm_unlock(); + } + } + + ret = ((cpu_pm_status & CPU_PM_INIT_READY) == CPU_PM_INIT_READY) ? + MTK_CPUPM_E_OK : MTK_CPUPM_E_FAIL; +#endif + return ret; +} + +static int cpupm_pwr_state_valid(unsigned int afflv, unsigned int state) +{ + if (cpu_pm_status == CPU_PM_LP_READY) { + return MTK_CPUPM_E_OK; + } + + if (cpupm_init() != MTK_CPUPM_E_OK) { + return MTK_CPUPM_E_FAIL; + } + + if (read_cntpct_el0() >= (uint64_t)CPUPM_BOOTUP_TIME_THR) { + plat_cpu_pm_lock(); + cpu_pm_status |= CPU_PM_PLAT_READY; + plat_cpu_pm_unlock(); + } + + if (!IS_PLAT_SYSTEM_SUSPEND(afflv) && (cpu_pm_status & CPU_PM_PLAT_READY) == 0) { + return MTK_CPUPM_E_FAIL; + } + + return MTK_CPUPM_E_OK; +} + +static struct mtk_cpu_pm_ops cpcv3_2_mcdi = { + .get_pstate = cpupm_get_pstate, + .pwr_state_valid = cpupm_pwr_state_valid, + .cpu_resume = cpupm_cpu_resume, + .mcusys_suspend = cpupm_mcusys_suspend, + .mcusys_resume = cpupm_mcusys_resume, +}; +#endif /* CONFIG_MTK_CPU_SUSPEND_EN */ + +#endif /* CONFIG_MTK_PM_SUPPORT */ + +/* + * Depend on mtk pm methodology, the psci op init must + * be invoked after cpu pm to avoid initialization fail. + */ +int mt_plat_cpu_pm_init(void) +{ + plat_cpu_pm_lock_init(); + + mtk_cpc_init(); +#if CONFIG_MTK_PM_SUPPORT + +#if CONFIG_MTK_CPU_SUSPEND_EN + register_cpu_pm_ops(CPU_PM_FN, &cpcv3_2_mcdi); +#endif /* CONFIG_MTK_CPU_SUSPEND_EN */ + +#if CONFIG_MTK_SMP_EN + register_cpu_smp_ops(CPU_PM_FN, &cpcv3_2_cpu_smp); +#endif /* CONFIG_MTK_SMP_EN */ + +#endif /* CONFIG_MTK_PM_SUPPORT */ + + INFO("[%s:%d] - CPU PM INIT finished\n", __func__, __LINE__); + return 0; +} +MTK_ARCH_INIT(mt_plat_cpu_pm_init); + +static const mmap_region_t cpu_pm_mmap[] MTK_MMAP_SECTION = { +#ifdef CPU_PM_TINYSYS_SUPPORT +#if CONFIG_MTK_PM_SUPPORT && CONFIG_MTK_CPU_SUSPEND_EN + MAP_REGION_FLAT(CPU_EB_TCM_BASE, CPU_EB_TCM_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#endif +#endif + {0} +}; +DECLARE_MTK_MMAP_REGIONS(cpu_pm_mmap); diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h new file mode 100644 index 000000000..4d99df1d9 --- /dev/null +++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_CPU_PM_H +#define MT_CPU_PM_H + +#include <assert.h> +#include <mcucfg.h> +#include <platform_def.h> + +/* + * After ARM v8.2, the cache will turn off automatically when powering down CPU. Therefore, there + * is no doubt to use the spin_lock here. + */ +#if !HW_ASSISTED_COHERENCY +#define MT_CPU_PM_USING_BAKERY_LOCK +#endif + +#define CPU_PM_FN (MTK_CPUPM_FN_CPUPM_GET_PWR_STATE | \ + MTK_CPUPM_FN_PWR_STATE_VALID | \ + MTK_CPUPM_FN_PWR_ON_CORE_PREPARE | \ + MTK_CPUPM_FN_RESUME_CORE | \ + MTK_CPUPM_FN_SUSPEND_MCUSYS | \ + MTK_CPUPM_FN_RESUME_MCUSYS | \ + MTK_CPUPM_FN_SMP_INIT | \ + MTK_CPUPM_FN_SMP_CORE_ON | \ + MTK_CPUPM_FN_SMP_CORE_OFF) + +#define CPU_PM_ASSERT(_cond) ({ \ + if (!(_cond)) { \ + INFO("[%s:%d] - %s\n", __func__, __LINE__, #_cond); \ + panic(); \ + } }) + +#define CPC_PWR_MASK_MCUSYS_MP0 (0xC001) + +#define PER_CPU_PWR_DATA(ctrl, cluster, core) \ + do { \ + ctrl.rvbaraddr_l = CORE_RVBRADDR_##cluster##_##core##_L; \ + ctrl.arch_addr = MCUCFG_MP0_CLUSTER_CFG5; \ + ctrl.pwpr = SPM_MP##cluster##_CPU##core##_PWR_CON; \ + } while (0) + +#define PER_CPU_PWR_CTRL(ctrl, cpu) ({ \ + switch (cpu) { \ + case 0: \ + PER_CPU_PWR_DATA(ctrl, 0, 0); \ + break; \ + case 1: \ + PER_CPU_PWR_DATA(ctrl, 0, 1); \ + break; \ + case 2: \ + PER_CPU_PWR_DATA(ctrl, 0, 2); \ + break; \ + case 3: \ + PER_CPU_PWR_DATA(ctrl, 0, 3); \ + break; \ + case 4: \ + PER_CPU_PWR_DATA(ctrl, 0, 4); \ + break; \ + case 5: \ + PER_CPU_PWR_DATA(ctrl, 0, 5); \ + break; \ + case 6: \ + PER_CPU_PWR_DATA(ctrl, 0, 6); \ + break; \ + case 7: \ + PER_CPU_PWR_DATA(ctrl, 0, 7); \ + break; \ + default: \ + assert(0); \ + break; \ + } }) + + +/* MCUSYS DREQ BIG VPROC ISO control */ +#define DREQ20_BIG_VPROC_ISO (MCUCFG_BASE + 0xad8c) + +/* Definition about bootup address for each core CORE_RVBRADDR_clusterid_cpuid */ +#define CORE_RVBRADDR_0_0_L (MCUCFG_BASE + 0xc900) +#define CORE_RVBRADDR_0_1_L (MCUCFG_BASE + 0xc908) +#define CORE_RVBRADDR_0_2_L (MCUCFG_BASE + 0xc910) +#define CORE_RVBRADDR_0_3_L (MCUCFG_BASE + 0xc918) +#define CORE_RVBRADDR_0_4_L (MCUCFG_BASE + 0xc920) +#define CORE_RVBRADDR_0_5_L (MCUCFG_BASE + 0xc928) +#define CORE_RVBRADDR_0_6_L (MCUCFG_BASE + 0xc930) +#define CORE_RVBRADDR_0_7_L (MCUCFG_BASE + 0xc938) +#define MCUCFG_MP0_CLUSTER_CFG5 (MCUCFG_BASE + 0xc8e4) + +struct cpu_pwr_ctrl { + unsigned int rvbaraddr_l; + unsigned int arch_addr; + unsigned int pwpr; +}; + +#define MCUSYS_STATUS_PDN BIT(0) +#define MCUSYS_STATUS_CPUSYS_PROTECT BIT(8) +#define MCUSYS_STATUS_MCUSYS_PROTECT BIT(9) + +/* cpu_pm function ID */ +enum mt_cpu_pm_user_id { + MCUSYS_STATUS, + CPC_COMMAND, +}; + +/* cpu_pm lp function ID */ +enum mt_cpu_pm_lp_smc_id { + LP_CPC_COMMAND, + IRQS_REMAIN_ALLOC, + IRQS_REMAIN_CTRL, + IRQS_REMAIN_IRQ, + IRQS_REMAIN_WAKEUP_CAT, + IRQS_REMAIN_WAKEUP_SRC, +}; + +#endif /* MT_CPU_PM_H */ diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_cpc.c b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_cpc.c new file mode 100644 index 000000000..4cc220386 --- /dev/null +++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_cpc.c @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <string.h> + +#include <drivers/delay_timer.h> + +#include "mt_cpu_pm.h" +#include "mt_cpu_pm_cpc.h" +#include "mt_smp.h" +#include <mt_timer.h> + +struct mtk_cpc_dev { + int auto_off; + unsigned int auto_thres_tick; +}; + +static struct mtk_cpc_dev cpc; + +static int mtk_cpc_last_core_prot(int prot_req, int resp_reg, int resp_ofs) +{ + unsigned int staus; + unsigned int retry = 0; + + while (retry < RETRY_CNT_MAX) { + retry++; + + mmio_write_32(CPC_MCUSYS_LAST_CORE_REQ, prot_req); + + udelay(1); + + staus = (mmio_read_32(resp_reg) >> resp_ofs) & CPC_PROT_RESP_MASK; + + if (staus == PROT_SUCCESS) { + return CPC_SUCCESS; + } else if (staus == PROT_GIVEUP) { + return CPC_ERR_FAIL; + } + } + + return CPC_ERR_TIMEOUT; +} + +static int mtk_cpu_pm_mcusys_prot_aquire(void) +{ + return mtk_cpc_last_core_prot(MCUSYS_PROT_SET, CPC_MCUSYS_LAST_CORE_RESP, MCUSYS_RESP_OFS); +} + +static void mtk_cpu_pm_mcusys_prot_release(void) +{ + mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR); +} + +int mtk_cpu_pm_cluster_prot_aquire(void) +{ + return mtk_cpc_last_core_prot(CPUSYS_PROT_SET, CPC_MCUSYS_MP_LAST_CORE_RESP, + CPUSYS_RESP_OFS); +} + +void mtk_cpu_pm_cluster_prot_release(void) +{ + mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR); +} + +static void mtk_cpc_cluster_cnt_backup(void) +{ + /* single cluster */ + uint32_t backup_cnt = mmio_read_32(CPC_CLUSTER_CNT_BACKUP); + uint32_t curr_cnt = mmio_read_32(CPC_MCUSYS_CLUSTER_COUNTER); + + if ((curr_cnt & 0x7fff) == 0) { + curr_cnt = (curr_cnt >> 16) & 0x7fff; + } else { + curr_cnt = curr_cnt & 0x7fff; + } + + mmio_write_32(CPC_CLUSTER_CNT_BACKUP, backup_cnt + curr_cnt); + mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, 0x3); +} + +static inline void mtk_cpc_mcusys_off_enable(bool enable) +{ + mmio_write_32(CPC_MCUSYS_PWR_CTRL, enable ? 1 : 0); +} + +void mtk_cpc_mcusys_off_reflect(void) +{ + mtk_cpc_mcusys_off_enable(false); + mtk_cpu_pm_mcusys_prot_release(); +} + +int mtk_cpc_mcusys_off_prepare(void) +{ + if (mtk_cpu_pm_mcusys_prot_aquire() != CPC_SUCCESS) { + return CPC_ERR_FAIL; + } + + mtk_cpc_cluster_cnt_backup(); + mtk_cpc_mcusys_off_enable(true); + + return CPC_SUCCESS; +} + +void mtk_cpc_core_on_hint_set(int cpu) +{ + mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_SET, BIT(cpu)); +} + +void mtk_cpc_core_on_hint_clr(int cpu) +{ + mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu)); +} + +static void mtk_cpc_dump_timestamp(void) +{ + unsigned int id; + + for (id = 0; id < CPC_TRACE_ID_NUM; id++) { + mmio_write_32(CPC_MCUSYS_TRACE_SEL, id); + + memcpy((void *)(uintptr_t)CPC_TRACE_SRAM(id), + (const void *)(uintptr_t)CPC_MCUSYS_TRACE_DATA, + CPC_TRACE_SIZE); + } +} + +void mtk_cpc_time_sync(void) +{ + uint64_t kt; + uint32_t systime_l, systime_h; + + kt = sched_clock(); + systime_l = mmio_read_32(CNTSYS_L_REG); + systime_h = mmio_read_32(CNTSYS_H_REG); + + /* sync kernel timer to cpc */ + mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE, (uint32_t)kt); + mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE, (uint32_t)(kt >> 32)); + + /* sync system timer to cpc */ + mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE, systime_l); + mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE, systime_h); +} + +static void mtk_cpc_config(unsigned int cfg, unsigned int data) +{ + switch (cfg) { + case CPC_SMC_CONFIG_PROF: + if (data) { + mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, CPC_PROF_EN); + } else { + mmio_clrbits_32(CPC_MCUSYS_CPC_DBG_SETTING, CPC_PROF_EN); + } + break; + case CPC_SMC_CONFIG_AUTO_OFF: + if (data) { + mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_AUTO_OFF_EN); + cpc.auto_off = 1; + } else { + mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_AUTO_OFF_EN); + cpc.auto_off = 0; + } + break; + case CPC_SMC_CONFIG_AUTO_OFF_THRES: + cpc.auto_thres_tick = US_TO_TICKS(data); + mmio_write_32(CPC_MCUSYS_CPC_OFF_THRES, cpc.auto_thres_tick); + break; + case CPC_SMC_CONFIG_CNT_CLR: + mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, 0x3); + break; + case CPC_SMC_CONFIG_TIME_SYNC: + mtk_cpc_time_sync(); + break; + default: + break; + } +} + +static unsigned int mtk_cpc_read_config(unsigned int cfg) +{ + unsigned int res = 0; + + switch (cfg) { + case CPC_SMC_CONFIG_PROF: + res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ? 1 : 0; + break; + case CPC_SMC_CONFIG_AUTO_OFF: + res = cpc.auto_off; + break; + case CPC_SMC_CONFIG_AUTO_OFF_THRES: + res = TICKS_TO_US(cpc.auto_thres_tick); + break; + case CPC_SMC_CONFIG_CNT_CLR: + default: + break; + } + + return res; +} + +uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2) +{ + uint64_t res = 0; + + switch (act) { + case CPC_SMC_EVENT_CPC_CONFIG: + mtk_cpc_config((unsigned int)arg1, (unsigned int)arg2); + break; + case CPC_SMC_EVENT_READ_CONFIG: + res = mtk_cpc_read_config((unsigned int)arg1); + break; + case CPC_SMC_EVENT_GIC_DPG_SET: + /* isolated_status = x2; */ + default: + break; + } + + return res; +} + +uint64_t mtk_cpc_trace_dump(uint64_t act, uint64_t arg1, uint64_t arg2) +{ + switch (act) { + case CPC_SMC_EVENT_DUMP_TRACE_DATA: + mtk_cpc_dump_timestamp(); + break; + default: + break; + } + + return 0; +} + +void mtk_cpc_init(void) +{ +#if CONFIG_MTK_SMP_EN + mt_smp_init(); +#endif + mmio_setbits_32(CPC_MCUSYS_CPC_DBG_SETTING, (CPC_DBG_EN | CPC_CALC_EN)); + + cpc.auto_off = 1; + mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, (CPC_OFF_PRE_EN | + ((cpc.auto_off > 0) ? CPC_AUTO_OFF_EN : 0))); + + mtk_cpc_config(CPC_SMC_CONFIG_AUTO_OFF_THRES, 8000); + + /* enable CPC */ + mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE); + mmio_setbits_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, SSPM_CORE_PWR_ON_EN); +} diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_cpc.h b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_cpc.h new file mode 100644 index 000000000..3004f414c --- /dev/null +++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_cpc.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_CPU_PM_CPC_H +#define MT_CPU_PM_CPC_H + +#include <lib/mmio.h> + +#include <mcucfg.h> +#include <platform_def.h> + +#define NEED_CPUSYS_PROT_WORKAROUND (1) + +/* system sram registers */ +#define CPUIDLE_SRAM_REG(r) (CPU_IDLE_SRAM_BASE + (r)) + +/* db dump */ +#define CPC_TRACE_SIZE (0x20) +#define CPC_TRACE_ID_NUM (10) +#define CPC_TRACE_SRAM(id) (CPUIDLE_SRAM_REG(0x10) + (id) * CPC_TRACE_SIZE) + +/* buckup off count */ +#define CPC_CLUSTER_CNT_BACKUP CPUIDLE_SRAM_REG(0x1f0) +#define CPC_MCUSYS_CNT CPUIDLE_SRAM_REG(0x1f4) + +/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG (0xA814): debug setting */ +#define CPC_PWR_ON_SEQ_DIS BIT(1) +#define CPC_PWR_ON_PRIORITY BIT(2) +#define CPC_AUTO_OFF_EN BIT(5) +#define CPC_DORMANT_WAIT_EN BIT(14) +#define CPC_CTRL_EN BIT(16) +#define CPC_OFF_PRE_EN BIT(29) + +/* CPC_MCUSYS_LAST_CORE_REQ (0xA818) : last core protection */ +#define CPUSYS_PROT_SET BIT(0) +#define MCUSYS_PROT_SET BIT(8) +#define CPUSYS_PROT_CLR BIT(8) +#define MCUSYS_PROT_CLR BIT(9) + +#define CPC_PROT_RESP_MASK (0x3) +#define CPUSYS_RESP_OFS (16) +#define MCUSYS_RESP_OFS (30) + +#define RETRY_CNT_MAX (1000) + +#define PROT_RETRY (0) +#define PROT_SUCCESS (1) +#define PROT_GIVEUP (2) + +/* CPC_MCUSYS_CPC_DBG_SETTING (0xAB00): debug setting */ +#define CPC_PROF_EN BIT(0) +#define CPC_DBG_EN BIT(1) +#define CPC_FREEZE BIT(2) +#define CPC_CALC_EN BIT(3) + +enum mcusys_cpc_lastcore_prot_status { + CPC_SUCCESS = 0, + CPC_ERR_FAIL, + CPC_ERR_TIMEOUT, + NF_CPC_ERR, +}; + +enum mcusys_cpc_smc_events { + CPC_SMC_EVENT_DUMP_TRACE_DATA, + CPC_SMC_EVENT_GIC_DPG_SET, + CPC_SMC_EVENT_CPC_CONFIG, + CPC_SMC_EVENT_READ_CONFIG, + NF_CPC_SMC_EVENT, +}; + +enum mcusys_cpc_smc_config { + CPC_SMC_CONFIG_PROF, + CPC_SMC_CONFIG_AUTO_OFF, + CPC_SMC_CONFIG_AUTO_OFF_THRES, + CPC_SMC_CONFIG_CNT_CLR, + CPC_SMC_CONFIG_TIME_SYNC, + NF_CPC_SMC_CONFIG, +}; + +#define US_TO_TICKS(us) ((us) * 13) +#define TICKS_TO_US(tick) ((tick) / 13) + +int mtk_cpu_pm_cluster_prot_aquire(void); +void mtk_cpu_pm_cluster_prot_release(void); + +void mtk_cpc_mcusys_off_reflect(void); +int mtk_cpc_mcusys_off_prepare(void); + +void mtk_cpc_core_on_hint_set(int cpu); +void mtk_cpc_core_on_hint_clr(int cpu); +void mtk_cpc_time_sync(void); + +uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2); +uint64_t mtk_cpc_trace_dump(uint64_t act, uint64_t arg1, uint64_t arg2); +void mtk_cpc_init(void); + +#endif /* MT_CPU_PM_CPC_H */ diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_mbox.c b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_mbox.c new file mode 100644 index 000000000..4d67e7b4c --- /dev/null +++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_mbox.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <errno.h> + +#include <lib/mmio.h> + +#include "mt_cpu_pm_mbox.h" +#include <platform_def.h> + +#ifdef __GNUC__ +#define MCDI_LIKELY(x) __builtin_expect(!!(x), 1) +#define MCDI_UNLIKELY(x) __builtin_expect(!!(x), 0) +#else +#define MCDI_LIKELY(x) (x) +#define MCDI_UNLIKELY(x) (x) +#endif + +#define MCUPM_MBOX_3_BASE (CPU_EB_TCM_BASE + CPU_EB_MBOX3_OFFSET) +#define MCUPM_MBOX_WRITE(id, val) mmio_write_32(MCUPM_MBOX_3_BASE + 4 * (id), val) +#define MCUPM_MBOX_READ(id) mmio_read_32(MCUPM_MBOX_3_BASE + 4 * (id)) + +void mtk_set_mcupm_pll_mode(unsigned int mode) +{ + if (mode < NF_MCUPM_ARMPLL_MODE) { + MCUPM_MBOX_WRITE(MCUPM_MBOX_ARMPLL_MODE, mode); + } +} + +int mtk_get_mcupm_pll_mode(void) +{ + return MCUPM_MBOX_READ(MCUPM_MBOX_ARMPLL_MODE); +} + +void mtk_set_mcupm_buck_mode(unsigned int mode) +{ + if (mode < NF_MCUPM_BUCK_MODE) { + MCUPM_MBOX_WRITE(MCUPM_MBOX_BUCK_MODE, mode); + } +} + +int mtk_get_mcupm_buck_mode(void) +{ + return MCUPM_MBOX_READ(MCUPM_MBOX_BUCK_MODE); +} + +void mtk_set_cpu_pm_preffered_cpu(unsigned int cpuid) +{ + return MCUPM_MBOX_WRITE(MCUPM_MBOX_WAKEUP_CPU, cpuid); +} + +unsigned int mtk_get_cpu_pm_preffered_cpu(void) +{ + return MCUPM_MBOX_READ(MCUPM_MBOX_WAKEUP_CPU); +} + +static int mtk_wait_mbox_init_done(void) +{ + int status = MCUPM_MBOX_READ(MCUPM_MBOX_TASK_STA); + + if (status != MCUPM_TASK_INIT) { + return status; + } + + mtk_set_mcupm_pll_mode(MCUPM_ARMPLL_OFF); + mtk_set_mcupm_buck_mode(MCUPM_BUCK_OFF_MODE); + + MCUPM_MBOX_WRITE(MCUPM_MBOX_PWR_CTRL_EN, (MCUPM_MCUSYS_CTRL | MCUPM_CM_CTRL | + MCUPM_BUCK_CTRL | MCUPM_ARMPLL_CTRL)); + + return status; +} + +int mtk_lp_depd_condition(enum cpupm_mbox_depd_type type) +{ + int status; + + if (type == CPUPM_MBOX_WAIT_DEV_INIT) { + status = mtk_wait_mbox_init_done(); + if (MCDI_UNLIKELY(status != MCUPM_TASK_INIT)) { + return -ENXIO; + } + MCUPM_MBOX_WRITE(MCUPM_MBOX_AP_READY, 1); + } else if (type == CPUPM_MBOX_WAIT_TASK_READY) { + status = MCUPM_MBOX_READ(MCUPM_MBOX_TASK_STA); + if (MCDI_UNLIKELY((status != MCUPM_TASK_WAIT) && + (status != MCUPM_TASK_INIT_FINISH))) { + return -ENXIO; + } + } + return 0; +} diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_mbox.h b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_mbox.h new file mode 100644 index 000000000..72be6bd6a --- /dev/null +++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm_mbox.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_CPU_PM_MBOX_H +#define MT_CPU_PM_MBOX_H + +#include <lib/utils_def.h> + +/* MCUPM Mbox */ +/* AP Write */ +#define MCUPM_MBOX_AP_READY (0) +#define MCUPM_MBOX_RESERVED_1 (1) +#define MCUPM_MBOX_RESERVED_2 (2) +#define MCUPM_MBOX_RESERVED_3 (3) +#define MCUPM_MBOX_PWR_CTRL_EN (4) +#define MCUPM_MBOX_L3_CACHE_MODE (5) +#define MCUPM_MBOX_BUCK_MODE (6) +#define MCUPM_MBOX_ARMPLL_MODE (7) +/* AP Read */ +#define MCUPM_MBOX_TASK_STA (8) +#define MCUPM_MBOX_RESERVED_9 (9) +#define MCUPM_MBOX_RESERVED_10 (10) +#define MCUPM_MBOX_RESERVED_11 (11) +#define MCUPM_MBOX_WAKEUP_CPU (12) + +/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN (4) */ +#define MCUPM_MCUSYS_CTRL BIT(0) +#define MCUPM_BUCK_CTRL BIT(1) +#define MCUPM_ARMPLL_CTRL BIT(2) +#define MCUPM_CM_CTRL BIT(3) +#define MCUPM_PWR_CTRL_MASK (BIT(3) - 1) + +/* Mbox Slot: APMCU_MCUPM_MBOX_L3_CACHE_MODE (5) */ +#define MCUPM_L3_OFF_MODE (0) /* default */ +#define MCUPM_L3_DORMANT_MODE (1) +#define NF_MCUPM_L3_MODE (2) + +/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE (6) */ +#define MCUPM_BUCK_NORMAL_MODE (0) /* default */ +#define MCUPM_BUCK_LP_MODE (1) +#define MCUPM_BUCK_OFF_MODE (2) +#define NF_MCUPM_BUCK_MODE (3) + +/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE (7) */ +#define MCUPM_ARMPLL_ON (0) /* default */ +#define MCUPM_ARMPLL_GATING (1) +#define MCUPM_ARMPLL_OFF (2) +#define NF_MCUPM_ARMPLL_MODE (3) + +/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA (9) */ +#define MCUPM_TASK_UNINIT (0) +#define MCUPM_TASK_INIT (1) +#define MCUPM_TASK_INIT_FINISH (2) +#define MCUPM_TASK_WAIT (3) +#define MCUPM_TASK_RUN (4) +#define MCUPM_TASK_PAUSE (5) + + +void mtk_set_mcupm_pll_mode(unsigned int mode); +int mtk_get_mcupm_pll_mode(void); + +void mtk_set_mcupm_buck_mode(unsigned int mode); +int mtk_get_mcupm_buck_mode(void); + +void mtk_set_cpu_pm_preffered_cpu(unsigned int cpuid); +unsigned int mtk_get_cpu_pm_preffered_cpu(void); + +enum cpupm_mbox_depd_type { + CPUPM_MBOX_WAIT_DEV_INIT, + CPUPM_MBOX_WAIT_TASK_READY, +}; + +int mtk_lp_depd_condition(enum cpupm_mbox_depd_type type); + +#endif /* MT_CPU_PM_MBOX_H */ diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.c b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.c new file mode 100644 index 000000000..a1d9c3115 --- /dev/null +++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <plat/common/platform.h> + +#include <lib/pm/mtk_pm.h> +#include <mcucfg.h> +#include "mt_cpu_pm.h" +#include "mt_smp.h" + +static inline int is_core_power_status_on(unsigned int cpuid) +{ + return !!(mmio_read_32(CPU_PWR_STATUS) & BIT(cpuid)); +} + +void mt_smp_core_init_arch(unsigned int cluster, unsigned int cpu, int arm64, + struct cpu_pwr_ctrl *pwr_ctrl) +{ + CPU_PM_ASSERT(cluster == 0); + CPU_PM_ASSERT(pwr_ctrl != NULL); + + /* aa64naa32 in bits[16:23] */ + if (arm64 != 0) { + mmio_setbits_32(pwr_ctrl->arch_addr, 1 << (16 + cpu)); + } else { + mmio_clrbits_32(pwr_ctrl->arch_addr, 1 << (16 + cpu)); + } +} + +void mt_smp_core_bootup_address_set(struct cpu_pwr_ctrl *pwr_ctrl, uintptr_t entry) +{ + CPU_PM_ASSERT(pwr_ctrl != NULL); + + /* Set bootup address */ + mmio_write_32(pwr_ctrl->rvbaraddr_l, entry); +} + +int mt_smp_power_core_on(unsigned int cpu_id, struct cpu_pwr_ctrl *pwr_ctrl) +{ + unsigned int val = is_core_power_status_on(cpu_id); + + CPU_PM_ASSERT(pwr_ctrl); + + mmio_clrbits_32(pwr_ctrl->pwpr, RESETPWRON_CONFIG); + if (val == 0) { + /* + * Set to 0 after BIG VPROC bulk powered on (configure in MCUPM) and + * before big core power-on sequence. + */ + if (cpu_id >= PLAT_CPU_PM_B_BUCK_ISO_ID) { + mmio_write_32(DREQ20_BIG_VPROC_ISO, 0); + } + + mmio_setbits_32(pwr_ctrl->pwpr, PWR_RST_B); + dsbsy(); + + /* set mp0_spmc_pwr_on_cpuX = 1 */ + mmio_setbits_32(pwr_ctrl->pwpr, PWR_ON); + + val = 0; + while (is_core_power_status_on(cpu_id) == 0) { + DO_SMP_CORE_ON_WAIT_TIMEOUT(val); + mmio_clrbits_32(pwr_ctrl->pwpr, PWR_ON); + mmio_setbits_32(pwr_ctrl->pwpr, PWR_ON); + } + } else { + INFO("[%s:%d] - core_%u haven been power on\n", __func__, __LINE__, cpu_id); + } + + return MTK_CPUPM_E_OK; +} + +int mt_smp_power_core_off(struct cpu_pwr_ctrl *pwr_ctrl) +{ + /* set mp0_spmc_pwr_on_cpuX = 1 */ + mmio_clrbits_32(pwr_ctrl->pwpr, PWR_ON); + return MTK_CPUPM_E_OK; +} + +void mt_smp_init(void) +{ + /* clear RESETPWRON_CONFIG of mcusys/cluster/core0 */ + mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG); + mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); +} diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.h b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.h new file mode 100644 index 000000000..4c2f8d2b7 --- /dev/null +++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_smp.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_SMP_H +#define MT_SMP_H + +#include <lib/mmio.h> +#include <platform_def.h> + +#define CPU_PWR_STATUS (MCUCFG_BASE + 0xA840) + +#define SMP_CORE_TIMEOUT_MAX (50000) +#define DO_SMP_CORE_ON_WAIT_TIMEOUT(k_cnt) ({ \ + CPU_PM_ASSERT(k_cnt < SMP_CORE_TIMEOUT_MAX); \ + k_cnt++; udelay(1); }) + +void mt_smp_core_init_arch(unsigned int cluster, unsigned int cpu, int arm64, + struct cpu_pwr_ctrl *pwr_ctrl); +void mt_smp_core_bootup_address_set(struct cpu_pwr_ctrl *pwr_ctrl, uintptr_t entry); +int mt_smp_power_core_on(unsigned int cpu_id, struct cpu_pwr_ctrl *pwr_ctrl); +int mt_smp_power_core_off(struct cpu_pwr_ctrl *pwr_ctrl); +void mt_smp_init(void); + +#endif /* MT_SMP_H */ diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/rules.mk b/plat/mediatek/drivers/cpu_pm/cpcv3_2/rules.mk new file mode 100644 index 000000000..858cf382e --- /dev/null +++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/rules.mk @@ -0,0 +1,19 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := cpcv${CONFIG_MTK_CPU_PM_ARCH} + +LOCAL_SRCS-y := ${LOCAL_DIR}/mt_cpu_pm.c ${LOCAL_DIR}/mt_cpu_pm_cpc.c + +LOCAL_SRCS-$(CPU_PM_TINYSYS_SUPPORT) += ${LOCAL_DIR}/mt_cpu_pm_mbox.c +LOCAL_SRCS-$(CONFIG_MTK_SMP_EN) += ${LOCAL_DIR}/mt_smp.c + +$(eval $(call add_defined_option,CPU_PM_TINYSYS_SUPPORT)) + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) + diff --git a/plat/mediatek/drivers/cpu_pm/rules.mk b/plat/mediatek/drivers/cpu_pm/rules.mk new file mode 100644 index 000000000..8df4f2189 --- /dev/null +++ b/plat/mediatek/drivers/cpu_pm/rules.mk @@ -0,0 +1,13 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := cpu_pm + +SUB_RULES-${CONFIG_MTK_CPU_PM_SUPPORT} := $(LOCAL_DIR)/cpcv${CONFIG_MTK_CPU_PM_ARCH} + +$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y))) diff --git a/plat/mediatek/drivers/dcm/mt8188/mtk_dcm_utils.c b/plat/mediatek/drivers/dcm/mt8188/mtk_dcm_utils.c new file mode 100644 index 000000000..c054de953 --- /dev/null +++ b/plat/mediatek/drivers/dcm/mt8188/mtk_dcm_utils.c @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/mmio.h> +#include <lib/utils_def.h> +#include <mtk_dcm_utils.h> + +#define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK BIT(17) +#define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | BIT(16) | BIT(17) | \ + BIT(18) | BIT(21)) +#define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | BIT(16) | BIT(17) | BIT(18)) +#define MP_CPUSYS_TOP_ADB_DCM_REG0_ON BIT(17) +#define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | BIT(16) | BIT(17) | \ + BIT(18) | BIT(21)) +#define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | BIT(16) | BIT(17) | BIT(18)) +#define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF (0x0 << 17) +#define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | (0x0 << 16) | \ + (0x0 << 17) | (0x0 << 18) | \ + (0x0 << 21)) +#define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | (0x0 << 16) | \ + (0x0 << 17) | (0x0 << 18)) + +bool dcm_mp_cpusys_top_adb_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, + MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG0_ON); + ret &= dcm_check_state(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, + MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG1_ON); + ret &= dcm_check_state(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, + MP_CPUSYS_TOP_ADB_DCM_REG2_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG2_ON); + + return ret; +} + +void dcm_mp_cpusys_top_adb_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, + MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG0_ON); + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, + MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG1_ON); + mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, + MP_CPUSYS_TOP_ADB_DCM_REG2_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG2_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, + MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG0_OFF); + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, + MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG1_OFF); + mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, + MP_CPUSYS_TOP_ADB_DCM_REG2_MASK, + MP_CPUSYS_TOP_ADB_DCM_REG2_OFF); + } +} + +#define MP_CPUSYS_TOP_APB_DCM_REG0_MASK BIT(5) +#define MP_CPUSYS_TOP_APB_DCM_REG1_MASK BIT(8) +#define MP_CPUSYS_TOP_APB_DCM_REG2_MASK BIT(16) +#define MP_CPUSYS_TOP_APB_DCM_REG0_ON BIT(5) +#define MP_CPUSYS_TOP_APB_DCM_REG1_ON BIT(8) +#define MP_CPUSYS_TOP_APB_DCM_REG2_ON BIT(16) +#define MP_CPUSYS_TOP_APB_DCM_REG0_OFF (0x0 << 5) +#define MP_CPUSYS_TOP_APB_DCM_REG1_OFF (0x0 << 8) +#define MP_CPUSYS_TOP_APB_DCM_REG2_OFF (0x0 << 16) + +bool dcm_mp_cpusys_top_apb_dcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG0_MASK, + MP_CPUSYS_TOP_APB_DCM_REG0_ON); + ret &= dcm_check_state(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG1_MASK, + MP_CPUSYS_TOP_APB_DCM_REG1_ON); + ret &= dcm_check_state(MP_CPUSYS_TOP_MP0_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG2_MASK, + MP_CPUSYS_TOP_APB_DCM_REG2_ON); + + return ret; +} + +void dcm_mp_cpusys_top_apb_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG0_MASK, + MP_CPUSYS_TOP_APB_DCM_REG0_ON); + mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG1_MASK, + MP_CPUSYS_TOP_APB_DCM_REG1_ON); + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG2_MASK, + MP_CPUSYS_TOP_APB_DCM_REG2_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG0_MASK, + MP_CPUSYS_TOP_APB_DCM_REG0_OFF); + mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG1_MASK, + MP_CPUSYS_TOP_APB_DCM_REG1_OFF); + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, + MP_CPUSYS_TOP_APB_DCM_REG2_MASK, + MP_CPUSYS_TOP_APB_DCM_REG2_OFF); + } +} + +#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11) | BIT(24) | BIT(25)) +#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11) | BIT(24) | BIT(25)) +#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11) | \ + (0x0 << 24) | \ + (0x0 << 25)) + +bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void) +{ + return dcm_check_state(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON); +} + +void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, + MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK BIT(0) +#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON BIT(0) +#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF (0x0 << 0) + +bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void) +{ + return dcm_check_state(MP_CPUSYS_TOP_MP0_DCM_CFG7, + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON); +} + +void dcm_mp_cpusys_top_core_stall_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, + MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK (0xffff << 0) +#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON (0xffff << 0) +#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF (0x0 << 0) + +bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void) +{ + return dcm_check_state(MP_CPUSYS_TOP_MCSIC_DCM0, + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON); +} + +void dcm_mp_cpusys_top_cpubiu_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0, + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0, + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(24) | BIT(25)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(24) | BIT(25)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 24) | (0x0 << 25)) + +bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void) +{ + return dcm_check_state(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON); +} + +void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(24) | BIT(25)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(24) | BIT(25)) +#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 24) | (0x0 << 25)) + +bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void) +{ + return dcm_check_state(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON); +} + +void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, + MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK BIT(4) +#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON BIT(4) +#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF (0x0 << 4) + +bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void) +{ + return dcm_check_state(MP_CPUSYS_TOP_MP0_DCM_CFG7, + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON); +} + +void dcm_mp_cpusys_top_fcm_stall_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, + MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK BIT(31) +#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON BIT(31) +#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF (0x0U << 31) + +bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void) +{ + return dcm_check_state(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON); +} + +void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, + MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | BIT(4)) +#define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | BIT(4)) +#define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | (0x0 << 4)) + +bool dcm_mp_cpusys_top_misc_dcm_is_on(void) +{ + return dcm_check_state(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, + MP_CPUSYS_TOP_MISC_DCM_REG0_ON); +} + +void dcm_mp_cpusys_top_misc_dcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, + MP_CPUSYS_TOP_MISC_DCM_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, + MP_CPUSYS_TOP_MISC_DCM_REG0_OFF); + } +} + +#define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK BIT(3) +#define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON BIT(3) +#define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3)) +#define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | (0x0 << 1) | \ + (0x0 << 2) | (0x0 << 3)) + +bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void) +{ + bool ret = true; + + ret &= dcm_check_state(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, + MP_CPUSYS_TOP_MP0_QDCM_REG0_ON); + ret &= dcm_check_state(MP_CPUSYS_TOP_MP0_DCM_CFG0, + MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK, + MP_CPUSYS_TOP_MP0_QDCM_REG1_ON); + + return ret; +} + +void dcm_mp_cpusys_top_mp0_qdcm(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, + MP_CPUSYS_TOP_MP0_QDCM_REG0_ON); + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, + MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK, + MP_CPUSYS_TOP_MP0_QDCM_REG1_ON); + } else { + /* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */ + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, + MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, + MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF); + mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, + MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK, + MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF); + } +} + +#define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | (0x0 << 1) | \ + (0x0 << 2) | (0x0 << 3)) + +bool dcm_cpccfg_reg_emi_wfifo_is_on(void) +{ + return dcm_check_state(CPCCFG_REG_EMI_WFIFO, + CPCCFG_REG_EMI_WFIFO_REG0_MASK, + CPCCFG_REG_EMI_WFIFO_REG0_ON); +} + +void dcm_cpccfg_reg_emi_wfifo(bool on) +{ + if (on) { + /* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */ + mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO, + CPCCFG_REG_EMI_WFIFO_REG0_MASK, + CPCCFG_REG_EMI_WFIFO_REG0_ON); + } else { + /* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */ + mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO, + CPCCFG_REG_EMI_WFIFO_REG0_MASK, + CPCCFG_REG_EMI_WFIFO_REG0_OFF); + } +} diff --git a/plat/mediatek/drivers/dcm/mt8188/mtk_dcm_utils.h b/plat/mediatek/drivers/dcm/mt8188/mtk_dcm_utils.h new file mode 100644 index 000000000..5d758dd82 --- /dev/null +++ b/plat/mediatek/drivers/dcm/mt8188/mtk_dcm_utils.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_DCM_UTILS_H +#define MTK_DCM_UTILS_H + +#include <stdbool.h> + +#include <mtk_dcm.h> +#include <platform_def.h> + +/* Base */ +#define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000) +#define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800) + +/* Register Definition */ +#define CPCCFG_REG_EMI_WFIFO (CPCCFG_REG_BASE + 0x100) +#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0) +#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4) +#define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0) +#define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440) +#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500) +#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510) +#define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518) +#define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0) +#define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880) +#define MP_CPUSYS_TOP_MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c) + +/* MP_CPUSYS_TOP */ +bool dcm_mp_cpusys_top_adb_dcm_is_on(void); +void dcm_mp_cpusys_top_adb_dcm(bool on); +bool dcm_mp_cpusys_top_apb_dcm_is_on(void); +void dcm_mp_cpusys_top_apb_dcm(bool on); +bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void); +void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on); +bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void); +void dcm_mp_cpusys_top_core_stall_dcm(bool on); +bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void); +void dcm_mp_cpusys_top_cpubiu_dcm(bool on); +bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void); +void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on); +bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void); +void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on); +bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void); +void dcm_mp_cpusys_top_fcm_stall_dcm(bool on); +bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void); +void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on); +bool dcm_mp_cpusys_top_misc_dcm_is_on(void); +void dcm_mp_cpusys_top_misc_dcm(bool on); +bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void); +void dcm_mp_cpusys_top_mp0_qdcm(bool on); +/* CPCCFG_REG */ +bool dcm_cpccfg_reg_emi_wfifo_is_on(void); +void dcm_cpccfg_reg_emi_wfifo(bool on); + +#endif diff --git a/plat/mediatek/drivers/dcm/mtk_dcm.c b/plat/mediatek/drivers/dcm/mtk_dcm.c new file mode 100644 index 000000000..ca79a209d --- /dev/null +++ b/plat/mediatek/drivers/dcm/mtk_dcm.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <lib/mmio.h> +#include <lib/mtk_init/mtk_init.h> +#include <mtk_dcm.h> +#include <mtk_dcm_utils.h> + +static void dcm_armcore(bool mode) +{ + dcm_mp_cpusys_top_bus_pll_div_dcm(mode); + dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode); + dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode); +} + +static void dcm_mcusys(bool on) +{ + dcm_mp_cpusys_top_adb_dcm(on); + dcm_mp_cpusys_top_apb_dcm(on); + dcm_mp_cpusys_top_cpubiu_dcm(on); + dcm_mp_cpusys_top_misc_dcm(on); + dcm_mp_cpusys_top_mp0_qdcm(on); + + /* CPCCFG_REG */ + dcm_cpccfg_reg_emi_wfifo(on); + dcm_mp_cpusys_top_last_cor_idle_dcm(on); +} + +static void dcm_stall(bool on) +{ + dcm_mp_cpusys_top_core_stall_dcm(on); + dcm_mp_cpusys_top_fcm_stall_dcm(on); +} + +static bool check_dcm_state(void) +{ + bool ret = true; + + ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); + ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); + ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); + + ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); + ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); + ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); + ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); + ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); + ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); + ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(); + + ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on(); + ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on(); + + return ret; +} + +bool dcm_check_state(uintptr_t addr, unsigned int mask, unsigned int compare) +{ + return ((mmio_read_32(addr) & mask) == compare); +} + +int dcm_set_init(void) +{ + int ret; + + dcm_armcore(true); + dcm_mcusys(true); + dcm_stall(true); + + if (check_dcm_state() == false) { + ERROR("Failed to set default dcm on!!\n"); + ret = -1; + } else { + INFO("%s, dcm pass\n", __func__); + ret = 0; + } + + return ret; +} +MTK_PLAT_SETUP_0_INIT(dcm_set_init); diff --git a/plat/mediatek/drivers/dcm/mtk_dcm.h b/plat/mediatek/drivers/dcm/mtk_dcm.h new file mode 100644 index 000000000..05f8d4586 --- /dev/null +++ b/plat/mediatek/drivers/dcm/mtk_dcm.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_DCM_H +#define MTK_DCM_H + +#include <stdbool.h> + +bool dcm_check_state(uintptr_t addr, unsigned int mask, unsigned int compare); +int dcm_set_init(void); + +#endif /* #ifndef MTK_DCM_H */ diff --git a/plat/mediatek/drivers/dcm/rules.mk b/plat/mediatek/drivers/dcm/rules.mk new file mode 100644 index 000000000..a8ee05e3d --- /dev/null +++ b/plat/mediatek/drivers/dcm/rules.mk @@ -0,0 +1,17 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := mtk_dcm + +LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_dcm.c +LOCAL_SRCS-y += ${LOCAL_DIR}/${MTK_SOC}/mtk_dcm_utils.c + +PLAT_INCLUDES += -I${LOCAL_DIR} +PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/dfd/dfd.c b/plat/mediatek/drivers/dfd/dfd.c new file mode 100644 index 000000000..5770d5014 --- /dev/null +++ b/plat/mediatek/drivers/dfd/dfd.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch_helpers.h> +#include <common/debug.h> +#include <lib/mmio.h> +#include <dfd.h> +#include <mtk_sip_svc.h> +#include <plat_dfd.h> + +static u_register_t dfd_smc_dispatcher(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3, + void *handle, struct smccc_res *smccc_ret) +{ + int ret = MTK_SIP_E_SUCCESS; + + switch (arg0) { + case PLAT_MTK_DFD_SETUP_MAGIC: + INFO("[%s] DFD setup call from kernel\n", __func__); + dfd_setup(arg1, arg2, arg3); + break; + case PLAT_MTK_DFD_READ_MAGIC: + /* only allow to access DFD register base + 0x200 */ + if (arg1 <= 0x200) { + ret = mmio_read_32(MISC1_CFG_BASE + arg1); + } + break; + case PLAT_MTK_DFD_WRITE_MAGIC: + /* only allow to access DFD register base + 0x200 */ + if (arg1 <= 0x200) { + sync_writel(MISC1_CFG_BASE + arg1, arg2); + } + break; + default: + ret = MTK_SIP_E_INVALID_PARAM; + break; + } + + return ret; +} +DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_DFD, dfd_smc_dispatcher); diff --git a/plat/mediatek/drivers/dfd/dfd.h b/plat/mediatek/drivers/dfd/dfd.h new file mode 100644 index 000000000..c088bd0ef --- /dev/null +++ b/plat/mediatek/drivers/dfd/dfd.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DFD_H +#define DFD_H + +#include <arch_helpers.h> +#include <lib/mmio.h> + +void dfd_resume(void); +void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump); + +#endif /* DFD_H */ diff --git a/plat/mediatek/drivers/dfd/mt8188/plat_dfd.c b/plat/mediatek/drivers/dfd/mt8188/plat_dfd.c new file mode 100644 index 000000000..1aa68f534 --- /dev/null +++ b/plat/mediatek/drivers/dfd/mt8188/plat_dfd.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch_helpers.h> +#include <common/debug.h> +#include <lib/mmio.h> +#include <dfd.h> +#include <plat_dfd.h> + +static uint64_t dfd_cache_dump; +static bool dfd_enabled; +static uint64_t dfd_base_addr; +static uint64_t dfd_chain_length; + +void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump) +{ + mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL); + mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL); + mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL); + + mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, BIT(2)); + mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1); + sync_writel(DFD_INTERNAL_CTL, 0x5); + mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); + mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); + mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); + mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); + + mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); + mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); + mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); + mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); + + mmio_write_32(DFD_TEST_SI_0, 0x0); + mmio_write_32(DFD_TEST_SI_1, 0x0); + mmio_write_32(DFD_TEST_SI_2, 0x0); + mmio_write_32(DFD_TEST_SI_3, 0x0); + + sync_writel(DFD_POWER_CTL, 0xF9); + sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL); + sync_writel(DFD_V30_CTL, 0xD); + + mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); + mmio_write_32(DFD_O_REG_0, 0); + + /* setup global variables for suspend and resume */ + dfd_enabled = true; + dfd_base_addr = base_addr; + dfd_chain_length = chain_length; + dfd_cache_dump = cache_dump; + + if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { + mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL); + sync_writel(DFD_V35_ENABLE, 0x1); + sync_writel(DFD_V35_TAP_NUMBER, 0xB); + sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); + sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); + + /* Cache dump only mode */ + sync_writel(DFD_V35_CTL, 0x1); + mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF); + mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL); + mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL); + mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL); + mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL); + + if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) { + sync_writel(DFD_HW_TRIGGER_MASK, 0xC); + mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); + } + } + dsbsy(); +} + +void dfd_resume(void) +{ + if (dfd_enabled == true) { + dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); + } +} diff --git a/plat/mediatek/drivers/dfd/mt8188/plat_dfd.h b/plat/mediatek/drivers/dfd/mt8188/plat_dfd.h new file mode 100644 index 000000000..5b98024a4 --- /dev/null +++ b/plat/mediatek/drivers/dfd/mt8188/plat_dfd.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DFD_H +#define PLAT_DFD_H + +#include <lib/mmio.h> +#include <platform_def.h> + +#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); dsbsy(); } while (0) + +#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150) +#define PLAT_MTK_DFD_READ_MAGIC (0x99716151) +#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152) + +#define MTK_DRM_LATCH_CTL1 (DRM_BASE + 0x40) +#define MTK_DRM_LATCH_CTL2 (DRM_BASE + 0x44) + +#define MTK_WDT_BASE (RGU_BASE) +#define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x10) +#define MTK_WDT_LATCH_CTL2 (MTK_WDT_BASE + 0x48) + +#define MCU_BIU_BASE (MCUCFG_BASE) +#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) +#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) +#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08) +#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C) +#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10) +#define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C) +#define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20) +#define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24) +#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28) +#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30) +#define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34) +#define DFD_INTERNAL_SW_NS_TRIGGER (MISC1_CFG_BASE + 0x3c) +#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48) +#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C) +#define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50) +#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58) +#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C) +#define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60) +#define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8) +#define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC) +#define DFD_READ_ADDR (MISC1_CFG_BASE + 0x1E8) +#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC) + +#define DFD_V35_ENABLE (MCU_BIU_BASE + 0xE0A8) +#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC) +#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0) +#define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4) +#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0) +#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4) +#define DFD_V50_GROUP_0_63_DIFF (MCU_BIU_BASE + 0xE2AC) + +#define DFD_O_PROTECT_EN_REG (0x10001220) +#define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C) +#define DFD_O_SET_BASEADDR_REG (0x10043000) +#define DFD_O_REG_0 (0x10001390) + +#define DFD_CACHE_DUMP_ENABLE (1U) +#define DFD_PARITY_ERR_TRIGGER (2U) + +#define DFD_V35_TAP_EN_VAL (0x43FF) +#define DFD_V35_SEQ0_0_VAL (0x63668820) +#define DFD_READ_ADDR_VAL (0x40000008) +#define DFD_CHAIN_LENGTH_VAL (0xFFFFFFFF) + +#define MTK_WDT_LATCH_CTL2_VAL (0x9507FFFF) +#define MTK_WDT_INTERVAL_VAL (0x6600000A) +#define MTK_DRM_LATCH_CTL2_VAL (0x950607D0) +#define MTK_DRM_LATCH_CTL2_CACHE_VAL (0x95065DC0) + +#define MTK_DRM_LATCH_CTL1_VAL (0x95000013) + +#endif /* PLAT_DFD_H */ diff --git a/plat/mediatek/drivers/dfd/rules.mk b/plat/mediatek/drivers/dfd/rules.mk new file mode 100644 index 000000000..60fbc88df --- /dev/null +++ b/plat/mediatek/drivers/dfd/rules.mk @@ -0,0 +1,17 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := mtk_dfd + +LOCAL_SRCS-y := ${LOCAL_DIR}/dfd.c +LOCAL_SRCS-y += ${LOCAL_DIR}/$(MTK_SOC)/plat_dfd.c + +PLAT_INCLUDES += -I${LOCAL_DIR} +PLAT_INCLUDES += -I${LOCAL_DIR}/$(MTK_SOC) + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/mt8195/drivers/dp/mt_dp.c b/plat/mediatek/drivers/dp/mt_dp.c index 5930cd553..8aa246f2b 100644 --- a/plat/mediatek/mt8195/drivers/dp/mt_dp.c +++ b/plat/mediatek/drivers/dp/mt_dp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,7 +15,7 @@ static uint32_t dp_write_sec_reg(uint32_t is_edp, uint32_t offset, uint32_t value, uint32_t mask) { - uint32_t reg = (is_edp != 0U) ? eDP_SEC_BASE : DP_SEC_BASE; + uint32_t reg = (is_edp != 0U) ? EDP_SEC_BASE : DP_SEC_BASE; mmio_clrsetbits_32(reg + offset, mask, value); @@ -53,7 +53,7 @@ int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val) if (ret == MTK_SIP_E_SUCCESS) { regmsk = (VIDEO_MUTE_SEL_SECURE_FLDMASK | - VIDEO_MUTE_SW_SECURE_FLDMASK); + VIDEO_MUTE_SW_SECURE_FLDMASK); if (para > 0U) { fldmask = VIDEO_MUTE_SW_SECURE_FLDMASK; } else { @@ -67,3 +67,13 @@ int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val) return ret; } + +u_register_t mtk_dp_sip_handler(u_register_t x1, u_register_t x2, + u_register_t x3, u_register_t x4, + void *handle, struct smccc_res *smccc_ret) +{ + uint32_t ret_val; + + return dp_secure_handler(x1, x2, &ret_val); +} +DECLARE_SMC_HANDLER(MTK_SIP_DP_CONTROL, mtk_dp_sip_handler); diff --git a/plat/mediatek/mt8195/drivers/dp/mt_dp.h b/plat/mediatek/drivers/dp/mt_dp.h index 8157598a8..d5dad2909 100644 --- a/plat/mediatek/mt8195/drivers/dp/mt_dp.h +++ b/plat/mediatek/drivers/dp/mt_dp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/drivers/dp/rules.mk b/plat/mediatek/drivers/dp/rules.mk new file mode 100644 index 000000000..786d5147e --- /dev/null +++ b/plat/mediatek/drivers/dp/rules.mk @@ -0,0 +1,14 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := dp +LOCAL_SRCS-y := $(LOCAL_DIR)/mt_dp.c + +PLAT_INCLUDES += -I${LOCAL_DIR} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/drivers/emi_mpu/emi_mpu.h new file mode 100644 index 000000000..66a369e95 --- /dev/null +++ b/plat/mediatek/drivers/emi_mpu/emi_mpu.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMI_MPU_H +#define EMI_MPU_H + +#include <emi_mpu_priv.h> +#include <platform_def.h> + +#define NO_PROTECTION (0) +#define SEC_RW (1) +#define SEC_RW_NSEC_R (2) +#define SEC_RW_NSEC_W (3) +#define SEC_R_NSEC_R (4) +#define FORBIDDEN (5) +#define SEC_R_NSEC_RW (6) + +#define LOCK (1) +#define UNLOCK (0) + +#if (EMI_MPU_DGROUP_NUM == 1) +#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \ +do { \ + apc_ary[1] = 0; \ + apc_ary[0] = \ + (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | \ + (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) | \ + (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \ + (((unsigned int) d1) << 3) | ((unsigned int) d0) | \ + ((unsigned int) lock << 31); \ +} while (0) +#elif (EMI_MPU_DGROUP_NUM == 2) +#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, \ + d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \ +do { \ + apc_ary[1] = \ + (((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) | \ + (((unsigned int) d13) << 15) | (((unsigned int) d12) << 12) | \ + (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) | \ + (((unsigned int) d9) << 3) | ((unsigned int) d8); \ + apc_ary[0] = \ + (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | \ + (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) | \ + (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \ + (((unsigned int) d1) << 3) | ((unsigned int) d0) | \ + ((unsigned int) lock << 31); \ +} while (0) +#endif + +struct emi_region_info_t { + unsigned long long start; + unsigned long long end; + unsigned int region; + unsigned int apc[EMI_MPU_DGROUP_NUM]; +}; + +int emi_mpu_init(void); +int emi_mpu_set_protection(struct emi_region_info_t *region_info); +void set_emi_mpu_regions(void); + +#endif diff --git a/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c b/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c new file mode 100644 index 000000000..27b2b07f9 --- /dev/null +++ b/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <string.h> +#include <common/debug.h> +#include <lib/mmio.h> +#include <emi_mpu.h> +#include <lib/mtk_init/mtk_init.h> + +#if ENABLE_EMI_MPU_SW_LOCK +static unsigned char region_lock_state[EMI_MPU_REGION_NUM]; +#endif + +#define EMI_MPU_START_MASK (0x00FFFFFF) +#define EMI_MPU_END_MASK (0x00FFFFFF) +#define EMI_MPU_APC_SW_LOCK_MASK (0x00FFFFFF) +#define EMI_MPU_APC_HW_LOCK_MASK (0x80FFFFFF) + +static int _emi_mpu_set_protection(unsigned int start, unsigned int end, + unsigned int apc) +{ + unsigned int dgroup; + unsigned int region; + + region = (start >> 24) & 0xFF; + start &= EMI_MPU_START_MASK; + dgroup = (end >> 24) & 0xFF; + end &= EMI_MPU_END_MASK; + + if ((region >= EMI_MPU_REGION_NUM) || (dgroup > EMI_MPU_DGROUP_NUM)) { + WARN("invalid region, domain\n"); + return -1; + } + +#if ENABLE_EMI_MPU_SW_LOCK + if (region_lock_state[region] == 1) { + WARN("invalid region\n"); + return -1; + } + + if ((dgroup == 0) && ((apc >> 31) & 0x1)) { + region_lock_state[region] = 1; + } + + apc &= EMI_MPU_APC_SW_LOCK_MASK; +#else + apc &= EMI_MPU_APC_HW_LOCK_MASK; +#endif + + if ((start >= DRAM_OFFSET) && (end >= start)) { + start -= DRAM_OFFSET; + end -= DRAM_OFFSET; + } else { + WARN("invalid range\n"); + return -1; + } + + mmio_write_32(EMI_MPU_SA(region), start); + mmio_write_32(EMI_MPU_EA(region), end); + mmio_write_32(EMI_MPU_APC(region, dgroup), apc); + +#if defined(SUB_EMI_MPU_BASE) + mmio_write_32(SUB_EMI_MPU_SA(region), start); + mmio_write_32(SUB_EMI_MPU_EA(region), end); + mmio_write_32(SUB_EMI_MPU_APC(region, dgroup), apc); +#endif + return 0; +} + +static void dump_emi_mpu_regions(void) +{ + int region, i; + + /* Only dump 8 regions(max: EMI_MPU_REGION_NUM --> 32) */ + for (region = 0; region < 8; ++region) { + INFO("region %d:\n", region); + INFO("\tsa: 0x%x, ea: 0x%x\n", + mmio_read_32(EMI_MPU_SA(region)), mmio_read_32(EMI_MPU_EA(region))); + + for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i) { + INFO("\tapc%d: 0x%x\n", i, mmio_read_32(EMI_MPU_APC(region, i))); + } + } +} + +int emi_mpu_set_protection(struct emi_region_info_t *region_info) +{ + unsigned int start, end; + int i; + + if (region_info->region >= EMI_MPU_REGION_NUM) { + WARN("invalid region\n"); + return -1; + } + + start = (unsigned int)(region_info->start >> EMI_MPU_ALIGN_BITS) | + (region_info->region << 24); + + for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) { + end = (unsigned int)(region_info->end >> EMI_MPU_ALIGN_BITS) | (i << 24); + + if (_emi_mpu_set_protection(start, end, region_info->apc[i]) < 0) { + WARN("Failed to set emi mpu protection(%d, %d, %d)\n", + start, end, region_info->apc[i]); + } + } + + return 0; +} + +int emi_mpu_init(void) +{ + INFO("[%s] emi mpu initialization\n", __func__); + + set_emi_mpu_regions(); + dump_emi_mpu_regions(); + + return 0; +} +MTK_PLAT_SETUP_0_INIT(emi_mpu_init); diff --git a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c new file mode 100644 index 000000000..558533d58 --- /dev/null +++ b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <emi_mpu.h> + +void set_emi_mpu_regions(void) +{ + /* TODO: set emi mpu region */ + INFO("%s, emi mpu is not setting currently\n", __func__); +} diff --git a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h new file mode 100644 index 000000000..1ee7397cf --- /dev/null +++ b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMI_MPU_PRIV_H +#define EMI_MPU_PRIV_H + +#define ENABLE_EMI_MPU_SW_LOCK (1) + +#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000) +#define EMI_MPU_DBG (EMI_MPU_BASE + 0x004) +#define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100) +#define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200) +#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region * 4)) +#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region * 4)) +#define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300) +#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100)) +#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800) +#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) +#define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900) +#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) + +#define SUB_EMI_MPU_CTRL (SUB_EMI_MPU_BASE + 0x000) +#define SUB_EMI_MPU_DBG (SUB_EMI_MPU_BASE + 0x004) +#define SUB_EMI_MPU_SA0 (SUB_EMI_MPU_BASE + 0x100) +#define SUB_EMI_MPU_EA0 (SUB_EMI_MPU_BASE + 0x200) +#define SUB_EMI_MPU_SA(region) (SUB_EMI_MPU_SA0 + (region * 4)) +#define SUB_EMI_MPU_EA(region) (SUB_EMI_MPU_EA0 + (region * 4)) +#define SUB_EMI_MPU_APC0 (SUB_EMI_MPU_BASE + 0x300) +#define SUB_EMI_MPU_APC(region, dgroup) (SUB_EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100)) +#define SUB_EMI_MPU_CTRL_D0 (SUB_EMI_MPU_BASE + 0x800) +#define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) +#define SUB_EMI_RG_MASK_D0 (SUB_EMI_MPU_BASE + 0x900) +#define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) + +#define EMI_MPU_DOMAIN_NUM (16) +#define EMI_MPU_REGION_NUM (32) +#define EMI_MPU_ALIGN_BITS (16) +#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS) + +#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8) + +#endif diff --git a/plat/mediatek/drivers/emi_mpu/rules.mk b/plat/mediatek/drivers/emi_mpu/rules.mk new file mode 100644 index 000000000..ed3d77719 --- /dev/null +++ b/plat/mediatek/drivers/emi_mpu/rules.mk @@ -0,0 +1,16 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := emi_mpu +LOCAL_SRCS-y := $(LOCAL_DIR)/emi_mpu_common.c +LOCAL_SRCS-y += ${LOCAL_DIR}/${MTK_SOC}/emi_mpu.c + +PLAT_INCLUDES += -I${LOCAL_DIR} +PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/common/drivers/gic600/mt_gic_v3.c b/plat/mediatek/drivers/gic600/mt_gic_v3.c index ae8d697a5..cca5d0a56 100644 --- a/plat/mediatek/common/drivers/gic600/mt_gic_v3.c +++ b/plat/mediatek/drivers/gic600/mt_gic_v3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ #include <bl31/interrupt_mgmt.h> #include <common/bl_common.h> #include <common/debug.h> - +#include <lib/mtk_init/mtk_init.h> #include <mt_gic_v3.h> #include <mtk_plat_common.h> #include <plat/common/platform.h> @@ -194,3 +194,15 @@ void mt_irq_set_pending(uint32_t irq) mmio_write_32(BASE_GICD_BASE + GICD_ISPENDR + irq / 32 * 4, bit); } + +int mt_gic_one_init(void) +{ + INFO("[%s] GIC initialization\n", __func__); + + /* Initialize the GIC driver, CPU and distributor interfaces */ + mt_gic_driver_init(); + mt_gic_init(); + + return 0; +} +MTK_PLAT_SETUP_0_INIT(mt_gic_one_init); diff --git a/plat/mediatek/common/drivers/gic600/mt_gic_v3.h b/plat/mediatek/drivers/gic600/mt_gic_v3.h index c4ab44fa3..31513ef41 100644 --- a/plat/mediatek/common/drivers/gic600/mt_gic_v3.h +++ b/plat/mediatek/drivers/gic600/mt_gic_v3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,5 +23,6 @@ void gic_sgi_save_all(void); void gic_sgi_restore_all(void); uint32_t mt_irq_get_pending(uint32_t irq); void mt_irq_set_pending(uint32_t irq); +int mt_gic_one_init(void); #endif /* MT_GIC_V3_H */ diff --git a/plat/mediatek/drivers/gic600/rules.mk b/plat/mediatek/drivers/gic600/rules.mk new file mode 100644 index 000000000..3070591ed --- /dev/null +++ b/plat/mediatek/drivers/gic600/rules.mk @@ -0,0 +1,14 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := gic600 +LOCAL_SRCS-y := $(LOCAL_DIR)/mt_gic_v3.c + +PLAT_INCLUDES += -I${LOCAL_DIR} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/gpio/mt8188/mtgpio.c b/plat/mediatek/drivers/gpio/mt8188/mtgpio.c new file mode 100644 index 000000000..9e9fc5de1 --- /dev/null +++ b/plat/mediatek/drivers/gpio/mt8188/mtgpio.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <mtgpio.h> +#include <platform_def.h> + +uintptr_t mt_gpio_find_reg_addr(uint32_t pin) +{ + uintptr_t reg_addr = 0U; + struct mt_pin_info gpio_info; + + assert(pin < MAX_GPIO_PIN); + + gpio_info = mt_pin_infos[pin]; + + switch (gpio_info.base & 0x0f) { + case 0: + reg_addr = IOCFG_RM_BASE; + break; + case 1: + reg_addr = IOCFG_LT_BASE; + break; + case 2: + reg_addr = IOCFG_LM_BASE; + break; + case 3: + reg_addr = IOCFG_RT_BASE; + break; + default: + break; + } + + return reg_addr; +} diff --git a/plat/mediatek/drivers/gpio/mt8188/mtgpio.h b/plat/mediatek/drivers/gpio/mt8188/mtgpio.h new file mode 100644 index 000000000..32a460838 --- /dev/null +++ b/plat/mediatek/drivers/gpio/mt8188/mtgpio.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_GPIO_H +#define MT_GPIO_H + +#include <mtgpio_common.h> + +/* Enumeration for GPIO pin */ +typedef enum GPIO_PIN { + GPIO_UNSUPPORTED = -1, + GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, + GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, + GPIO15, GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, + GPIO23, GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, + GPIO31, GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, + GPIO39, GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, + GPIO47, GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, + GPIO55, GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, + GPIO63, GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, + GPIO71, GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, + GPIO79, GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, + GPIO87, GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, + GPIO95, GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, + GPIO103, GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, + GPIO111, GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, + GPIO119, GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, + GPIO127, GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, + GPIO135, GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, + GPIO143, GPIO144, GPIO145, GPIO146, GPIO147, GPIO148, GPIO149, GPIO150, + GPIO151, GPIO152, GPIO153, GPIO154, GPIO155, GPIO156, GPIO157, GPIO158, + GPIO159, GPIO160, GPIO161, GPIO162, GPIO163, GPIO164, GPIO165, GPIO166, + GPIO167, GPIO168, GPIO169, GPIO170, GPIO171, GPIO172, GPIO173, GPIO174, + GPIO175, GPIO176, + MT_GPIO_BASE_MAX +} GPIO_PIN; + +static const struct mt_pin_info mt_pin_infos[] = { + PIN(0, 0, 6, 0x30, 0xb0), + PIN(1, 0, 7, 0x30, 0xb0), + PIN(2, 0, 8, 0x30, 0xb0), + PIN(3, 0, 9, 0x30, 0xb0), + PIN(4, 0, 10, 0x30, 0xb0), + PIN(5, 0, 11, 0x30, 0xb0), + PIN(6, 0, 12, 0x30, 0xb0), + PIN(7, 0, 13, 0x30, 0xb0), + PIN(8, 0, 14, 0x30, 0xb0), + PIN(9, 0, 15, 0x30, 0xb0), + PIN(10, 0, 16, 0x30, 0xb0), + PIN(11, 0, 17, 0x30, 0xb0), + PIN(12, 0, 12, 0x31, 0xa0), + PIN(13, 0, 13, 0x31, 0xa0), + PIN(14, 0, 14, 0x31, 0xa0), + PIN(15, 0, 15, 0x31, 0xa0), + PIN(16, 0, 1, 0x22, 0x50), + PIN(17, 0, 2, 0x22, 0x50), + PIN(18, 0, 3, 0x23, 0x60), + PIN(19, 0, 4, 0x23, 0x60), + PIN(20, 0, 5, 0x23, 0x60), + PIN(21, 0, 6, 0x23, 0x60), + PIN(22, 0, 0, 0x23, 0x60), + PIN(23, 0, 1, 0x23, 0x60), + PIN(24, 0, 2, 0x23, 0x60), + PIN(25, 0, 3, 0x30, 0xb0), + PIN(26, 0, 2, 0x30, 0xb0), + PIN(27, 0, 5, 0x30, 0xb0), + PIN(28, 0, 4, 0x30, 0xb0), + PIN(29, 0, 0, 0x30, 0xb0), + PIN(30, 0, 1, 0x30, 0xb0), + PIN(31, 0, 11, 0x30, 0xc0), + PIN(32, 0, 10, 0x30, 0xc0), + PIN(33, 0, 13, 0x30, 0xc0), + PIN(34, 0, 12, 0x30, 0xc0), + PIN(35, 0, 15, 0x30, 0xc0), + PIN(36, 0, 14, 0x30, 0xc0), + PIN(37, 0, 21, 0x30, 0xb0), + PIN(38, 0, 18, 0x30, 0xb0), + PIN(39, 0, 19, 0x30, 0xb0), + PIN(40, 0, 20, 0x30, 0xb0), + PIN(41, 0, 22, 0x30, 0xb0), + PIN(42, 1, 12, 0x31, 0xc0), + PIN(43, 1, 13, 0x31, 0xc0), + PIN(44, 1, 14, 0x31, 0xc0), + PIN(45, 1, 15, 0x31, 0xc0), + PIN(46, 0, 0, 0x22, 0x50), + PIN(47, 0, 25, 0x30, 0xb0), + PIN(48, 0, 24, 0x30, 0xb0), + PIN(49, 0, 23, 0x30, 0xb0), + PIN(50, 0, 5, 0x22, 0x50), + PIN(51, 0, 4, 0x22, 0x50), + PIN(52, 0, 3, 0x22, 0x50), + PIN(53, 0, 6, 0x22, 0x50), + PIN(54, 0, 7, 0x22, 0x50), + PIN(55, 0, 26, 0x30, 0xb0), + PIN(56, 0, 29, 0x30, 0xb0), + PIN(57, 0, 6, 0x31, 0xb0), + PIN(58, 0, 9, 0x31, 0xb0), + PIN(59, 0, 27, 0x30, 0xb0), + PIN(60, 0, 30, 0x30, 0xb0), + PIN(61, 0, 28, 0x30, 0xb0), + PIN(62, 0, 31, 0x30, 0xb0), + PIN(63, 0, 7, 0x31, 0xb0), + PIN(64, 0, 10, 0x31, 0xb0), + PIN(65, 0, 7, 0x23, 0x60), + PIN(66, 0, 9, 0x23, 0x60), + PIN(67, 0, 8, 0x23, 0x60), + PIN(68, 0, 10, 0x23, 0x60), + PIN(69, 0, 1, 0x30, 0xc0), + PIN(70, 0, 0, 0x30, 0xc0), + PIN(71, 0, 5, 0x30, 0xc0), + PIN(72, 0, 4, 0x30, 0xc0), + PIN(73, 0, 2, 0x30, 0xc0), + PIN(74, 0, 3, 0x30, 0xc0), + PIN(75, 0, 7, 0x30, 0xc0), + PIN(76, 0, 6, 0x30, 0xc0), + PIN(77, 0, 9, 0x30, 0xc0), + PIN(78, 0, 8, 0x30, 0xc0), + PIN(79, 0, 12, 0x23, 0x60), + PIN(80, 0, 11, 0x23, 0x60), + PIN(81, 0, 14, 0x23, 0x60), + PIN(82, 0, 13, 0x23, 0x60), + PIN(83, 0, 16, 0x31, 0xb0), + PIN(84, 0, 15, 0x31, 0xb0), + PIN(85, 0, 17, 0x31, 0xb0), + PIN(86, 0, 19, 0x31, 0xb0), + PIN(87, 0, 18, 0x31, 0xb0), + PIN(88, 0, 20, 0x31, 0xb0), + PIN(89, 0, 22, 0x31, 0xb0), + PIN(90, 0, 21, 0x31, 0xb0), + PIN(91, 0, 23, 0x31, 0xb0), + PIN(92, 0, 3, 0x31, 0xb0), + PIN(93, 0, 2, 0x31, 0xb0), + PIN(94, 0, 5, 0x31, 0xb0), + PIN(95, 0, 4, 0x31, 0xb0), + PIN(96, 0, 31, 0x31, 0xa0), + PIN(97, 0, 0, 0x31, 0xb0), + PIN(98, 0, 8, 0x31, 0xb0), + PIN(99, 0, 30, 0x31, 0xa0), + PIN(100, 0, 1, 0x31, 0xb0), + PIN(101, 0, 0, 0x31, 0xa0), + PIN(102, 0, 5, 0x31, 0xa0), + PIN(103, 0, 3, 0x31, 0xa0), + PIN(104, 0, 4, 0x31, 0xa0), + PIN(105, 0, 1, 0x31, 0xa0), + PIN(106, 0, 2, 0x31, 0xa0), + PIN(107, 0, 21, 0x31, 0xa0), + PIN(108, 0, 16, 0x31, 0xa0), + PIN(109, 0, 22, 0x31, 0xa0), + PIN(110, 0, 17, 0x31, 0xa0), + PIN(111, 0, 18, 0x31, 0xa0), + PIN(112, 0, 19, 0x31, 0xa0), + PIN(113, 0, 20, 0x31, 0xa0), + PIN(114, 0, 28, 0x31, 0xa0), + PIN(115, 0, 23, 0x31, 0xa0), + PIN(116, 0, 29, 0x31, 0xa0), + PIN(117, 0, 24, 0x31, 0xa0), + PIN(118, 0, 25, 0x31, 0xa0), + PIN(119, 0, 26, 0x31, 0xa0), + PIN(120, 0, 27, 0x31, 0xa0), + PIN(121, 0, 8, 0x22, 0x50), + PIN(122, 0, 11, 0x22, 0x50), + PIN(123, 0, 10, 0x22, 0x50), + PIN(124, 0, 9, 0x22, 0x50), + PIN(125, 0, 6, 0x31, 0xa0), + PIN(126, 0, 7, 0x31, 0xa0), + PIN(127, 0, 8, 0x31, 0xa0), + PIN(128, 0, 9, 0x31, 0xa0), + PIN(129, 0, 10, 0x31, 0xa0), + PIN(130, 0, 11, 0x31, 0xa0), + PIN(131, 1, 1, 0x30, 0xd0), + PIN(132, 1, 2, 0x30, 0xd0), + PIN(133, 1, 9, 0x30, 0xd0), + PIN(134, 1, 10, 0x30, 0xd0), + PIN(135, 1, 11, 0x30, 0xd0), + PIN(136, 1, 12, 0x30, 0xd0), + PIN(137, 1, 13, 0x30, 0xd0), + PIN(138, 1, 14, 0x30, 0xd0), + PIN(139, 1, 15, 0x30, 0xd0), + PIN(140, 1, 16, 0x30, 0xd0), + PIN(141, 1, 3, 0x30, 0xd0), + PIN(142, 1, 4, 0x30, 0xd0), + PIN(143, 1, 5, 0x30, 0xd0), + PIN(144, 1, 6, 0x30, 0xd0), + PIN(145, 1, 7, 0x30, 0xd0), + PIN(146, 1, 8, 0x30, 0xd0), + PIN(147, 1, 18, 0x30, 0xd0), + PIN(148, 1, 19, 0x30, 0xd0), + PIN(149, 1, 17, 0x30, 0xd0), + PIN(150, 1, 0, 0x30, 0xd0), + PIN(151, 1, 9, 0x31, 0xc0), + PIN(152, 1, 8, 0x31, 0xc0), + PIN(153, 1, 7, 0x31, 0xc0), + PIN(154, 1, 6, 0x31, 0xc0), + PIN(155, 1, 11, 0x31, 0xc0), + PIN(156, 1, 1, 0x31, 0xc0), + PIN(157, 1, 0, 0x31, 0xc0), + PIN(158, 1, 5, 0x31, 0xc0), + PIN(159, 1, 4, 0x31, 0xc0), + PIN(160, 1, 3, 0x31, 0xc0), + PIN(161, 1, 2, 0x31, 0xc0), + PIN(162, 1, 10, 0x31, 0xc0), + PIN(163, 1, 1, 0x23, 0x70), + PIN(164, 1, 0, 0x23, 0x70), + PIN(165, 1, 2, 0x23, 0x70), + PIN(166, 1, 3, 0x23, 0x70), + PIN(167, 1, 4, 0x23, 0x70), + PIN(168, 1, 5, 0x23, 0x70), + PIN(169, 1, 1, 0x22, 0x60), + PIN(170, 1, 0, 0x22, 0x60), + PIN(171, 1, 2, 0x22, 0x60), + PIN(172, 1, 3, 0x22, 0x60), + PIN(173, 1, 4, 0x22, 0x60), + PIN(174, 1, 5, 0x22, 0x60), + PIN(175, 0, 11, 0x31, 0xb0), + PIN(176, 0, 12, 0x31, 0xb0), +}; + +#endif /* MT_GPIO_H */ diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.c b/plat/mediatek/drivers/gpio/mtgpio_common.c index 89977a550..bad0190d5 100644 --- a/plat/mediatek/common/drivers/gpio/mtgpio_common.c +++ b/plat/mediatek/drivers/gpio/mtgpio_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include <drivers/delay_timer.h> #include <drivers/gpio.h> #include <lib/mmio.h> +#include <lib/mtk_init/mtk_init.h> #include <mtgpio.h> #include <platform_def.h> @@ -292,7 +293,10 @@ const gpio_ops_t mtgpio_ops = { .get_pull = mt_get_gpio_pull, }; -void mt_gpio_init(void) +int mt_gpio_init(void) { gpio_init(&mtgpio_ops); + + return 0; } +MTK_PLAT_SETUP_0_INIT(mt_gpio_init); diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.h b/plat/mediatek/drivers/gpio/mtgpio_common.h index bf5105571..d6b858c86 100644 --- a/plat/mediatek/common/drivers/gpio/mtgpio_common.h +++ b/plat/mediatek/drivers/gpio/mtgpio_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -104,6 +104,6 @@ struct mt_pin_info { uint16_t offset; }; -void mt_gpio_init(void); +int mt_gpio_init(void); uintptr_t mt_gpio_find_reg_addr(uint32_t pin); #endif /* MT_GPIO_COMMON_H */ diff --git a/plat/mediatek/drivers/gpio/rules.mk b/plat/mediatek/drivers/gpio/rules.mk new file mode 100644 index 000000000..78061a86f --- /dev/null +++ b/plat/mediatek/drivers/gpio/rules.mk @@ -0,0 +1,18 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := gpio + +LOCAL_SRCS-y := drivers/gpio/gpio.c +LOCAL_SRCS-y += ${LOCAL_DIR}/mtgpio_common.c +LOCAL_SRCS-y += ${LOCAL_DIR}/${MTK_SOC}/mtgpio.c + +PLAT_INCLUDES += -I${LOCAL_DIR} +PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c new file mode 100644 index 000000000..1d6863ff5 --- /dev/null +++ b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <mtk_iommu_plat.h> +#include <mtk_mmap_pool.h> +#include <platform_def.h> + +/* mm iommu */ +#define SMI_L0_ID (0) +#define SMI_L1_ID (1) +#define SMI_L2_ID (2) +#define SMI_L3_ID (3) +#define SMI_L4_ID (4) +#define SMI_L5_ID (5) +#define SMI_L6_ID (6) +#define SMI_L7_ID (7) +#define SMI_L9_ID (8) +#define SMI_L10_ID (9) +#define SMI_L11A_ID (10) +#define SMI_L11B_ID (11) +#define SMI_L11C_ID (12) +#define SMI_L12_ID (13) +#define SMI_L13_ID (14) +#define SMI_L14_ID (15) +#define SMI_L15_ID (16) +#define SMI_L16A_ID (17) +#define SMI_L16B_ID (18) +#define SMI_L17A_ID (19) +#define SMI_L17B_ID (20) +#define SMI_L19_ID (21) +#define SMI_L21_ID (22) +#define SMI_L23_ID (23) +#define SMI_L27_ID (24) +#define SMI_L28_ID (25) + +/* infra iommu */ +#define PERI_MST_PROT (0x710) +#define PERICFG_AO_IOMMU_1 (0x714) +#define MMU_DEV_PCIE_0 (0) +#define IFR_CFG_GROUP_NUM (1) + +static struct mtk_smi_larb_config mt8188_larb_cfg[SMI_LARB_NUM] = { + [SMI_L0_ID] = LARB_CFG_ENTRY(SMI_LARB_0_BASE, 7, 0), + [SMI_L1_ID] = LARB_CFG_ENTRY(SMI_LARB_1_BASE, 7, 0), + [SMI_L2_ID] = LARB_CFG_ENTRY(SMI_LARB_2_BASE, 5, 0), + [SMI_L3_ID] = LARB_CFG_ENTRY(SMI_LARB_3_BASE, 7, 0), + [SMI_L4_ID] = LARB_CFG_ENTRY(SMI_LARB_4_BASE, 7, 0), + [SMI_L5_ID] = LARB_CFG_ENTRY(SMI_LARB_5_BASE, 8, 0), + [SMI_L6_ID] = LARB_CFG_ENTRY(SMI_LARB_6_BASE, 4, 0), + [SMI_L7_ID] = LARB_CFG_ENTRY(SMI_LARB_7_BASE, 3, 0), + [SMI_L9_ID] = LARB_CFG_ENTRY(SMI_LARB_9_BASE, 25, 0), + [SMI_L10_ID] = LARB_CFG_ENTRY(SMI_LARB_10_BASE, 20, 0), + [SMI_L11A_ID] = LARB_CFG_ENTRY(SMI_LARB_11A_BASE, 30, 0), + [SMI_L11B_ID] = LARB_CFG_ENTRY(SMI_LARB_11B_BASE, 30, 0), + [SMI_L11C_ID] = LARB_CFG_ENTRY(SMI_LARB_11C_BASE, 30, 0), + [SMI_L12_ID] = LARB_CFG_ENTRY(SMI_LARB_12_BASE, 16, 0), + [SMI_L13_ID] = LARB_CFG_ENTRY(SMI_LARB_13_BASE, 24, 0), + [SMI_L14_ID] = LARB_CFG_ENTRY(SMI_LARB_14_BASE, 23, 0), + [SMI_L15_ID] = LARB_CFG_ENTRY(SMI_LARB_15_BASE, 19, 0), + [SMI_L16A_ID] = LARB_CFG_ENTRY(SMI_LARB_16A_BASE, 17, 0), + [SMI_L16B_ID] = LARB_CFG_ENTRY(SMI_LARB_16B_BASE, 17, 0), + [SMI_L17A_ID] = LARB_CFG_ENTRY(SMI_LARB_17A_BASE, 7, 0), + [SMI_L17B_ID] = LARB_CFG_ENTRY(SMI_LARB_17B_BASE, 7, 0), + /* venc nbm ports (5/6/11/15/16/17) to sram */ + [SMI_L19_ID] = LARB_CFG_ENTRY_WITH_PATH(SMI_LARB_19_BASE, 27, 0, 0x38860), + [SMI_L21_ID] = LARB_CFG_ENTRY(SMI_LARB_21_BASE, 11, 0), + [SMI_L23_ID] = LARB_CFG_ENTRY(SMI_LARB_23_BASE, 9, 0), + [SMI_L27_ID] = LARB_CFG_ENTRY(SMI_LARB_27_BASE, 4, 0), + [SMI_L28_ID] = LARB_CFG_ENTRY(SMI_LARB_28_BASE, 0, 0), +}; + +static bool is_protected; + +static uint32_t mt8188_ifr_mst_cfg_base[IFR_CFG_GROUP_NUM] = { + PERICFG_AO_BASE, +}; +static uint32_t mt8188_ifr_mst_cfg_offs[IFR_CFG_GROUP_NUM] = { + PERICFG_AO_IOMMU_1, +}; +static struct mtk_ifr_mst_config mt8188_ifr_mst_cfg[MMU_DEV_NUM] = { + [MMU_DEV_PCIE_0] = IFR_MST_CFG_ENTRY(0, 18), +}; + +struct mtk_smi_larb_config *g_larb_cfg = &mt8188_larb_cfg[0]; +struct mtk_ifr_mst_config *g_ifr_mst_cfg = &mt8188_ifr_mst_cfg[0]; +uint32_t *g_ifr_mst_cfg_base = &mt8188_ifr_mst_cfg_base[0]; +uint32_t *g_ifr_mst_cfg_offs = &mt8188_ifr_mst_cfg_offs[0]; + +/* Protect infra iommu enable setting registers as secure access. */ +void mtk_infra_iommu_enable_protect(void) +{ + if (!is_protected) { + mmio_write_32(PERICFG_AO_BASE + PERI_MST_PROT, 0xffffffff); + is_protected = true; + } +} diff --git a/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h new file mode 100644 index 000000000..a59e0c78f --- /dev/null +++ b/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IOMMU_PLAT_H +#define IOMMU_PLAT_H + +#include <mtk_iommu_priv.h> + +/* mm iommu */ +#define SMI_LARB_NUM (26) +extern struct mtk_smi_larb_config *g_larb_cfg; + +/* infra iommu */ +#define MMU_DEV_NUM (1) +extern struct mtk_ifr_mst_config *g_ifr_mst_cfg; +extern uint32_t *g_ifr_mst_cfg_base; +extern uint32_t *g_ifr_mst_cfg_offs; + +extern void mtk_infra_iommu_enable_protect(void); + +#endif /* IOMMU_PLAT_H */ diff --git a/plat/mediatek/drivers/iommu/mtk_iommu_priv.h b/plat/mediatek/drivers/iommu/mtk_iommu_priv.h new file mode 100644 index 000000000..3404d313b --- /dev/null +++ b/plat/mediatek/drivers/iommu/mtk_iommu_priv.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IOMMU_PRIV_H +#define IOMMU_PRIV_H + +#include <common/debug.h> +#include <lib/mmio.h> +#include <mtk_sip_svc.h> + +#define LARB_CFG_ENTRY(bs, p_nr, dom) \ + { .base = (bs), .port_nr = (p_nr), \ + .dom_id = (dom), .to_sram = 0, } + +#define LARB_CFG_ENTRY_WITH_PATH(bs, p_nr, dom, sram) \ + { .base = (bs), .port_nr = (p_nr), \ + .dom_id = (dom), .to_sram = (sram), } + +#define IFR_MST_CFG_ENTRY(idx, bit) \ + { .cfg_addr_idx = (idx), .r_mmu_en_bit = (bit), } + +enum IOMMU_ATF_CMD { + IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to enable iommu */ + IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */ + IOMMU_ATF_CMD_COUNT, +}; + +struct mtk_smi_larb_config { + uint32_t base; + uint32_t port_nr; + uint32_t dom_id; + uint32_t to_sram; + uint32_t sec_en_msk; +}; + +struct mtk_ifr_mst_config { + uint8_t cfg_addr_idx; + uint8_t r_mmu_en_bit; +}; + +#endif /* IOMMU_PRIV_H */ diff --git a/plat/mediatek/drivers/iommu/mtk_iommu_smc.c b/plat/mediatek/drivers/iommu/mtk_iommu_smc.c new file mode 100644 index 000000000..9762d0b2c --- /dev/null +++ b/plat/mediatek/drivers/iommu/mtk_iommu_smc.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stddef.h> +#include <mtk_iommu_plat.h> + +/* defination */ +/* smi larb */ +#define SMI_LARB_NON_SEC_CON(port) (0x380 + ((port) << 2)) +#define PATH_SEL_MASK (0xf0000) /* to sram (INT) */ +#define SMI_LARB_SEC_CON_INT(port) (0xf00 + ((port) << 2)) +#define SMI_LARB_SEC_CON(port) (0xf80 + ((port) << 2)) +#define MMU_MASK BIT(0) +#define MMU_EN(en) ((!!(en)) << 0) +#define SEC_MASK BIT(1) +#define SEC_EN(en) ((!!(en)) << 1) +#define DOMAIN_MASK (0x1f << 4) +#define SMI_MMU_EN(port) (0x1 << (port)) + +/* infra master */ +#define IFR_CFG_MMU_EN_MSK(r_bit) (0x3 << (r_bit)) + +/* smi larb configure */ +/* + * If multimedia security config is enabled, the SMI config register must be + * configurated in security world. + * And the SRAM path is also configurated here to enhance security. + */ +static void mtk_smi_larb_port_config_to_sram( + const struct mtk_smi_larb_config *larb, + uint32_t port_id) +{ + mmio_clrbits_32(larb->base + SMI_LARB_SEC_CON_INT(port_id), + MMU_MASK | SEC_MASK | DOMAIN_MASK); + + mmio_setbits_32(larb->base + SMI_LARB_NON_SEC_CON(port_id), + PATH_SEL_MASK); +} + +static void mtk_smi_port_config(const struct mtk_smi_larb_config *larb, + uint32_t port_id, uint8_t mmu_en, uint8_t sec_en) +{ + mmio_clrsetbits_32(larb->base + SMI_LARB_SEC_CON(port_id), + MMU_MASK | SEC_MASK | DOMAIN_MASK, + MMU_EN(mmu_en) | SEC_EN(sec_en)); +} + +static int mtk_smi_larb_port_config_sec(uint32_t larb_id, uint32_t mmu_en_msk) +{ + uint32_t port_id, port_nr; + const struct mtk_smi_larb_config *larb; + uint32_t to_sram; + uint8_t mmu_en; + + if (larb_id >= SMI_LARB_NUM) { + return MTK_SIP_E_INVALID_PARAM; + } + + larb = &g_larb_cfg[larb_id]; + port_nr = larb->port_nr; + to_sram = larb->to_sram; + + for (port_id = 0; port_id < port_nr; port_id++) { + if ((to_sram & BIT(port_id)) > 0U) { + mtk_smi_larb_port_config_to_sram(larb, port_id); + continue; + } + mmu_en = !!(mmu_en_msk & SMI_MMU_EN(port_id)); + mtk_smi_port_config(larb, port_id, mmu_en, 0); + } + + return MTK_SIP_E_SUCCESS; +} + +static int mtk_infra_master_config_sec(uint32_t dev_id, uint32_t enable) +{ + const struct mtk_ifr_mst_config *ifr_cfg; + uint32_t reg_addr; + + mtk_infra_iommu_enable_protect(); + + if (dev_id >= MMU_DEV_NUM) { + return MTK_SIP_E_NOT_SUPPORTED; + } + + ifr_cfg = &g_ifr_mst_cfg[dev_id]; + reg_addr = g_ifr_mst_cfg_base[(ifr_cfg->cfg_addr_idx)] + + g_ifr_mst_cfg_offs[(ifr_cfg->cfg_addr_idx)]; + + if (enable > 0U) { + mmio_setbits_32(reg_addr, IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit)); + } else { + mmio_clrbits_32(reg_addr, IFR_CFG_MMU_EN_MSK(ifr_cfg->r_mmu_en_bit)); + } + + return MTK_SIP_E_SUCCESS; +} + +static u_register_t mtk_iommu_handler(u_register_t x1, u_register_t x2, + u_register_t x3, u_register_t x4, + void *handle, struct smccc_res *smccc_ret) +{ + uint32_t cmd_id = x1, mdl_id = x2, val = x3; + int ret = MTK_SIP_E_NOT_SUPPORTED; + + (void)x4; + (void)handle; + + switch (cmd_id) { + case IOMMU_ATF_CMD_CONFIG_SMI_LARB: + ret = mtk_smi_larb_port_config_sec(mdl_id, val); + break; + case IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU: + ret = mtk_infra_master_config_sec(mdl_id, val); + break; + default: + break; + } + + return ret; +} +DECLARE_SMC_HANDLER(MTK_SIP_IOMMU_CONTROL, mtk_iommu_handler); diff --git a/plat/mediatek/drivers/iommu/rules.mk b/plat/mediatek/drivers/iommu/rules.mk new file mode 100644 index 000000000..5490f4120 --- /dev/null +++ b/plat/mediatek/drivers/iommu/rules.mk @@ -0,0 +1,17 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := mtk_iommu + +LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_iommu_smc.c +LOCAL_SRCS-y += ${LOCAL_DIR}/${MTK_SOC}/mtk_iommu_plat.c + +PLAT_INCLUDES += -I${LOCAL_DIR} +PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/mcusys/mcusys.c b/plat/mediatek/drivers/mcusys/mcusys.c new file mode 100644 index 000000000..63edb233a --- /dev/null +++ b/plat/mediatek/drivers/mcusys/mcusys.c @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> +#include <mtk_mmap_pool.h> +#include <platform_def.h> + +static const mmap_region_t mcusys_mmap[] MTK_MMAP_SECTION = { + MAP_REGION_FLAT(MCUCFG_BASE, MCUCFG_REG_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + {0} +}; +DECLARE_MTK_MMAP_REGIONS(mcusys_mmap); diff --git a/plat/mediatek/drivers/mcusys/rules.mk b/plat/mediatek/drivers/mcusys/rules.mk new file mode 100644 index 000000000..54389988d --- /dev/null +++ b/plat/mediatek/drivers/mcusys/rules.mk @@ -0,0 +1,15 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := mcusys + +PLAT_INCLUDES += -I$(LOCAL_DIR)/$(MCUSYS_VERSION) + +LOCAL_SRCS-y := $(LOCAL_DIR)/mcusys.c + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/mcusys/v1/mcucfg.h b/plat/mediatek/drivers/mcusys/v1/mcucfg.h new file mode 100644 index 000000000..7aced5aef --- /dev/null +++ b/plat/mediatek/drivers/mcusys/v1/mcucfg.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MCUCFG_V1_H +#define MCUCFG_V1_H + +#ifndef __ASSEMBLER__ +#include <stdint.h> +#endif /*__ASSEMBLER__*/ + +#include <platform_def.h> + +#define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_BASE + 0x2290 + ((cpu) * 8)) +#define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_BASE + 0x2294 + ((cpu) * 8)) + +#define MP2_CPUCFG (MCUCFG_BASE + 0x2208) + +#define MP0_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x788) +#define MP1_CPUTOP_SPMC_CTL (MCUCFG_BASE + 0x78C) +#define MP1_CPUTOP_SPMC_SRAM_CTL (MCUCFG_BASE + 0x790) + +#define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) (MCUCFG_BASE + 0x1C30 + \ + (cluster) * 0x2000 + (cpu) * 4) + +#define CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1C30) +#define CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1C34) +#define CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1C38) +#define CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1C3C) + +#define CPUSYS1_CPU0_SPMC_CTL (MCUCFG_BASE + 0x3C30) +#define CPUSYS1_CPU1_SPMC_CTL (MCUCFG_BASE + 0x3C34) +#define CPUSYS1_CPU2_SPMC_CTL (MCUCFG_BASE + 0x3C38) +#define CPUSYS1_CPU3_SPMC_CTL (MCUCFG_BASE + 0x3C3C) + +/* CPC related registers */ +#define CPC_MCUSYS_CPC_OFF_THRES (MCUCFG_BASE + 0xA714) +#define CPC_MCUSYS_PWR_CTRL (MCUCFG_BASE + 0xA804) +#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUCFG_BASE + 0xA814) +#define CPC_MCUSYS_LAST_CORE_REQ (MCUCFG_BASE + 0xA818) +#define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUCFG_BASE + 0xA81C) +#define CPC_MCUSYS_LAST_CORE_RESP (MCUCFG_BASE + 0xA824) +#define CPC_MCUSYS_PWR_ON_MASK (MCUCFG_BASE + 0xA828) +#define CPC_SPMC_PWR_STATUS (MCUCFG_BASE + 0xA840) +#define CPC_MCUSYS_CPU_ON_SW_HINT_SET (MCUCFG_BASE + 0xA8A8) +#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR (MCUCFG_BASE + 0xA8AC) +#define CPC_MCUSYS_CPC_DBG_SETTING (MCUCFG_BASE + 0xAB00) +#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE (MCUCFG_BASE + 0xAB04) +#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE (MCUCFG_BASE + 0xAB08) +#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE (MCUCFG_BASE + 0xAB0C) +#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE (MCUCFG_BASE + 0xAB10) +#define CPC_MCUSYS_TRACE_SEL (MCUCFG_BASE + 0xAB14) +#define CPC_MCUSYS_TRACE_DATA (MCUCFG_BASE + 0xAB20) +#define CPC_MCUSYS_CLUSTER_COUNTER (MCUCFG_BASE + 0xAB70) +#define CPC_MCUSYS_CLUSTER_COUNTER_CLR (MCUCFG_BASE + 0xAB74) + +/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG bit control */ +#define CPC_CTRL_ENABLE BIT(16) +#define SSPM_CORE_PWR_ON_EN BIT(7) /* for cpu-hotplug */ +#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */ +#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu) + +#define CPC_MCUSYS_CPC_RESET_ON_KEEP_ON BIT(17) +#define CPC_MCUSYS_CPC_RESET_PWR_ON_EN BIT(20) + +/* SPMC related registers */ +#define SPM_MCUSYS_PWR_CON (MCUCFG_BASE + 0xD200) +#define SPM_MP0_CPUTOP_PWR_CON (MCUCFG_BASE + 0xD204) +#define SPM_MP0_CPU0_PWR_CON (MCUCFG_BASE + 0xD208) +#define SPM_MP0_CPU1_PWR_CON (MCUCFG_BASE + 0xD20C) +#define SPM_MP0_CPU2_PWR_CON (MCUCFG_BASE + 0xD210) +#define SPM_MP0_CPU3_PWR_CON (MCUCFG_BASE + 0xD214) +#define SPM_MP0_CPU4_PWR_CON (MCUCFG_BASE + 0xD218) +#define SPM_MP0_CPU5_PWR_CON (MCUCFG_BASE + 0xD21C) +#define SPM_MP0_CPU6_PWR_CON (MCUCFG_BASE + 0xD220) +#define SPM_MP0_CPU7_PWR_CON (MCUCFG_BASE + 0xD224) + +/* bit fields of SPM_*_PWR_CON */ +#define PWR_ON_ACK BIT(31) +#define VPROC_EXT_OFF BIT(7) +#define DORMANT_EN BIT(6) +#define RESETPWRON_CONFIG BIT(5) +#define PWR_CLK_DIS BIT(4) +#define PWR_ON BIT(2) +#define PWR_RST_B BIT(0) + +#define SPARK2LDO (MCUCFG_BASE + 0x2700) +/* APB Module mcucfg */ +#define MP0_CA7_CACHE_CONFIG (MCUCFG_BASE + 0x000) +#define MP0_AXI_CONFIG (MCUCFG_BASE + 0x02C) +#define MP0_MISC_CONFIG0 (MCUCFG_BASE + 0x030) +#define MP0_MISC_CONFIG1 (MCUCFG_BASE + 0x034) +#define MP0_MISC_CONFIG2 (MCUCFG_BASE + 0x038) +#define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x038 + ((cpu) * 8)) +#define MP0_MISC_CONFIG3 (MCUCFG_BASE + 0x03C) +#define MP0_MISC_CONFIG9 (MCUCFG_BASE + 0x054) +#define MP0_CA7_MISC_CONFIG (MCUCFG_BASE + 0x064) + +#define MP0_RW_RSVD0 (MCUCFG_BASE + 0x06C) +#define MP1_CA7_CACHE_CONFIG (MCUCFG_BASE + 0x200) +#define MP1_AXI_CONFIG (MCUCFG_BASE + 0x22C) +#define MP1_MISC_CONFIG0 (MCUCFG_BASE + 0x230) +#define MP1_MISC_CONFIG1 (MCUCFG_BASE + 0x234) +#define MP1_MISC_CONFIG2 (MCUCFG_BASE + 0x238) +#define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x238 + ((cpu) * 8)) +#define MP1_MISC_CONFIG3 (MCUCFG_BASE + 0x23C) +#define MP1_MISC_CONFIG9 (MCUCFG_BASE + 0x254) +#define MP1_CA7_MISC_CONFIG (MCUCFG_BASE + 0x264) + +#define CCI_ADB400_DCM_CONFIG (MCUCFG_BASE + 0x740) +#define SYNC_DCM_CONFIG (MCUCFG_BASE + 0x744) + +#define MP0_CLUSTER_CFG0 (MCUCFG_BASE + 0xC8D0) + +#define MP0_SPMC (MCUCFG_BASE + 0x788) +#define MP1_SPMC (MCUCFG_BASE + 0x78C) +#define MP2_AXI_CONFIG (MCUCFG_BASE + 0x220C) +#define MP2_AXI_CONFIG_ACINACTM BIT(0) +#define MP2_AXI_CONFIG_AINACTS BIT(4) + +#define MPx_AXI_CONFIG_ACINACTM BIT(4) +#define MPx_AXI_CONFIG_AINACTS BIT(5) + +#define MPx_CA7_MISC_CONFIG_standbywfil2 BIT(28) + +#define MP0_CPU0_STANDBYWFE BIT(20) +#define MP0_CPU1_STANDBYWFE BIT(21) +#define MP0_CPU2_STANDBYWFE BIT(22) +#define MP0_CPU3_STANDBYWFE BIT(23) + +#define MP1_CPU0_STANDBYWFE BIT(20) +#define MP1_CPU1_STANDBYWFE BIT(21) +#define MP1_CPU2_STANDBYWFE BIT(22) +#define MP1_CPU3_STANDBYWFE BIT(23) + +#define CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE+0x1c00) +#define CPUSYS0_SPARKEN (MCUCFG_BASE+0x1c04) +#define CPUSYS0_AMUXSEL (MCUCFG_BASE+0x1c08) +#define CPUSYS1_SPARKVRETCNTRL (MCUCFG_BASE+0x3c00) +#define CPUSYS1_SPARKEN (MCUCFG_BASE+0x3c04) +#define CPUSYS1_AMUXSEL (MCUCFG_BASE+0x3c08) + +#define MP2_PWR_RST_CTL (MCUCFG_BASE + 0x2008) +#define MP2_PTP3_CPUTOP_SPMC0 (MCUCFG_BASE + 0x22A0) +#define MP2_PTP3_CPUTOP_SPMC1 (MCUCFG_BASE + 0x22A4) + +#define MP2_COQ (MCUCFG_BASE + 0x22BC) +#define MP2_COQ_SW_DIS BIT(0) + +#define MP2_CA15M_MON_SEL (MCUCFG_BASE + 0x2400) +#define MP2_CA15M_MON_L (MCUCFG_BASE + 0x2404) + +#define CPUSYS2_CPU0_SPMC_CTL (MCUCFG_BASE + 0x2430) +#define CPUSYS2_CPU1_SPMC_CTL (MCUCFG_BASE + 0x2438) +#define CPUSYS2_CPU0_SPMC_STA (MCUCFG_BASE + 0x2434) +#define CPUSYS2_CPU1_SPMC_STA (MCUCFG_BASE + 0x243C) + +#define MP0_CA7L_DBG_PWR_CTRL (MCUCFG_BASE + 0x068) +#define MP1_CA7L_DBG_PWR_CTRL (MCUCFG_BASE + 0x268) +#define BIG_DBG_PWR_CTRL (MCUCFG_BASE + 0x75C) + +#define MP2_SW_RST_B BIT(0) +#define MP2_TOPAON_APB_MASK BIT(1) +#define B_SW_HOT_PLUG_RESET BIT(30) +#define B_SW_PD_OFFSET (18) +#define B_SW_PD (0x3F << B_SW_PD_OFFSET) + +#define B_SW_SRAM_SLEEPB_OFFSET (12) +#define B_SW_SRAM_SLEEPB (0x3F << B_SW_SRAM_SLEEPB_OFFSET) + +#define B_SW_SRAM_ISOINTB BIT(9) +#define B_SW_ISO BIT(8) +#define B_SW_LOGIC_PDB BIT(7) +#define B_SW_LOGIC_PRE2_PDB BIT(6) +#define B_SW_LOGIC_PRE1_PDB BIT(5) +#define B_SW_FSM_OVERRIDE BIT(4) +#define B_SW_PWR_ON BIT(3) +#define B_SW_PWR_ON_OVERRIDE_EN BIT(2) + +#define B_FSM_STATE_OUT_OFFSET (6) +#define B_FSM_STATE_OUT_MASK (0x1F << B_FSM_STATE_OUT_OFFSET) +#define B_SW_LOGIC_PDBO_ALL_OFF_ACK BIT(5) +#define B_SW_LOGIC_PDBO_ALL_ON_ACK BIT(4) +#define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK BIT(3) +#define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK BIT(2) + + +#define B_FSM_OFF (0U << B_FSM_STATE_OUT_OFFSET) +#define B_FSM_ON (1U << B_FSM_STATE_OUT_OFFSET) +#define B_FSM_RET (2U << B_FSM_STATE_OUT_OFFSET) + +#ifndef __ASSEMBLER__ +/* cpu boot mode */ +enum mp0_coucfg_64bit_ctrl { + MP0_CPUCFG_64BIT_SHIFT = 12, + MP1_CPUCFG_64BIT_SHIFT = 28, + MP0_CPUCFG_64BIT = 0xfu << MP0_CPUCFG_64BIT_SHIFT, + MP1_CPUCFG_64BIT = 0xfu << MP1_CPUCFG_64BIT_SHIFT, +}; + +enum mp1_dis_rgu0_ctrl { + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = 0xF << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = 0xF << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = 0xF << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = 0xF << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = 0xF << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT, +}; + +enum mp1_ainacts_ctrl { + MP1_AINACTS_SHIFT = 4, + MP1_AINACTS = 1U << MP1_AINACTS_SHIFT, +}; + +enum mp1_sw_cg_gen { + MP1_SW_CG_GEN_SHIFT = 12, + MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT, +}; + +enum mp1_l2rstdisable { + MP1_L2RSTDISABLE_SHIFT = 14, + MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT, +}; +#endif /*__ASSEMBLER__*/ + +#endif /* MCUCFG_V1_H */ diff --git a/plat/mediatek/drivers/msdc/mt8186/mt_msdc_priv.h b/plat/mediatek/drivers/msdc/mt8186/mt_msdc_priv.h new file mode 100644 index 000000000..b3337caf6 --- /dev/null +++ b/plat/mediatek/drivers/msdc/mt8186/mt_msdc_priv.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_MSDC_PRIV_H +#define MT_MSDC_PRIV_H + +#define MSDC_CQHCI_CFG 0x808 +#define MSDC_CQHCI_CRYPTO_ENABLE BIT(1) + +#endif diff --git a/plat/mediatek/drivers/msdc/mt_msdc.c b/plat/mediatek/drivers/msdc/mt_msdc.c new file mode 100644 index 000000000..ccf440fcd --- /dev/null +++ b/plat/mediatek/drivers/msdc/mt_msdc.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <lib/mmio.h> +#include <mt_msdc.h> +#include <platform_def.h> + +uint64_t msdc_smc_dispatcher(uint64_t arg0, uint64_t arg1, + uint64_t arg2, uint64_t arg3) +{ + INFO("[%s] msdc setup call from kernel\n", __func__); + mmio_setbits_32(MSDC0_BASE + MSDC_CQHCI_CFG, MSDC_CQHCI_CRYPTO_ENABLE); + + return 0L; +} diff --git a/plat/mediatek/drivers/msdc/mt_msdc.h b/plat/mediatek/drivers/msdc/mt_msdc.h new file mode 100644 index 000000000..1c500c29d --- /dev/null +++ b/plat/mediatek/drivers/msdc/mt_msdc.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_MSDC_H +#define MT_MSDC_H + +#include <mt_msdc_priv.h> + +uint64_t msdc_smc_dispatcher(uint64_t arg0, uint64_t arg1, + uint64_t arg2, uint64_t arg3); + +#endif diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic.c b/plat/mediatek/drivers/pmic/pmic.c index cca441397..a11ad9a8b 100644 --- a/plat/mediatek/mt8195/drivers/pmic/pmic.c +++ b/plat/mediatek/drivers/pmic/pmic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic.h b/plat/mediatek/drivers/pmic/pmic.h index aac22afa3..6c10f65f6 100644 --- a/plat/mediatek/mt8195/drivers/pmic/pmic.h +++ b/plat/mediatek/drivers/pmic/pmic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #ifndef PMIC_H #define PMIC_H -#define PMIC_PWRHOLD 0xa08 +#define PMIC_PWRHOLD (0xa08) /* external API */ void pmic_power_off(void); diff --git a/plat/mediatek/drivers/pmic/rules.mk b/plat/mediatek/drivers/pmic/rules.mk new file mode 100644 index 000000000..e408b034f --- /dev/null +++ b/plat/mediatek/drivers/pmic/rules.mk @@ -0,0 +1,15 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := pmic + +LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c + +PLAT_INCLUDES += -I${LOCAL_DIR}/ + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/pmic_wrap/mt8188/pmic_wrap_init.h b/plat/mediatek/drivers/pmic_wrap/mt8188/pmic_wrap_init.h new file mode 100644 index 000000000..9027daf15 --- /dev/null +++ b/plat/mediatek/drivers/pmic_wrap/mt8188/pmic_wrap_init.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMIC_WRAP_INIT_H +#define PMIC_WRAP_INIT_H + +#include <stdint.h> + +#include "platform_def.h" +#include <pmic_wrap_init_common.h> + +static struct mt8188_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; + +/* PMIC_WRAP registers */ +struct mt8188_pmic_wrap_regs { + uint32_t init_done; + uint32_t reserved[543]; + uint32_t wacs2_cmd; + uint32_t wacs2_wdata; + uint32_t reserved1[3]; + uint32_t wacs2_rdata; + uint32_t reserved2[3]; + uint32_t wacs2_vldclr; + uint32_t wacs2_sta; +}; + +#endif /* PMIC_WRAP_INIT_H */ diff --git a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init.c index e3cfd46a0..0ee1c6498 100644 --- a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init.c +++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * Copyright (c) 2019-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h new file mode 100644 index 000000000..4ba1f5c7b --- /dev/null +++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMIC_WRAP_INIT_COMMON_H +#define PMIC_WRAP_INIT_COMMON_H + +#include <stdint.h> + +#include "platform_def.h" + +/* external API */ +int32_t pwrap_read(uint32_t adr, uint32_t *rdata); +int32_t pwrap_write(uint32_t adr, uint32_t wdata); + +#define GET_WACS_FSM(x) ((x >> 1) & 0x7) + +/* macro for SWINF_FSM */ +#define SWINF_FSM_IDLE (0x00) +#define SWINF_FSM_REQ (0x02) +#define SWINF_FSM_WFDLE (0x04) +#define SWINF_FSM_WFVLDCLR (0x06) +#define SWINF_INIT_DONE (0x01) + +/* timeout setting */ +#define PWRAP_READ_US (1000) +#define PWRAP_WAIT_IDLE_US (1000) + +/* error information flag */ +enum pwrap_errno { + E_PWR_INVALID_ARG = 1, + E_PWR_INVALID_RW = 2, + E_PWR_INVALID_ADDR = 3, + E_PWR_INVALID_WDAT = 4, + E_PWR_INVALID_OP_MANUAL = 5, + E_PWR_NOT_IDLE_STATE = 6, + E_PWR_NOT_INIT_DONE = 7, + E_PWR_NOT_INIT_DONE_READ = 8, + E_PWR_WAIT_IDLE_TIMEOUT = 9, + E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, + E_PWR_INIT_SIDLY_FAIL = 11, + E_PWR_RESET_TIMEOUT = 12, + E_PWR_TIMEOUT = 13, + E_PWR_INIT_RESET_SPI = 20, + E_PWR_INIT_SIDLY = 21, + E_PWR_INIT_REG_CLOCK = 22, + E_PWR_INIT_ENABLE_PMIC = 23, + E_PWR_INIT_DIO = 24, + E_PWR_INIT_CIPHER = 25, + E_PWR_INIT_WRITE_TEST = 26, + E_PWR_INIT_ENABLE_CRC = 27, + E_PWR_INIT_ENABLE_DEWRAP = 28, + E_PWR_INIT_ENABLE_EVENT = 29, + E_PWR_READ_TEST_FAIL = 30, + E_PWR_WRITE_TEST_FAIL = 31, + E_PWR_SWITCH_DIO = 32, +}; + +#endif /* PMIC_WRAP_INIT_COMMON_H */ diff --git a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v2.c index d9a79c494..80f55de48 100644 --- a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c +++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/drivers/pmic_wrap/rules.mk b/plat/mediatek/drivers/pmic_wrap/rules.mk new file mode 100644 index 000000000..9ba44a6bf --- /dev/null +++ b/plat/mediatek/drivers/pmic_wrap/rules.mk @@ -0,0 +1,20 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := pmic_wrap + +ifeq (${USE_PMIC_WRAP_INIT_V2}, 1) +LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v2.c +else +LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init.c +endif + +PLAT_INCLUDES += -I${LOCAL_DIR}/ +PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/ptp3/mt8188/ptp3_plat.h b/plat/mediatek/drivers/ptp3/mt8188/ptp3_plat.h new file mode 100644 index 000000000..aa7d7ca47 --- /dev/null +++ b/plat/mediatek/drivers/ptp3/mt8188/ptp3_plat.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PTP3_PLAT_H +#define PTP3_PLAT_H + +#include <lib/mmio.h> +#include <lib/utils_def.h> +#include <ptp3_common.h> + +/* CPU Info */ +#define NR_PTP3_CFG_CPU U(8) +#define PTP3_CFG_CPU_START_ID_L U(0) +#define PTP3_CFG_CPU_START_ID_B U(6) +#define PTP3_CFG_CPU_END_ID U(7) + +#define NR_PTP3_CFG1_DATA U(2) +#define PTP3_CFG1_MASK (0x3000) + +#define NR_PTP3_CFG2_DATA U(5) + +#define PTP3_CFG3_MASK1 (0x1180) +#define PTP3_CFG3_MASK2 (0x35C0) +#define PTP3_CFG3_MASK3 (0x3DC0) + + +/* Central control */ +static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = { + {0x0C53A2A0, 0x1000}, + {0x0C53A2A4, 0x1000} +}; + +static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = { + {0x0C530404, 0x3A1000}, + {0x0C530428, 0x13E0408}, + {0x0C530434, 0xB22800}, + {0x0C53043C, 0x750}, + {0x0C530440, 0x0222c4cc} +}; + +static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0xC00}; +static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00}; + +#endif /* PTP3_PLAT_H */ diff --git a/plat/mediatek/drivers/ptp3/ptp3_common.c b/plat/mediatek/drivers/ptp3/ptp3_common.c new file mode 100644 index 000000000..68468529e --- /dev/null +++ b/plat/mediatek/drivers/ptp3/ptp3_common.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#if MTK_PUBEVENT_ENABLE +#include <lib/pm/mtk_pm.h> +#endif +#include <ptp3_plat.h> + +#define PTP3_CORE_OFT(core) (0x800 * (core)) + +static void ptp3_init(unsigned int core) +{ + unsigned int i, addr, value; + + if (core < PTP3_CFG_CPU_START_ID_B) { + mmio_clrsetbits_32(ptp3_cfg1[0][PTP3_CFG_ADDR], PTP3_CFG1_MASK, + ptp3_cfg1[0][PTP3_CFG_VALUE]); + } else { + mmio_clrsetbits_32(ptp3_cfg1[1][PTP3_CFG_ADDR], PTP3_CFG1_MASK, + ptp3_cfg1[1][PTP3_CFG_VALUE]); + } + + if (core < PTP3_CFG_CPU_START_ID_B) { + for (i = 0; i < NR_PTP3_CFG2_DATA; i++) { + addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); + value = ptp3_cfg2[i][PTP3_CFG_VALUE]; + + mmio_write_32(addr, value); + } + } else { + for (i = 0; i < NR_PTP3_CFG2_DATA; i++) { + addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); + + if (i == 2) { + value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0; + } else { + value = ptp3_cfg2[i][PTP3_CFG_VALUE]; + } + mmio_write_32(addr, value); + } + } + + if (core < PTP3_CFG_CPU_START_ID_B) { + addr = ptp3_cfg3[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); + value = ptp3_cfg3[PTP3_CFG_VALUE]; + } else { + addr = ptp3_cfg3_ext[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); + value = ptp3_cfg3_ext[PTP3_CFG_VALUE]; + } + mmio_write_32(addr, value & PTP3_CFG3_MASK1); + mmio_write_32(addr, value & PTP3_CFG3_MASK2); + mmio_write_32(addr, value & PTP3_CFG3_MASK3); +} + +static void pdp_proc_arm_write(unsigned int pdp_n) +{ + unsigned long v = 0; + + dsb(); + __asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v)); + v |= (UL(0x0) << 52); + v |= (UL(0x1) << 53); + v |= (UL(0x0) << 54); + v |= (UL(0x0) << 48); + v |= (UL(0x1) << 49); + __asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v)); + dsb(); +} + +static void pdp_init(unsigned int pdp_cpu) +{ + if ((pdp_cpu >= PTP3_CFG_CPU_START_ID_B) && (pdp_cpu < NR_PTP3_CFG_CPU)) { + pdp_proc_arm_write(pdp_cpu); + } +} + +void ptp3_core_init(unsigned int core) +{ + ptp3_init(core); + pdp_init(core); +} + +void ptp3_core_deinit(unsigned int core) +{ + /* TBD */ +} + +#if MTK_PUBEVENT_ENABLE +/* Handle for power on domain */ +void *ptp3_handle_pwr_on_event(const void *arg) +{ + if (arg != NULL) { + struct mt_cpupm_event_data *data = (struct mt_cpupm_event_data *)arg; + + if ((data->pwr_domain & MT_CPUPM_PWR_DOMAIN_CORE) > 0) { + ptp3_core_init(data->cpuid); + } + } + return (void *)arg; +} +MT_CPUPM_SUBCRIBE_EVENT_PWR_ON(ptp3_handle_pwr_on_event); + +/* Handle for power off domain */ +void *ptp3_handle_pwr_off_event(const void *arg) +{ + if (arg != NULL) { + struct mt_cpupm_event_data *data = (struct mt_cpupm_event_data *)arg; + + if ((data->pwr_domain & MT_CPUPM_PWR_DOMAIN_CORE) > 0) { + ptp3_core_deinit(data->cpuid); + } + } + return (void *)arg; +} +MT_CPUPM_SUBCRIBE_EVENT_PWR_OFF(ptp3_handle_pwr_off_event); +#else +#pragma message "PSCI hint not enable" +#endif diff --git a/plat/mediatek/drivers/ptp3/ptp3_common.h b/plat/mediatek/drivers/ptp3/ptp3_common.h new file mode 100644 index 000000000..83ce62b72 --- /dev/null +++ b/plat/mediatek/drivers/ptp3/ptp3_common.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PTP3_COMMON_H +#define PTP3_COMMON_H + +/* config enum */ +enum PTP3_CFG { + PTP3_CFG_ADDR, + PTP3_CFG_VALUE, + NR_PTP3_CFG, +}; + +/* prototype */ +void ptp3_core_init(unsigned int core); +void ptp3_core_deinit(unsigned int core); + +#endif /* PTP3_COMMON_H */ diff --git a/plat/mediatek/drivers/ptp3/rules.mk b/plat/mediatek/drivers/ptp3/rules.mk new file mode 100644 index 000000000..81d79d269 --- /dev/null +++ b/plat/mediatek/drivers/ptp3/rules.mk @@ -0,0 +1,16 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := mtk_ptp3 + +LOCAL_SRCS-y := ${LOCAL_DIR}/ptp3_common.c + +PLAT_INCLUDES += -I${LOCAL_DIR} +PLAT_INCLUDES += -I${LOCAL_DIR}/$(MTK_SOC) + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/drivers/rtc/mt8188/rtc.h b/plat/mediatek/drivers/rtc/mt8188/rtc.h new file mode 100644 index 000000000..734e89fcd --- /dev/null +++ b/plat/mediatek/drivers/rtc/mt8188/rtc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RTC_H +#define RTC_H + +#include <rtc_mt6359p.h> + +#endif /* RTC_H */ diff --git a/plat/mediatek/common/drivers/rtc/rtc_common.c b/plat/mediatek/drivers/rtc/rtc_common.c index cad12a03b..4efddffb4 100644 --- a/plat/mediatek/common/drivers/rtc/rtc_common.c +++ b/plat/mediatek/drivers/rtc/rtc_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, MediaTek Inc. All rights reserved. + * Copyright (c) 2019-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/common/drivers/rtc/rtc_mt6359p.c b/plat/mediatek/drivers/rtc/rtc_mt6359p.c index 124bc8fbe..3bf433793 100644 --- a/plat/mediatek/common/drivers/rtc/rtc_mt6359p.c +++ b/plat/mediatek/drivers/rtc/rtc_mt6359p.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h b/plat/mediatek/drivers/rtc/rtc_mt6359p.h index 04726e390..199f1522e 100644 --- a/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h +++ b/plat/mediatek/drivers/rtc/rtc_mt6359p.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/drivers/rtc/rules.mk b/plat/mediatek/drivers/rtc/rules.mk new file mode 100644 index 000000000..2398f8a9e --- /dev/null +++ b/plat/mediatek/drivers/rtc/rules.mk @@ -0,0 +1,20 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := rtc + +LOCAL_SRCS-y := ${LOCAL_DIR}/rtc_common.c + +ifeq (${USE_RTC_MT6359P}, 1) +LOCAL_SRCS-y += ${LOCAL_DIR}/rtc_mt6359p.c +PLAT_INCLUDES += -I${LOCAL_DIR} +endif + +PLAT_INCLUDES += -I${LOCAL_DIR}/${MTK_SOC} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/common/drivers/timer/mt_timer.c b/plat/mediatek/drivers/timer/mt_timer.c index 08608854a..11e457253 100644 --- a/plat/mediatek/common/drivers/timer/mt_timer.c +++ b/plat/mediatek/drivers/timer/mt_timer.c @@ -1,15 +1,16 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch_helpers.h> +#include <common/debug.h> #include <lib/mmio.h> +#include <lib/mtk_init/mtk_init.h> #include <mt_timer.h> #include <platform_def.h> - uint64_t normal_time_base; uint64_t atf_time_base; @@ -30,9 +31,14 @@ uint64_t sched_clock(void) return cval; } -void mt_systimer_init(void) +int mt_systimer_init(void) { + INFO("[%s] systimer initialization\n", __func__); + /* Enable access in NS mode */ mmio_write_32(CNTWACR_REG, CNT_WRITE_ACCESS_CTL_MASK); mmio_write_32(CNTRACR_REG, CNT_READ_ACCESS_CTL_MASK); + + return 0; } +MTK_PLAT_SETUP_0_INIT(mt_systimer_init); diff --git a/plat/mediatek/common/drivers/timer/mt_timer.h b/plat/mediatek/drivers/timer/mt_timer.h index b35317715..1c08f9099 100644 --- a/plat/mediatek/common/drivers/timer/mt_timer.h +++ b/plat/mediatek/drivers/timer/mt_timer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,6 +30,6 @@ void sched_clock_init(uint64_t normal_base, uint64_t atf_base); uint64_t sched_clock(void); -void mt_systimer_init(void); +int mt_systimer_init(void); #endif /* MT_TIMER_H */ diff --git a/plat/mediatek/drivers/timer/rules.mk b/plat/mediatek/drivers/timer/rules.mk new file mode 100644 index 000000000..005cf45a2 --- /dev/null +++ b/plat/mediatek/drivers/timer/rules.mk @@ -0,0 +1,14 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := timer +LOCAL_SRCS-y := $(LOCAL_DIR)/mt_timer.c + +PLAT_INCLUDES += -I${LOCAL_DIR} + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/common/drivers/uart/8250_console.S b/plat/mediatek/drivers/uart/8250_console.S index 7a946f9a3..66f998d40 100644 --- a/plat/mediatek/common/drivers/uart/8250_console.S +++ b/plat/mediatek/drivers/uart/8250_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/common/drivers/uart/uart.c b/plat/mediatek/drivers/uart/uart.c index b940eb339..fdaa793ba 100644 --- a/plat/mediatek/common/drivers/uart/uart.c +++ b/plat/mediatek/drivers/uart/uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/common/drivers/uart/uart.h b/plat/mediatek/drivers/uart/uart.h index ac8b94dd1..2ca74fa3f 100644 --- a/plat/mediatek/common/drivers/uart/uart.h +++ b/plat/mediatek/drivers/uart/uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/common/drivers/uart/uart8250.h b/plat/mediatek/drivers/uart/uart8250.h index da7c7a125..f0541d608 100644 --- a/plat/mediatek/common/drivers/uart/uart8250.h +++ b/plat/mediatek/drivers/uart/uart8250.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/plat/mediatek/helpers/armv8_2/arch_helpers.S b/plat/mediatek/helpers/armv8_2/arch_helpers.S new file mode 100644 index 000000000..02d8d530c --- /dev/null +++ b/plat/mediatek/helpers/armv8_2/arch_helpers.S @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2022, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <assert_macros.S> +#include <cpu_macros.S> +#if CONFIG_MTK_MCUSYS +#include <mcucfg.h> +#endif +#include <platform_def.h> + /* + * Declare as weak function so that can be + * overwritten by platform helpers + */ + .weak platform_mem_init + .weak plat_core_pos_by_mpidr + .weak plat_my_core_pos + .weak plat_mediatek_calc_core_pos + .global plat_mpidr_by_core_pos + .global plat_reset_handler + + /* ----------------------------------------------------- + * unsigned long plat_mpidr_by_core_pos(uint32_t cpuid) + * This function calcuate mpidr by cpu pos if cpu + * topology is linear. + * + * Clobbers: x0-x1 + * ----------------------------------------------------- + */ +func plat_mpidr_by_core_pos + lsl x0, x0, #MPIDR_AFF1_SHIFT + mrs x1, mpidr_el1 + and x1, x1, #MPIDR_MT_MASK + orr x0, x0, x1 + ret +endfunc plat_mpidr_by_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_arm_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_mediatek_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * int plat_mediatek_calc_core_pos(u_register_t mpidr); + * + * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and + * AFF0 is thread id. There is only one cluster in ARMv8.2 + * and one thread in current implementation. + * + * With this function: CorePos = CoreID (AFF1) + * we do it with x0 = (x0 >> 8) & 0xff + * ----------------------------------------------------- + */ +func plat_mediatek_calc_core_pos + b plat_core_pos_by_mpidr +endfunc plat_mediatek_calc_core_pos + + /* ------------------------------------------------------ + * int32_t plat_core_pos_by_mpidr(u_register_t mpidr) + * + * This function implements a part of the critical + * interface between the psci generic layer and the + * platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. + * + * Clobbers: x0-x1 + * ------------------------------------------------------ + */ +func plat_core_pos_by_mpidr + mov x1, #MPIDR_AFFLVL_MASK + and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT + ret +endfunc plat_core_pos_by_mpidr + + /* -------------------------------------------------------- + * void platform_mem_init (void); + * + * Any memory init, relocation to be done before the + * platform boots. Called very early in the boot process. + * -------------------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + +func plat_reset_handler +#if CONFIG_MTK_MCUSYS + mov x10, x30 + bl plat_my_core_pos + mov x30, x10 + mov w1, #0x1 + lsl w1, w1, w0 + ldr x0, =CPC_MCUSYS_CPU_ON_SW_HINT_SET + str w1, [x0] + dsb sy +#endif + +#if CONFIG_MTK_ECC + mov x10, x30 + /* enable sequence of ecc for cpus */ + bl disable_core_ecc + bl ft_ecc_clear_per_core + bl enable_core_ecc + mov x30, x10 +#endif + + ret +endfunc plat_reset_handler diff --git a/plat/mediatek/helpers/rules.mk b/plat/mediatek/helpers/rules.mk new file mode 100644 index 000000000..ae8068e79 --- /dev/null +++ b/plat/mediatek/helpers/rules.mk @@ -0,0 +1,12 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := helpers +LOCAL_SRCS-y += $(LOCAL_DIR)/$(ARCH_VERSION)/arch_helpers.S + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/include/armv8_2/arch_def.h b/plat/mediatek/include/armv8_2/arch_def.h new file mode 100644 index 000000000..61f818fca --- /dev/null +++ b/plat/mediatek/include/armv8_2/arch_def.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2022, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ARCH_DEF_H +#define ARCH_DEF_H + +/* Topology constants */ +#define PLAT_MAX_PWR_LVL (2) +#define PLAT_MAX_RET_STATE (1) +#define PLAT_MAX_OFF_STATE (2) + +#define PLATFORM_SYSTEM_COUNT (1) +#define PLATFORM_CLUSTER_COUNT (1) +#define PLATFORM_CLUSTER0_CORE_COUNT (8) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER (8) +#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +/* Cachline size */ +#define CACHE_WRITEBACK_SHIFT (6) +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#endif /* ARCH_DEF_H */ + diff --git a/plat/mediatek/include/lib/mtk_init/mtk_init.h b/plat/mediatek/include/lib/mtk_init/mtk_init.h new file mode 100644 index 000000000..6f23a9b46 --- /dev/null +++ b/plat/mediatek/include/lib/mtk_init/mtk_init.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_INIT_H +#define MTK_INIT_H + +#include <cdefs.h> +#include <lib/mtk_init/mtk_init_def.h> + +#define INIT_CALL_EXPAND_AS_ENUMERATION(_section_enum, _section_name, _level) \ + _section_enum = _level, + +#define EXPAND_AS_LINK_SECTION(_section_enum, _section_name, _level) \ + __##_section_enum##_START__ = .; \ + KEEP(*(_section_name##_level)); + +#define EXPAND_AS_EXTERN(_section_enum, _section_name, _level) \ + extern struct initcall __##_section_enum##_START__[]; + +#define EXPAND_AS_SYMBOL_ARR(_section_enum, _section_name, _level) \ + __##_section_enum##_START__, + +#define DECLARE_MTK_INITCALL(_fn, _level) \ + const struct initcall _mtk_initcall_##_fn \ + __used \ + __aligned(sizeof(void *)) \ + __section(".mtk_plat_initcall_"#_level) \ + = { \ + .name = #_fn, \ + .fn = _fn \ + } + +/* initcall helpers */ +#define MTK_EARLY_PLAT_INIT(_fn) DECLARE_MTK_INITCALL(_fn, 0) +#define MTK_ARCH_INIT(_fn) DECLARE_MTK_INITCALL(_fn, 1) +#define MTK_PLAT_SETUP_0_INIT(_fn) DECLARE_MTK_INITCALL(_fn, 2) +#define MTK_PLAT_SETUP_1_INIT(_fn) DECLARE_MTK_INITCALL(_fn, 3) +#define MTK_PLAT_RUNTIME_INIT(_fn) DECLARE_MTK_INITCALL(_fn, 4) +#define MTK_PLAT_BL33_DEFER_INIT(_fn) DECLARE_MTK_INITCALL(_fn, 5) + +#ifndef __ASSEMBLER__ +struct initcall { + const char *name; + int (*fn)(void); +}; + +enum { + INIT_CALL_TABLE(INIT_CALL_EXPAND_AS_ENUMERATION) + MTK_INIT_LVL_MAX +}; + +void mtk_init_one_level(unsigned int level); +#endif + +#endif /* MTK_INIT_H */ diff --git a/plat/mediatek/include/lib/mtk_init/mtk_init_def.h b/plat/mediatek/include/lib/mtk_init/mtk_init_def.h new file mode 100644 index 000000000..8aae41d5c --- /dev/null +++ b/plat/mediatek/include/lib/mtk_init/mtk_init_def.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_INIT_DEF_H +#define MTK_INIT_DEF_H + +/* + * Define init call sections here. _func is for 2nd level expansion, init + * section enum, and init section name. + */ +#define INIT_CALL_TABLE(_func) \ + _func(MTK_INIT_LVL_EARLY_PLAT, .mtk_plat_initcall_, 0) \ + _func(MTK_INIT_LVL_ARCH, .mtk_plat_initcall_, 1) \ + _func(MTK_INIT_LVL_PLAT_SETUP_0, .mtk_plat_initcall_, 2) \ + _func(MTK_INIT_LVL_PLAT_SETUP_1, .mtk_plat_initcall_, 3) \ + _func(MTK_INIT_LVL_PLAT_RUNTIME, .mtk_plat_initcall_, 4) \ + _func(MTK_INIT_LVL_BL33_DEFER, .mtk_plat_initcall_, 5) + +#endif /* MTK_INIT_DEF_H */ diff --git a/plat/mediatek/include/mtk_mmap_pool.h b/plat/mediatek/include/mtk_mmap_pool.h new file mode 100644 index 000000000..99d1bff5c --- /dev/null +++ b/plat/mediatek/include/mtk_mmap_pool.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_MMAP_POOL_H +#define MTK_MMAP_POOL_H + +#include <cdefs.h> +#include <lib/xlat_tables/xlat_tables_compat.h> + +struct mtk_mmap_descriptor { + const char *mmap_name; + const mmap_region_t *mmap_ptr; + const uint32_t mmap_size; +}; + +#define MTK_MMAP_SECTION \ + __used \ + __aligned(sizeof(void *)) \ + __section(".mtk_mmap_lists") + +#define DECLARE_MTK_MMAP_REGIONS(_mmap_array) \ + static const struct mtk_mmap_descriptor _mtk_mmap_descriptor_##_mmap_array \ + __used \ + __aligned(sizeof(void *)) \ + __section(".mtk_mmap_pool") \ + = { \ + .mmap_name = #_mmap_array, \ + .mmap_ptr = _mmap_array, \ + .mmap_size = ARRAY_SIZE(_mmap_array) \ + } + +#define MAP_BL_RW MAP_REGION_FLAT( \ + DATA_START, \ + BL_END - DATA_START, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#if SEPARATE_CODE_AND_RODATA +#define MAP_BL_RO \ + MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE), \ + MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) +#else +#define MAP_BL_RO MAP_REGION_FLAT(BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) +#endif + +void mtk_xlat_init(const mmap_region_t *bl_regions); + +#endif /* MTK_MMAP_POOL_H */ diff --git a/plat/mediatek/include/mtk_sip_def.h b/plat/mediatek/include/mtk_sip_def.h new file mode 100644 index 000000000..2039017e3 --- /dev/null +++ b/plat/mediatek/include/mtk_sip_def.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_SIP_DEF_H +#define MTK_SIP_DEF_H + +/* Define SiP SMC ID here */ +#define MTK_SIP_SMC_FROM_NS_EL1_TABLE(_func) \ + _func(MTK_SIP_KERNEL_TIME_SYNC, 0x202) \ + _func(MTK_SIP_KERNEL_DFD, 0x205) \ + _func(MTK_SIP_KERNEL_MSDC, 0x273) \ + _func(MTK_SIP_VCORE_CONTROL, 0x506) \ + _func(MTK_SIP_IOMMU_CONTROL, 0x514) \ + _func(MTK_SIP_AUDIO_CONTROL, 0x517) \ + _func(MTK_SIP_APUSYS_CONTROL, 0x51E) \ + _func(MTK_SIP_DP_CONTROL, 0x523) \ + _func(MTK_SIP_KERNEL_GIC_OP, 0x526) + +#define MTK_SIP_SMC_FROM_BL33_TABLE(_func) \ + _func(MTK_SIP_KERNEL_BOOT, 0x115) + +#endif /* MTK_SIP_DEF_H */ diff --git a/plat/mediatek/include/mtk_sip_svc.h b/plat/mediatek/include/mtk_sip_svc.h new file mode 100644 index 000000000..ce51048e6 --- /dev/null +++ b/plat/mediatek/include/mtk_sip_svc.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_SIP_SVC_H +#define MTK_SIP_SVC_H + +#include <stdint.h> +#include <lib/smccc.h> +#include <mtk_sip_def.h> + +/* SMC function IDs for SiP Service queries */ +#define SIP_SVC_CALL_COUNT U(0x8200ff00) +#define SIP_SVC_UID U(0x8200ff01) +/* 0x8200ff02 is reserved */ +#define SIP_SVC_VERSION U(0x8200ff03) + +/* MediaTek SiP Service Calls version numbers */ +#define MTK_SIP_SVC_VERSION_MAJOR U(0x0) +#define MTK_SIP_SVC_VERSION_MINOR U(0x1) + +/* Number of MediaTek SiP Calls implemented */ +#define MTK_COMMON_SIP_NUM_CALLS U(4) + +/* MediaTek SiP Service Calls function IDs */ +#define MTK_SIP_SET_AUTHORIZED_SECURE_REG U(0x82000001) + +#define SMC_ID_EXPAND_AS_ENUM(_smc_id, _smc_num) \ + _smc_id##_AARCH32 = ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + ((0) << FUNCID_CC_SHIFT) | \ + (OEN_SIP_START << FUNCID_OEN_SHIFT) | \ + ((_smc_num) << FUNCID_NUM_SHIFT)), \ + _smc_id##_AARCH64 = ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + ((1) << FUNCID_CC_SHIFT) | \ + (OEN_SIP_START << FUNCID_OEN_SHIFT) | \ + ((_smc_num) << FUNCID_NUM_SHIFT)), + +#define SMC_ID_EXPAND_AS_EXTERN_SMC_INDEX(_smc_id, _smc_num) \ + extern short _smc_id##_descriptor_index; + +/* Bind SMC handler with SMC ID */ +#define DECLARE_SMC_HANDLER(_smc_id, _smc_handler) \ + const struct smc_descriptor _smc_id##_descriptor \ + __used \ + __aligned(sizeof(void *)) \ + __section(".mtk_smc_descriptor_pool") = { \ + .smc_handler = _smc_handler, \ + .smc_name = #_smc_id, \ + .smc_id_aarch32 = _smc_id##_AARCH32, \ + .smc_id_aarch64 = _smc_id##_AARCH64, \ + .smc_descriptor_index = &_smc_id##_descriptor_index \ + } + +MTK_SIP_SMC_FROM_BL33_TABLE(SMC_ID_EXPAND_AS_EXTERN_SMC_INDEX); +MTK_SIP_SMC_FROM_NS_EL1_TABLE(SMC_ID_EXPAND_AS_EXTERN_SMC_INDEX); + +/* Expand SiP SMC ID table as enum */ +enum { + MTK_SIP_SMC_FROM_BL33_TABLE(SMC_ID_EXPAND_AS_ENUM) + MTK_SIP_SMC_FROM_NS_EL1_TABLE(SMC_ID_EXPAND_AS_ENUM) + MTK_SIP_SMC_MAX_NUMBER +}; + +/* MediaTek SiP Calls error code */ +enum { + MTK_SIP_E_SUCCESS = 0, + MTK_SIP_E_INVALID_PARAM = -1, + MTK_SIP_E_NOT_SUPPORTED = -2, + MTK_SIP_E_INVALID_RANGE = -3, + MTK_SIP_E_PERMISSION_DENY = -4, + MTK_SIP_E_LOCK_FAIL = -5, +}; + +struct smccc_res { + uint64_t a1; + uint64_t a2; + uint64_t a3; +}; + +typedef uintptr_t (*smc_handler_t)(u_register_t, + u_register_t, + u_register_t, + u_register_t, + void *, + struct smccc_res *); + +struct smc_descriptor { + smc_handler_t smc_handler; + const uint32_t smc_id_aarch32; + const uint32_t smc_id_aarch64; + const char *smc_name; + short *const smc_descriptor_index; +}; + +/* + * This function should be implemented in MediaTek SOC directory. It fullfills + * MTK_SIP_SET_AUTHORIZED_SECURE_REG SiP call by checking the sreg with the + * predefined secure register list, if a match was found, set val to sreg. + * + * Return MTK_SIP_E_SUCCESS on success, and MTK_SIP_E_INVALID_PARAM on failure. + */ +uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val); + +#endif /* MTK_SIP_SVC_H */ diff --git a/plat/mediatek/include/plat.ld.rodata.inc b/plat/mediatek/include/plat.ld.rodata.inc new file mode 100644 index 000000000..06ad49109 --- /dev/null +++ b/plat/mediatek/include/plat.ld.rodata.inc @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_LD_RODATA_INC +#define PLAT_LD_RODATA_INC + +#include <lib/mtk_init/mtk_init.h> + . = ALIGN(32); + INIT_CALL_TABLE(EXPAND_AS_LINK_SECTION); + __MTK_PLAT_INITCALL_END__ = .; + . = ALIGN(32); + __MTK_MMAP_POINTER_POOL_START__ = .; + KEEP(*(.mtk_mmap_pool)) + __MTK_MMAP_POINTER_POOL_END_UNALIGNED__ = .; + . = ALIGN(8); + __MTK_MMAP_POOL_START__ = .; + KEEP(*(.mtk_mmap_lists)) + __MTK_MMAP_POOL_END_UNALIGNED__ = .; + . = ALIGN(32); + __MTK_SMC_POOL_START__ = .; + KEEP(*(.mtk_smc_descriptor_pool)) + __MTK_SMC_POOL_END_UNALIGNED__ = .; + . = ALIGN(8); +#include <vendor_pubsub_events.h> + *(mtk_plat_ro) + +#endif /* PLAT_LD_RODATA_INC */ diff --git a/plat/mediatek/include/vendor_pubsub_events.h b/plat/mediatek/include/vendor_pubsub_events.h new file mode 100644 index 000000000..cb8d87857 --- /dev/null +++ b/plat/mediatek/include/vendor_pubsub_events.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VENDOR_PUBSUB_EVENTS_H +#define VENDOR_PUBSUB_EVENTS_H + +#include <lib/el3_runtime/pubsub.h> + +REGISTER_PUBSUB_EVENT(lpm_publish_event); +REGISTER_PUBSUB_EVENT(suspend_publish_event); +REGISTER_PUBSUB_EVENT(mt_cpupm_publish_pwr_on); +REGISTER_PUBSUB_EVENT(mt_cpupm_publish_pwr_off); +REGISTER_PUBSUB_EVENT(mt_cpupm_publish_afflv_pwr_on); +REGISTER_PUBSUB_EVENT(mt_cpupm_publish_afflv_pwr_off); +REGISTER_PUBSUB_EVENT(publish_check_wakeup_irq); +REGISTER_PUBSUB_EVENT(watchdog_timeout); + +#endif /* VENDOR_PUBSUB_EVENTS_H */ diff --git a/plat/mediatek/lib/mtk_init/mtk_init.c b/plat/mediatek/lib/mtk_init/mtk_init.c new file mode 100644 index 000000000..228965926 --- /dev/null +++ b/plat/mediatek/lib/mtk_init/mtk_init.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <lib/utils_def.h> +#include <lib/mtk_init/mtk_init.h> + +INIT_CALL_TABLE(EXPAND_AS_EXTERN); +extern struct initcall __MTK_PLAT_INITCALL_END__[]; + +struct initcall *initcall_list[] = { + INIT_CALL_TABLE(EXPAND_AS_SYMBOL_ARR) + __MTK_PLAT_INITCALL_END__ +}; + +void mtk_init_one_level(uint32_t level) +{ + const struct initcall *entry; + int error; + + if (level >= MTK_INIT_LVL_MAX) { + ERROR("invalid level:%u\n", level); + panic(); + } + + INFO("init calling level:%u\n", level); + for (entry = initcall_list[level]; + (entry != NULL) && (entry < initcall_list[level + 1]); + entry++) { + INFO("calling %s\n", entry->name); + error = entry->fn(); + if (error != 0) { + ERROR("init %s fail, errno:%d\n", entry->name, error); + } + } +} diff --git a/plat/mediatek/lib/mtk_init/mtk_mmap_init.c b/plat/mediatek/lib/mtk_init/mtk_mmap_init.c new file mode 100644 index 000000000..e3dada01a --- /dev/null +++ b/plat/mediatek/lib/mtk_init/mtk_mmap_init.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <drivers/console.h> +#include <lib/xlat_tables/xlat_tables_compat.h> +#include <mtk_mmap_pool.h> + +IMPORT_SYM(uintptr_t, __MTK_MMAP_POINTER_POOL_START__, MTK_MMAP_POINTER_POOL_START); +IMPORT_SYM(uintptr_t, __MTK_MMAP_POINTER_POOL_END_UNALIGNED__, MTK_MMAP_POINTER_POOL_END_UNALIGNED); +IMPORT_SYM(uintptr_t, __RW_START__, RW_START); +IMPORT_SYM(uintptr_t, __DATA_START__, DATA_START); + +#define MAP_MTK_SECTIONS MAP_REGION_FLAT(RW_START, \ + DATA_START - RW_START, \ + MT_MEMORY | MT_RO | MT_SECURE) + + +static void print_mmap(const mmap_region_t *regions) +{ + while (regions->size != 0U) { + VERBOSE("Region: 0x%lx - 0x%lx has attributes 0x%x\n", + regions->base_va, + regions->base_va + regions->size, + regions->attr); + regions++; + } +} + +void mtk_xlat_init(const mmap_region_t *bl_regions) +{ + struct mtk_mmap_descriptor *iter; + const mmap_region_t *regions = bl_regions; + + print_mmap(regions); + mmap_add(bl_regions); + if (MTK_MMAP_POINTER_POOL_START != MTK_MMAP_POINTER_POOL_END_UNALIGNED) { + for (iter = (struct mtk_mmap_descriptor *)MTK_MMAP_POINTER_POOL_START; + (char *)iter < (char *)MTK_MMAP_POINTER_POOL_END_UNALIGNED; + iter++) { + regions = iter->mmap_ptr; + INFO("mmap_name: %s\n", iter->mmap_name); + INFO("mmap_size: 0x%x\n", iter->mmap_size); + print_mmap(regions); + mmap_add(regions); + } + } + init_xlat_tables(); + enable_mmu_el3(0); +} diff --git a/plat/mediatek/lib/mtk_init/rules.mk b/plat/mediatek/lib/mtk_init/rules.mk new file mode 100644 index 000000000..cc6ca9569 --- /dev/null +++ b/plat/mediatek/lib/mtk_init/rules.mk @@ -0,0 +1,14 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := mtk_init + +LOCAL_SRCS-y := $(LOCAL_DIR)/mtk_init.c +LOCAL_SRCS-y += $(LOCAL_DIR)/mtk_mmap_init.c + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/lib/pm/armv8_2/pwr_ctrl.c b/plat/mediatek/lib/pm/armv8_2/pwr_ctrl.c new file mode 100644 index 000000000..447234a32 --- /dev/null +++ b/plat/mediatek/lib/pm/armv8_2/pwr_ctrl.c @@ -0,0 +1,543 @@ +/* + * Copyright (c) 2022, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> + +#include <common/debug.h> +#include <drivers/arm/gicv3.h> +#include <lib/psci/psci.h> +#include <lib/utils.h> +#ifdef MTK_PUBEVENT_ENABLE +#include <vendor_pubsub_events.h> +#endif +#include <plat/arm/common/plat_arm.h> +#include <plat/common/platform.h> + +#include <dfd.h> +#include <lib/mtk_init/mtk_init.h> +#include <lib/pm/mtk_pm.h> +#include <mt_gic_v3.h> +#include <platform_def.h> + +#define IS_AFFLV_PUBEVENT(_pstate) \ + ((_pstate & (MT_CPUPM_PWR_DOMAIN_MCUSYS | MT_CPUPM_PWR_DOMAIN_CLUSTER)) != 0) + +#ifdef MTK_PUBEVENT_ENABLE +#define MT_CPUPM_EVENT_PWR_ON(x) ({ \ + PUBLISH_EVENT_ARG(mt_cpupm_publish_pwr_on, (const void *)(x)); }) + +#define MT_CPUPM_EVENT_PWR_OFF(x) ({ \ + PUBLISH_EVENT_ARG(mt_cpupm_publish_pwr_off, (const void *)(x)); }) + +#define MT_CPUPM_EVENT_AFFLV_PWR_ON(x) ({ \ + PUBLISH_EVENT_ARG(mt_cpupm_publish_afflv_pwr_on, (const void *)(x)); }) + +#define MT_CPUPM_EVENT_AFFLV_PWR_OFF(x) ({ \ + PUBLISH_EVENT_ARG(mt_cpupm_publish_afflv_pwr_off, (const void *)(x)); }) + +#else +#define MT_CPUPM_EVENT_PWR_ON(x) ({ (void)x; }) +#define MT_CPUPM_EVENT_PWR_OFF(x) ({ (void)x; }) +#define MT_CPUPM_EVENT_AFFLV_PWR_ON(x) ({ (void)x; }) +#define MT_CPUPM_EVENT_AFFLV_PWR_OFF(x) ({ (void)x; }) +#endif + +/* + * The cpu require to cluster power stattus + * [0] : The cpu require cluster power down + * [1] : The cpu require cluster power on + */ +#define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff) +#define coordinate_cluster_pwron() coordinate_cluster(1) +#define coordinate_cluster_pwroff() coordinate_cluster(0) + +/* defaultly disable all functions */ +#define MTK_CPUPM_FN_MASK_DEFAULT (0) + +struct mtk_cpu_pwr_ctrl { + unsigned int fn_mask; + struct mtk_cpu_pm_ops *ops; + struct mtk_cpu_smp_ops *smp; +}; + +static struct mtk_cpu_pwr_ctrl mtk_cpu_pwr = { + .fn_mask = MTK_CPUPM_FN_MASK_DEFAULT, + .ops = NULL, +}; + +#define IS_CPUIDLE_FN_ENABLE(x) ((mtk_cpu_pwr.ops != NULL) && ((mtk_cpu_pwr.fn_mask & x) != 0)) +#define IS_CPUSMP_FN_ENABLE(x) ((mtk_cpu_pwr.smp != NULL) && ((mtk_cpu_pwr.fn_mask & x) != 0)) + +/* per-cpu power state */ +static unsigned int armv8_2_power_state[PLATFORM_CORE_COUNT]; + +#define armv8_2_get_pwr_stateid(cpu) psci_get_pstate_id(armv8_2_power_state[cpu]) + +static unsigned int get_mediatek_pstate(unsigned int domain, unsigned int psci_state, + struct mtk_cpupm_pwrstate *state) +{ + if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_CPUPM_GET_PWR_STATE)) { + return mtk_cpu_pwr.ops->get_pstate(domain, psci_state, state); + } + + return 0; +} + +unsigned int armv8_2_get_pwr_afflv(const psci_power_state_t *state_info) +{ + int i; + + for (i = (int)PLAT_MAX_PWR_LVL; i >= (int)PSCI_CPU_PWR_LVL; i--) { + if (is_local_state_run(state_info->pwr_domain_state[i]) == 0) { + return (unsigned int) i; + } + } + + return PSCI_INVALID_PWR_LVL; +} + +/* MediaTek mcusys power on control interface */ +static void armv8_2_mcusys_pwr_on_common(const struct mtk_cpupm_pwrstate *state) +{ + gicv3_distif_init(); + mt_gic_distif_restore(); + gic_sgi_restore_all(); + + dfd_resume(); + + /* Add code here that behavior before system enter mcusys'on */ + if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_RESUME_MCUSYS)) { + mtk_cpu_pwr.ops->mcusys_resume(state); + } +} + +/* MediaTek mcusys power down control interface */ +static void armv8_2_mcusys_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state) +{ + mt_gic_distif_save(); + gic_sgi_save_all(); + + /* Add code here that behaves before entering mcusys off */ + if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_SUSPEND_MCUSYS)) { + mtk_cpu_pwr.ops->mcusys_suspend(state); + } +} + +/* MediaTek Cluster power on control interface */ +static void armv8_2_cluster_pwr_on_common(const struct mtk_cpupm_pwrstate *state) +{ + /* Add code here that behavior before system enter cluster'on */ +#if defined(MTK_CM_MGR) && !defined(MTK_FPGA_EARLY_PORTING) + /* init cpu stall counter */ + init_cpu_stall_counter_all(); +#endif + + if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_RESUME_CLUSTER)) { + mtk_cpu_pwr.ops->cluster_resume(state); + } +} + +/* MediaTek Cluster power down control interface */ +static void armv8_2_cluster_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state) +{ + if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_SUSPEND_CLUSTER)) { + mtk_cpu_pwr.ops->cluster_suspend(state); + } +} + +/* MediaTek CPU power on control interface */ +static void armv8_2_cpu_pwr_on_common(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) +{ + coordinate_cluster_pwron(); + + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); + + /* If MCUSYS has been powered down then restore GIC redistributor for all CPUs. */ + if (IS_PLAT_SYSTEM_RETENTION(state->pwr.afflv)) { + mt_gic_rdistif_restore_all(); + } else { + mt_gic_rdistif_restore(); + } +} + +/* MediaTek CPU power down control interface */ +static void armv8_2_cpu_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) +{ + if ((pstate & MT_CPUPM_PWR_DOMAIN_PERCORE_DSU) != 0) { + coordinate_cluster_pwroff(); + } + + mt_gic_rdistif_save(); + gicv3_cpuif_disable(plat_my_core_pos()); + gicv3_rdistif_off(plat_my_core_pos()); +} + +static void armv8_2_cpu_pwr_resume(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) +{ + armv8_2_cpu_pwr_on_common(state, pstate); + if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_RESUME_CORE)) { + mtk_cpu_pwr.ops->cpu_resume(state); + } +} + +static void armv8_2_cpu_pwr_suspend(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) +{ + if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_SUSPEND_CORE)) { + mtk_cpu_pwr.ops->cpu_suspend(state); + } + armv8_2_cpu_pwr_dwn_common(state, pstate); +} + +static void armv8_2_cpu_pwr_on(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) +{ + armv8_2_cpu_pwr_on_common(state, pstate); + + if (IS_CPUSMP_FN_ENABLE(MTK_CPUPM_FN_SMP_CORE_ON)) { + mtk_cpu_pwr.smp->cpu_on(state); + } +} + +static void armv8_2_cpu_pwr_off(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) +{ + if (IS_CPUSMP_FN_ENABLE(MTK_CPUPM_FN_SMP_CORE_OFF)) { + mtk_cpu_pwr.smp->cpu_off(state); + } + armv8_2_cpu_pwr_dwn_common(state, pstate); +} + +/* MediaTek PSCI power domain */ +static int armv8_2_power_domain_on(u_register_t mpidr) +{ + int ret = PSCI_E_SUCCESS; + int cpu = plat_core_pos_by_mpidr(mpidr); + uintptr_t entry = plat_pm_get_warm_entry(); + + if (IS_CPUSMP_FN_ENABLE(MTK_CPUPM_FN_PWR_ON_CORE_PREPARE)) { + if (mtk_cpu_pwr.smp->cpu_pwr_on_prepare(cpu, entry) != 0) { + ret = PSCI_E_DENIED; + } + } + INFO("CPU %u power domain prepare on\n", cpu); + return ret; +} + +/* MediaTek PSCI power domain */ +static void armv8_2_power_domain_on_finish(const psci_power_state_t *state) +{ + struct mt_cpupm_event_data nb; + unsigned int pstate = (MT_CPUPM_PWR_DOMAIN_CORE | MT_CPUPM_PWR_DOMAIN_PERCORE_DSU); + struct mtk_cpupm_pwrstate pm_state = { + .info = { + .cpuid = plat_my_core_pos(), + .mode = MTK_CPU_PM_SMP, + }, + .pwr = { + .afflv = armv8_2_get_pwr_afflv(state), + .state_id = 0x0, + }, + }; + + armv8_2_cpu_pwr_on(&pm_state, pstate); + + nb.cpuid = pm_state.info.cpuid; + nb.pwr_domain = pstate; + MT_CPUPM_EVENT_PWR_ON(&nb); + + INFO("CPU %u power domain on finished\n", pm_state.info.cpuid); +} + +/* MediaTek PSCI power domain */ +static void armv8_2_power_domain_off(const psci_power_state_t *state) +{ + struct mt_cpupm_event_data nb; + unsigned int pstate = (MT_CPUPM_PWR_DOMAIN_CORE | MT_CPUPM_PWR_DOMAIN_PERCORE_DSU); + struct mtk_cpupm_pwrstate pm_state = { + .info = { + .cpuid = plat_my_core_pos(), + .mode = MTK_CPU_PM_SMP, + }, + .pwr = { + .afflv = armv8_2_get_pwr_afflv(state), + .state_id = 0x0, + }, + }; + armv8_2_cpu_pwr_off(&pm_state, pstate); + + nb.cpuid = pm_state.info.cpuid; + nb.pwr_domain = pstate; + MT_CPUPM_EVENT_PWR_OFF(&nb); + + INFO("CPU %u power domain off\n", pm_state.info.cpuid); +} + +/* MediaTek PSCI power domain */ +static void armv8_2_power_domain_suspend(const psci_power_state_t *state) +{ + unsigned int pstate = 0; + struct mt_cpupm_event_data nb; + struct mtk_cpupm_pwrstate pm_state = { + .info = { + .cpuid = plat_my_core_pos(), + .mode = MTK_CPU_PM_CPUIDLE, + }, + }; + + pm_state.pwr.state_id = armv8_2_get_pwr_stateid(pm_state.info.cpuid); + pm_state.pwr.afflv = armv8_2_get_pwr_afflv(state); + pm_state.pwr.raw = state; + + pstate = get_mediatek_pstate(CPUPM_PWR_OFF, + armv8_2_power_state[pm_state.info.cpuid], &pm_state); + + armv8_2_cpu_pwr_suspend(&pm_state, pstate); + + if ((pstate & MT_CPUPM_PWR_DOMAIN_CLUSTER) != 0) { + armv8_2_cluster_pwr_dwn_common(&pm_state); + } + + if ((pstate & MT_CPUPM_PWR_DOMAIN_MCUSYS) != 0) { + armv8_2_mcusys_pwr_dwn_common(&pm_state); + } + + nb.cpuid = pm_state.info.cpuid; + nb.pwr_domain = pstate; + MT_CPUPM_EVENT_PWR_OFF(&nb); + + if (IS_AFFLV_PUBEVENT(pstate)) { + MT_CPUPM_EVENT_AFFLV_PWR_OFF(&nb); + } +} + +/* MediaTek PSCI power domain */ +static void armv8_2_power_domain_suspend_finish(const psci_power_state_t *state) +{ + unsigned int pstate = 0; + struct mt_cpupm_event_data nb; + struct mtk_cpupm_pwrstate pm_state = { + .info = { + .cpuid = plat_my_core_pos(), + .mode = MTK_CPU_PM_CPUIDLE, + }, + }; + + pm_state.pwr.state_id = armv8_2_get_pwr_stateid(pm_state.info.cpuid); + pm_state.pwr.afflv = armv8_2_get_pwr_afflv(state); + pm_state.pwr.raw = state; + + pstate = get_mediatek_pstate(CPUPM_PWR_ON, + armv8_2_power_state[pm_state.info.cpuid], &pm_state); + + if ((pstate & MT_CPUPM_PWR_DOMAIN_MCUSYS) != 0) { + armv8_2_mcusys_pwr_on_common(&pm_state); + } + + if ((pstate & MT_CPUPM_PWR_DOMAIN_CLUSTER) != 0) { + armv8_2_cluster_pwr_on_common(&pm_state); + } + + armv8_2_cpu_pwr_resume(&pm_state, pstate); + + nb.cpuid = pm_state.info.cpuid; + nb.pwr_domain = pstate; + MT_CPUPM_EVENT_PWR_ON(&nb); + + if (IS_AFFLV_PUBEVENT(pstate)) { + MT_CPUPM_EVENT_AFFLV_PWR_ON(&nb); + } +} + +/* MediaTek PSCI power domain */ +static int armv8_2_validate_power_state(unsigned int power_state, psci_power_state_t *req_state) +{ + unsigned int i; + unsigned int pstate = psci_get_pstate_type(power_state); + unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state); + unsigned int my_core_pos = plat_my_core_pos(); + + if (mtk_cpu_pwr.ops == NULL) { + return PSCI_E_INVALID_PARAMS; + } + + if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_PWR_STATE_VALID)) { + if (mtk_cpu_pwr.ops->pwr_state_valid(aff_lvl, pstate) != 0) { + return PSCI_E_INVALID_PARAMS; + } + } + + if (pstate == PSTATE_TYPE_STANDBY) { + req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE; + } else { + for (i = PSCI_CPU_PWR_LVL; i <= aff_lvl; i++) { + req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; + } + } + armv8_2_power_state[my_core_pos] = power_state; + + return PSCI_E_SUCCESS; +} + +/* MediaTek PSCI power domain */ +#if CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND +static void armv8_2_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + unsigned int i; + int ret; + unsigned int power_state; + unsigned int my_core_pos = plat_my_core_pos(); + + ret = mtk_cpu_pwr.ops->pwr_state_valid(PLAT_MAX_PWR_LVL, + PSTATE_TYPE_POWERDOWN); + + if (ret != MTK_CPUPM_E_OK) { + /* Avoid suspend due to platform is not ready. */ + req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = + PLAT_MAX_RET_STATE; + for (i = PSCI_CPU_PWR_LVL + 1; i <= PLAT_MAX_PWR_LVL; i++) { + req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN; + } + + power_state = psci_make_powerstate(0, PSTATE_TYPE_STANDBY, PSCI_CPU_PWR_LVL); + } else { + for (i = PSCI_CPU_PWR_LVL; i <= PLAT_MAX_PWR_LVL; i++) { + req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; + } + + power_state = psci_make_powerstate(MT_PLAT_PWR_STATE_SUSPEND, + PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL); + } + + armv8_2_power_state[my_core_pos] = power_state; + flush_dcache_range((uintptr_t)&armv8_2_power_state[my_core_pos], + sizeof(armv8_2_power_state[my_core_pos])); +} +#endif +static void armv8_2_pm_smp_init(unsigned int cpu_id, uintptr_t entry_point) +{ + if (entry_point == 0) { + ERROR("%s, warm_entry_point is null\n", __func__); + panic(); + } + if (IS_CPUSMP_FN_ENABLE(MTK_CPUPM_FN_SMP_INIT)) { + mtk_cpu_pwr.smp->init(cpu_id, entry_point); + } + INFO("[%s:%d] - Initialize finished\n", __func__, __LINE__); +} + +static struct plat_pm_pwr_ctrl armv8_2_pwr_ops = { + .pwr_domain_suspend = armv8_2_power_domain_suspend, + .pwr_domain_suspend_finish = armv8_2_power_domain_suspend_finish, + .validate_power_state = armv8_2_validate_power_state, +#if CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND + .get_sys_suspend_power_state = armv8_2_get_sys_suspend_power_state, +#endif +}; + +struct plat_pm_smp_ctrl armv8_2_smp_ops = { + .init = armv8_2_pm_smp_init, + .pwr_domain_on = armv8_2_power_domain_on, + .pwr_domain_off = armv8_2_power_domain_off, + .pwr_domain_on_finish = armv8_2_power_domain_on_finish, +}; + +#define ISSUE_CPU_PM_REG_FAIL(_success) ({ _success = false; assert(0); }) + +#define CPM_PM_FN_CHECK(_fns, _ops, _id, _func, _result, _flag) ({ \ + if ((_fns & _id)) { \ + if (_ops->_func) \ + _flag |= _id; \ + else { \ + ISSUE_CPU_PM_REG_FAIL(_result); \ + } \ + } }) + +int register_cpu_pm_ops(unsigned int fn_flags, struct mtk_cpu_pm_ops *ops) +{ + bool success = true; + unsigned int fns = 0; + + if ((ops == NULL) || (mtk_cpu_pwr.ops != NULL)) { + ERROR("[%s:%d] register cpu_pm fail !!\n", __FILE__, __LINE__); + return MTK_CPUPM_E_ERR; + } + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_RESUME_CORE, + cpu_resume, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SUSPEND_CORE, + cpu_suspend, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_RESUME_CLUSTER, + cluster_resume, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SUSPEND_CLUSTER, + cluster_suspend, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_RESUME_MCUSYS, + mcusys_resume, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SUSPEND_MCUSYS, + mcusys_suspend, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_CPUPM_GET_PWR_STATE, + get_pstate, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_PWR_STATE_VALID, + pwr_state_valid, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_INIT, + init, success, fns); + + if (success) { + mtk_cpu_pwr.ops = ops; + mtk_cpu_pwr.fn_mask |= fns; + plat_pm_ops_setup_pwr(&armv8_2_pwr_ops); + INFO("[%s:%d] CPU pwr ops register success, support:0x%x\n", + __func__, __LINE__, fns); + } else { + ERROR("[%s:%d] register cpu_pm ops fail !, fn:0x%x\n", + __func__, __LINE__, fn_flags); + assert(0); + } + return MTK_CPUPM_E_OK; +} + +int register_cpu_smp_ops(unsigned int fn_flags, struct mtk_cpu_smp_ops *ops) +{ + bool success = true; + unsigned int fns = 0; + + if ((ops == NULL) || (mtk_cpu_pwr.smp != NULL)) { + ERROR("[%s:%d] register cpu_smp fail !!\n", __FILE__, __LINE__); + return MTK_CPUPM_E_ERR; + } + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SMP_INIT, + init, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_PWR_ON_CORE_PREPARE, + cpu_pwr_on_prepare, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SMP_CORE_ON, + cpu_on, success, fns); + + CPM_PM_FN_CHECK(fn_flags, ops, MTK_CPUPM_FN_SMP_CORE_OFF, + cpu_off, success, fns); + + if (success == true) { + mtk_cpu_pwr.smp = ops; + mtk_cpu_pwr.fn_mask |= fns; + plat_pm_ops_setup_smp(&armv8_2_smp_ops); + INFO("[%s:%d] CPU smp ops register success, support:0x%x\n", + __func__, __LINE__, fns); + } else { + ERROR("[%s:%d] register cpu_smp ops fail !, fn:0x%x\n", + __func__, __LINE__, fn_flags); + assert(0); + } + return MTK_CPUPM_E_OK; +} diff --git a/plat/mediatek/lib/pm/armv8_2/rules.mk b/plat/mediatek/lib/pm/armv8_2/rules.mk new file mode 100644 index 000000000..0e065c54c --- /dev/null +++ b/plat/mediatek/lib/pm/armv8_2/rules.mk @@ -0,0 +1,12 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := armv${CONFIG_MTK_PM_ARCH} +LOCAL_SRCS-y := ${LOCAL_DIR}/pwr_ctrl.c + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/lib/pm/mtk_pm.c b/plat/mediatek/lib/pm/mtk_pm.c new file mode 100644 index 000000000..3dbeb511e --- /dev/null +++ b/plat/mediatek/lib/pm/mtk_pm.c @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <plat/common/platform.h> +#include <lib/pm/mtk_pm.h> + +#define MTK_PM_ST_SMP_READY BIT(0) +#define MTK_PM_ST_PWR_READY BIT(1) +#define MTK_PM_ST_RESET_READY BIT(2) + +static uintptr_t mtk_secure_entrypoint; +static plat_init_func mtk_plat_smp_init; +static plat_psci_ops_t mtk_pm_ops; +static unsigned int mtk_pm_status; + +uintptr_t plat_pm_get_warm_entry(void) +{ + return mtk_secure_entrypoint; +} + +int plat_pm_ops_setup_pwr(struct plat_pm_pwr_ctrl *ops) +{ + if (!ops) { + return MTK_CPUPM_E_FAIL; + } + +#if CONFIG_MTK_CPU_SUSPEND_EN + if (!mtk_pm_ops.pwr_domain_suspend) { + mtk_pm_ops.pwr_domain_suspend = ops->pwr_domain_suspend; + } + + if (!mtk_pm_ops.pwr_domain_suspend_finish) { + mtk_pm_ops.pwr_domain_suspend_finish = ops->pwr_domain_suspend_finish; + } + + if (!mtk_pm_ops.validate_power_state) { + mtk_pm_ops.validate_power_state = ops->validate_power_state; + } + + if (!mtk_pm_ops.get_sys_suspend_power_state) { + mtk_pm_ops.get_sys_suspend_power_state = ops->get_sys_suspend_power_state; + } + + mtk_pm_status |= MTK_PM_ST_PWR_READY; +#endif + return MTK_CPUPM_E_OK; +} + +int plat_pm_ops_setup_smp(struct plat_pm_smp_ctrl *ops) +{ + if (!ops) { + return MTK_CPUPM_E_FAIL; + } + +#if CONFIG_MTK_SMP_EN + if (!mtk_pm_ops.pwr_domain_on) { + mtk_pm_ops.pwr_domain_on = ops->pwr_domain_on; + } + + if (!mtk_pm_ops.pwr_domain_on_finish) { + mtk_pm_ops.pwr_domain_on_finish = ops->pwr_domain_on_finish; + } + + if (!mtk_pm_ops.pwr_domain_off) { + mtk_pm_ops.pwr_domain_off = ops->pwr_domain_off; + } + + if (!mtk_plat_smp_init) { + mtk_plat_smp_init = ops->init; + } + + mtk_pm_status |= MTK_PM_ST_SMP_READY; +#endif + return MTK_CPUPM_E_OK; +} + +int plat_pm_ops_setup_reset(struct plat_pm_reset_ctrl *ops) +{ + if (!ops) { + return MTK_CPUPM_E_FAIL; + } + + if (!mtk_pm_ops.system_off) { + mtk_pm_ops.system_off = ops->system_off; + } + + if (!mtk_pm_ops.system_reset) { + mtk_pm_ops.system_reset = ops->system_reset; + } + + if (!mtk_pm_ops.system_reset2) { + mtk_pm_ops.system_reset2 = ops->system_reset2; + } + + mtk_pm_status |= MTK_PM_ST_RESET_READY; + + return MTK_CPUPM_E_OK; +} + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + *psci_ops = &mtk_pm_ops; + mtk_secure_entrypoint = sec_entrypoint; + + if (mtk_plat_smp_init) { + unsigned int cpu_id = plat_my_core_pos(); + + mtk_plat_smp_init(cpu_id, mtk_secure_entrypoint); + } + INFO("%s, smp:(%d), pwr_ctrl:(%d), system_reset:(%d)\n", __func__, + !!(mtk_pm_status & MTK_PM_ST_SMP_READY), + !!(mtk_pm_status & MTK_PM_ST_PWR_READY), + !!(mtk_pm_status & MTK_PM_ST_RESET_READY)); + return 0; +} diff --git a/plat/mediatek/lib/pm/mtk_pm.h b/plat/mediatek/lib/pm/mtk_pm.h new file mode 100644 index 000000000..4a2943956 --- /dev/null +++ b/plat/mediatek/lib/pm/mtk_pm.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2022, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MTK_PM_H +#define MTK_PM_H +#include <lib/psci/psci.h> + +#if MTK_PUBEVENT_ENABLE +#include <vendor_pubsub_events.h> +#endif + +#define MTK_CPUPM_E_OK (0) +#define MTK_CPUPM_E_UNKNOWN (-1) +#define MTK_CPUPM_E_ERR (-2) +#define MTK_CPUPM_E_FAIL (-3) +#define MTK_CPUPM_E_NOT_SUPPORT (-4) + + +#define MTK_CPUPM_FN_PWR_LOCK_AQUIRE BIT(0) +#define MTK_CPUPM_FN_INIT BIT(1) +#define MTK_CPUPM_FN_PWR_STATE_VALID BIT(2) +#define MTK_CPUPM_FN_PWR_ON_CORE_PREPARE BIT(3) +#define MTK_CPUPM_FN_SUSPEND_CORE BIT(4) +#define MTK_CPUPM_FN_RESUME_CORE BIT(5) +#define MTK_CPUPM_FN_SUSPEND_CLUSTER BIT(6) +#define MTK_CPUPM_FN_RESUME_CLUSTER BIT(7) +#define MTK_CPUPM_FN_SUSPEND_MCUSYS BIT(8) +#define MTK_CPUPM_FN_RESUME_MCUSYS BIT(9) +#define MTK_CPUPM_FN_CPUPM_GET_PWR_STATE BIT(10) +#define MTK_CPUPM_FN_SMP_INIT BIT(11) +#define MTK_CPUPM_FN_SMP_CORE_ON BIT(12) +#define MTK_CPUPM_FN_SMP_CORE_OFF BIT(13) + +enum mtk_cpupm_pstate { + MTK_CPUPM_CORE_ON, + MTK_CPUPM_CORE_OFF, + MTK_CPUPM_CORE_SUSPEND, + MTK_CPUPM_CORE_RESUME, + MTK_CPUPM_CLUSTER_SUSPEND, + MTK_CPUPM_CLUSTER_RESUME, + MTK_CPUPM_MCUSYS_SUSPEND, + MTK_CPUPM_MCUSYS_RESUME, +}; + +enum mtk_cpu_pm_mode { + MTK_CPU_PM_CPUIDLE, + MTK_CPU_PM_SMP, +}; + +#define MT_IRQ_REMAIN_MAX (32) +#define MT_IRQ_REMAIN_CAT_LOG BIT(31) + +struct mt_irqremain { + unsigned int count; + unsigned int irqs[MT_IRQ_REMAIN_MAX]; + unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX]; + unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX]; +}; + +typedef void (*plat_init_func)(unsigned int, uintptr_t); + +struct plat_pm_smp_ctrl { + plat_init_func init; + int (*pwr_domain_on)(u_register_t mpidr); + void (*pwr_domain_off)(const psci_power_state_t *target_state); + void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); +}; + +struct plat_pm_pwr_ctrl { + void (*pwr_domain_suspend)(const psci_power_state_t *target_state); + void (*pwr_domain_on_finish_late)(const psci_power_state_t *target_state); + void (*pwr_domain_suspend_finish)(const psci_power_state_t *target_state); + int (*validate_power_state)(unsigned int power_state, psci_power_state_t *req_state); + void (*get_sys_suspend_power_state)(psci_power_state_t *req_state); +}; + +struct plat_pm_reset_ctrl { + __dead2 void (*system_off)(); + __dead2 void (*system_reset)(); + int (*system_reset2)(int is_vendor, int reset_type, u_register_t cookie); +}; + +struct mtk_cpu_pm_info { + unsigned int cpuid; + unsigned int mode; +}; + +struct mtk_cpu_pm_state { + unsigned int afflv; + unsigned int state_id; + const psci_power_state_t *raw; +}; + +struct mtk_cpupm_pwrstate { + struct mtk_cpu_pm_info info; + struct mtk_cpu_pm_state pwr; +}; + +struct mtk_cpu_smp_ops { + void (*init)(unsigned int cpu, uintptr_t sec_entrypoint); + int (*cpu_pwr_on_prepare)(unsigned int cpu, uintptr_t entry); + void (*cpu_on)(const struct mtk_cpupm_pwrstate *state); + void (*cpu_off)(const struct mtk_cpupm_pwrstate *state); + int (*invoke)(unsigned int funcID, void *priv); +}; + +#define MT_CPUPM_PWR_DOMAIN_CORE BIT(0) +#define MT_CPUPM_PWR_DOMAIN_PERCORE_DSU BIT(1) +#define MT_CPUPM_PWR_DOMAIN_PERCORE_DSU_MEM BIT(2) +#define MT_CPUPM_PWR_DOMAIN_CLUSTER BIT(3) +#define MT_CPUPM_PWR_DOMAIN_MCUSYS BIT(4) +#define MT_CPUPM_PWR_DOMAIN_SUSPEND BIT(5) + +enum mt_cpupm_pwr_domain { + CPUPM_PWR_ON, + CPUPM_PWR_OFF, +}; + +typedef unsigned int mtk_pstate_type; + +struct mtk_cpu_pm_ops { + void (*init)(unsigned int cpu, uintptr_t sec_entrypoint); + unsigned int (*get_pstate)(enum mt_cpupm_pwr_domain domain, + const mtk_pstate_type psci_state, + const struct mtk_cpupm_pwrstate *state); + int (*pwr_state_valid)(unsigned int afflv, unsigned int state); + void (*cpu_suspend)(const struct mtk_cpupm_pwrstate *state); + void (*cpu_resume)(const struct mtk_cpupm_pwrstate *state); + void (*cluster_suspend)(const struct mtk_cpupm_pwrstate *state); + void (*cluster_resume)(const struct mtk_cpupm_pwrstate *state); + void (*mcusys_suspend)(const struct mtk_cpupm_pwrstate *state); + void (*mcusys_resume)(const struct mtk_cpupm_pwrstate *state); + int (*invoke)(unsigned int funcID, void *priv); +}; + +int register_cpu_pm_ops(unsigned int fn_flags, struct mtk_cpu_pm_ops *ops); +int register_cpu_smp_ops(unsigned int fn_flags, struct mtk_cpu_smp_ops *ops); + +struct mt_cpupm_event_data { + unsigned int cpuid; + unsigned int pwr_domain; +}; + +/* Extension event for platform driver */ +#if MTK_PUBEVENT_ENABLE +/* [PUB_EVENT] Core power on */ +#define MT_CPUPM_SUBCRIBE_EVENT_PWR_ON(_fn) \ + SUBSCRIBE_TO_EVENT(mt_cpupm_publish_pwr_on, _fn) + +/* [PUB_EVENT] Core power off */ +#define MT_CPUPM_SUBCRIBE_EVENT_PWR_OFF(_fn) \ + SUBSCRIBE_TO_EVENT(mt_cpupm_publish_pwr_off, _fn) + +/* [PUB_EVENT] Cluster power on */ +#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_ON(_fn) \ + SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_on, _fn) + +/* [PUB_EVENT] Cluster power off */ +#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_OFF(_fn) \ + SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_off, _fn) + +/* [PUB_EVENT] Mcusys power on */ +#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_ON(_fn) \ + SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_on, _fn) + +/* [PUB_EVENT] Mcusys power off */ +#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_OFF(_fn) \ + SUBSCRIBE_TO_EVENT(mt_cpupm_publish_afflv_pwr_off, _fn) + +#else +#define MT_CPUPM_SUBCRIBE_EVENT_PWR_ON(_fn) +#define MT_CPUPM_SUBCRIBE_EVENT_PWR_OFF(_fn) +#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_ON(_fn) +#define MT_CPUPM_SUBCRIBE_CLUSTER_PWR_OFF(_fn) +#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_ON(_fn) +#define MT_CPUPM_SUBCRIBE_MCUSYS_PWR_OFF(_fn) +#endif + +/* + * Definition c-state power domain. + * bit[7:4] (main state id): + * - 1: Cluster. + * - 2: Mcusys. + * - 3: Memory. + * - 4: System pll. + * - 5: System bus. + * - 6: SoC 26m/DCXO. + * - 7: Vcore buck. + * - 15: Suspend. + * bit[3:0] (reserved for state_id extension): + * - 4: CPU buck. + */ +#define MT_PLAT_PWR_STATE_CLUSTER (0x0010) +#define MT_PLAT_PWR_STATE_MCUSYS (0x0020) +#define MT_PLAT_PWR_STATE_MCUSYS_BUCK (0x0024) +#define MT_PLAT_PWR_STATE_SYSTEM_MEM (0x0030) +#define MT_PLAT_PWR_STATE_SYSTEM_PLL (0x0040) +#define MT_PLAT_PWR_STATE_SYSTEM_BUS (0x0050) +#define MT_PLAT_PWR_STATE_SUSPEND (0x00f0) + +#define IS_MT_PLAT_PWR_STATE(state, target_state) ((state & target_state) == target_state) +#define IS_MT_PLAT_PWR_STATE_MCUSYS(state) IS_MT_PLAT_PWR_STATE(state, MT_PLAT_PWR_STATE_MCUSYS) + +#define PLAT_MT_SYSTEM_SUSPEND PLAT_MAX_OFF_STATE +#define PLAT_MT_CPU_SUSPEND_CLUSTER PLAT_MAX_RET_STATE +#define PLAT_MT_CPU_SUSPEND_MCUSYS PLAT_MAX_RET_STATE + +#define IS_PLAT_SYSTEM_SUSPEND(aff) (aff == PLAT_MT_SYSTEM_SUSPEND) +#define IS_PLAT_SYSTEM_RETENTION(aff) (aff >= PLAT_MAX_RET_STATE) + +#define IS_PLAT_SUSPEND_ID(stateid) (stateid == MT_PLAT_PWR_STATE_SUSPEND) + +#define IS_PLAT_MCUSYSOFF_AFFLV(afflv) (afflv >= PLAT_MT_CPU_SUSPEND_MCUSYS) + +int plat_pm_ops_setup_pwr(struct plat_pm_pwr_ctrl *ops); +int plat_pm_ops_setup_reset(struct plat_pm_reset_ctrl *ops); +int plat_pm_ops_setup_smp(struct plat_pm_smp_ctrl *ops); +uintptr_t plat_pm_get_warm_entry(void); + +#endif diff --git a/plat/mediatek/lib/pm/rules.mk b/plat/mediatek/lib/pm/rules.mk new file mode 100644 index 000000000..29265c485 --- /dev/null +++ b/plat/mediatek/lib/pm/rules.mk @@ -0,0 +1,17 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := pm + +LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_pm.c + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) + +SUB_RULES-$(CONFIG_MTK_PM_SUPPORT) := $(LOCAL_DIR)/armv${CONFIG_MTK_PM_ARCH} +$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y))) diff --git a/plat/mediatek/lib/system_reset/reset_cros.c b/plat/mediatek/lib/system_reset/reset_cros.c new file mode 100644 index 000000000..40e68ba9f --- /dev/null +++ b/plat/mediatek/lib/system_reset/reset_cros.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/gpio.h> +#include <lib/mtk_init/mtk_init.h> +#include <lib/pm/mtk_pm.h> +#include <plat_params.h> +#include <pmic.h> +#include <rtc.h> + +static void __dead2 mtk_system_reset_cros(void) +{ + struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset(); + + INFO("MTK System Reset\n"); + + gpio_set_value(gpio_reset->index, gpio_reset->polarity); + + wfi(); + ERROR("MTK System Reset: operation not handled.\n"); + panic(); +} + +static void __dead2 mtk_system_off_cros(void) +{ + INFO("MTK System Off\n"); + + rtc_power_off_sequence(); + pmic_power_off(); + + wfi(); + ERROR("MTK System Off: operation not handled.\n"); + panic(); +} + +static struct plat_pm_reset_ctrl lib_reset_ctrl = { + .system_off = mtk_system_off_cros, + .system_reset = mtk_system_reset_cros, + .system_reset2 = NULL, +}; + +static int lib_reset_ctrl_init(void) +{ + INFO("Reset init\n"); + + plat_pm_ops_setup_reset(&lib_reset_ctrl); + + return 0; +} +MTK_ARCH_INIT(lib_reset_ctrl_init); diff --git a/plat/mediatek/lib/system_reset/rules.mk b/plat/mediatek/lib/system_reset/rules.mk new file mode 100644 index 000000000..4f2066341 --- /dev/null +++ b/plat/mediatek/lib/system_reset/rules.mk @@ -0,0 +1,14 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := system_reset + +LOCAL_SRCS-y := ${LOCAL_DIR}/reset_cros.c + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk index f62802cb9..6bf1aa735 100644 --- a/plat/mediatek/mt8173/platform.mk +++ b/plat/mediatek/mt8173/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -8,6 +8,7 @@ MTK_PLAT := plat/mediatek MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ + -I${MTK_PLAT}/include/ \ -Iinclude/plat/arm/common/aarch64 \ -I${MTK_PLAT_SOC}/drivers/crypt/ \ -I${MTK_PLAT_SOC}/drivers/mtcmos/ \ @@ -36,10 +37,10 @@ BL31_SOURCES += common/desc_image_load.c \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ - ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \ - ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/mtk_sip_svc.c \ + ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init.c \ + ${MTK_PLAT}/drivers/rtc/rtc_common.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/aarch64/platform_common.c \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk index 1615cf953..a737d24b8 100644 --- a/plat/mediatek/mt8183/platform.mk +++ b/plat/mediatek/mt8183/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2019, MediaTek Inc. All rights reserved. +# Copyright (c) 2019-2022, MediaTek Inc. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -8,7 +8,8 @@ MTK_PLAT := plat/mediatek MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ - -I${MTK_PLAT}/common/drivers/uart/ \ + -I${MTK_PLAT}/drivers/uart/ \ + -I${MTK_PLAT}/include/ \ -I${MTK_PLAT_SOC}/drivers/ \ -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \ -I${MTK_PLAT_SOC}/drivers/devapc/ \ @@ -43,10 +44,10 @@ BL31_SOURCES += common/desc_image_load.c \ lib/cpus/aarch64/cortex_a73.S \ plat/common/plat_gicv3.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ - ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \ - ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ - ${MTK_PLAT}/common/drivers/uart/uart.c \ ${MTK_PLAT}/common/params_setup.c \ + ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init.c \ + ${MTK_PLAT}/drivers/rtc/rtc_common.c \ + ${MTK_PLAT}/drivers/uart/uart.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/aarch64/platform_common.c \ ${MTK_PLAT_SOC}/drivers/devapc/devapc.c \ diff --git a/plat/mediatek/mt8186/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8186/drivers/emi_mpu/emi_mpu.c index 989ecf199..1133c86d2 100644 --- a/plat/mediatek/mt8186/drivers/emi_mpu/emi_mpu.c +++ b/plat/mediatek/mt8186/drivers/emi_mpu/emi_mpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -96,5 +96,38 @@ int emi_mpu_set_protection(struct emi_region_info_t *region_info) void emi_mpu_init(void) { - /* TODO: more setting for EMI MPU. */ + struct emi_region_info_t region_info; + + /* SCP DRAM */ + region_info.start = 0x50000000ULL; + region_info.end = 0x5109FFFFULL; + region_info.region = 2; + SET_ACCESS_PERMISSION(region_info.apc, 1, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION, + FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION); + emi_mpu_set_protection(®ion_info); + + /* DSP protect address */ + region_info.start = 0x60000000ULL; /* dram base addr */ + region_info.end = 0x610FFFFFULL; + region_info.region = 3; + SET_ACCESS_PERMISSION(region_info.apc, 1, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION); + emi_mpu_set_protection(®ion_info); + + /* Forbidden All */ + region_info.start = 0x40000000ULL; /* dram base addr */ + region_info.end = 0x1FFFF0000ULL; + region_info.region = 4; + SET_ACCESS_PERMISSION(region_info.apc, 1, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, + FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION); + emi_mpu_set_protection(®ion_info); } diff --git a/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c index 42b2808f9..b5a028439 100644 --- a/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c +++ b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c @@ -4,9 +4,9 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <mt_cirq.h> #include <mt_lp_irqremain.h> #include <mt_lp_rm.h> -#include <mtk_cirq.h> #include <plat_mtk_lpm.h> #define KEYPAD_IRQ_ID U(138) diff --git a/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h index e837456fb..e8cbf7ee6 100644 --- a/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h +++ b/plat/mediatek/mt8186/drivers/pmic/pmic_wrap_init.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,7 @@ #include <stdint.h> #include "platform_def.h" - -/* external API */ -int32_t pwrap_read(uint32_t adr, uint32_t *rdata); -int32_t pwrap_write(uint32_t adr, uint32_t wdata); +#include <pmic_wrap_init_common.h> static struct mt8186_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; @@ -61,34 +58,4 @@ enum { WACS_SYNC_BUSY = 0x00 }; -/* error information flag */ -enum { - E_PWR_INVALID_ARG = 1, - E_PWR_INVALID_RW = 2, - E_PWR_INVALID_ADDR = 3, - E_PWR_INVALID_WDAT = 4, - E_PWR_INVALID_OP_MANUAL = 5, - E_PWR_NOT_IDLE_STATE = 6, - E_PWR_NOT_INIT_DONE = 7, - E_PWR_NOT_INIT_DONE_READ = 8, - E_PWR_WAIT_IDLE_TIMEOUT = 9, - E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, - E_PWR_INIT_SIDLY_FAIL = 11, - E_PWR_RESET_TIMEOUT = 12, - E_PWR_TIMEOUT = 13, - E_PWR_INIT_RESET_SPI = 20, - E_PWR_INIT_SIDLY = 21, - E_PWR_INIT_REG_CLOCK = 22, - E_PWR_INIT_ENABLE_PMIC = 23, - E_PWR_INIT_DIO = 24, - E_PWR_INIT_CIPHER = 25, - E_PWR_INIT_WRITE_TEST = 26, - E_PWR_INIT_ENABLE_CRC = 27, - E_PWR_INIT_ENABLE_DEWRAP = 28, - E_PWR_INIT_ENABLE_EVENT = 29, - E_PWR_READ_TEST_FAIL = 30, - E_PWR_WRITE_TEST_FAIL = 31, - E_PWR_SWITCH_DIO = 32 -}; - #endif /* PMIC_WRAP_INIT_H */ diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c index 66fbe912a..dd2aee8f8 100644 --- a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c +++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c @@ -26,7 +26,7 @@ #include <mt_spm_suspend.h> #ifndef ATF_PLAT_CIRQ_UNSUPPORT -#include <mtk_cirq.h> +#include <mt_cirq.h> #endif #include <plat_mtk_lpm.h> diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c index 849ffb7e1..c0000ed74 100644 --- a/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c +++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c @@ -51,10 +51,10 @@ static struct pmic_wrap_setting pw66 = { .addr = { {0UL, 0UL} }, .set[PMIC_WRAP_PHASE_ALLINONE] = { ._[CMD_0] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), }, - ._[CMD_1] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(75000), }, - ._[CMD_2] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(70000), }, - ._[CMD_3] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(65000), }, - ._[CMD_4] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(60000), }, + ._[CMD_1] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), }, + ._[CMD_2] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), }, + ._[CMD_3] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), }, + ._[CMD_4] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), }, ._[CMD_5] = { TOP_SPI_CON0_66, 0x1, }, ._[CMD_6] = { TOP_SPI_CON0_66, 0x0, }, .nr_idx = NR_IDX_ALL, diff --git a/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c index 198bac532..20ef011af 100644 --- a/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c +++ b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c @@ -11,7 +11,7 @@ #include <mt_spm_sspm_intc.h> #include <sspm_reg.h> -#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_3_BASE + x) +#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x) #define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL)) #define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0) diff --git a/plat/mediatek/mt8186/include/plat_sip_calls.h b/plat/mediatek/mt8186/include/plat_sip_calls.h index 9e3726b50..f5c15e38b 100644 --- a/plat/mediatek/mt8186/include/plat_sip_calls.h +++ b/plat/mediatek/mt8186/include/plat_sip_calls.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,6 @@ /******************************************************************************* * Plat SiP function constants ******************************************************************************/ -#define MTK_PLAT_SIP_NUM_CALLS (2) - -/* DFD */ -#define MTK_SIP_KERNEL_DFD_AARCH32 (0x82000205) -#define MTK_SIP_KERNEL_DFD_AARCH64 (0xC2000205) +#define MTK_PLAT_SIP_NUM_CALLS (6) #endif /* PLAT_SIP_CALLS_H */ diff --git a/plat/mediatek/mt8186/include/platform_def.h b/plat/mediatek/mt8186/include/platform_def.h index b8b877a6d..850ce2fc4 100644 --- a/plat/mediatek/mt8186/include/platform_def.h +++ b/plat/mediatek/mt8186/include/platform_def.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,6 +26,8 @@ #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) #define SPM_BASE (IO_PHYS + 0x00006000) #define APMIXEDSYS (IO_PHYS + 0x0000C000) +#define SSPM_MCDI_SHARE_SRAM (IO_PHYS + 0x00420000) +#define SSPM_CFGREG_BASE (IO_PHYS + 0x00440000) /* SSPM view: 0x30040000 */ #define SSPM_MBOX_BASE (IO_PHYS + 0x00480000) #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) #define VPPSYS0_BASE (IO_PHYS + 0x04000000) @@ -70,6 +72,11 @@ #define EMI_MPU_BASE (IO_PHYS + 0x0021B000) /******************************************************************************* + * MSDC related constants + ******************************************************************************/ +#define MSDC0_BASE (IO_PHYS + 0x01230000) + +/******************************************************************************* * GIC-600 & interrupt handling related constants ******************************************************************************/ /* Base MTK_platform compatible GIC memory map */ diff --git a/plat/mediatek/mt8186/include/sspm_reg.h b/plat/mediatek/mt8186/include/sspm_reg.h index 3e8c3e24a..40b71ac93 100644 --- a/plat/mediatek/mt8186/include/sspm_reg.h +++ b/plat/mediatek/mt8186/include/sspm_reg.h @@ -9,12 +9,8 @@ #include "platform_def.h" -#define SSPM_CFGREG_BASE (IO_PHYS + 0x440000) /* SSPM view: 0x30040000 */ #define SSPM_CFGREG_ADDR(ofs) (SSPM_CFGREG_BASE + (ofs)) -#define SSPM_MCDI_SHARE_SRAM (IO_PHYS + 0x420000) -#define SSPM_MBOX_3_BASE (IO_PHYS + 0x480000) - #define SSPM_HW_SEM SSPM_CFGREG_ADDR(0x0048) #define SSPM_ACAO_INT_SET SSPM_CFGREG_ADDR(0x00D8) #define SSPM_ACAO_INT_CLR SSPM_CFGREG_ADDR(0x00DC) diff --git a/plat/mediatek/mt8186/plat_sip_calls.c b/plat/mediatek/mt8186/plat_sip_calls.c index cb66218c9..0e9c27043 100644 --- a/plat/mediatek/mt8186/plat_sip_calls.c +++ b/plat/mediatek/mt8186/plat_sip_calls.c @@ -6,6 +6,8 @@ #include <common/debug.h> #include <common/runtime_svc.h> +#include <lib/mmio.h> +#include <mt_msdc.h> #include <mt_spm_vcorefs.h> #include <mtk_sip_svc.h> #include <plat_dfd.h> @@ -23,8 +25,8 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, uint64_t ret; switch (smc_fid) { - case MTK_SIP_VCORE_CONTROL_ARCH32: - case MTK_SIP_VCORE_CONTROL_ARCH64: + case MTK_SIP_VCORE_CONTROL_AARCH32: + case MTK_SIP_VCORE_CONTROL_AARCH64: ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); SMC_RET2(handle, ret, x4); break; @@ -33,6 +35,11 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, ret = dfd_smc_dispatcher(x1, x2, x3, x4); SMC_RET1(handle, ret); break; + case MTK_SIP_KERNEL_MSDC_AARCH32: + case MTK_SIP_KERNEL_MSDC_AARCH64: + ret = msdc_smc_dispatcher(x1, x2, x3, x4); + SMC_RET1(handle, ret); + break; default: ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); break; diff --git a/plat/mediatek/mt8186/platform.mk b/plat/mediatek/mt8186/platform.mk index b6d9ca8c3..68f4a1f91 100644 --- a/plat/mediatek/mt8186/platform.mk +++ b/plat/mediatek/mt8186/platform.mk @@ -8,16 +8,21 @@ MTK_PLAT := plat/mediatek MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ - -I${MTK_PLAT}/common/drivers/gic600/ \ - -I${MTK_PLAT}/common/drivers/gpio/ \ - -I${MTK_PLAT}/common/drivers/uart/ \ - -I${MTK_PLAT}/common/drivers/timer/ \ - -I${MTK_PLAT}/common/lpm/ \ + -I${MTK_PLAT}/common/lpm \ + -I${MTK_PLAT}/drivers/cirq/ \ + -I${MTK_PLAT}/drivers/gic600/ \ + -I${MTK_PLAT}/drivers/gpio/ \ + -I${MTK_PLAT}/drivers/msdc/ \ + -I${MTK_PLAT}/drivers/msdc/${PLAT} \ + -I${MTK_PLAT}/drivers/pmic_wrap/ \ + -I${MTK_PLAT}/drivers/timer/ \ + -I${MTK_PLAT}/drivers/uart/ \ + -I${MTK_PLAT}/include/ \ -I${MTK_PLAT_SOC}/drivers/spm/ \ -I${MTK_PLAT_SOC}/drivers/dcm/ \ - -I${MTK_PLAT_SOC}/drivers/dfd/ \ + -I${MTK_PLAT_SOC}/drivers/dfd/ \ -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \ - -I${MTK_PLAT_SOC}/drivers/gpio/ \ + -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/mcdi/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ -I${MTK_PLAT_SOC}/drivers/rtc/ \ @@ -43,17 +48,18 @@ BL31_SOURCES += common/desc_image_load.c \ lib/cpus/aarch64/cortex_a55.S \ lib/cpus/aarch64/cortex_a76.S \ plat/common/plat_gicv3.c \ - ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \ - ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \ - ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \ - ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/mtk_sip_svc.c \ ${MTK_PLAT}/common/params_setup.c \ - ${MTK_PLAT}/common/drivers/timer/mt_timer.c \ - ${MTK_PLAT}/common/drivers/uart/uart.c \ - ${MTK_PLAT}/common/mtk_cirq.c \ - ${MTK_PLAT}/common/lpm/mt_lp_rm.c \ + ${MTK_PLAT}/common/lpm/mt_lp_rm.c \ + ${MTK_PLAT}/drivers/cirq/mt_cirq.c \ + ${MTK_PLAT}/drivers/gic600/mt_gic_v3.c \ + ${MTK_PLAT}/drivers/gpio/mtgpio_common.c \ + ${MTK_PLAT}/drivers/msdc/mt_msdc.c \ + ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init.c \ + ${MTK_PLAT}/drivers/rtc/rtc_common.c \ + ${MTK_PLAT}/drivers/timer/mt_timer.c \ + ${MTK_PLAT}/drivers/uart/uart.c \ ${MTK_PLAT_SOC}/aarch64/platform_common.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ diff --git a/plat/mediatek/mt8188/include/plat_helpers.h b/plat/mediatek/mt8188/include/plat_helpers.h new file mode 100644 index 000000000..eb78623ce --- /dev/null +++ b/plat/mediatek/mt8188/include/plat_helpers.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_HELPERS_H +#define PLAT_HELPERS_H + +unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr); + +#endif /* PLAT_HELPERS_H */ diff --git a/plat/mediatek/mt8188/include/plat_macros.S b/plat/mediatek/mt8188/include/plat_macros.S new file mode 100644 index 000000000..a6e05a961 --- /dev/null +++ b/plat/mediatek/mt8188/include/plat_macros.S @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <platform_def.h> + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception + * is taken in BL31. + * Clobbers: x0 - x10, x26, x27, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + /* TODO: leave implementation to GIC owner */ + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/mediatek/mt8188/include/plat_private.h b/plat/mediatek/mt8188/include/plat_private.h new file mode 100644 index 000000000..4d4ac852f --- /dev/null +++ b/plat/mediatek/mt8188/include/plat_private.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_configure_mmu_el3(uintptr_t total_base, + uintptr_t total_size, + uintptr_t ro_start, + uintptr_t ro_limit); + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h new file mode 100644 index 000000000..156a7e28f --- /dev/null +++ b/plat/mediatek/mt8188/include/platform_def.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch_def.h> + +#define PLAT_PRIMARY_CPU (0x0) + +#define MT_GIC_BASE (0x0C000000) +#define MCUCFG_BASE (0x0C530000) +#define MCUCFG_REG_SIZE (0x10000) +#define IO_PHYS (0x10000000) + +/* Aggregate of all devices for MMU mapping */ +#define MTK_DEV_RNG0_BASE (MT_GIC_BASE) +#define MTK_DEV_RNG0_SIZE (0x600000) +#define MTK_DEV_RNG1_BASE (IO_PHYS) +#define MTK_DEV_RNG1_SIZE (0x10000000) + +/******************************************************************************* + * AUDIO related constants + ******************************************************************************/ +#define AUDIO_BASE (IO_PHYS + 0x00b10000) + +/******************************************************************************* + * SPM related constants + ******************************************************************************/ +#define SPM_BASE (IO_PHYS + 0x00006000) + +/******************************************************************************* + * GPIO related constants + ******************************************************************************/ +#define GPIO_BASE (IO_PHYS + 0x00005000) +#define RGU_BASE (IO_PHYS + 0x00007000) +#define DRM_BASE (IO_PHYS + 0x0000D000) +#define IOCFG_RM_BASE (IO_PHYS + 0x01C00000) +#define IOCFG_LT_BASE (IO_PHYS + 0x01E10000) +#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) +#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define UART0_BASE (IO_PHYS + 0x01002000) +#define UART_BAUDRATE (115200) + +/******************************************************************************* + * PMIC related constants + ******************************************************************************/ +#define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) + +/******************************************************************************* + * Infra IOMMU related constants + ******************************************************************************/ +#define PERICFG_AO_BASE (IO_PHYS + 0x01003000) +#define PERICFG_AO_REG_SIZE (0x1000) + +/******************************************************************************* + * GIC-600 & interrupt handling related constants + ******************************************************************************/ +/* Base MTK_platform compatible GIC memory map */ +#define BASE_GICD_BASE (MT_GIC_BASE) +#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) + +/******************************************************************************* + * CIRQ related constants + ******************************************************************************/ +#define SYS_CIRQ_BASE (IO_PHYS + 0x204000) +#define MD_WDT_IRQ_BIT_ID (141) +#define CIRQ_IRQ_NUM (730) +#define CIRQ_REG_NUM (23) +#define CIRQ_SPI_START (96) + +/******************************************************************************* + * MM IOMMU & SMI related constants + ******************************************************************************/ +#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) +#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) +#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) +#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) +#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) +#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) +#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) +#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) +#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) +#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) +#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) +#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) +#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) +#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) +#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) +#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) +#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) +#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) +#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) +#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) +#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) +#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) +#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) +#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) +#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) +#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) +#define SMI_LARB_REG_RNG_SIZE (0x1000) + +/******************************************************************************* + * DP related constants + ******************************************************************************/ +#define EDP_SEC_BASE (IO_PHYS + 0x0C504000) +#define DP_SEC_BASE (IO_PHYS + 0x0C604000) +#define EDP_SEC_SIZE (0x1000) +#define DP_SEC_SIZE (0x1000) + +/******************************************************************************* + * EMI MPU related constants + *******************************************************************************/ +#define EMI_MPU_BASE (IO_PHYS + 0x00226000) +#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000) + +/******************************************************************************* + * System counter frequency related constants + ******************************************************************************/ +#define SYS_COUNTER_FREQ_IN_HZ (13000000) +#define SYS_COUNTER_FREQ_IN_MHZ (13) + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ +#define PLATFORM_STACK_SIZE (0x800) +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" +#define SOC_CHIP_ID U(0x8188) + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define TZRAM_BASE (0x54600000) +#define TZRAM_SIZE (0x00030000) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL3-1 debug size plus a + * little space for growth. + */ +#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define MAX_XLAT_TABLES (16) +#define MAX_MMAP_REGIONS (16) + +/******************************************************************************* + * CPU_EB TCM handling related constants + ******************************************************************************/ +#define CPU_EB_TCM_BASE (0x0C550000) +#define CPU_EB_TCM_SIZE (0x10000) +#define CPU_EB_MBOX3_OFFSET (0xFCE0) + +/******************************************************************************* + * CPU PM definitions + *******************************************************************************/ +#define PLAT_CPU_PM_B_BUCK_ISO_ID (6) +#define PLAT_CPU_PM_ILDO_ID (6) +#define CPU_IDLE_SRAM_BASE (0x11B000) +#define CPU_IDLE_SRAM_SIZE (0x1000) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/mediatek/mt8188/include/spm_reg.h b/plat/mediatek/mt8188/include/spm_reg.h new file mode 100644 index 000000000..e20f1aab4 --- /dev/null +++ b/plat/mediatek/mt8188/include/spm_reg.h @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2022, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPM_REG_H +#define SPM_REG_H + +#include <platform_def.h> + +/* Register_SPM_CFG */ +#define MD32PCM_CFG_BASE (SPM_BASE + 0xA00) +#define POWERON_CONFIG_EN (SPM_BASE + 0x000) +#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) +#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) +#define SPM_CLK_CON (SPM_BASE + 0x00C) +#define SPM_CLK_SETTLE (SPM_BASE + 0x010) +#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) +#define PCM_CON0 (SPM_BASE + 0x018) +#define PCM_CON1 (SPM_BASE + 0x01C) +#define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020) +#define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024) +#define PCM_REG_DATA_INI (SPM_BASE + 0x028) +#define PCM_PWR_IO_EN (SPM_BASE + 0x02C) +#define PCM_TIMER_VAL (SPM_BASE + 0x030) +#define PCM_WDT_VAL (SPM_BASE + 0x034) +#define SPM_SW_RST_CON (SPM_BASE + 0x040) +#define SPM_SW_RST_CON_SET (SPM_BASE + 0x044) +#define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048) +#define SPM_ARBITER_EN (SPM_BASE + 0x050) +#define SCPSYS_CLK_CON (SPM_BASE + 0x054) +#define SPM_SRAM_RSV_CON (SPM_BASE + 0x058) +#define SPM_SWINT (SPM_BASE + 0x05C) +#define SPM_SWINT_SET (SPM_BASE + 0x060) +#define SPM_SWINT_CLR (SPM_BASE + 0x064) +#define SPM_SCP_MAILBOX (SPM_BASE + 0x068) +#define SCP_SPM_MAILBOX (SPM_BASE + 0x06C) +#define SPM_SCP_IRQ (SPM_BASE + 0x070) +#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x074) +#define SPM_IRQ_MASK (SPM_BASE + 0x078) +#define SPM_SRC_REQ (SPM_BASE + 0x080) +#define SPM_SRC_MASK (SPM_BASE + 0x084) +#define SPM_SRC2_MASK (SPM_BASE + 0x088) +#define SPM_SRC3_MASK (SPM_BASE + 0x090) +#define SPM_SRC4_MASK (SPM_BASE + 0x094) +#define SPM_WAKEUP_EVENT_MASK2 (SPM_BASE + 0x098) +#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x09C) +#define SPM_WAKEUP_EVENT_SENS (SPM_BASE + 0x0A0) +#define SPM_WAKEUP_EVENT_CLEAR (SPM_BASE + 0x0A4) +#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0A8) +#define SCP_CLK_CON (SPM_BASE + 0x0AC) +#define PCM_DEBUG_CON (SPM_BASE + 0x0B0) +#define DDREN_DBC_CON (SPM_BASE + 0x0B4) +#define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0B8) +#define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0BC) +#define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0C0) +#define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0C4) +#define SPM_RESOURCE_ACK_CON4 (SPM_BASE + 0x0C8) +#define SPM_SRAM_CON (SPM_BASE + 0x0CC) +#define PCM_REG0_DATA (SPM_BASE + 0x100) +#define PCM_REG2_DATA (SPM_BASE + 0x104) +#define PCM_REG6_DATA (SPM_BASE + 0x108) +#define PCM_REG7_DATA (SPM_BASE + 0x10C) +#define PCM_REG13_DATA (SPM_BASE + 0x110) +#define SRC_REQ_STA_0 (SPM_BASE + 0x114) +#define SRC_REQ_STA_1 (SPM_BASE + 0x118) +#define SRC_REQ_STA_2 (SPM_BASE + 0x120) +#define SRC_REQ_STA_3 (SPM_BASE + 0x124) +#define SRC_REQ_STA_4 (SPM_BASE + 0x128) +#define PCM_TIMER_OUT (SPM_BASE + 0x130) +#define PCM_WDT_OUT (SPM_BASE + 0x134) +#define SPM_IRQ_STA (SPM_BASE + 0x138) +#define MD32PCM_WAKEUP_STA (SPM_BASE + 0x13C) +#define MD32PCM_EVENT_STA (SPM_BASE + 0x140) +#define SPM_WAKEUP_STA (SPM_BASE + 0x144) +#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x148) +#define SPM_WAKEUP_MISC (SPM_BASE + 0x14C) +#define MM_DVFS_HALT (SPM_BASE + 0x150) +#define SUBSYS_IDLE_STA (SPM_BASE + 0x164) +#define PCM_STA (SPM_BASE + 0x168) +#define PWR_STATUS (SPM_BASE + 0x16C) +#define PWR_STATUS_2ND (SPM_BASE + 0x170) +#define CPU_PWR_STATUS (SPM_BASE + 0x174) +#define CPU_PWR_STATUS_2ND (SPM_BASE + 0x178) +#define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C) +#define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180) +#define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184) +#define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188) +#define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C) +#define MD32PCM_STA (SPM_BASE + 0x190) +#define MD32PCM_PC (SPM_BASE + 0x194) +#define OTHER_PWR_STATUS (SPM_BASE + 0x198) +#define DVFSRC_EVENT_STA (SPM_BASE + 0x19C) +#define BUS_PROTECT_RDY (SPM_BASE + 0x1A0) +#define BUS_PROTECT1_RDY (SPM_BASE + 0x1A4) +#define BUS_PROTECT2_RDY (SPM_BASE + 0x1A8) +#define BUS_PROTECT3_RDY (SPM_BASE + 0x1AC) +#define BUS_PROTECT4_RDY (SPM_BASE + 0x1B0) +#define BUS_PROTECT5_RDY (SPM_BASE + 0x1B4) +#define BUS_PROTECT6_RDY (SPM_BASE + 0x1B8) +#define BUS_PROTECT7_RDY (SPM_BASE + 0x1BC) +#define BUS_PROTECT8_RDY (SPM_BASE + 0x1C0) +#define BUS_PROTECT9_RDY (SPM_BASE + 0x1C4) +#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0) +#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4) +#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8) +#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC) +#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0) +#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4) +#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8) +#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC) +#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0) +#define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4) +#define SPM_DVFS_STA (SPM_BASE + 0x1F8) +#define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC) +#define CPUEB_PWR_CON (SPM_BASE + 0x200) +#define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x204) +#define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x208) +#define SPM_CPU0_PWR_CON (SPM_BASE + 0x20C) +#define SPM_CPU1_PWR_CON (SPM_BASE + 0x210) +#define SPM_CPU2_PWR_CON (SPM_BASE + 0x214) +#define SPM_CPU3_PWR_CON (SPM_BASE + 0x218) +#define SPM_CPU4_PWR_CON (SPM_BASE + 0x21C) +#define SPM_CPU5_PWR_CON (SPM_BASE + 0x220) +#define SPM_CPU6_PWR_CON (SPM_BASE + 0x224) +#define SPM_CPU7_PWR_CON (SPM_BASE + 0x228) +#define ARMPLL_CLK_CON (SPM_BASE + 0x22C) +#define MCUSYS_IDLE_STA (SPM_BASE + 0x230) +#define GIC_WAKEUP_STA (SPM_BASE + 0x234) +#define CPU_SPARE_CON (SPM_BASE + 0x238) +#define CPU_SPARE_CON_SET (SPM_BASE + 0x23C) +#define CPU_SPARE_CON_CLR (SPM_BASE + 0x240) +#define ARMPLL_CLK_SEL (SPM_BASE + 0x244) +#define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248) +#define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C) +#define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250) +#define CPU_IRQ_MASK (SPM_BASE + 0x260) +#define CPU_IRQ_MASK_SET (SPM_BASE + 0x264) +#define CPU_IRQ_MASK_CLR (SPM_BASE + 0x268) +#define CPU_WFI_EN (SPM_BASE + 0x280) +#define CPU_WFI_EN_SET (SPM_BASE + 0x284) +#define CPU_WFI_EN_CLR (SPM_BASE + 0x288) +#define SYSRAM_CON (SPM_BASE + 0x290) +#define SYSROM_CON (SPM_BASE + 0x294) +#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) +#define ROOT_CORE_ADDR (SPM_BASE + 0x2A4) +#define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) +#define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4) +#define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8) +#define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC) +#define SW2SPM_INT (SPM_BASE + 0x2E0) +#define SW2SPM_INT_SET (SPM_BASE + 0x2E4) +#define SW2SPM_INT_CLR (SPM_BASE + 0x2E8) +#define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC) +#define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0) +#define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4) +#define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8) +#define SW2SPM_CFG (SPM_BASE + 0x2FC) +#define MFG0_PWR_CON (SPM_BASE + 0x300) +#define MFG1_PWR_CON (SPM_BASE + 0x304) +#define MFG2_PWR_CON (SPM_BASE + 0x308) +#define MFG3_PWR_CON (SPM_BASE + 0x30C) +#define MFG4_PWR_CON (SPM_BASE + 0x310) +#define MFG5_PWR_CON (SPM_BASE + 0x314) +#define IFR_PWR_CON (SPM_BASE + 0x318) +#define IFR_SUB_PWR_CON (SPM_BASE + 0x31C) +#define PERI_PWR_CON (SPM_BASE + 0x320) +#define PEXTP_MAC_TOP_P0_PWR_CON (SPM_BASE + 0x324) +#define PEXTP_PHY_TOP_PWR_CON (SPM_BASE + 0x328) +#define APHY_N_PWR_CON (SPM_BASE + 0x32C) +#define APHY_S_PWR_CON (SPM_BASE + 0x330) +#define ETHER_PWR_CON (SPM_BASE + 0x338) +#define DPY0_PWR_CON (SPM_BASE + 0x33C) +#define DPY1_PWR_CON (SPM_BASE + 0x340) +#define DPM0_PWR_CON (SPM_BASE + 0x344) +#define DPM1_PWR_CON (SPM_BASE + 0x348) +#define AUDIO_PWR_CON (SPM_BASE + 0x34C) +#define AUDIO_ASRC_PWR_CON (SPM_BASE + 0x350) +#define ADSP_PWR_CON (SPM_BASE + 0x354) +#define ADSP_INFRA_PWR_CON (SPM_BASE + 0x358) +#define ADSP_AO_PWR_CON (SPM_BASE + 0x35C) +#define VPPSYS0_PWR_CON (SPM_BASE + 0x360) +#define VPPSYS1_PWR_CON (SPM_BASE + 0x364) +#define VDOSYS0_PWR_CON (SPM_BASE + 0x368) +#define VDOSYS1_PWR_CON (SPM_BASE + 0x36C) +#define WPESYS_PWR_CON (SPM_BASE + 0x370) +#define DP_TX_PWR_CON (SPM_BASE + 0x374) +#define EDP_TX_PWR_CON (SPM_BASE + 0x378) +#define HDMI_TX_PWR_CON (SPM_BASE + 0x37C) +#define VDE0_PWR_CON (SPM_BASE + 0x380) +#define VDE1_PWR_CON (SPM_BASE + 0x384) +#define VDE2_PWR_CON (SPM_BASE + 0x388) +#define VEN_PWR_CON (SPM_BASE + 0x38C) +#define VEN_CORE1_PWR_CON (SPM_BASE + 0x390) +#define CAM_MAIN_PWR_CON (SPM_BASE + 0x394) +#define CAM_SUBA_PWR_CON (SPM_BASE + 0x398) +#define CAM_SUBB_PWR_CON (SPM_BASE + 0x39C) +#define CAM_VCORE_PWR_CON (SPM_BASE + 0x3A0) +#define IMG_VCORE_PWR_CON (SPM_BASE + 0x3A4) +#define IMG_MAIN_PWR_CON (SPM_BASE + 0x3A8) +#define IMG_DIP_PWR_CON (SPM_BASE + 0x3AC) +#define IMG_IPE_PWR_CON (SPM_BASE + 0x3B0) +#define NNA0_PWR_CON (SPM_BASE + 0x3B4) +#define NNA1_PWR_CON (SPM_BASE + 0x3B8) +#define IPNNA_PWR_CON (SPM_BASE + 0x3C0) +#define CSI_RX_TOP_PWR_CON (SPM_BASE + 0x3C4) +#define SSPM_SRAM_CON (SPM_BASE + 0x3CC) +#define SCP_SRAM_CON (SPM_BASE + 0x3D0) +#define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x3D8) +#define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x3DC) +#define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x3E0) +#define USB_SRAM_CON (SPM_BASE + 0x3E4) +#define DUMMY_SRAM_CON (SPM_BASE + 0x3E8) +#define EXT_BUCK_ISO (SPM_BASE + 0x3EC) +#define MSDC_SRAM_CON (SPM_BASE + 0x3F0) +#define DEBUGTOP_SRAM_CON (SPM_BASE + 0x3F4) +#define DPMAIF_SRAM_CON (SPM_BASE + 0x3F8) +#define GCPU_SRAM_CON (SPM_BASE + 0x3FC) +#define SPM_MEM_CK_SEL (SPM_BASE + 0x400) +#define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404) +#define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408) +#define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C) +#define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410) +#define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414) +#define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x418) +#define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x41C) +#define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x420) +#define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x424) +#define SPM_BUS_PROTECT9_MASK_B (SPM_BASE + 0x428) +#define SPM_EMI_BW_MODE (SPM_BASE + 0x42C) +#define SPM2MM_CON (SPM_BASE + 0x434) +#define SPM2CPUEB_CON (SPM_BASE + 0x438) +#define AP_MDSRC_REQ (SPM_BASE + 0x43C) +#define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x440) +#define SPM_PLL_CON (SPM_BASE + 0x444) +#define RC_SPM_CTRL (SPM_BASE + 0x448) +#define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x44C) +#define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x450) +#define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x454) +#define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x458) +#define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x45C) +#define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x460) +#define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x464) +#define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x468) +#define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x46C) +#define RELAY_DVFS_LEVEL (SPM_BASE + 0x470) +#define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x474) +#define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x478) +#define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x47C) +#define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x480) +#define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x484) +#define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x488) +#define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x48C) +#define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x490) +#define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x494) +#define SPM_DVFS_LEVEL (SPM_BASE + 0x498) +#define SPM_CIRQ_CON (SPM_BASE + 0x49C) +#define SPM_DVFS_MISC (SPM_BASE + 0x4A0) +#define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4A4) +#define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4A8) +#define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4AC) +#define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4B0) +#define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4B4) +#define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4B8) +#define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4BC) +#define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4C0) +#define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4C4) +#define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4C8) +#define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4CC) +#define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4D0) +#define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4D4) +#define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4D8) +#define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4DC) +#define SPM_CG_CHECK_CON (SPM_BASE + 0x4E0) +#define SPM_SRC_RDY_STA (SPM_BASE + 0x4E4) +#define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4E8) +#define SPM_FORCE_DVFS (SPM_BASE + 0x4EC) +#define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x4F0) +#define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x4F4) +#define DPY_SHU_SRAM_CON (SPM_BASE + 0x4F8) +#define DPY_SHU2_SRAM_CON (SPM_BASE + 0x4FC) +#define SPM_DPM_P2P_STA (SPM_BASE + 0x514) +#define SPM_DPM_P2P_CON (SPM_BASE + 0x518) +#define SPM_SW_FLAG_0 (SPM_BASE + 0x600) +#define SPM_SW_DEBUG_0 (SPM_BASE + 0x604) +#define SPM_SW_FLAG_1 (SPM_BASE + 0x608) +#define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C) +#define SPM_SW_RSV_0 (SPM_BASE + 0x610) +#define SPM_SW_RSV_1 (SPM_BASE + 0x614) +#define SPM_SW_RSV_2 (SPM_BASE + 0x618) +#define SPM_SW_RSV_3 (SPM_BASE + 0x61C) +#define SPM_SW_RSV_4 (SPM_BASE + 0x620) +#define SPM_SW_RSV_5 (SPM_BASE + 0x624) +#define SPM_SW_RSV_6 (SPM_BASE + 0x628) +#define SPM_SW_RSV_7 (SPM_BASE + 0x62C) +#define SPM_SW_RSV_8 (SPM_BASE + 0x630) +#define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634) +#define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638) +#define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C) +#define SPM_BK_PCM_TIMER (SPM_BASE + 0x640) +#define ULPOSC_CON (SPM_BASE + 0x644) +#define SPM_RSV_CON_0 (SPM_BASE + 0x650) +#define SPM_RSV_CON_1 (SPM_BASE + 0x654) +#define SPM_RSV_STA_0 (SPM_BASE + 0x658) +#define SPM_RSV_STA_1 (SPM_BASE + 0x65C) +#define SPM_SPARE_CON (SPM_BASE + 0x660) +#define SPM_SPARE_CON_SET (SPM_BASE + 0x664) +#define SPM_SPARE_CON_CLR (SPM_BASE + 0x668) +#define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C) +#define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670) +#define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674) +#define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678) +#define SCP_VCORE_LEVEL (SPM_BASE + 0x67C) +#define SC_MM_CK_SEL_CON (SPM_BASE + 0x680) +#define SPARE_ACK_MASK (SPM_BASE + 0x684) +#define SPM_DV_CON_0 (SPM_BASE + 0x68C) +#define SPM_DV_CON_1 (SPM_BASE + 0x690) +#define SPM_DV_STA (SPM_BASE + 0x694) +#define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698) +#define SPM_SEMA_M0 (SPM_BASE + 0x69C) +#define SPM_SEMA_M1 (SPM_BASE + 0x6A0) +#define SPM_SEMA_M2 (SPM_BASE + 0x6A4) +#define SPM_SEMA_M3 (SPM_BASE + 0x6A8) +#define SPM_SEMA_M4 (SPM_BASE + 0x6AC) +#define SPM_SEMA_M5 (SPM_BASE + 0x6B0) +#define SPM_SEMA_M6 (SPM_BASE + 0x6B4) +#define SPM_SEMA_M7 (SPM_BASE + 0x6B8) +#define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC) +#define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0) +#define SPM_ADSP_IRQ (SPM_BASE + 0x6C4) +#define SPM_MD32_IRQ (SPM_BASE + 0x6C8) +#define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC) +#define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0) +#define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4) +#define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8) +#define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC) +#define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0) +#define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4) +#define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8) +#define SPM_AP_SEMA (SPM_BASE + 0x6F8) +#define SPM_SPM_SEMA (SPM_BASE + 0x6FC) +#define SPM_DVFS_CON (SPM_BASE + 0x700) +#define SPM_DVFS_CON_STA (SPM_BASE + 0x704) +#define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708) +#define SPM_DVFS_CMD0 (SPM_BASE + 0x710) +#define SPM_DVFS_CMD1 (SPM_BASE + 0x714) +#define SPM_DVFS_CMD2 (SPM_BASE + 0x718) +#define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) +#define SPM_DVFS_CMD4 (SPM_BASE + 0x720) +#define SPM_DVFS_CMD5 (SPM_BASE + 0x724) +#define SPM_DVFS_CMD6 (SPM_BASE + 0x728) +#define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) +#define SPM_DVFS_CMD8 (SPM_BASE + 0x730) +#define SPM_DVFS_CMD9 (SPM_BASE + 0x734) +#define SPM_DVFS_CMD10 (SPM_BASE + 0x738) +#define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) +#define SPM_DVFS_CMD12 (SPM_BASE + 0x740) +#define SPM_DVFS_CMD13 (SPM_BASE + 0x744) +#define SPM_DVFS_CMD14 (SPM_BASE + 0x748) +#define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) +#define SPM_DVFS_CMD16 (SPM_BASE + 0x750) +#define SPM_DVFS_CMD17 (SPM_BASE + 0x754) +#define SPM_DVFS_CMD18 (SPM_BASE + 0x758) +#define SPM_DVFS_CMD19 (SPM_BASE + 0x75C) +#define SPM_DVFS_CMD20 (SPM_BASE + 0x760) +#define SPM_DVFS_CMD21 (SPM_BASE + 0x764) +#define SPM_DVFS_CMD22 (SPM_BASE + 0x768) +#define SPM_DVFS_CMD23 (SPM_BASE + 0x76C) +#define SYS_TIMER_VALUE_L (SPM_BASE + 0x770) +#define SYS_TIMER_VALUE_H (SPM_BASE + 0x774) +#define SYS_TIMER_START_L (SPM_BASE + 0x778) +#define SYS_TIMER_START_H (SPM_BASE + 0x77C) +#define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780) +#define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784) +#define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788) +#define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C) +#define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790) +#define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794) +#define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798) +#define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C) +#define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0) +#define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4) +#define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8) +#define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC) +#define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0) +#define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4) +#define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8) +#define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC) +#define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0) +#define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4) +#define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8) +#define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC) +#define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0) +#define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4) +#define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8) +#define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC) +#define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0) +#define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4) +#define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8) +#define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC) +#define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0) +#define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4) +#define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8) +#define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC) +#define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) +#define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) +#define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) +#define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) +#define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) +#define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) +#define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) +#define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) +#define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) +#define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) +#define PCM_WDT_LATCH_10 (SPM_BASE + 0x828) +#define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C) +#define PCM_WDT_LATCH_12 (SPM_BASE + 0x830) +#define PCM_WDT_LATCH_13 (SPM_BASE + 0x834) +#define PCM_WDT_LATCH_14 (SPM_BASE + 0x838) +#define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C) +#define PCM_WDT_LATCH_16 (SPM_BASE + 0x840) +#define PCM_WDT_LATCH_17 (SPM_BASE + 0x844) +#define PCM_WDT_LATCH_18 (SPM_BASE + 0x848) +#define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C) +#define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850) +#define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854) +#define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0) +#define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4) +#define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8) +#define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC) +#define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0) +#define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4) +#define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4) +#define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900) +#define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904) +#define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908) +#define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C) +#define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910) +#define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914) +#define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x920) +#define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x924) +#define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x928) +#define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x92C) +#define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x930) +#define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x934) +#define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x940) +#define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x944) +#define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x948) +#define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x94C) +#define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x950) +#define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x954) +#define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960) +#define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x964) +#define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x968) +#define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x96C) +#define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x970) +#define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x974) +#define SPM_COUNTER_0 (SPM_BASE + 0x978) +#define SPM_COUNTER_1 (SPM_BASE + 0x97C) +#define SPM_COUNTER_2 (SPM_BASE + 0x980) +#define SYS_TIMER_CON (SPM_BASE + 0x98C) +#define SPM_TWAM_CON (SPM_BASE + 0x990) +#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x994) +#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x998) +#define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x99C) +#define PMSR_LAST_DAT (SPM_BASE + 0xF00) +#define PMSR_LAST_CNT (SPM_BASE + 0xF04) +#define PMSR_LAST_ACK (SPM_BASE + 0xF08) +#define SPM_PMSR_SEL_CON0 (SPM_BASE + 0xF10) +#define SPM_PMSR_SEL_CON1 (SPM_BASE + 0xF14) +#define SPM_PMSR_SEL_CON2 (SPM_BASE + 0xF18) +#define SPM_PMSR_SEL_CON3 (SPM_BASE + 0xF1C) +#define SPM_PMSR_SEL_CON4 (SPM_BASE + 0xF20) +#define SPM_PMSR_SEL_CON5 (SPM_BASE + 0xF24) +#define SPM_PMSR_SEL_CON6 (SPM_BASE + 0xF28) +#define SPM_PMSR_SEL_CON7 (SPM_BASE + 0xF2C) +#define SPM_PMSR_SEL_CON8 (SPM_BASE + 0xF30) +#define SPM_PMSR_SEL_CON9 (SPM_BASE + 0xF34) +#define SPM_PMSR_SEL_CON10 (SPM_BASE + 0xF3C) +#define SPM_PMSR_SEL_CON11 (SPM_BASE + 0xF40) +#define SPM_PMSR_TIEMR_STA0 (SPM_BASE + 0xFB8) +#define SPM_PMSR_TIEMR_STA1 (SPM_BASE + 0xFBC) +#define SPM_PMSR_TIEMR_STA2 (SPM_BASE + 0xFC0) +#define SPM_PMSR_GENERAL_CON0 (SPM_BASE + 0xFC4) +#define SPM_PMSR_GENERAL_CON1 (SPM_BASE + 0xFC8) +#define SPM_PMSR_GENERAL_CON2 (SPM_BASE + 0xFCC) +#define SPM_PMSR_GENERAL_CON3 (SPM_BASE + 0xFD0) +#define SPM_PMSR_GENERAL_CON4 (SPM_BASE + 0xFD4) +#define SPM_PMSR_GENERAL_CON5 (SPM_BASE + 0xFD8) +#define SPM_PMSR_SW_RESET (SPM_BASE + 0xFDC) +#define SPM_PMSR_MON_CON0 (SPM_BASE + 0xFE0) +#define SPM_PMSR_MON_CON1 (SPM_BASE + 0xFE4) +#define SPM_PMSR_MON_CON2 (SPM_BASE + 0xFE8) +#define SPM_PMSR_LEN_CON0 (SPM_BASE + 0xFEC) +#define SPM_PMSR_LEN_CON1 (SPM_BASE + 0xFF0) +#define SPM_PMSR_LEN_CON2 (SPM_BASE + 0xFF4) + +#endif /* SPM_REG_H */ diff --git a/plat/mediatek/mt8188/plat_config.mk b/plat/mediatek/mt8188/plat_config.mk new file mode 100644 index 000000000..137318e7a --- /dev/null +++ b/plat/mediatek/mt8188/plat_config.mk @@ -0,0 +1,48 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Separate text code and read only data +SEPARATE_CODE_AND_RODATA := 1 +# ARMv8.2 and above need enable HW assist coherence +HW_ASSISTED_COHERENCY := 1 +# No need coherency memory because of HW assistency +USE_COHERENT_MEM := 0 +# GIC600 +GICV3_SUPPORT_GIC600 := 1 +# +# MTK options +# +PLAT_EXTRA_RODATA_INCLUDES := 1 +USE_PMIC_WRAP_INIT_V2 := 1 +USE_RTC_MT6359P := 1 + +# Configs for A78 and A55 +CTX_INCLUDE_AARCH32_REGS := 0 +ERRATA_A55_1530923 := 1 +ERRATA_A55_1221012 := 1 +ERRATA_A78_1688305 := 1 +ERRATA_A78_1941498 := 1 +ERRATA_A78_1951500 := 1 +ERRATA_A78_1821534 := 1 +ERRATA_A78_2132060 := 1 +ERRATA_A78_2242635 := 1 +ERRATA_A78_2376745 := 1 +ERRATA_A78_2395406 := 1 + +CONFIG_ARCH_ARM_V8_2 := y +CONFIG_MTK_MCUSYS := y +MCUSYS_VERSION := v1 +CONFIG_MTK_PM_SUPPORT := y +CONFIG_MTK_PM_ARCH := 8_2 +CONFIG_MTK_CPU_PM_SUPPORT := y +CONFIG_MTK_CPU_PM_ARCH := 3_2 +CONFIG_MTK_SMP_EN := y +CONFIG_MTK_CPU_SUSPEND_EN := y +CPU_PM_TINYSYS_SUPPORT := y +MTK_PUBEVENT_ENABLE := y + +MACH_MT8188 := 1 +$(eval $(call add_define,MACH_MT8188)) diff --git a/plat/mediatek/mt8188/plat_mmap.c b/plat/mediatek/mt8188/plat_mmap.c new file mode 100644 index 000000000..a611d2235 --- /dev/null +++ b/plat/mediatek/mt8188/plat_mmap.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> +#include <mtk_mmap_pool.h> +#include <platform_def.h> + +static const mmap_region_t plat_mmap[] = { + MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(CPU_IDLE_SRAM_BASE, CPU_IDLE_SRAM_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; +DECLARE_MTK_MMAP_REGIONS(plat_mmap); diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk new file mode 100644 index 000000000..b6a17aa4c --- /dev/null +++ b/plat/mediatek/mt8188/platform.mk @@ -0,0 +1,65 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +MTK_PLAT := plat/mediatek +MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} +MTK_SOC := ${PLAT} + +include plat/mediatek/build_helpers/mtk_build_helpers.mk +include drivers/arm/gic/v3/gicv3.mk +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_INCLUDES := -I${MTK_PLAT}/common \ + -I${MTK_PLAT}/include \ + -I${MTK_PLAT}/include/${ARCH_VERSION} \ + -I${MTK_PLAT} \ + -I${MTK_PLAT_SOC}/include \ + -Idrivers/arm/gic \ + +MODULES-y += $(MTK_PLAT)/common +MODULES-y += $(MTK_PLAT)/common/lpm +MODULES-y += $(MTK_PLAT)/lib/mtk_init +MODULES-y += $(MTK_PLAT)/lib/pm +MODULES-y += $(MTK_PLAT)/lib/system_reset +MODULES-y += $(MTK_PLAT)/drivers/audio +MODULES-y += $(MTK_PLAT)/drivers/cirq +MODULES-y += $(MTK_PLAT)/drivers/cpu_pm +MODULES-y += $(MTK_PLAT)/drivers/dcm +MODULES-y += $(MTK_PLAT)/drivers/dfd +MODULES-y += $(MTK_PLAT)/drivers/dp +MODULES-y += $(MTK_PLAT)/drivers/emi_mpu +MODULES-y += $(MTK_PLAT)/drivers/gic600 +MODULES-y += $(MTK_PLAT)/drivers/gpio +MODULES-y += $(MTK_PLAT)/drivers/iommu +MODULES-y += $(MTK_PLAT)/drivers/mcusys +MODULES-y += $(MTK_PLAT)/drivers/pmic +MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap +MODULES-y += $(MTK_PLAT)/drivers/ptp3 +MODULES-y += $(MTK_PLAT)/drivers/rtc +MODULES-y += $(MTK_PLAT)/drivers/timer +MODULES-y += $(MTK_PLAT)/helpers +MODULES-y += $(MTK_PLAT)/topology + +PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \ + drivers/ti/uart/aarch64/16550_console.S \ + lib/bl_aux_params/bl_aux_params.c + +BL31_SOURCES += drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + lib/cpus/aarch64/cortex_a55.S \ + lib/cpus/aarch64/cortex_a78.S \ + ${GICV3_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} \ + plat/common/plat_gicv3.c \ + plat/common/plat_psci_common.c \ + plat/common/aarch64/crash_console_helpers.S \ + ${MTK_PLAT}/common/mtk_plat_common.c \ + ${MTK_PLAT}/common/params_setup.c \ + $(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c + +include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk + +include lib/coreboot/coreboot.mk diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c index e74d3e7bc..872f4d02c 100644 --- a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c +++ b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#include <mt_lp_rm.h> +#include <mt_cirq.h> #include <mt_lp_irqremain.h> -#include <mtk_cirq.h> +#include <mt_lp_rm.h> #include <plat_mtk_lpm.h> #define EDMA0_IRQ_ID U(448) diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic.c b/plat/mediatek/mt8192/drivers/pmic/pmic.c deleted file mode 100644 index cca441397..000000000 --- a/plat/mediatek/mt8192/drivers/pmic/pmic.c +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <pmic.h> -#include <pmic_wrap_init.h> - -void pmic_power_off(void) -{ - pwrap_write(PMIC_PWRHOLD, 0x0); -} diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic.h b/plat/mediatek/mt8192/drivers/pmic/pmic.h deleted file mode 100644 index aac22afa3..000000000 --- a/plat/mediatek/mt8192/drivers/pmic/pmic.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef PMIC_H -#define PMIC_H - -#define PMIC_PWRHOLD 0xa08 - -/* external API */ -void pmic_power_off(void); - -#endif /* PMIC_H */ diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h index ae892ed5a..b9ab586d5 100644 --- a/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h +++ b/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,7 @@ #include <stdint.h> #include "platform_def.h" - -/* external API */ -int32_t pwrap_read(uint32_t adr, uint32_t *rdata); -int32_t pwrap_write(uint32_t adr, uint32_t wdata); +#include <pmic_wrap_init_common.h> static struct mt8192_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; @@ -30,47 +27,4 @@ struct mt8192_pmic_wrap_regs { uint32_t wacs2_sta; }; -#define GET_WACS_FSM(x) ((x >> 1) & 0x7) - -/* macro for SWINF_FSM */ -#define SWINF_FSM_IDLE (0x00) -#define SWINF_FSM_REQ (0x02) -#define SWINF_FSM_WFDLE (0x04) -#define SWINF_FSM_WFVLDCLR (0x06) -#define SWINF_INIT_DONE (0x01) - -/* timeout setting */ -#define PWRAP_READ_US 1000 -#define PWRAP_WAIT_IDLE_US 1000 - -/* error information flag */ -enum pwrap_errno { - E_PWR_INVALID_ARG = 1, - E_PWR_INVALID_RW = 2, - E_PWR_INVALID_ADDR = 3, - E_PWR_INVALID_WDAT = 4, - E_PWR_INVALID_OP_MANUAL = 5, - E_PWR_NOT_IDLE_STATE = 6, - E_PWR_NOT_INIT_DONE = 7, - E_PWR_NOT_INIT_DONE_READ = 8, - E_PWR_WAIT_IDLE_TIMEOUT = 9, - E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, - E_PWR_INIT_SIDLY_FAIL = 11, - E_PWR_RESET_TIMEOUT = 12, - E_PWR_TIMEOUT = 13, - E_PWR_INIT_RESET_SPI = 20, - E_PWR_INIT_SIDLY = 21, - E_PWR_INIT_REG_CLOCK = 22, - E_PWR_INIT_ENABLE_PMIC = 23, - E_PWR_INIT_DIO = 24, - E_PWR_INIT_CIPHER = 25, - E_PWR_INIT_WRITE_TEST = 26, - E_PWR_INIT_ENABLE_CRC = 27, - E_PWR_INIT_ENABLE_DEWRAP = 28, - E_PWR_INIT_ENABLE_EVENT = 29, - E_PWR_READ_TEST_FAIL = 30, - E_PWR_WRITE_TEST_FAIL = 31, - E_PWR_SWITCH_DIO = 32 -}; - #endif /* PMIC_WRAP_INIT_H */ diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c index f66b8ec93..18c43b1cc 100644 --- a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c +++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,8 +23,8 @@ #include <plat_mtk_lpm.h> #ifndef ATF_PLAT_CIRQ_UNSUPPORT +#include <mt_cirq.h> #include <mt_gic_v3.h> -#include <mtk_cirq.h> #endif #define CONSTRAINT_BUS26M_ALLOW \ diff --git a/plat/mediatek/mt8192/include/plat_sip_calls.h b/plat/mediatek/mt8192/include/plat_sip_calls.h index f68a4eabf..fdc7bea46 100644 --- a/plat/mediatek/mt8192/include/plat_sip_calls.h +++ b/plat/mediatek/mt8192/include/plat_sip_calls.h @@ -10,10 +10,6 @@ /******************************************************************************* * Plat SiP function constants ******************************************************************************/ -#define MTK_PLAT_SIP_NUM_CALLS 2 - -/* DFD */ -#define MTK_SIP_KERNEL_DFD_AARCH32 0x82000205 -#define MTK_SIP_KERNEL_DFD_AARCH64 0xC2000205 +#define MTK_PLAT_SIP_NUM_CALLS (4) #endif /* PLAT_SIP_CALLS_H */ diff --git a/plat/mediatek/mt8192/plat_sip_calls.c b/plat/mediatek/mt8192/plat_sip_calls.c index 353faf8a2..0fffed57c 100644 --- a/plat/mediatek/mt8192/plat_sip_calls.c +++ b/plat/mediatek/mt8192/plat_sip_calls.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,8 +25,8 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, uint32_t rnd_val0 = 0U; switch (smc_fid) { - case MTK_SIP_VCORE_CONTROL_ARCH32: - case MTK_SIP_VCORE_CONTROL_ARCH64: + case MTK_SIP_VCORE_CONTROL_AARCH32: + case MTK_SIP_VCORE_CONTROL_AARCH64: ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); SMC_RET2(handle, ret, x4); break; diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk index cbdaadd94..a19fc45d2 100644 --- a/plat/mediatek/mt8192/platform.mk +++ b/plat/mediatek/mt8192/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2020, MediaTek Inc. All rights reserved. +# Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -8,12 +8,16 @@ MTK_PLAT := plat/mediatek MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ - -I${MTK_PLAT}/common/drivers/gic600/ \ - -I${MTK_PLAT}/common/drivers/gpio/ \ - -I${MTK_PLAT}/common/drivers/rtc/ \ - -I${MTK_PLAT}/common/drivers/timer/ \ - -I${MTK_PLAT}/common/drivers/uart/ \ -I${MTK_PLAT}/common/lpm/ \ + -I${MTK_PLAT}/drivers/cirq/ \ + -I${MTK_PLAT}/drivers/gic600/ \ + -I${MTK_PLAT}/drivers/gpio/ \ + -I${MTK_PLAT}/drivers/pmic/ \ + -I${MTK_PLAT}/drivers/pmic_wrap/ \ + -I${MTK_PLAT}/drivers/rtc/ \ + -I${MTK_PLAT}/drivers/timer/ \ + -I${MTK_PLAT}/drivers/uart/ \ + -I${MTK_PLAT}/include/ \ -I${MTK_PLAT_SOC}/include/ \ -I${MTK_PLAT_SOC}/drivers/ \ -I${MTK_PLAT_SOC}/drivers/apusys/ \ @@ -45,22 +49,22 @@ BL31_SOURCES += common/desc_image_load.c \ lib/cpus/aarch64/cortex_a55.S \ lib/cpus/aarch64/cortex_a76.S \ plat/common/plat_gicv3.c \ - ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \ - ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \ - ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \ - ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ - ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c \ - ${MTK_PLAT}/common/drivers/timer/mt_timer.c \ - ${MTK_PLAT}/common/drivers/uart/uart.c \ - ${MTK_PLAT}/common/lpm/mt_lp_rm.c \ - ${MTK_PLAT}/common/mtk_cirq.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/mtk_sip_svc.c \ ${MTK_PLAT}/common/params_setup.c \ + ${MTK_PLAT}/common/lpm/mt_lp_rm.c \ + ${MTK_PLAT}/drivers/cirq/mt_cirq.c \ + ${MTK_PLAT}/drivers/gic600/mt_gic_v3.c \ + ${MTK_PLAT}/drivers/gpio/mtgpio_common.c \ + ${MTK_PLAT}/drivers/pmic/pmic.c \ + ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init_v2.c \ + ${MTK_PLAT}/drivers/rtc/rtc_common.c \ + ${MTK_PLAT}/drivers/rtc/rtc_mt6359p.c \ + ${MTK_PLAT}/drivers/timer/mt_timer.c \ + ${MTK_PLAT}/drivers/uart/uart.c \ ${MTK_PLAT_SOC}/aarch64/platform_common.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ - ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ ${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_topology.c \ ${MTK_PLAT_SOC}/plat_sip_calls.c \ diff --git a/plat/mediatek/mt8195/aarch64/platform_common.c b/plat/mediatek/mt8195/aarch64/platform_common.c index 2b95171dd..1f5c5facd 100644 --- a/plat/mediatek/mt8195/aarch64/platform_common.c +++ b/plat/mediatek/mt8195/aarch64/platform_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,7 +19,7 @@ const mmap_region_t plat_mmap[] = { MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(eDP_SEC_BASE, eDP_SEC_SIZE, + MAP_REGION_FLAT(EDP_SEC_BASE, EDP_SEC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE, MT_DEVICE | MT_RW | MT_SECURE), diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c index 4147184f2..f415cb82b 100644 --- a/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c +++ b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c @@ -1,15 +1,14 @@ /* - * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#include <mt_lp_rm.h> +#include <mt_cirq.h> #include <mt_lp_irqremain.h> -#include <mtk_cirq.h> +#include <mt_lp_rm.h> #include <plat_mtk_lpm.h> - #define KEYPAD_IRQ_ID U(138) #define KEYPAD_WAKESRC 0x4 diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h index 39e78f5f3..9e6e74cb6 100644 --- a/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h +++ b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,7 @@ #include <stdint.h> #include "platform_def.h" - -/* external API */ -int32_t pwrap_read(uint32_t adr, uint32_t *rdata); -int32_t pwrap_write(uint32_t adr, uint32_t wdata); +#include <pmic_wrap_init_common.h> static struct mt8195_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; @@ -30,47 +27,4 @@ struct mt8195_pmic_wrap_regs { uint32_t wacs2_sta; }; -#define GET_WACS_FSM(x) ((x >> 1) & 0x7) - -/* macro for SWINF_FSM */ -#define SWINF_FSM_IDLE (0x00) -#define SWINF_FSM_REQ (0x02) -#define SWINF_FSM_WFDLE (0x04) -#define SWINF_FSM_WFVLDCLR (0x06) -#define SWINF_INIT_DONE (0x01) - -/* timeout setting */ -#define PWRAP_READ_US 1000 -#define PWRAP_WAIT_IDLE_US 1000 - -/* error information flag */ -enum pwrap_errno { - E_PWR_INVALID_ARG = 1, - E_PWR_INVALID_RW = 2, - E_PWR_INVALID_ADDR = 3, - E_PWR_INVALID_WDAT = 4, - E_PWR_INVALID_OP_MANUAL = 5, - E_PWR_NOT_IDLE_STATE = 6, - E_PWR_NOT_INIT_DONE = 7, - E_PWR_NOT_INIT_DONE_READ = 8, - E_PWR_WAIT_IDLE_TIMEOUT = 9, - E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, - E_PWR_INIT_SIDLY_FAIL = 11, - E_PWR_RESET_TIMEOUT = 12, - E_PWR_TIMEOUT = 13, - E_PWR_INIT_RESET_SPI = 20, - E_PWR_INIT_SIDLY = 21, - E_PWR_INIT_REG_CLOCK = 22, - E_PWR_INIT_ENABLE_PMIC = 23, - E_PWR_INIT_DIO = 24, - E_PWR_INIT_CIPHER = 25, - E_PWR_INIT_WRITE_TEST = 26, - E_PWR_INIT_ENABLE_CRC = 27, - E_PWR_INIT_ENABLE_DEWRAP = 28, - E_PWR_INIT_ENABLE_EVENT = 29, - E_PWR_READ_TEST_FAIL = 30, - E_PWR_WRITE_TEST_FAIL = 31, - E_PWR_SWITCH_DIO = 32 -}; - #endif /* PMIC_WRAP_INIT_H */ diff --git a/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h deleted file mode 100644 index 341cf8602..000000000 --- a/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2021, MediaTek Inc. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef MTK_PTP3_COMMON_H -#define MTK_PTP3_COMMON_H - -#include <lib/mmio.h> -#include <lib/utils_def.h> - -/************************************************ - * CPU info - ************************************************/ -#define NR_PTP3_CFG_CPU U(8) -#define PTP3_CFG_CPU_START_ID_L U(0) -#define PTP3_CFG_CPU_START_ID_B U(4) -#define PTP3_CFG_CPU_END_ID U(7) - -#define NR_PTP3_CFG1_DATA U(2) -#define PTP3_CFG1_MASK 0x3000 - -#define NR_PTP3_CFG2_DATA U(5) - -#define PTP3_CFG3_MASK1 0x1180 -#define PTP3_CFG3_MASK2 0x35C0 -#define PTP3_CFG3_MASK3 0x3DC0 - -/************************************************ - * register read/write - ************************************************/ -#define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val) -#define ptp3_clrsetbits(addr, clear, set) \ - mmio_clrsetbits_32((uintptr_t)addr, clear, set) - -/************************************************ - * config enum - ************************************************/ -enum PTP3_CFG { - PTP3_CFG_ADDR, - PTP3_CFG_VALUE, - NR_PTP3_CFG, -}; - -/************************************ - * prototype - ************************************/ -extern void ptp3_core_init(unsigned int core); -extern void ptp3_core_unInit(unsigned int core); - -#endif /* MTK_PTP3_COMMON_H */ diff --git a/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c deleted file mode 100644 index 540cb33cb..000000000 --- a/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2021, MediaTek Inc. All rights reserved. \ - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch_helpers.h> -#include <mtk_ptp3_common.h> - -#define PTP3_CORE_OFT(core) (0x800 * (core)) - -/************************************************ - * Central control - ************************************************/ -static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = { - {0x0C53A2A0, 0x1000}, - {0x0C53A2A4, 0x1000} -}; - -static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = { - {0x0C530404, 0x3A1000}, - {0x0C530428, 0x13E0408}, - {0x0C530434, 0xB22800}, - {0x0C53043C, 0x750}, - {0x0C530440, 0x0222c4cc} -}; - -static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0x2D80}; -static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00}; - -static void ptp3_init(unsigned int core) -{ - unsigned int i, addr, value; - - if (core < PTP3_CFG_CPU_START_ID_B) { - ptp3_clrsetbits(ptp3_cfg1[0][PTP3_CFG_ADDR], PTP3_CFG1_MASK, - ptp3_cfg1[0][PTP3_CFG_VALUE]); - } else { - ptp3_clrsetbits(ptp3_cfg1[1][PTP3_CFG_ADDR], PTP3_CFG1_MASK, - ptp3_cfg1[1][PTP3_CFG_VALUE]); - } - - if (core < PTP3_CFG_CPU_START_ID_B) { - for (i = 0; i < NR_PTP3_CFG2_DATA; i++) { - addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + - PTP3_CORE_OFT(core); - value = ptp3_cfg2[i][PTP3_CFG_VALUE]; - - ptp3_write(addr, value); - } - } else { - for (i = 0; i < NR_PTP3_CFG2_DATA; i++) { - addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + - PTP3_CORE_OFT(core); - - if (i == 2) { - value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0; - } else { - value = ptp3_cfg2[i][PTP3_CFG_VALUE]; - } - ptp3_write(addr, value); - } - } - - if (core < PTP3_CFG_CPU_START_ID_B) { - addr = ptp3_cfg3[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); - value = ptp3_cfg3[PTP3_CFG_VALUE]; - - ptp3_write(addr, value & PTP3_CFG3_MASK1); - ptp3_write(addr, value & PTP3_CFG3_MASK2); - ptp3_write(addr, value & PTP3_CFG3_MASK3); - } else { - addr = ptp3_cfg3_ext[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); - value = ptp3_cfg3_ext[PTP3_CFG_VALUE]; - - ptp3_write(addr, value & PTP3_CFG3_MASK1); - ptp3_write(addr, value & PTP3_CFG3_MASK2); - ptp3_write(addr, value & PTP3_CFG3_MASK3); - } -} - -void pdp_proc_ARM_write(unsigned int pdp_n) -{ - unsigned long v = 0; - - dsb(); - __asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v)); - v |= (UL(0x0) << 52); - v |= (UL(0x1) << 53); - v |= (UL(0x0) << 54); - v |= (UL(0x0) << 48); - v |= (UL(0x1) << 49); - __asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v)); - dsb(); -} - -void pdp_init(unsigned int pdp_cpu, unsigned int en) -{ - if ((pdp_cpu >= PTP3_CFG_CPU_START_ID_B) && - (pdp_cpu < NR_PTP3_CFG_CPU)) { - pdp_proc_ARM_write(pdp_cpu); - } -} - -static void dt_proc_ARM_write(unsigned int dt_n) -{ - unsigned long v = 0; - - dsb(); - __asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v)); - v |= (UL(0x0) << 33); - v |= (UL(0x0) << 32); - __asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v)); - dsb(); -} - -void dt_init(unsigned int dt_cpu, unsigned int en) -{ - if ((dt_cpu >= PTP3_CFG_CPU_START_ID_B) && - (dt_cpu < NR_PTP3_CFG_CPU)) { - dt_proc_ARM_write(dt_cpu); - } -} -void ptp3_core_init(unsigned int core) -{ - /* init for ptp3 */ - ptp3_init(core); - /* init for pdp */ - pdp_init(core, 1); - /* init for dt */ - dt_init(core, 1); -} - -void ptp3_core_unInit(unsigned int core) -{ - /* TBD */ -} diff --git a/plat/mediatek/mt8195/drivers/ptp3/ptp3_plat.h b/plat/mediatek/mt8195/drivers/ptp3/ptp3_plat.h new file mode 100644 index 000000000..7d5391c97 --- /dev/null +++ b/plat/mediatek/mt8195/drivers/ptp3/ptp3_plat.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PTP3_PLAT_H +#define PTP3_PLAT_H + +#include <lib/mmio.h> +#include <lib/utils_def.h> +#include <ptp3_common.h> + +/* CPU info */ +#define NR_PTP3_CFG_CPU U(8) +#define PTP3_CFG_CPU_START_ID_L U(0) +#define PTP3_CFG_CPU_START_ID_B U(4) +#define PTP3_CFG_CPU_END_ID U(7) + +#define NR_PTP3_CFG1_DATA U(2) +#define PTP3_CFG1_MASK 0x3000 + +#define NR_PTP3_CFG2_DATA U(5) + +#define PTP3_CFG3_MASK1 0x1180 +#define PTP3_CFG3_MASK2 0x35C0 +#define PTP3_CFG3_MASK3 0x3DC0 + +/* Central control */ +static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = { + {0x0C53A2A0, 0x1000}, + {0x0C53A2A4, 0x1000} +}; + +static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = { + {0x0C530404, 0x3A1000}, + {0x0C530428, 0x13E0408}, + {0x0C530434, 0xB22800}, + {0x0C53043C, 0x750}, + {0x0C530440, 0x0222c4cc} +}; + +static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0x2D80}; +static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00}; + +#endif /* PTP3_PLAT_H */ diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c index d2ad282dc..87278d727 100644 --- a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c +++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,8 +23,8 @@ #include <plat_mtk_lpm.h> #ifndef ATF_PLAT_CIRQ_UNSUPPORT +#include <mt_cirq.h> #include <mt_gic_v3.h> -#include <mtk_cirq.h> #endif #define CONSTRAINT_BUS26M_ALLOW \ diff --git a/plat/mediatek/mt8195/include/plat_sip_calls.h b/plat/mediatek/mt8195/include/plat_sip_calls.h index 5562a6762..7d1f9fcfb 100644 --- a/plat/mediatek/mt8195/include/plat_sip_calls.h +++ b/plat/mediatek/mt8195/include/plat_sip_calls.h @@ -10,18 +10,6 @@ /******************************************************************************* * Plat SiP function constants ******************************************************************************/ -#define MTK_PLAT_SIP_NUM_CALLS 6 - -/* DFD */ -#define MTK_SIP_KERNEL_DFD_AARCH32 0x82000205 -#define MTK_SIP_KERNEL_DFD_AARCH64 0xC2000205 - -/* DP/eDP */ -#define MTK_SIP_DP_CONTROL_AARCH32 0x82000523 -#define MTK_SIP_DP_CONTROL_AARCH64 0xC2000523 - -/* APUSYS SMC call */ -#define MTK_SIP_APUSYS_CONTROL_AARCH32 0x8200051E -#define MTK_SIP_APUSYS_CONTROL_AARCH64 0xC200051E +#define MTK_PLAT_SIP_NUM_CALLS (8) #endif /* PLAT_SIP_CALLS_H */ diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h index d4f2f83b4..2a2f559da 100644 --- a/plat/mediatek/mt8195/include/platform_def.h +++ b/plat/mediatek/mt8195/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -48,9 +48,9 @@ /******************************************************************************* * DP/eDP related constants ******************************************************************************/ -#define eDP_SEC_BASE (IO_PHYS + 0x0C504000) +#define EDP_SEC_BASE (IO_PHYS + 0x0C504000) #define DP_SEC_BASE (IO_PHYS + 0x0C604000) -#define eDP_SEC_SIZE 0x1000 +#define EDP_SEC_SIZE 0x1000 #define DP_SEC_SIZE 0x1000 /******************************************************************************* diff --git a/plat/mediatek/mt8195/plat_pm.c b/plat/mediatek/mt8195/plat_pm.c index b77ab27a4..bd8a3faf9 100644 --- a/plat/mediatek/mt8195/plat_pm.c +++ b/plat/mediatek/mt8195/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, MediaTek Inc. All rights reserved. + * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,15 +13,15 @@ #include <lib/psci/psci.h> /* platform specific headers */ +#include <plat/common/platform.h> #include <mt_gic_v3.h> -#include <mtk_ptp3_common.h> #include <mtspmc.h> -#include <plat/common/platform.h> #include <plat_dfd.h> #include <plat_mtk_lpm.h> #include <plat_params.h> #include <plat_pm.h> #include <pmic.h> +#include <ptp3_common.h> #include <rtc.h> /* diff --git a/plat/mediatek/mt8195/plat_sip_calls.c b/plat/mediatek/mt8195/plat_sip_calls.c index 7d3c5128e..1cdd62298 100644 --- a/plat/mediatek/mt8195/plat_sip_calls.c +++ b/plat/mediatek/mt8195/plat_sip_calls.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,8 +32,8 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, ret = dp_secure_handler(x1, x2, &ret_val); SMC_RET2(handle, ret, ret_val); break; - case MTK_SIP_VCORE_CONTROL_ARCH32: - case MTK_SIP_VCORE_CONTROL_ARCH64: + case MTK_SIP_VCORE_CONTROL_AARCH32: + case MTK_SIP_VCORE_CONTROL_AARCH64: ret = spm_vcorefs_v2_args(x1, x2, x3, &x4); SMC_RET2(handle, ret, x4); break; diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk index a81c093bf..07d39cb7c 100644 --- a/plat/mediatek/mt8195/platform.mk +++ b/plat/mediatek/mt8195/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2021, MediaTek Inc. All rights reserved. +# Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -8,22 +8,27 @@ MTK_PLAT := plat/mediatek MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ - -I${MTK_PLAT}/common/drivers/gic600/ \ - -I${MTK_PLAT}/common/drivers/gpio/ \ - -I${MTK_PLAT}/common/drivers/rtc/ \ - -I${MTK_PLAT}/common/drivers/timer/ \ - -I${MTK_PLAT}/common/drivers/uart/ \ -I${MTK_PLAT}/common/lpm/ \ + -I${MTK_PLAT}/drivers/cirq/ \ + -I${MTK_PLAT}/drivers/dp/ \ + -I${MTK_PLAT}/drivers/gic600/ \ + -I${MTK_PLAT}/drivers/gpio/ \ + -I${MTK_PLAT}/drivers/pmic/ \ + -I${MTK_PLAT}/drivers/pmic_wrap/ \ + -I${MTK_PLAT}/drivers/ptp3/ \ + -I${MTK_PLAT}/drivers/rtc/ \ + -I${MTK_PLAT}/drivers/timer/ \ + -I${MTK_PLAT}/drivers/uart/ \ + -I${MTK_PLAT}/include/ \ -I${MTK_PLAT_SOC}/drivers/apusys/ \ -I${MTK_PLAT_SOC}/drivers/dcm \ -I${MTK_PLAT_SOC}/drivers/dfd \ - -I${MTK_PLAT_SOC}/drivers/dp/ \ -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \ -I${MTK_PLAT_SOC}/drivers/gpio/ \ -I${MTK_PLAT_SOC}/drivers/mcdi/ \ -I${MTK_PLAT_SOC}/drivers/pmic/ \ -I${MTK_PLAT_SOC}/drivers/spmc/ \ - -I${MTK_PLAT_SOC}/drivers/ptp3/ \ + -I${MTK_PLAT_SOC}/drivers/ptp3/ \ -I${MTK_PLAT_SOC}/include/ GICV3_SUPPORT_GIC600 := 1 @@ -45,37 +50,37 @@ BL31_SOURCES += common/desc_image_load.c \ lib/cpus/aarch64/cortex_a55.S \ lib/cpus/aarch64/cortex_a78.S \ plat/common/plat_gicv3.c \ - ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \ - ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \ - ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \ - ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \ - ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c \ - ${MTK_PLAT}/common/drivers/timer/mt_timer.c \ - ${MTK_PLAT}/common/drivers/uart/uart.c \ - ${MTK_PLAT}/common/lpm/mt_lp_rm.c \ - ${MTK_PLAT}/common/mtk_cirq.c \ ${MTK_PLAT}/common/mtk_plat_common.c \ ${MTK_PLAT}/common/mtk_sip_svc.c \ ${MTK_PLAT}/common/params_setup.c \ + ${MTK_PLAT}/common/lpm/mt_lp_rm.c \ + ${MTK_PLAT}/drivers/cirq/mt_cirq.c \ + ${MTK_PLAT}/drivers/dp/mt_dp.c \ + ${MTK_PLAT}/drivers/gic600/mt_gic_v3.c \ + ${MTK_PLAT}/drivers/gpio/mtgpio_common.c \ + ${MTK_PLAT}/drivers/pmic/pmic.c \ + ${MTK_PLAT}/drivers/pmic_wrap/pmic_wrap_init_v2.c \ + ${MTK_PLAT}/drivers/ptp3/ptp3_common.c \ + ${MTK_PLAT}/drivers/rtc/rtc_common.c \ + ${MTK_PLAT}/drivers/rtc/rtc_mt6359p.c \ + ${MTK_PLAT}/drivers/timer/mt_timer.c \ + ${MTK_PLAT}/drivers/uart/uart.c \ ${MTK_PLAT_SOC}/aarch64/platform_common.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ ${MTK_PLAT_SOC}/drivers/apusys/apupll.c \ ${MTK_PLAT_SOC}/drivers/apusys/apupwr_clkctl.c \ - ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \ + ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \ ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \ ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \ ${MTK_PLAT_SOC}/drivers/dfd/plat_dfd.c \ - ${MTK_PLAT_SOC}/drivers/dp/mt_dp.c \ ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \ ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \ ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \ - ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \ + ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ - ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ - ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \ ${MTK_PLAT_SOC}/plat_pm.c \ ${MTK_PLAT_SOC}/plat_sip_calls.c \ diff --git a/plat/mediatek/topology/armv8_2/topology.c b/plat/mediatek/topology/armv8_2/topology.c new file mode 100644 index 000000000..1627bbdb0 --- /dev/null +++ b/plat/mediatek/topology/armv8_2/topology.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022, Mediatek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <lib/psci/psci.h> +#include <platform_def.h> + +#pragma weak plat_get_power_domain_tree_desc + +static const unsigned char mtk_power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_SYSTEM_COUNT, + /* Number of children for the root node */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first cluster node */ + PLATFORM_CLUSTER0_CORE_COUNT, +}; + +/******************************************************************************* + * This function returns the default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return mtk_power_domain_tree_desc; +} diff --git a/plat/mediatek/topology/rules.mk b/plat/mediatek/topology/rules.mk new file mode 100644 index 000000000..29f15bbb5 --- /dev/null +++ b/plat/mediatek/topology/rules.mk @@ -0,0 +1,12 @@ +# +# Copyright (c) 2022, MediaTek Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +LOCAL_DIR := $(call GET_LOCAL_DIR) + +MODULE := topology +LOCAL_SRCS-y := $(LOCAL_DIR)/$(ARCH_VERSION)/topology.c + +$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL))) diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk index 758383380..631c92691 100644 --- a/plat/nvidia/tegra/soc/t194/platform_t194.mk +++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk @@ -33,7 +33,7 @@ MAX_MMAP_REGIONS := 30 $(eval $(call add_define,MAX_MMAP_REGIONS)) # enable RAS handling -HANDLE_EA_EL3_FIRST := 1 +HANDLE_EA_EL3_FIRST_NS := 1 RAS_EXTENSION := 1 # platform files diff --git a/plat/nxp/common/nv_storage/plat_nv_storage.c b/plat/nxp/common/nv_storage/plat_nv_storage.c index 7ec4fdbce..af3b96669 100644 --- a/plat/nxp/common/nv_storage/plat_nv_storage.c +++ b/plat/nxp/common/nv_storage/plat_nv_storage.c @@ -13,6 +13,7 @@ #include <stdlib.h> #include <string.h> +#include <platform_def.h> #include <common/debug.h> #ifndef NXP_COINED_BB #include <flash_info.h> diff --git a/plat/nxp/common/tbbr/tbbr.mk b/plat/nxp/common/tbbr/tbbr.mk index 7edcfbc8c..4aac9d634 100644 --- a/plat/nxp/common/tbbr/tbbr.mk +++ b/plat/nxp/common/tbbr/tbbr.mk @@ -133,13 +133,13 @@ else $(ROT_KEY): | $(BUILD_PLAT) @echo " OPENSSL $@" @if [ ! -f $(ROT_KEY) ]; then \ - openssl genrsa 2048 > $@ 2>/dev/null; \ + ${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \ fi $(ROTPK_HASH): $(ROT_KEY) @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null endif #MBEDTLS_DIR diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c b/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c index 2231c18d4..28e2dab63 100644 --- a/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c +++ b/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c @@ -85,32 +85,36 @@ int ddr_board_options(struct ddr_info *priv) return 0; } -/* DDR model number: MT40A512M8HX-093E */ +/* DDR model number: MT40A1G8SA-062E:R */ struct dimm_params ddr_raw_timing = { .n_ranks = U(1), .rank_density = ULL(2147483648), .capacity = ULL(2147483648), .primary_sdram_width = U(32), - .n_row_addr = U(15), + .ec_sdram_width = U(4), + .rdimm = U(0), + .mirrored_dimm = U(0), + .n_row_addr = U(16), .n_col_addr = U(10), .bank_group_bits = U(2), + .edc_config = U(2), .burst_lengths_bitmask = U(0x0c), - .tckmin_x_ps = 938, - .tckmax_ps = 1500, - .caslat_x = U(0x000DFA00), + .tckmin_x_ps = 625, + .tckmax_ps = 2200, + .caslat_x = U(0x0001FFE00), .taa_ps = 13500, .trcd_ps = 13500, .trp_ps = 13500, - .tras_ps = 33000, - .trc_ps = 46500, + .tras_ps = 32000, + .trc_ps = 45500, .twr_ps = 15000, - .trfc1_ps = 260000, - .trfc2_ps = 160000, - .trfc4_ps = 110000, + .trfc1_ps = 350000, + .trfc2_ps = 260000, + .trfc4_ps = 160000, .tfaw_ps = 21000, - .trrds_ps = 3700, - .trrdl_ps = 5300, - .tccdl_ps = 5355, + .trrds_ps = 3000, + .trrdl_ps = 4900, + .tccdl_ps = 5000, .refresh_rate_ps = U(7800000), .rc = U(0x1f), }; diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c b/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c index 6d1707ccf..89c9c0ae9 100644 --- a/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c +++ b/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c @@ -12,6 +12,7 @@ #include <lib/utils.h> #include <errata.h> +#include "platform_def.h" static const struct rc_timing rce[] = { {U(1600), U(8), U(7)}, diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h index 9ea0e3b71..7d3b145fc 100644 --- a/plat/qemu/qemu/include/platform_def.h +++ b/plat/qemu/qemu/include/platform_def.h @@ -146,7 +146,7 @@ * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the * current BL3-1 debug size plus a little space for growth. */ -#define BL31_BASE (BL31_LIMIT - 0xe0000) +#define BL31_BASE (BL31_LIMIT - 0x160000) #define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) #define BL31_PROGBITS_LIMIT BL1_RW_BASE diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk index e23076417..097e426c3 100644 --- a/plat/qemu/qemu/platform.mk +++ b/plat/qemu/qemu/platform.mk @@ -92,12 +92,12 @@ ifneq (${TRUSTED_BOARD_BOOT},0) $(ROT_KEY): | $(BUILD_PLAT) @echo " OPENSSL $@" - $(Q)openssl genrsa 2048 > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null $(ROTPK_HASH): $(ROT_KEY) @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null endif # Include Measured Boot makefile before any Crypto library makefile. @@ -108,6 +108,10 @@ ifeq (${MEASURED_BOOT},1) $(info Including ${MEASURED_BOOT_MK}) include ${MEASURED_BOOT_MK} + ifneq (${MBOOT_EL_HASH_ALG}, sha256) + $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) + endif + BL2_SOURCES += plat/qemu/qemu/qemu_measured_boot.c \ plat/qemu/qemu/qemu_common_measured_boot.c \ plat/qemu/qemu/qemu_helpers.c \ @@ -259,5 +263,8 @@ $(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE $(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) -# Do not enable SVE -ENABLE_SVE_FOR_NS := 0 +# Later QEMU versions support SME and SVE. +ifneq (${ARCH},aarch32) + ENABLE_SVE_FOR_NS := 1 + ENABLE_SME_FOR_NS := 1 +endif diff --git a/plat/qemu/qemu/qemu_helpers.c b/plat/qemu/qemu/qemu_helpers.c index 01b824977..1b31ab531 100644 --- a/plat/qemu/qemu/qemu_helpers.c +++ b/plat/qemu/qemu/qemu_helpers.c @@ -6,10 +6,12 @@ #include <assert.h> +#include <common/bl_common.h> #if MEASURED_BOOT #include <common/desc_image_load.h> #endif #include <common/fdt_wrappers.h> +#include <platform_def.h> #include <libfdt.h> diff --git a/plat/qti/common/inc/qti_plat.h b/plat/qti/common/inc/qti_plat.h index 4d9d3204a..7483c4945 100644 --- a/plat/qti/common/inc/qti_plat.h +++ b/plat/qti/common/inc/qti_plat.h @@ -25,13 +25,14 @@ int qti_mmap_remove_dynamic_region(uintptr_t base_va, size_t size); /* * Utility functions common to ARM standard platforms */ -void qti_setup_page_tables(uintptr_t total_base, +void qti_setup_page_tables( + uintptr_t total_base, size_t total_size, uintptr_t code_start, uintptr_t code_limit, uintptr_t rodata_start, - uintptr_t rodata_limit, - uintptr_t coh_start, uintptr_t coh_limit); + uintptr_t rodata_limit + ); /* * Mandatory functions required in ARM standard platforms @@ -53,4 +54,9 @@ void gic_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr); void qti_pmic_prepare_reset(void); void qti_pmic_prepare_shutdown(void); +typedef struct chip_id_info { + uint16_t jtag_id; + uint16_t chipinfo_id; +} chip_id_info_t; + #endif /* QTI_PLAT_H */ diff --git a/plat/qti/common/src/aarch64/qti_helpers.S b/plat/qti/common/src/aarch64/qti_helpers.S index c1ea7b32f..d34b5301d 100644 --- a/plat/qti/common/src/aarch64/qti_helpers.S +++ b/plat/qti/common/src/aarch64/qti_helpers.S @@ -72,17 +72,10 @@ func plat_reset_handler /* save the lr */ mov x18, x30 - /* Serialize CPUSS boot setup. Multi core enter simultaneously. */ - ldr x0, =g_qti_cpuss_boot_lock - bl spin_lock - /* pass cold boot status. */ ldr w0, g_qti_bl31_cold_booted /* Execuete CPUSS boot set up on every core. */ bl qtiseclib_cpuss_reset_asm - ldr x0, =g_qti_cpuss_boot_lock - bl spin_unlock - ret x18 endfunc plat_reset_handler diff --git a/plat/qti/common/src/aarch64/qti_kryo4_gold.S b/plat/qti/common/src/aarch64/qti_kryo4_gold.S index a1b40c8d1..9bcdf5425 100644 --- a/plat/qti/common/src/aarch64/qti_kryo4_gold.S +++ b/plat/qti/common/src/aarch64/qti_kryo4_gold.S @@ -28,19 +28,11 @@ func qti_kryo4_gold_reset_func mov x19, x30 bl qtiseclib_kryo4_gold_reset_asm - - ret x19 + mov x30, x19 + b cortex_a76_reset_func endfunc qti_kryo4_gold_reset_func -/* ---------------------------------------------------- - * The CPU Ops core power down function for Kryo-3 Gold - * ---------------------------------------------------- - */ -func qti_kryo4_gold_core_pwr_dwn - ret -endfunc qti_kryo4_gold_core_pwr_dwn - /* ------------------------------------------------------- * The CPU Ops cluster power down function for Kryo-3 Gold * ------------------------------------------------------- @@ -77,7 +69,9 @@ func qti_kryo4_gold_cpu_reg_dump ret endfunc qti_kryo4_gold_cpu_reg_dump -declare_cpu_ops qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \ +declare_cpu_ops_wa qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \ qti_kryo4_gold_reset_func, \ - qti_kryo4_gold_core_pwr_dwn, \ + CPU_NO_EXTRA1_FUNC, \ + cortex_a76_disable_wa_cve_2018_3639, \ + cortex_a76_core_pwr_dwn, \ qti_kryo4_gold_cluster_pwr_dwn diff --git a/plat/qti/common/src/aarch64/qti_kryo4_silver.S b/plat/qti/common/src/aarch64/qti_kryo4_silver.S index 183eeb0fa..36374b739 100644 --- a/plat/qti/common/src/aarch64/qti_kryo4_silver.S +++ b/plat/qti/common/src/aarch64/qti_kryo4_silver.S @@ -22,19 +22,11 @@ func qti_kryo4_silver_reset_func mov x19, x30 bl qtiseclib_kryo4_silver_reset_asm - - ret x19 + mov x30, x19 + b cortex_a55_reset_func endfunc qti_kryo4_silver_reset_func -/* ------------------------------------------------------ - * The CPU Ops core power down function for Kryo-3 Silver - * ------------------------------------------------------ - */ -func qti_kryo4_silver_core_pwr_dwn - ret -endfunc qti_kryo4_silver_core_pwr_dwn - /* --------------------------------------------------------- * The CPU Ops cluster power down function for Kryo-3 Silver * --------------------------------------------------------- @@ -75,5 +67,5 @@ endfunc qti_kryo4_silver_cpu_reg_dump declare_cpu_ops qti_kryo4_silver, QTI_KRYO4_SILVER_MIDR, \ qti_kryo4_silver_reset_func, \ - qti_kryo4_silver_core_pwr_dwn, \ + cortex_a55_core_pwr_dwn, \ qti_kryo4_silver_cluster_pwr_dwn diff --git a/plat/qti/common/src/aarch64/qti_kryo6_gold.S b/plat/qti/common/src/aarch64/qti_kryo6_gold.S index db1a304ea..577e7ff60 100644 --- a/plat/qti/common/src/aarch64/qti_kryo6_gold.S +++ b/plat/qti/common/src/aarch64/qti_kryo6_gold.S @@ -28,19 +28,11 @@ func qti_kryo6_gold_reset_func mov x19, x30 bl qtiseclib_kryo6_gold_reset_asm - - ret x19 + mov x30, x19 + b cortex_a78_reset_func endfunc qti_kryo6_gold_reset_func -/* ---------------------------------------------------- - * The CPU Ops core power down function for Kryo-3 Gold - * ---------------------------------------------------- - */ -func qti_kryo6_gold_core_pwr_dwn - ret -endfunc qti_kryo6_gold_core_pwr_dwn - /* ------------------------------------------------------- * The CPU Ops cluster power down function for Kryo-3 Gold * ------------------------------------------------------- @@ -79,5 +71,5 @@ endfunc qti_kryo6_gold_cpu_reg_dump declare_cpu_ops qti_kryo6_gold, QTI_KRYO6_GOLD_MIDR, \ qti_kryo6_gold_reset_func, \ - qti_kryo6_gold_core_pwr_dwn, \ + cortex_a78_core_pwr_dwn, \ qti_kryo6_gold_cluster_pwr_dwn diff --git a/plat/qti/common/src/aarch64/qti_kryo6_silver.S b/plat/qti/common/src/aarch64/qti_kryo6_silver.S index 2d189f233..6ad0bcae1 100644 --- a/plat/qti/common/src/aarch64/qti_kryo6_silver.S +++ b/plat/qti/common/src/aarch64/qti_kryo6_silver.S @@ -22,19 +22,11 @@ func qti_kryo6_silver_reset_func mov x19, x30 bl qtiseclib_kryo6_silver_reset_asm - - ret x19 + mov x30, x19 + b cortex_a55_reset_func endfunc qti_kryo6_silver_reset_func -/* ------------------------------------------------------ - * The CPU Ops core power down function for Kryo-3 Silver - * ------------------------------------------------------ - */ -func qti_kryo6_silver_core_pwr_dwn - ret -endfunc qti_kryo6_silver_core_pwr_dwn - /* --------------------------------------------------------- * The CPU Ops cluster power down function for Kryo-3 Silver * --------------------------------------------------------- @@ -75,5 +67,5 @@ endfunc qti_kryo6_silver_cpu_reg_dump declare_cpu_ops qti_kryo6_silver, QTI_KRYO6_SILVER_MIDR, \ qti_kryo6_silver_reset_func, \ - qti_kryo6_silver_core_pwr_dwn, \ + cortex_a55_core_pwr_dwn, \ qti_kryo6_silver_cluster_pwr_dwn diff --git a/plat/qti/common/src/qti_bl31_setup.c b/plat/qti/common/src/qti_bl31_setup.c index b2bc5436f..dac025356 100644 --- a/plat/qti/common/src/qti_bl31_setup.c +++ b/plat/qti/common/src/qti_bl31_setup.c @@ -36,16 +36,10 @@ static entry_point_info_t bl33_image_ep_info; static uint64_t g_qti_cpu_cntfrq; /* - * Lock variable to serialize cpuss reset execution. - */ -spinlock_t g_qti_cpuss_boot_lock __attribute__ ((section("tzfw_coherent_mem"), - aligned(CACHE_WRITEBACK_GRANULE))) = {0x0}; - -/* * Variable to hold bl31 cold boot status. Default value 0x0 means yet to boot. * Any other value means cold booted. */ -uint32_t g_qti_bl31_cold_booted __attribute__ ((section("tzfw_coherent_mem"))) = 0x0; +uint32_t g_qti_bl31_cold_booted; /******************************************************************************* * Perform any BL31 early platform setup common to ARM standard platforms. @@ -91,13 +85,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, ******************************************************************************/ void bl31_plat_arch_setup(void) { - qti_setup_page_tables(BL_CODE_BASE, - BL_COHERENT_RAM_END - BL_CODE_BASE, + qti_setup_page_tables( + BL31_START, + BL31_END-BL31_START, BL_CODE_BASE, BL_CODE_END, BL_RO_DATA_BASE, - BL_RO_DATA_END, - BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); + BL_RO_DATA_END + ); enable_mmu_el3(0); } diff --git a/plat/qti/common/src/qti_common.c b/plat/qti/common/src/qti_common.c index da0eaec44..74ccb5b41 100644 --- a/plat/qti/common/src/qti_common.c +++ b/plat/qti/common/src/qti_common.c @@ -17,6 +17,7 @@ #include <services/arm_arch_svc.h> #include <platform_def.h> +#include <qti_map_chipinfo.h> #include <qti_plat.h> #include <qtiseclib_interface.h> @@ -77,13 +78,14 @@ unsigned int plat_qti_my_cluster_pos(void) * - Read-only data section; * - Coherent memory region, if applicable. */ -void qti_setup_page_tables(uintptr_t total_base, +void qti_setup_page_tables( + uintptr_t total_base, size_t total_size, uintptr_t code_start, uintptr_t code_limit, uintptr_t rodata_start, - uintptr_t rodata_limit, - uintptr_t coh_start, uintptr_t coh_limit) + uintptr_t rodata_limit + ) { /* * Map the Trusted SRAM with appropriate memory attributes. @@ -106,12 +108,6 @@ void qti_setup_page_tables(uintptr_t total_base, mmap_add_region(rodata_start, rodata_start, rodata_limit - rodata_start, MT_RO_DATA | MT_SECURE); - /* Re-map the coherent memory region */ - VERBOSE("Coherent region: %p - %p\n", - (void *)coh_start, (void *)coh_limit); - mmap_add_region(coh_start, coh_start, - coh_limit - coh_start, MT_DEVICE | MT_RW | MT_SECURE); - /* Now (re-)map the platform-specific memory regions */ mmap_add(plat_qti_mmap); @@ -159,9 +155,22 @@ int qti_mmap_remove_dynamic_region(uintptr_t base_va, size_t size) */ int32_t plat_get_soc_version(void) { - uint32_t soc_version = (QTI_SOC_VERSION & QTI_SOC_VERSION_MASK); + int i = 0; + /* Variant other than in mapped g_map_jtag_chipinfo_id variable will have + * default chipinfo id as 0xFFFF + */ + uint32_t soc_version = (QTI_DEFAULT_CHIPINFO_ID & QTI_SOC_VERSION_MASK); uint32_t jep106az_code = (JEDEC_QTI_BKID << QTI_SOC_CONTINUATION_SHIFT) | (JEDEC_QTI_MFID << QTI_SOC_IDENTIFICATION_SHIFT); + uint32_t jtag_id = mmio_read_32(QTI_JTAG_ID_REG); + uint32_t jtag_id_val = (jtag_id >> QTI_JTAG_ID_SHIFT) + & QTI_SOC_VERSION_MASK; + + for (i = 0; i < ARRAY_SIZE(g_map_jtag_chipinfo_id); i++) { + if (g_map_jtag_chipinfo_id[i].jtag_id == jtag_id_val) + soc_version = g_map_jtag_chipinfo_id[i].chipinfo_id + & QTI_SOC_VERSION_MASK; + } return (int32_t)(jep106az_code | (soc_version)); } diff --git a/plat/qti/common/src/qti_interrupt_svc.c b/plat/qti/common/src/qti_interrupt_svc.c index 89cd7b555..3017dc793 100644 --- a/plat/qti/common/src/qti_interrupt_svc.c +++ b/plat/qti/common/src/qti_interrupt_svc.c @@ -55,6 +55,7 @@ int qti_interrupt_svc_init(void) * & we don't have S-EL1 support. */ set_interrupt_rm_flag(flags, NON_SECURE); + set_interrupt_rm_flag(flags, SECURE); /* Register handler for EL3 interrupts */ ret = register_interrupt_type_handler(INTR_TYPE_EL3, diff --git a/plat/qti/qtiseclib/src/qtiseclib_interface_stub.c b/plat/qti/qtiseclib/src/qtiseclib_interface_stub.c index 9c93d51da..cdaa0a7c8 100644 --- a/plat/qti/qtiseclib/src/qtiseclib_interface_stub.c +++ b/plat/qti/qtiseclib/src/qtiseclib_interface_stub.c @@ -50,6 +50,21 @@ void qtiseclib_kryo4_silver_reset_asm(void) } /* + * Execute CPU (Kryo4 gold) specific reset handler / system initialization. + * This takes care of executing required CPU errata's. + * + * Clobbers: x0 - x16 + */ +void qtiseclib_kryo6_gold_reset_asm(void) +{ +} + + +void qtiseclib_kryo6_silver_reset_asm(void) +{ +} + +/* * C Api's */ void qtiseclib_bl31_platform_setup(void) diff --git a/plat/qti/sc7180/inc/platform_def.h b/plat/qti/sc7180/inc/platform_def.h index e3dc81108..b69dfd95b 100644 --- a/plat/qti/sc7180/inc/platform_def.h +++ b/plat/qti/sc7180/inc/platform_def.h @@ -185,7 +185,6 @@ /*----------------------------------------------------------------------------*/ /* SOC hw version register */ /*----------------------------------------------------------------------------*/ -#define QTI_SOC_VERSION U(0x7180) #define QTI_SOC_VERSION_MASK U(0xFFFF) #define QTI_SOC_REVISION_REG 0x1FC8000 #define QTI_SOC_REVISION_MASK U(0xFFFF) diff --git a/plat/qti/sc7180/inc/qti_map_chipinfo.h b/plat/qti/sc7180/inc/qti_map_chipinfo.h new file mode 100644 index 000000000..4ab6191db --- /dev/null +++ b/plat/qti/sc7180/inc/qti_map_chipinfo.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef QTI_MAP_CHIPINFO_H +#define QTI_MAP_CHIPINFO_H + +#include <stdint.h> + +#include <qti_plat.h> + +#define QTI_JTAG_ID_REG 0x786130 +#define QTI_SOC_VERSION_MASK U(0xFFFF) +#define QTI_SOC_REVISION_REG 0x1FC8000 +#define QTI_SOC_REVISION_MASK U(0xFFFF) +#define QTI_JTAG_ID_SHIFT 12 +#define QTI_JTAG_ID_SC7180 U(0x012C) +#define QTI_JTAG_ID_SC7180P U(0x0195) +#define QTI_CHIPINFO_ID_SC7180 U(0x01A9) +#define QTI_CHIPINFO_ID_SC7180P U(0x01EF) +#define QTI_DEFAULT_CHIPINFO_ID U(0xFFFF) + +static const chip_id_info_t g_map_jtag_chipinfo_id[] = { + {QTI_JTAG_ID_SC7180, QTI_CHIPINFO_ID_SC7180}, + {QTI_JTAG_ID_SC7180P, QTI_CHIPINFO_ID_SC7180P}, +}; +#endif /* QTI_MAP_CHIPINFO_H */ diff --git a/plat/qti/sc7180/platform.mk b/plat/qti/sc7180/platform.mk index 141e2c39f..41a08ca30 100644 --- a/plat/qti/sc7180/platform.mk +++ b/plat/qti/sc7180/platform.mk @@ -12,12 +12,17 @@ CHIPSET := ${PLAT} # Turn On Separate code & data. SEPARATE_CODE_AND_RODATA := 1 -USE_COHERENT_MEM := 1 +USE_COHERENT_MEM := 0 WARMBOOT_ENABLE_DCACHE_EARLY := 1 +HW_ASSISTED_COHERENCY := 1 # Disable the PSCI platform compatibility layer ENABLE_PLAT_COMPAT := 0 +#Enable errata for cortex_a55 and cortex_a76 +ERRATA_A55_1530923 := 1 +ERRATA_A76_1165522 := 1 + # Enable PSCI v1.0 extended state ID format PSCI_EXTENDED_STATE_ID := 1 ARM_RECOM_STATE_ID_ENC := 1 @@ -93,10 +98,14 @@ TIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \ GIC_SOURCES := plat/common/plat_gicv3.c \ ${GICV3_SOURCES} \ -BL31_SOURCES += ${QTI_BL31_SOURCES} \ - ${PSCI_SOURCES} \ - ${GIC_SOURCES} \ - ${TIMER_SOURCES} \ +CPU_SOURCES := lib/cpus/aarch64/cortex_a76.S \ + lib/cpus/aarch64/cortex_a55.S \ + +BL31_SOURCES += ${QTI_BL31_SOURCES} \ + ${PSCI_SOURCES} \ + ${GIC_SOURCES} \ + ${TIMER_SOURCES} \ + ${CPU_SOURCES} \ LIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET} diff --git a/plat/qti/sc7280/inc/platform_def.h b/plat/qti/sc7280/inc/platform_def.h index da7eddc7a..48b48acf9 100644 --- a/plat/qti/sc7280/inc/platform_def.h +++ b/plat/qti/sc7280/inc/platform_def.h @@ -185,7 +185,6 @@ /*----------------------------------------------------------------------------*/ /* SOC hw version register */ /*----------------------------------------------------------------------------*/ -#define QTI_SOC_VERSION U(0x7280) #define QTI_SOC_VERSION_MASK U(0xFFFF) #define QTI_SOC_REVISION_REG 0x1FC8000 #define QTI_SOC_REVISION_MASK U(0xFFFF) diff --git a/plat/qti/sc7280/inc/qti_map_chipinfo.h b/plat/qti/sc7280/inc/qti_map_chipinfo.h new file mode 100644 index 000000000..7303e2088 --- /dev/null +++ b/plat/qti/sc7280/inc/qti_map_chipinfo.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef QTI_MAP_CHIPINFO_H +#define QTI_MAP_CHIPINFO_H + +#include <stdint.h> + +#include <qti_plat.h> + +#define QTI_JTAG_ID_REG 0x786130 +#define QTI_JTAG_ID_SHIFT 12 +#define QTI_JTAG_ID_SC7280 U(0x0193) +#define QTI_JTAG_ID_SC7280P U(0x01EB) +#define QTI_JTAG_ID_SC8270 U(0x01E3) +#define QTI_JTAG_ID_SC8270P U(0x020A) +#define QTI_JTAG_ID_SC7270P U(0x0215) +#define QTI_CHIPINFO_ID_SC7280 U(0x01E7) +#define QTI_CHIPINFO_ID_SC7280P U(0x0222) +#define QTI_CHIPINFO_ID_SC8270 U(0x0229) +#define QTI_CHIPINFO_ID_SC8270P U(0x0233) +#define QTI_CHIPINFO_ID_SC7270P U(0x0237) +#define QTI_DEFAULT_CHIPINFO_ID U(0xFFFF) + +static const chip_id_info_t g_map_jtag_chipinfo_id[] = { + {QTI_JTAG_ID_SC7280, QTI_CHIPINFO_ID_SC7280}, + {QTI_JTAG_ID_SC7280P, QTI_CHIPINFO_ID_SC7280P}, + {QTI_JTAG_ID_SC8270, QTI_CHIPINFO_ID_SC8270}, + {QTI_JTAG_ID_SC8270P, QTI_CHIPINFO_ID_SC8270P}, + {QTI_JTAG_ID_SC7270P, QTI_CHIPINFO_ID_SC7270P}, +}; +#endif /* QTI_MAP_CHIPINFO_H */ diff --git a/plat/qti/sc7280/platform.mk b/plat/qti/sc7280/platform.mk index bc2c2210c..df07bc4a7 100644 --- a/plat/qti/sc7280/platform.mk +++ b/plat/qti/sc7280/platform.mk @@ -12,8 +12,15 @@ CHIPSET := ${PLAT} # Turn On Separate code & data. SEPARATE_CODE_AND_RODATA := 1 -USE_COHERENT_MEM := 1 +USE_COHERENT_MEM := 0 WARMBOOT_ENABLE_DCACHE_EARLY := 1 +HW_ASSISTED_COHERENCY := 1 + +#Enable errata configs for cortex_a78 and cortex_a55 +ERRATA_A55_1530923 := 1 +ERRATA_A78_1941498 := 1 +ERRATA_A78_1951500 := 1 +ERRATA_A78_2132060 := 1 # Disable the PSCI platform compatibility layer ENABLE_PLAT_COMPAT := 0 @@ -93,10 +100,14 @@ TIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \ GIC_SOURCES := plat/common/plat_gicv3.c \ ${GICV3_SOURCES} \ -BL31_SOURCES += ${QTI_BL31_SOURCES} \ - ${PSCI_SOURCES} \ - ${GIC_SOURCES} \ - ${TIMER_SOURCES} \ +CPU_SOURCES := lib/cpus/aarch64/cortex_a78.S \ + lib/cpus/aarch64/cortex_a55.S \ + +BL31_SOURCES += ${QTI_BL31_SOURCES} \ + ${PSCI_SOURCES} \ + ${GIC_SOURCES} \ + ${TIMER_SOURCES} \ + ${CPU_SOURCES} \ LIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET} diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk index aef0ad149..ca61f0e8d 100644 --- a/plat/renesas/common/common.mk +++ b/plat/renesas/common/common.mk @@ -15,7 +15,7 @@ ENABLE_SVE_FOR_NS := 0 MULTI_CONSOLE_API := 1 CRASH_REPORTING := 1 -HANDLE_EA_EL3_FIRST := 1 +HANDLE_EA_EL3_FIRST_NS := 1 # This option gets enabled automatically if the TRUSTED_BOARD_BOOT # is set via root Makefile, but Renesas support Trusted-Boot without @@ -140,5 +140,4 @@ BL31_SOURCES += ${RCAR_GIC_SOURCES} \ drivers/arm/cci/cci.c include lib/xlat_tables_v2/xlat_tables.mk -include drivers/auth/mbedtls/mbedtls_crypto.mk PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index bbfa16927..f85db8d65 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -574,7 +574,7 @@ static void bl2_add_rpc_node(void) goto err; } - node = ret = fdt_add_subnode(fdt, node, "rpc@ee200000"); + node = ret = fdt_add_subnode(fdt, node, "spi@ee200000"); if (ret < 0) { goto err; } diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c index aec53eee2..68054ad19 100644 --- a/plat/rockchip/common/params_setup.c +++ b/plat/rockchip/common/params_setup.c @@ -38,7 +38,7 @@ static uint32_t rk_uart_base = PLAT_RK_UART_BASE; static uint32_t rk_uart_baudrate = PLAT_RK_UART_BAUDRATE; static uint32_t rk_uart_clock = PLAT_RK_UART_CLOCK; #define FDT_BUFFER_SIZE 0x20000 -static uint8_t fdt_buffer[FDT_BUFFER_SIZE]; +static uint64_t fdt_buffer[FDT_BUFFER_SIZE / 8]; void *plat_get_fdt(void) { diff --git a/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h b/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h index 34af29a8a..bcd2a7ce1 100644 --- a/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h +++ b/plat/rockchip/common/pmusram/cpus_on_fixed_addr.h @@ -48,7 +48,7 @@ CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG, CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR, assert_psram_dt_mpidr_offset_mistmatch); -extern void *sys_sleep_flag_sram; +extern struct psram_data_t sys_sleep_flag_sram; #endif /* __ASSEMBLER__ */ diff --git a/plat/rpi/common/rpi3_pm.c b/plat/rpi/common/rpi3_pm.c index 86c61f7a6..d98ac66f4 100644 --- a/plat/rpi/common/rpi3_pm.c +++ b/plat/rpi/common/rpi3_pm.c @@ -123,15 +123,6 @@ static void rpi3_pwr_domain_off(const psci_power_state_t *target_state) #endif } -void __dead2 plat_secondary_cold_boot_setup(void); - -static void __dead2 -rpi3_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) -{ - disable_mmu_el3(); - plat_secondary_cold_boot_setup(); -} - /******************************************************************************* * Platform handler called when a power domain is about to be turned on. The * mpidr determines the CPU to be turned on. @@ -196,8 +187,9 @@ static void __dead2 rpi3_pwr_down_wfi( write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT); - while (1) - ; + while (1) { + wfi(); + } } /******************************************************************************* @@ -262,7 +254,6 @@ static void __dead2 rpi3_system_off(void) static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { .cpu_standby = rpi3_cpu_standby, .pwr_domain_off = rpi3_pwr_domain_off, - .pwr_domain_pwr_down_wfi = rpi3_pwr_domain_pwr_down_wfi, .pwr_domain_on = rpi3_pwr_domain_on, .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, .pwr_domain_pwr_down_wfi = rpi3_pwr_down_wfi, diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk index 6c239230d..53c97e225 100644 --- a/plat/rpi/rpi3/platform.mk +++ b/plat/rpi/rpi3/platform.mk @@ -212,10 +212,10 @@ ifneq (${TRUSTED_BOARD_BOOT},0) $(ROT_KEY): | $(BUILD_PLAT) @echo " OPENSSL $@" - $(Q)openssl genrsa 2048 > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null $(ROTPK_HASH): $(ROT_KEY) @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null endif diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h index 49ffbf9a5..d6bfe42e1 100644 --- a/plat/socionext/synquacer/include/platform_def.h +++ b/plat/socionext/synquacer/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -42,16 +42,52 @@ #define MAX_XLAT_TABLES 8 #define MAX_MMAP_REGIONS 8 +#if TRUSTED_BOARD_BOOT +#define PLATFORM_STACK_SIZE 0x1000 +#else #define PLATFORM_STACK_SIZE 0x400 +#endif + +#if !RESET_TO_BL31 + +/* A mailbox page will be mapped from BL2 and BL31 */ +#define BL2_MAILBOX_BASE 0x0403f000 +#define BL2_MAILBOX_SIZE 0x1000 + +#define PLAT_SQ_BOOTIDX_BASE 0x08510000 +#define PLAT_SQ_MAX_BOOT_INDEX 2 + +#define MAX_IO_HANDLES 2 +#define MAX_IO_DEVICES 2 +#define MAX_IO_BLOCK_DEVICES U(1) + +#define BL2_BASE 0x04000000 +#define BL2_SIZE (256 * 1024) +#define BL2_LIMIT (BL2_BASE + BL2_SIZE) + +/* If BL2 is enabled, the BL31 is loaded on secure DRAM */ +#define BL31_BASE 0xfbe00000 +#define BL31_SIZE 0x00100000 +#else #define BL31_BASE 0x04000000 #define BL31_SIZE 0x00080000 +#endif + #define BL31_LIMIT (BL31_BASE + BL31_SIZE) #define BL32_BASE 0xfc000000 #define BL32_SIZE 0x03c00000 #define BL32_LIMIT (BL32_BASE + BL32_SIZE) +/* Alternative BL33 */ +#define PLAT_SQ_BL33_BASE 0xe0000000 +#define PLAT_SQ_BL33_SIZE 0x00200000 + +/* FWU FIP IO base */ +#define PLAT_SQ_FIP_IOBASE 0x08600000 +#define PLAT_SQ_FIP_MAXSIZE 0x00400000 + #define PLAT_SQ_CCN_BASE 0x32000000 #define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \ 0, /* Cluster 0 */ \ diff --git a/plat/socionext/synquacer/include/sq_common.h b/plat/socionext/synquacer/include/sq_common.h index b09d22a03..eef0e1fb1 100644 --- a/plat/socionext/synquacer/include/sq_common.h +++ b/plat/socionext/synquacer/include/sq_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,6 +39,8 @@ void sq_gic_cpuif_enable(void); void sq_gic_cpuif_disable(void); void sq_gic_pcpu_init(void); +int sq_io_setup(void); +struct image_info *sq_get_image_info(unsigned int image_id); void sq_mmap_setup(uintptr_t total_base, size_t total_size, const struct mmap_region *mmap); diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk index dcd5d31ee..b76ae8841 100644 --- a/plat/socionext/synquacer/platform.mk +++ b/plat/socionext/synquacer/platform.mk @@ -1,18 +1,26 @@ # -# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # -override RESET_TO_BL31 := 1 override PROGRAMMABLE_RESET_ADDRESS := 1 override USE_COHERENT_MEM := 1 override SEPARATE_CODE_AND_RODATA := 1 override ENABLE_SVE_FOR_NS := 0 # Enable workarounds for selected Cortex-A53 erratas. ERRATA_A53_855873 := 1 -# Enable SCMI support -SQ_USE_SCMI_DRIVER ?= 0 + +ifeq (${RESET_TO_BL31}, 1) +override RESET_TO_BL31 := 1 +override TRUSTED_BOARD_BOOT := 0 +SQ_USE_SCMI_DRIVER ?= 0 +else +override RESET_TO_BL31 := 0 +override BL2_AT_EL3 := 1 +SQ_USE_SCMI_DRIVER := 1 +BL2_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC +endif # Libraries include lib/xlat_tables_v2/xlat_tables.mk @@ -28,14 +36,55 @@ PLAT_BL_COMMON_SOURCES += $(PLAT_PATH)/sq_helpers.S \ drivers/arm/pl011/aarch64/pl011_console.S \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ + lib/cpus/aarch64/cortex_a53.S \ + $(PLAT_PATH)/sq_xlat_setup.c \ ${XLAT_TABLES_LIB_SRCS} # Include GICv3 driver files include drivers/arm/gic/v3/gicv3.mk +ifneq (${RESET_TO_BL31}, 1) +BL2_SOURCES += common/desc_image_load.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + $(PLAT_PATH)/sq_bl2_setup.c \ + $(PLAT_PATH)/sq_image_desc.c \ + $(PLAT_PATH)/sq_io_storage.c + +ifeq (${TRUSTED_BOARD_BOOT},1) +include drivers/auth/mbedtls/mbedtls_crypto.mk +include drivers/auth/mbedtls/mbedtls_x509.mk +BL2_SOURCES += drivers/auth/auth_mod.c \ + drivers/auth/crypto_mod.c \ + drivers/auth/img_parser_mod.c \ + drivers/auth/tbbr/tbbr_cot_common.c \ + drivers/auth/tbbr/tbbr_cot_bl2.c \ + plat/common/tbbr/plat_tbbr.c \ + $(PLAT_PATH)/sq_rotpk.S \ + $(PLAT_PATH)/sq_tbbr.c + +ROT_KEY = $(BUILD_PLAT)/rot_key.pem +ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin + +$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) +$(BUILD_PLAT)/bl2/sq_rotpk.o: $(ROTPK_HASH) + +certificates: $(ROT_KEY) +$(ROT_KEY): | $(BUILD_PLAT) + @echo " OPENSSL $@" + $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null + +$(ROTPK_HASH): $(ROT_KEY) + @echo " OPENSSL $@" + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null + +endif # TRUSTED_BOARD_BOOT +endif + BL31_SOURCES += drivers/arm/ccn/ccn.c \ ${GICV3_SOURCES} \ - lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_gicv3.c \ plat/common/plat_psci_common.c \ $(PLAT_PATH)/sq_bl31_setup.c \ @@ -43,7 +92,6 @@ BL31_SOURCES += drivers/arm/ccn/ccn.c \ $(PLAT_PATH)/sq_topology.c \ $(PLAT_PATH)/sq_psci.c \ $(PLAT_PATH)/sq_gicv3.c \ - $(PLAT_PATH)/sq_xlat_setup.c \ $(PLAT_PATH)/drivers/scp/sq_scp.c ifeq (${SQ_USE_SCMI_DRIVER},0) diff --git a/plat/socionext/synquacer/sq_bl2_setup.c b/plat/socionext/synquacer/sq_bl2_setup.c new file mode 100644 index 000000000..a98d91220 --- /dev/null +++ b/plat/socionext/synquacer/sq_bl2_setup.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2022, Socionext Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <errno.h> + +#include <common/bl_common.h> +#include <common/debug.h> +#include <common/desc_image_load.h> +#include <common/image_decompress.h> +#include <drivers/arm/pl011.h> +#include <drivers/io/io_storage.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> + +#include <platform_def.h> +#include <sq_common.h> + +static console_t console; + +void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, + u_register_t x2, u_register_t x3) +{ + /* Initialize the console to provide early debug support */ + (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, + PLAT_SQ_BOOT_UART_CLK_IN_HZ, + SQ_CONSOLE_BAUDRATE, &console); + console_set_scope(&console, CONSOLE_FLAG_BOOT); +} + +void bl2_el3_plat_arch_setup(void) +{ + int ret; + + sq_mmap_setup(BL2_BASE, BL2_SIZE, NULL); + + ret = sq_io_setup(); + if (ret) { + ERROR("failed to setup io devices\n"); + plat_error_handler(ret); + } +} + +void bl2_platform_setup(void) +{ +} + +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} + +void bl2_plat_preload_setup(void) +{ +} + +int bl2_plat_handle_pre_image_load(unsigned int image_id) +{ + struct image_info *image_info; + + image_info = sq_get_image_info(image_id); + + return mmap_add_dynamic_region(image_info->image_base, + image_info->image_base, + image_info->image_max_size, + MT_MEMORY | MT_RW | MT_NS); +} + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + return 0; +} diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c index a7a0ce0be..967437b29 100644 --- a/plat/socionext/synquacer/sq_bl31_setup.c +++ b/plat/socionext/synquacer/sq_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,6 +44,35 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; } +#if !RESET_TO_BL31 +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + void *from_bl2 = (void *) arg0; + bl_params_node_t *bl_params = ((bl_params_t *) from_bl2)->head; + + /* Initialize the console to provide early debug support */ + (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, + PLAT_SQ_BOOT_UART_CLK_IN_HZ, + SQ_CONSOLE_BAUDRATE, &console); + + console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); + + /* Initialize power controller before setting up topology */ + plat_sq_pwrc_setup(); + + while (bl_params) { + if (bl_params->image_id == BL32_IMAGE_ID) + bl32_image_ep_info = *bl_params->ep_info; + + if (bl_params->image_id == BL33_IMAGE_ID) + bl33_image_ep_info = *bl_params->ep_info; + + bl_params = bl_params->next_params_info; + } +} + +#else /******************************************************************************* * Gets SPSR for BL32 entry ******************************************************************************/ @@ -129,6 +158,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); } +#endif static void sq_configure_sys_timer(void) { @@ -192,6 +222,11 @@ void bl31_plat_arch_setup(void) PLAT_SQ_SP_PRIV_SIZE, MT_RW_DATA | MT_SECURE), #endif +#if !RESET_TO_BL31 + MAP_REGION_FLAT(BL2_MAILBOX_BASE, + BL2_MAILBOX_SIZE, + MT_RW | MT_SECURE), +#endif {0}, }; diff --git a/plat/socionext/synquacer/sq_helpers.S b/plat/socionext/synquacer/sq_helpers.S index 7a2d97b33..5f9eab41e 100644 --- a/plat/socionext/synquacer/sq_helpers.S +++ b/plat/socionext/synquacer/sq_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,7 +46,12 @@ endfunc platform_mem_init * code that secondary CPUs jump to. */ func plat_secondary_cold_boot_setup +#if !RESET_TO_BL31 + mov_imm x0, BL2_MAILBOX_BASE + ldr x0, [x0] +#else ldr x0, sq_sec_entrypoint +#endif /* Wait until the mailbox gets populated */ poll_mailbox: diff --git a/plat/socionext/synquacer/sq_image_desc.c b/plat/socionext/synquacer/sq_image_desc.c new file mode 100644 index 000000000..5fe125b56 --- /dev/null +++ b/plat/socionext/synquacer/sq_image_desc.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2022, Socionext Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <arch.h> +#include <common/desc_image_load.h> + +#include <platform_def.h> + +static struct bl_mem_params_node sq_image_descs[] = { + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_SIZE, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), + + .next_handoff_image_id = BL32_IMAGE_ID, + }, + { + .image_id = BL32_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_SIZE, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), + + .next_handoff_image_id = BL33_IMAGE_ID, + }, + { + .image_id = BL33_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_SQ_BL33_BASE, + .image_info.image_max_size = PLAT_SQ_BL33_SIZE, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + NON_SECURE | EXECUTABLE), + .ep_info.pc = PLAT_SQ_BL33_BASE, + .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +}; +REGISTER_BL_IMAGE_DESCS(sq_image_descs) + +struct image_info *sq_get_image_info(unsigned int image_id) +{ + struct bl_mem_params_node *desc; + + desc = get_bl_mem_params_node(image_id); + assert(desc); + return &desc->image_info; +} diff --git a/plat/socionext/synquacer/sq_io_storage.c b/plat/socionext/synquacer/sq_io_storage.c new file mode 100644 index 000000000..ea83dadfd --- /dev/null +++ b/plat/socionext/synquacer/sq_io_storage.c @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2022, Socionext Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdint.h> + +#include <drivers/io/io_block.h> +#include <drivers/io/io_driver.h> +#include <drivers/io/io_fip.h> +#include <drivers/io/io_memmap.h> +#include <lib/mmio.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <tools_share/firmware_image_package.h> + +#include <platform_def.h> +#include <sq_common.h> + +static const io_dev_connector_t *sq_fip_dev_con; +static uintptr_t sq_fip_dev_handle; + +static const io_dev_connector_t *sq_backend_dev_con; +static uintptr_t sq_backend_dev_handle; + +static io_block_spec_t sq_fip_spec = { + .offset = PLAT_SQ_FIP_IOBASE, /* FIP Image is at 5MB offset on memory-mapped NOR flash */ + .length = PLAT_SQ_FIP_MAXSIZE, /* Expected maximum FIP image size */ +}; + +static const io_uuid_spec_t sq_bl2_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, +}; + +static const io_uuid_spec_t sq_bl31_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t sq_bl32_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t sq_bl33_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t sq_tb_fw_cert_spec = { + .uuid = UUID_TRUSTED_BOOT_FW_CERT, +}; + +static const io_uuid_spec_t sq_trusted_key_cert_spec = { + .uuid = UUID_TRUSTED_KEY_CERT, +}; + +static const io_uuid_spec_t sq_soc_fw_key_cert_spec = { + .uuid = UUID_SOC_FW_KEY_CERT, +}; + +static const io_uuid_spec_t sq_tos_fw_key_cert_spec = { + .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, +}; + +static const io_uuid_spec_t sq_nt_fw_key_cert_spec = { + .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, +}; + +static const io_uuid_spec_t sq_soc_fw_cert_spec = { + .uuid = UUID_SOC_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t sq_tos_fw_cert_spec = { + .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t sq_nt_fw_cert_spec = { + .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, +}; +#endif /* TRUSTED_BOARD_BOOT */ + +struct sq_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + uintptr_t init_params; +}; + +static const struct sq_io_policy sq_io_policies[] = { + [FIP_IMAGE_ID] = { + .dev_handle = &sq_backend_dev_handle, + .image_spec = (uintptr_t)&sq_fip_spec, + }, + [BL2_IMAGE_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_bl2_spec, + .init_params = FIP_IMAGE_ID, + }, + [BL31_IMAGE_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_bl31_spec, + .init_params = FIP_IMAGE_ID, + }, + [BL32_IMAGE_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_bl32_spec, + .init_params = FIP_IMAGE_ID, + }, + [BL33_IMAGE_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_bl33_spec, + .init_params = FIP_IMAGE_ID, + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_BOOT_FW_CERT_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_tb_fw_cert_spec, + .init_params = FIP_IMAGE_ID, + }, + [TRUSTED_KEY_CERT_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_trusted_key_cert_spec, + .init_params = FIP_IMAGE_ID, + }, + [SOC_FW_KEY_CERT_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_soc_fw_key_cert_spec, + .init_params = FIP_IMAGE_ID, + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_tos_fw_key_cert_spec, + .init_params = FIP_IMAGE_ID, + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_nt_fw_key_cert_spec, + .init_params = FIP_IMAGE_ID, + }, + [SOC_FW_CONTENT_CERT_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_soc_fw_cert_spec, + .init_params = FIP_IMAGE_ID, + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_tos_fw_cert_spec, + .init_params = FIP_IMAGE_ID, + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + .dev_handle = &sq_fip_dev_handle, + .image_spec = (uintptr_t)&sq_nt_fw_cert_spec, + .init_params = FIP_IMAGE_ID, + }, +#endif +}; + +static int sq_update_fip_spec(void) +{ + uint32_t boot_index; + int ret; + + ret = mmap_add_dynamic_region(PLAT_SQ_BOOTIDX_BASE, PLAT_SQ_BOOTIDX_BASE, + PAGE_SIZE, MT_RO_DATA | MT_SECURE); + if (ret) { + return ret; + } + + boot_index = mmio_read_32(PLAT_SQ_BOOTIDX_BASE); + if (boot_index < PLAT_SQ_MAX_BOOT_INDEX) { + sq_fip_spec.offset += PLAT_SQ_FIP_MAXSIZE * boot_index; + INFO("FWU Enabled: boot_index %d\n", boot_index); + } else { + WARN("FWU Disabled: wrong boot_index value. Fallback to index 0.\n"); + } + + mmap_remove_dynamic_region(PLAT_SQ_BOOTIDX_BASE, PAGE_SIZE); + return 0; +} + +static int sq_io_memmap_setup(void) +{ + int ret; + + ret = sq_update_fip_spec(); + if (ret) { + return ret; + } + + ret = mmap_add_dynamic_region(sq_fip_spec.offset, sq_fip_spec.offset, + sq_fip_spec.length, MT_RO_DATA | MT_SECURE); + if (ret) { + return ret; + } + + ret = register_io_dev_memmap(&sq_backend_dev_con); + if (ret) { + return ret; + } + + return io_dev_open(sq_backend_dev_con, 0, &sq_backend_dev_handle); +} + +static int sq_io_fip_setup(void) +{ + int ret; + + ret = register_io_dev_fip(&sq_fip_dev_con); + if (ret) { + return ret; + } + + return io_dev_open(sq_fip_dev_con, 0, &sq_fip_dev_handle); +} + +int sq_io_setup(void) +{ + int ret; + + ret = sq_io_memmap_setup(); + if (ret) { + return ret; + } + + ret = sq_io_fip_setup(); + if (ret) { + return ret; + } + + return 0; +} + +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + uintptr_t init_params; + + assert(image_id < ARRAY_SIZE(sq_io_policies)); + + *dev_handle = *sq_io_policies[image_id].dev_handle; + *image_spec = sq_io_policies[image_id].image_spec; + init_params = sq_io_policies[image_id].init_params; + + return io_dev_init(*dev_handle, init_params); +} diff --git a/plat/socionext/synquacer/sq_psci.c b/plat/socionext/synquacer/sq_psci.c index 3062f6318..017516ff8 100644 --- a/plat/socionext/synquacer/sq_psci.c +++ b/plat/socionext/synquacer/sq_psci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -197,9 +197,17 @@ const plat_psci_ops_t sq_psci_ops = { int plat_setup_psci_ops(uintptr_t sec_entrypoint, const struct plat_psci_ops **psci_ops) { +#if !RESET_TO_BL31 + uintptr_t *sq_sec_ep = (uintptr_t *)BL2_MAILBOX_BASE; + + *sq_sec_ep = sec_entrypoint; + flush_dcache_range((uint64_t)sq_sec_ep, + sizeof(*sq_sec_ep)); +#else sq_sec_entrypoint = sec_entrypoint; flush_dcache_range((uint64_t)&sq_sec_entrypoint, sizeof(sq_sec_entrypoint)); +#endif *psci_ops = &sq_psci_ops; diff --git a/plat/socionext/synquacer/sq_rotpk.S b/plat/socionext/synquacer/sq_rotpk.S new file mode 100644 index 000000000..61227ed42 --- /dev/null +++ b/plat/socionext/synquacer/sq_rotpk.S @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2022, Socionext Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global sq_rotpk_hash + .global sq_rotpk_hash_end + .section .rodata.sq_rotpk_hash, "a" +sq_rotpk_hash: + /* DER header */ + .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 + .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 + /* SHA256 */ + .incbin ROTPK_HASH +sq_rotpk_hash_end: diff --git a/plat/socionext/synquacer/sq_tbbr.c b/plat/socionext/synquacer/sq_tbbr.c new file mode 100644 index 000000000..e9fa18c0e --- /dev/null +++ b/plat/socionext/synquacer/sq_tbbr.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022, Socionext Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <plat/common/platform.h> + +extern char sq_rotpk_hash[], sq_rotpk_hash_end[]; + +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + *key_ptr = sq_rotpk_hash; + *key_len = sq_rotpk_hash_end - sq_rotpk_hash; + *flags = ROTPK_IS_HASH; + + return 0; +} + +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + /* + * No support for non-volatile counter. Update the ROT key to protect + * the system against rollback. + */ + *nv_ctr = 0; + + return 0; +} + +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + return 0; +} + +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + return get_mbedtls_heap_helper(heap_addr, heap_size); +} diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk index 6edd181f4..378497aef 100644 --- a/plat/socionext/uniphier/platform.mk +++ b/plat/socionext/uniphier/platform.mk @@ -107,12 +107,12 @@ $(BUILD_PLAT)/bl2/uniphier_rotpk.o: $(ROTPK_HASH) certificates: $(ROT_KEY) $(ROT_KEY): | $(BUILD_PLAT) @echo " OPENSSL $@" - $(Q)openssl genrsa 2048 > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null $(ROTPK_HASH): $(ROT_KEY) @echo " OPENSSL $@" - $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ - openssl dgst -sha256 -binary > $@ 2>/dev/null + $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ + ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null endif diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c index b2038bc65..b271ed6d3 100644 --- a/plat/st/common/bl2_io_storage.c +++ b/plat/st/common/bl2_io_storage.c @@ -14,6 +14,7 @@ #include <drivers/fwu/fwu_metadata.h> #include <drivers/io/io_block.h> #include <drivers/io/io_driver.h> +#include <drivers/io/io_encrypted.h> #include <drivers/io/io_fip.h> #include <drivers/io/io_memmap.h> #include <drivers/io/io_mtd.h> @@ -37,6 +38,7 @@ #include <platform_def.h> #include <stm32cubeprogrammer.h> +#include <stm32mp_efi.h> #include <stm32mp_fconf_getter.h> #include <stm32mp_io_storage.h> #include <usb_dfu.h> @@ -47,6 +49,11 @@ uintptr_t storage_dev_handle; static const io_dev_connector_t *fip_dev_con; +#ifndef DECRYPTION_SUPPORT_none +static const io_dev_connector_t *enc_dev_con; +uintptr_t enc_dev_handle; +#endif + #if STM32MP_SDMMC || STM32MP_EMMC static struct mmc_device_info mmc_info; @@ -117,11 +124,65 @@ int open_fip(const uintptr_t spec) return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); } +#ifndef DECRYPTION_SUPPORT_none +int open_enc_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(enc_dev_handle, (uintptr_t)ENC_IMAGE_ID); + if (result != 0) { + return result; + } + + result = io_open(enc_dev_handle, spec, &local_image_handle); + if (result != 0) { + return result; + } + + VERBOSE("Using encrypted FIP\n"); + io_close(local_image_handle); + + return 0; +} +#endif + int open_storage(const uintptr_t spec) { return io_dev_init(storage_dev_handle, 0); } +#if STM32MP_EMMC_BOOT +static uint32_t get_boot_part_fip_header(void) +{ + io_block_spec_t emmc_boot_fip_block_spec = { + .offset = STM32MP_EMMC_BOOT_FIP_OFFSET, + .length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */ + }; + uint32_t magic = 0U; + int io_result; + size_t bytes_read; + uintptr_t fip_hdr_handle; + + io_result = io_open(storage_dev_handle, (uintptr_t)&emmc_boot_fip_block_spec, + &fip_hdr_handle); + assert(io_result == 0); + + io_result = io_read(fip_hdr_handle, (uintptr_t)&magic, sizeof(magic), + &bytes_read); + if ((io_result != 0) || (bytes_read != sizeof(magic))) { + panic(); + } + + io_close(fip_hdr_handle); + + VERBOSE("%s: eMMC boot magic at offset 256K: %08x\n", + __func__, magic); + + return magic; +} +#endif + static void print_boot_device(boot_api_context_t *boot_context) { switch (boot_context->boot_interface_selected) { @@ -189,13 +250,17 @@ static void boot_mmc(enum mmc_device_type mmc_dev_type, break; } + if (mmc_dev_type != MMC_IS_EMMC) { + params.flags = MMC_FLAG_SD_CMD6; + } + params.device_info = &mmc_info; if (stm32_sdmmc2_mmc_init(¶ms) != 0) { ERROR("SDMMC%u init failed\n", boot_interface_instance); panic(); } - /* Open MMC as a block device to read GPT table */ + /* Open MMC as a block device to read FIP */ io_result = register_io_dev_block(&mmc_dev_con); if (io_result != 0) { panic(); @@ -204,6 +269,26 @@ static void boot_mmc(enum mmc_device_type mmc_dev_type, io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, &storage_dev_handle); assert(io_result == 0); + +#if STM32MP_EMMC_BOOT + if (mmc_dev_type == MMC_IS_EMMC) { + io_result = mmc_part_switch_current_boot(); + assert(io_result == 0); + + if (get_boot_part_fip_header() != TOC_HEADER_NAME) { + WARN("%s: Can't find FIP header on eMMC boot partition. Trying GPT\n", + __func__); + io_result = mmc_part_switch_user(); + assert(io_result == 0); + return; + } + + VERBOSE("%s: FIP header found on eMMC boot partition\n", + __func__); + image_block_spec.offset = STM32MP_EMMC_BOOT_FIP_OFFSET; + image_block_spec.length = mmc_boot_part_size() - STM32MP_EMMC_BOOT_FIP_OFFSET; + } +#endif } #endif /* STM32MP_SDMMC || STM32MP_EMMC */ @@ -327,6 +412,15 @@ void stm32mp_io_setup(void) io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle); +#ifndef DECRYPTION_SUPPORT_none + io_result = register_io_dev_enc(&enc_dev_con); + assert(io_result == 0); + + io_result = io_dev_open(enc_dev_con, (uintptr_t)NULL, + &enc_dev_handle); + assert(io_result == 0); +#endif + switch (boot_context->boot_interface_selected) { #if STM32MP_SDMMC case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: @@ -385,8 +479,14 @@ int bl2_plat_handle_pre_image_load(unsigned int image_id) switch (boot_itf) { #if STM32MP_SDMMC || STM32MP_EMMC - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: +#if STM32MP_EMMC_BOOT + if (image_block_spec.offset == STM32MP_EMMC_BOOT_FIP_OFFSET) { + break; + } +#endif + /* fallthrough */ + case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: if (!gpt_init_done) { /* * With FWU Multi Bank feature enabled, the selection of @@ -395,13 +495,20 @@ int bl2_plat_handle_pre_image_load(unsigned int image_id) */ #if !PSA_FWU_SUPPORT const partition_entry_t *entry; + const struct efi_guid img_type_guid = STM32MP_FIP_GUID; + uuid_t img_type_uuid; + guidcpy(&img_type_uuid, &img_type_guid); partition_init(GPT_IMAGE_ID); - entry = get_partition_entry(FIP_IMAGE_NAME); + entry = get_partition_entry_by_type(&img_type_uuid); if (entry == NULL) { - ERROR("Could NOT find the %s partition!\n", - FIP_IMAGE_NAME); - return -ENOENT; + entry = get_partition_entry(FIP_IMAGE_NAME); + if (entry == NULL) { + ERROR("Could NOT find the %s partition!\n", + FIP_IMAGE_NAME); + + return -ENOENT; + } } image_block_spec.offset = entry->start; diff --git a/plat/st/common/bl2_stm32_io_storage.c b/plat/st/common/bl2_stm32_io_storage.c deleted file mode 100644 index 43911955a..000000000 --- a/plat/st/common/bl2_stm32_io_storage.c +++ /dev/null @@ -1,667 +0,0 @@ -/* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <string.h> - -#include <arch_helpers.h> -#include <common/debug.h> -#include <drivers/io/io_block.h> -#include <drivers/io/io_driver.h> -#include <drivers/io/io_dummy.h> -#include <drivers/io/io_mtd.h> -#include <drivers/io/io_storage.h> -#include <drivers/mmc.h> -#include <drivers/partition/partition.h> -#include <drivers/raw_nand.h> -#include <drivers/spi_nand.h> -#include <drivers/spi_nor.h> -#include <drivers/st/io_mmc.h> -#include <drivers/st/io_stm32image.h> -#include <drivers/st/stm32_fmc2_nand.h> -#include <drivers/st/stm32_qspi.h> -#include <drivers/st/stm32_sdmmc2.h> -#include <lib/mmio.h> -#include <lib/utils.h> -#include <plat/common/platform.h> - -#include <platform_def.h> - -/* IO devices */ -#ifndef AARCH32_SP_OPTEE -static const io_dev_connector_t *dummy_dev_con; -static uintptr_t dummy_dev_handle; -static uintptr_t dummy_dev_spec; -#endif - -static uintptr_t image_dev_handle; -static uintptr_t storage_dev_handle; - -#if STM32MP_SDMMC || STM32MP_EMMC -static struct mmc_device_info mmc_info; -static io_block_spec_t gpt_block_spec = { - .offset = 0U, - .length = 34U * MMC_BLOCK_SIZE, /* Size of GPT table */ -}; - -static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); - -static const io_block_dev_spec_t mmc_block_dev_spec = { - /* It's used as temp buffer in block driver */ - .buffer = { - .offset = (size_t)&block_buffer, - .length = MMC_BLOCK_SIZE, - }, - .ops = { - .read = mmc_read_blocks, - .write = NULL, - }, - .block_size = MMC_BLOCK_SIZE, -}; - -#if STM32MP_EMMC_BOOT -static io_block_spec_t emmc_boot_ssbl_block_spec = { - .offset = PLAT_EMMC_BOOT_SSBL_OFFSET, - .length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */ -}; - -static const io_block_dev_spec_t mmc_block_dev_boot_part_spec = { - /* It's used as temp buffer in block driver */ - .buffer = { - .offset = (size_t)&block_buffer, - .length = MMC_BLOCK_SIZE, - }, - .ops = { - .read = mmc_boot_part_read_blocks, - .write = NULL, - }, - .block_size = MMC_BLOCK_SIZE, -}; -#endif - -static struct io_mmc_dev_spec mmc_device_spec = { - .use_boot_part = false, -}; - -static const io_dev_connector_t *mmc_dev_con; -#endif /* STM32MP_SDMMC || STM32MP_EMMC */ - -#if STM32MP_SPI_NOR -static io_mtd_dev_spec_t spi_nor_dev_spec = { - .ops = { - .init = spi_nor_init, - .read = spi_nor_read, - }, -}; -#endif - -#if STM32MP_RAW_NAND -static io_mtd_dev_spec_t nand_dev_spec = { - .ops = { - .init = nand_raw_init, - .read = nand_read, - }, -}; - -static const io_dev_connector_t *nand_dev_con; -#endif - -#if STM32MP_SPI_NAND -static io_mtd_dev_spec_t spi_nand_dev_spec = { - .ops = { - .init = spi_nand_init, - .read = nand_read, - }, -}; -#endif - -#if STM32MP_SPI_NAND || STM32MP_SPI_NOR -static const io_dev_connector_t *spi_dev_con; -#endif - -#ifdef AARCH32_SP_OPTEE -static const struct stm32image_part_info optee_header_partition_spec = { - .name = OPTEE_HEADER_IMAGE_NAME, - .binary_type = OPTEE_HEADER_BINARY_TYPE, -}; - -static const struct stm32image_part_info optee_core_partition_spec = { - .name = OPTEE_CORE_IMAGE_NAME, - .binary_type = OPTEE_CORE_BINARY_TYPE, -}; - -static const struct stm32image_part_info optee_paged_partition_spec = { - .name = OPTEE_PAGED_IMAGE_NAME, - .binary_type = OPTEE_PAGED_BINARY_TYPE, -}; -#else -static const io_block_spec_t bl32_block_spec = { - .offset = BL32_BASE, - .length = STM32MP_BL32_SIZE -}; -#endif - -static const struct stm32image_part_info bl33_partition_spec = { - .name = BL33_IMAGE_NAME, - .binary_type = BL33_BINARY_TYPE, -}; - -enum { - IMG_IDX_BL33, -#ifdef AARCH32_SP_OPTEE - IMG_IDX_OPTEE_HEADER, - IMG_IDX_OPTEE_CORE, - IMG_IDX_OPTEE_PAGED, -#endif - IMG_IDX_NUM -}; - -static struct stm32image_device_info stm32image_dev_info_spec __unused = { - .lba_size = MMC_BLOCK_SIZE, - .part_info[IMG_IDX_BL33] = { - .name = BL33_IMAGE_NAME, - .binary_type = BL33_BINARY_TYPE, - }, -#ifdef AARCH32_SP_OPTEE - .part_info[IMG_IDX_OPTEE_HEADER] = { - .name = OPTEE_HEADER_IMAGE_NAME, - .binary_type = OPTEE_HEADER_BINARY_TYPE, - }, - .part_info[IMG_IDX_OPTEE_CORE] = { - .name = OPTEE_CORE_IMAGE_NAME, - .binary_type = OPTEE_CORE_BINARY_TYPE, - }, - .part_info[IMG_IDX_OPTEE_PAGED] = { - .name = OPTEE_PAGED_IMAGE_NAME, - .binary_type = OPTEE_PAGED_BINARY_TYPE, - }, -#endif -}; - -static io_block_spec_t stm32image_block_spec = { - .offset = 0U, - .length = 0U, -}; - -static const io_dev_connector_t *stm32image_dev_con __unused; - -#ifndef AARCH32_SP_OPTEE -static int open_dummy(const uintptr_t spec); -#endif -static int open_image(const uintptr_t spec); -static int open_storage(const uintptr_t spec); - -struct plat_io_policy { - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -static const struct plat_io_policy policies[] = { -#ifdef AARCH32_SP_OPTEE - [BL32_IMAGE_ID] = { - .dev_handle = &image_dev_handle, - .image_spec = (uintptr_t)&optee_header_partition_spec, - .check = open_image - }, - [BL32_EXTRA1_IMAGE_ID] = { - .dev_handle = &image_dev_handle, - .image_spec = (uintptr_t)&optee_core_partition_spec, - .check = open_image - }, - [BL32_EXTRA2_IMAGE_ID] = { - .dev_handle = &image_dev_handle, - .image_spec = (uintptr_t)&optee_paged_partition_spec, - .check = open_image - }, -#else - [BL32_IMAGE_ID] = { - .dev_handle = &dummy_dev_handle, - .image_spec = (uintptr_t)&bl32_block_spec, - .check = open_dummy - }, -#endif - [BL33_IMAGE_ID] = { - .dev_handle = &image_dev_handle, - .image_spec = (uintptr_t)&bl33_partition_spec, - .check = open_image - }, -#if STM32MP_SDMMC || STM32MP_EMMC - [GPT_IMAGE_ID] = { - .dev_handle = &storage_dev_handle, - .image_spec = (uintptr_t)&gpt_block_spec, - .check = open_storage - }, -#endif - [STM32_IMAGE_ID] = { - .dev_handle = &storage_dev_handle, - .image_spec = (uintptr_t)&stm32image_block_spec, - .check = open_storage - } -}; - -#ifndef AARCH32_SP_OPTEE -static int open_dummy(const uintptr_t spec) -{ - return io_dev_init(dummy_dev_handle, 0); -} -#endif - -static int open_image(const uintptr_t spec) -{ - return io_dev_init(image_dev_handle, 0); -} - -static int open_storage(const uintptr_t spec) -{ - return io_dev_init(storage_dev_handle, 0); -} - -#if STM32MP_EMMC_BOOT -static uint32_t get_boot_part_ssbl_header(void) -{ - uint32_t magic = 0U; - int io_result; - size_t bytes_read; - - io_result = register_io_dev_block(&mmc_dev_con); - if (io_result != 0) { - panic(); - } - - io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_boot_part_spec, - &storage_dev_handle); - assert(io_result == 0); - - io_result = io_open(storage_dev_handle, (uintptr_t)&emmc_boot_ssbl_block_spec, - &image_dev_handle); - assert(io_result == 0); - - io_result = io_read(image_dev_handle, (uintptr_t)&magic, sizeof(magic), - &bytes_read); - assert(io_result == 0); - assert(bytes_read == sizeof(magic)); - - io_result = io_dev_close(storage_dev_handle); - assert(io_result == 0); - - return magic; -} -#endif - -static void print_boot_device(boot_api_context_t *boot_context) -{ - switch (boot_context->boot_interface_selected) { - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: - INFO("Using SDMMC\n"); - break; - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: - INFO("Using EMMC\n"); - break; - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: - INFO("Using QSPI NOR\n"); - break; - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: - INFO("Using FMC NAND\n"); - break; - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: - INFO("Using SPI NAND\n"); - break; - default: - ERROR("Boot interface not found\n"); - panic(); - break; - } - - if (boot_context->boot_interface_instance != 0U) { - INFO(" Instance %d\n", boot_context->boot_interface_instance); - } -} - -static void stm32image_io_setup(void) -{ - int io_result __unused; - - io_result = register_io_dev_stm32image(&stm32image_dev_con); - assert(io_result == 0); - - io_result = io_dev_open(stm32image_dev_con, - (uintptr_t)&stm32image_dev_info_spec, - &image_dev_handle); - assert(io_result == 0); -} - -#if STM32MP_SDMMC || STM32MP_EMMC -static void boot_mmc(enum mmc_device_type mmc_dev_type, - uint16_t boot_interface_instance) -{ - int io_result __unused; - uint8_t idx; - struct stm32image_part_info *part; - struct stm32_sdmmc2_params params; - const partition_entry_t *entry __unused; - uint32_t magic __unused; - - zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); - - mmc_info.mmc_dev_type = mmc_dev_type; - - switch (boot_interface_instance) { - case 1: - params.reg_base = STM32MP_SDMMC1_BASE; - break; - case 2: - params.reg_base = STM32MP_SDMMC2_BASE; - break; - case 3: - params.reg_base = STM32MP_SDMMC3_BASE; - break; - default: - WARN("SDMMC instance not found, using default\n"); - if (mmc_dev_type == MMC_IS_SD) { - params.reg_base = STM32MP_SDMMC1_BASE; - } else { - params.reg_base = STM32MP_SDMMC2_BASE; - } - break; - } - - params.device_info = &mmc_info; - if (stm32_sdmmc2_mmc_init(¶ms) != 0) { - ERROR("SDMMC%u init failed\n", boot_interface_instance); - panic(); - } - - stm32image_dev_info_spec.device_size = - stm32_sdmmc2_mmc_get_device_size(); - -#if STM32MP_EMMC_BOOT - if (mmc_dev_type == MMC_IS_EMMC) { - magic = get_boot_part_ssbl_header(); - - if (magic == BOOT_API_IMAGE_HEADER_MAGIC_NB) { - VERBOSE("%s, header found, jump to emmc load\n", __func__); - idx = IMG_IDX_BL33; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = PLAT_EMMC_BOOT_SSBL_OFFSET; - part->bkp_offset = 0U; - mmc_device_spec.use_boot_part = true; - - goto emmc_boot; - } else { - WARN("%s: Can't find STM32 header on a boot partition\n", __func__); - } - } -#endif - - /* Open MMC as a block device to read GPT table */ - io_result = register_io_dev_block(&mmc_dev_con); - if (io_result != 0) { - panic(); - } - - io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, - &storage_dev_handle); - assert(io_result == 0); - - partition_init(GPT_IMAGE_ID); - - io_result = io_dev_close(storage_dev_handle); - assert(io_result == 0); - - for (idx = 0U; idx < IMG_IDX_NUM; idx++) { - part = &stm32image_dev_info_spec.part_info[idx]; - entry = get_partition_entry(part->name); - if (entry == NULL) { - ERROR("Partition %s not found\n", part->name); - panic(); - } - - part->part_offset = entry->start; - part->bkp_offset = 0U; - } - -#if STM32MP_EMMC_BOOT -emmc_boot: -#endif - /* - * Re-open MMC with io_mmc, for better perfs compared to - * io_block. - */ - io_result = register_io_dev_mmc(&mmc_dev_con); - assert(io_result == 0); - - io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_device_spec, - &storage_dev_handle); - assert(io_result == 0); -} -#endif /* STM32MP_SDMMC || STM32MP_EMMC */ - -#if STM32MP_SPI_NOR -static void boot_spi_nor(boot_api_context_t *boot_context) -{ - int io_result __unused; - uint8_t idx; - struct stm32image_part_info *part; - - io_result = stm32_qspi_init(); - assert(io_result == 0); - - io_result = register_io_dev_mtd(&spi_dev_con); - assert(io_result == 0); - - /* Open connections to device */ - io_result = io_dev_open(spi_dev_con, - (uintptr_t)&spi_nor_dev_spec, - &storage_dev_handle); - assert(io_result == 0); - - stm32image_dev_info_spec.device_size = spi_nor_dev_spec.device_size; - - idx = IMG_IDX_BL33; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NOR_BL33_OFFSET; - part->bkp_offset = 0U; - -#ifdef AARCH32_SP_OPTEE - idx = IMG_IDX_OPTEE_HEADER; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NOR_TEEH_OFFSET; - part->bkp_offset = 0U; - - idx = IMG_IDX_OPTEE_PAGED; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NOR_TEED_OFFSET; - part->bkp_offset = 0U; - - idx = IMG_IDX_OPTEE_CORE; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NOR_TEEX_OFFSET; - part->bkp_offset = 0U; -#endif -} -#endif /* STM32MP_SPI_NOR */ - -#if STM32MP_RAW_NAND -static void boot_fmc2_nand(boot_api_context_t *boot_context) -{ - int io_result __unused; - uint8_t idx; - struct stm32image_part_info *part; - - io_result = stm32_fmc2_init(); - assert(io_result == 0); - - /* Register the IO device on this platform */ - io_result = register_io_dev_mtd(&nand_dev_con); - assert(io_result == 0); - - /* Open connections to device */ - io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, - &storage_dev_handle); - assert(io_result == 0); - - stm32image_dev_info_spec.device_size = nand_dev_spec.device_size; - - idx = IMG_IDX_BL33; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NAND_BL33_OFFSET; - part->bkp_offset = nand_dev_spec.erase_size; - -#ifdef AARCH32_SP_OPTEE - idx = IMG_IDX_OPTEE_HEADER; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NAND_TEEH_OFFSET; - part->bkp_offset = nand_dev_spec.erase_size; - - idx = IMG_IDX_OPTEE_PAGED; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NAND_TEED_OFFSET; - part->bkp_offset = nand_dev_spec.erase_size; - - idx = IMG_IDX_OPTEE_CORE; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NAND_TEEX_OFFSET; - part->bkp_offset = nand_dev_spec.erase_size; -#endif -} -#endif /* STM32MP_RAW_NAND */ - -#if STM32MP_SPI_NAND -static void boot_spi_nand(boot_api_context_t *boot_context) -{ - int io_result __unused; - uint8_t idx; - struct stm32image_part_info *part; - - io_result = stm32_qspi_init(); - assert(io_result == 0); - - io_result = register_io_dev_mtd(&spi_dev_con); - assert(io_result == 0); - - /* Open connections to device */ - io_result = io_dev_open(spi_dev_con, - (uintptr_t)&spi_nand_dev_spec, - &storage_dev_handle); - assert(io_result == 0); - - stm32image_dev_info_spec.device_size = - spi_nand_dev_spec.device_size; - - idx = IMG_IDX_BL33; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NAND_BL33_OFFSET; - part->bkp_offset = spi_nand_dev_spec.erase_size; - -#ifdef AARCH32_SP_OPTEE - idx = IMG_IDX_OPTEE_HEADER; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NAND_TEEH_OFFSET; - part->bkp_offset = spi_nand_dev_spec.erase_size; - - idx = IMG_IDX_OPTEE_PAGED; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NAND_TEED_OFFSET; - part->bkp_offset = spi_nand_dev_spec.erase_size; - - idx = IMG_IDX_OPTEE_CORE; - part = &stm32image_dev_info_spec.part_info[idx]; - part->part_offset = STM32MP_NAND_TEEX_OFFSET; - part->bkp_offset = spi_nand_dev_spec.erase_size; -#endif -} -#endif /* STM32MP_SPI_NAND */ - -void stm32mp_io_setup(void) -{ - int io_result __unused; - boot_api_context_t *boot_context = - (boot_api_context_t *)stm32mp_get_boot_ctx_address(); - - print_boot_device(boot_context); - - if ((boot_context->boot_partition_used_toboot == 1U) || - (boot_context->boot_partition_used_toboot == 2U)) { - INFO("Boot used partition fsbl%u\n", - boot_context->boot_partition_used_toboot); - } - -#ifndef AARCH32_SP_OPTEE - io_result = register_io_dev_dummy(&dummy_dev_con); - assert(io_result == 0); - - io_result = io_dev_open(dummy_dev_con, dummy_dev_spec, - &dummy_dev_handle); - assert(io_result == 0); -#endif - - switch (boot_context->boot_interface_selected) { -#if STM32MP_SDMMC - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: - dmbsy(); - boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); - stm32image_io_setup(); - break; -#endif -#if STM32MP_EMMC - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: - dmbsy(); - boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); - stm32image_io_setup(); - break; -#endif -#if STM32MP_SPI_NOR - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: - dmbsy(); - boot_spi_nor(boot_context); - stm32image_io_setup(); - break; -#endif -#if STM32MP_RAW_NAND - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: - dmbsy(); - boot_fmc2_nand(boot_context); - stm32image_io_setup(); - break; -#endif -#if STM32MP_SPI_NAND - case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: - dmbsy(); - boot_spi_nand(boot_context); - stm32image_io_setup(); - break; -#endif - - default: - ERROR("Boot interface %d not supported\n", - boot_context->boot_interface_selected); - panic(); - break; - } -} - -/* - * Return an IO device handle and specification which can be used to access - * an image. Use this to enforce platform load policy. - */ -int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int rc; - const struct plat_io_policy *policy; - - assert(image_id < ARRAY_SIZE(policies)); - - policy = &policies[image_id]; - rc = policy->check(policy->image_spec); - if (rc == 0) { - *image_spec = policy->image_spec; - *dev_handle = *(policy->dev_handle); - } - - return rc; -} diff --git a/plat/st/common/include/stm32mp_auth.h b/plat/st/common/include/stm32mp_auth.h deleted file mode 100644 index 3075d18ac..000000000 --- a/plat/st/common/include/stm32mp_auth.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STM32MP_AUTH_H -#define STM32MP_AUTH_H - -struct stm32mp_auth_ops { - uint32_t (*check_key)(uint8_t *pubkey_in, uint8_t *pubkey_out); - uint32_t (*verify_signature)(uint8_t *hash_in, uint8_t *pubkey_in, - uint8_t *signature, uint32_t ecc_algo); -}; - -void stm32mp_init_auth(struct stm32mp_auth_ops *init_ptr); -int stm32mp_auth_image(boot_api_image_header_t *header, uintptr_t buffer); - -#endif /* STM32MP_AUTH_H */ diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h index 0010cd8f3..a5316b668 100644 --- a/plat/st/common/include/stm32mp_common.h +++ b/plat/st/common/include/stm32mp_common.h @@ -109,16 +109,6 @@ void stm32mp_print_boardinfo(void); /* Initialise the IO layer and register platform IO devices */ void stm32mp_io_setup(void); -#if STM32MP_USE_STM32IMAGE -/* - * Check that the STM32 header of a .stm32 binary image is valid - * @param header: pointer to the stm32 image header - * @param buffer: address of the binary image (payload) - * @return: 0 on success, negative value in case of error - */ -int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer); -#endif /* STM32MP_USE_STM32IMAGE */ - /* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */ int stm32mp_map_ddr_non_cacheable(void); int stm32mp_unmap_ddr(void); @@ -127,10 +117,13 @@ int stm32mp_unmap_ddr(void); void stm32_save_boot_interface(uint32_t interface, uint32_t instance); void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance); -#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT +/* Functions to save and get boot authentication status and partition used */ +void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition); + +#if PSA_FWU_SUPPORT void stm32mp1_fwu_set_boot_idx(void); uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void); void stm32_set_max_fwu_trial_boot_cnt(void); -#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ +#endif /* PSA_FWU_SUPPORT */ #endif /* STM32MP_COMMON_H */ diff --git a/plat/st/common/include/stm32mp_io_storage.h b/plat/st/common/include/stm32mp_io_storage.h index 989c890d4..3c04c4716 100644 --- a/plat/st/common/include/stm32mp_io_storage.h +++ b/plat/st/common/include/stm32mp_io_storage.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,11 +13,15 @@ /* IO devices handle */ extern uintptr_t storage_dev_handle; extern uintptr_t fip_dev_handle; +extern uintptr_t enc_dev_handle; extern io_block_spec_t image_block_spec; /* Function declarations */ int open_fip(const uintptr_t spec); +#ifndef DECRYPTION_SUPPORT_none +int open_enc_fip(const uintptr_t spec); +#endif int open_storage(const uintptr_t spec); #endif /* STM32MP_IO_STORAGE_H */ diff --git a/plat/st/common/stm32cubeprogrammer_uart.c b/plat/st/common/stm32cubeprogrammer_uart.c index 46ac9cf17..d004dcfe4 100644 --- a/plat/st/common/stm32cubeprogrammer_uart.c +++ b/plat/st/common/stm32cubeprogrammer_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -486,13 +486,12 @@ static int uart_read(uint8_t id, uintptr_t buffer, size_t length) /* Init UART: 115200, 8bit 1stop parity even and enable FIFO mode */ const struct stm32_uart_init_s init = { - .baud_rate = U(115200), + .baud_rate = STM32MP_UART_BAUDRATE, .word_length = STM32_UART_WORDLENGTH_9B, .stop_bits = STM32_UART_STOPBITS_1, .parity = STM32_UART_PARITY_EVEN, .hw_flow_control = STM32_UART_HWCONTROL_NONE, .mode = STM32_UART_MODE_TX_RX, - .over_sampling = STM32_UART_OVERSAMPLING_16, .fifo_mode = STM32_UART_FIFOMODE_EN, }; diff --git a/plat/st/common/stm32cubeprogrammer_usb.c b/plat/st/common/stm32cubeprogrammer_usb.c index 19a6bbae8..75e803859 100644 --- a/plat/st/common/stm32cubeprogrammer_usb.c +++ b/plat/st/common/stm32cubeprogrammer_usb.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> #include <errno.h> +#include <string.h> #include <tools_share/firmware_image_package.h> diff --git a/plat/st/common/stm32mp_auth.c b/plat/st/common/stm32mp_auth.c deleted file mode 100644 index 97fbffa2e..000000000 --- a/plat/st/common/stm32mp_auth.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <errno.h> - -#include <common/debug.h> -#include <drivers/io/io_storage.h> -#include <drivers/st/bsec.h> -#include <drivers/st/stm32_hash.h> -#include <lib/xlat_tables/xlat_tables_v2.h> -#include <plat/common/platform.h> - -#include <platform_def.h> - -static const struct stm32mp_auth_ops *auth_ops; - -void stm32mp_init_auth(struct stm32mp_auth_ops *init_ptr) -{ - if ((init_ptr == NULL) || - (init_ptr->check_key == NULL) || - (init_ptr->verify_signature == NULL) || - (stm32_hash_register() != 0)) { - panic(); - } - - auth_ops = init_ptr; -} - -int stm32mp_auth_image(boot_api_image_header_t *header, uintptr_t buffer) -{ - int ret; - uint8_t image_hash[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES]; - uint32_t header_skip_cksum = sizeof(header->magic) + - sizeof(header->image_signature) + - sizeof(header->payload_checksum); - - /* Check Security Status */ - if (!stm32mp_is_closed_device()) { - if (header->option_flags != 0U) { - WARN("Skip signature check (header option)\n"); - return 0; - } - INFO("Check signature on Open device\n"); - } - - if (auth_ops == NULL) { - ERROR("Device doesn't support image authentication\n"); - return -EOPNOTSUPP; - } - - ret = mmap_add_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_BASE, - STM32MP_ROM_SIZE_2MB_ALIGNED, MT_CODE | MT_SECURE); - if (ret != 0) { - return ret; - } - - /* Check Public Key */ - if (auth_ops->check_key(header->ecc_pubk, NULL) != BOOT_API_RETURN_OK) { - ret = -EINVAL; - goto err; - } - - /* Compute end of header hash and payload hash */ - stm32_hash_init(HASH_SHA256); - - ret = stm32_hash_update((uint8_t *)&header->header_version, - sizeof(boot_api_image_header_t) - - header_skip_cksum); - if (ret != 0) { - ERROR("Hash of header failed, %i\n", ret); - goto err; - } - - ret = stm32_hash_final_update((uint8_t *)buffer, - header->image_length, image_hash); - if (ret != 0) { - ERROR("Hash of payload failed\n"); - goto err; - } - - /* Verify signature */ - if (auth_ops->verify_signature(image_hash, header->ecc_pubk, - header->image_signature, - header->ecc_algo_type) != - BOOT_API_RETURN_OK) { - ret = -EINVAL; - } - -err: - mmap_remove_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_SIZE_2MB_ALIGNED); - return ret; -} diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c index d922d3c84..bb56bac75 100644 --- a/plat/st/common/stm32mp_common.c +++ b/plat/st/common/stm32mp_common.c @@ -85,43 +85,6 @@ bool stm32mp_lock_available(void) return (read_sctlr() & c_m_bits) == c_m_bits; } -#if STM32MP_USE_STM32IMAGE -int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer) -{ - uint32_t i; - uint32_t img_checksum = 0U; - - /* - * Check header/payload validity: - * - Header magic - * - Header version - * - Payload checksum - */ - if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) { - ERROR("Header magic\n"); - return -EINVAL; - } - - if ((header->header_version & HEADER_VERSION_MAJOR_MASK) != - (BOOT_API_HEADER_VERSION & HEADER_VERSION_MAJOR_MASK)) { - ERROR("Header version\n"); - return -EINVAL; - } - - for (i = 0U; i < header->image_length; i++) { - img_checksum += *(uint8_t *)(buffer + i); - } - - if (header->payload_checksum != img_checksum) { - ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum, - header->payload_checksum); - return -EINVAL; - } - - return 0; -} -#endif /* STM32MP_USE_STM32IMAGE */ - int stm32mp_map_ddr_non_cacheable(void) { return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, @@ -274,8 +237,11 @@ int stm32mp_uart_console_setup(void) #if STM32MP_EARLY_CONSOLE void stm32mp_setup_early_console(void) { +#if defined(IMAGE_BL2) || STM32MP_RECONFIGURE_CONSOLE plat_crash_console_init(); +#endif set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ); + NOTICE("Early console setup\n"); } #endif /* STM32MP_EARLY_CONSOLE */ diff --git a/plat/st/common/stm32mp_crypto_lib.c b/plat/st/common/stm32mp_crypto_lib.c new file mode 100644 index 000000000..d64424278 --- /dev/null +++ b/plat/st/common/stm32mp_crypto_lib.c @@ -0,0 +1,661 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <endian.h> +#include <errno.h> + +#include <common/debug.h> +#include <drivers/auth/crypto_mod.h> +#include <drivers/io/io_storage.h> +#include <drivers/st/bsec.h> +#include <drivers/st/stm32_hash.h> +#include <drivers/st/stm32_pka.h> +#include <drivers/st/stm32_rng.h> +#include <drivers/st/stm32_saes.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <mbedtls/asn1.h> +#include <mbedtls/md.h> +#include <mbedtls/oid.h> +#include <mbedtls/platform.h> +#include <mbedtls/x509.h> +#include <plat/common/platform.h> +#include <tools_share/firmware_encrypted.h> + +#include <platform_def.h> + +#define CRYPTO_HASH_MAX_SIZE 32U +#define CRYPTO_SIGN_MAX_SIZE 64U +#define CRYPTO_PUBKEY_MAX_SIZE 64U +#define CRYPTO_MAX_TAG_SIZE 16U + +/* brainpoolP256t1 OID is not defined in mbedTLS */ +#define OID_EC_GRP_BP256T1 MBEDTLS_OID_EC_BRAINPOOL_V1 "\x08" + +#if STM32MP_CRYPTO_ROM_LIB +struct stm32mp_auth_ops { + uint32_t (*verify_signature)(uint8_t *hash_in, uint8_t *pubkey_in, + uint8_t *signature, uint32_t ecc_algo); +}; + +static struct stm32mp_auth_ops auth_ops; +#endif + +static void crypto_lib_init(void) +{ + boot_api_context_t *boot_context __maybe_unused; + int ret; + + NOTICE("TRUSTED_BOARD_BOOT support enabled\n"); + + ret = stm32_hash_register(); + if (ret != 0) { + ERROR("HASH init (%d)\n", ret); + panic(); + } + + if (stm32mp_is_closed_device() || stm32mp_is_auth_supported()) { +#if STM32MP_CRYPTO_ROM_LIB + boot_context = (boot_api_context_t *)stm32mp_get_boot_ctx_address(); + auth_ops.verify_signature = boot_context->bootrom_ecdsa_verify_signature; +#else + /* Use hardware peripherals */ + if (stm32_rng_init() != 0) { + panic(); + } + + if (stm32_saes_driver_init() != 0) { + panic(); + } + + if (stm32_pka_init() != 0) { + panic(); + } +#endif + } +} + +int get_plain_pk_from_asn1(void *pk_ptr, unsigned int pk_len, void **plain_pk, + unsigned int *len, int *pk_alg) +{ + int ret; + mbedtls_pk_context mbedtls_pk = {0}; + unsigned char *p, *end; + mbedtls_asn1_buf alg_params = {0}; + mbedtls_asn1_buf alg_oid = {0}; + + *plain_pk = NULL; + *len = 0U; + + /* Parse the public key */ + mbedtls_pk_init(&mbedtls_pk); + p = (unsigned char *)pk_ptr; + end = (unsigned char *)(p + pk_len); + + ret = mbedtls_asn1_get_tag(&p, end, len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return -EINVAL; + } + + end = p + *len; + ret = mbedtls_asn1_get_alg(&p, end, &alg_oid, &alg_params); + if (ret != 0) { + VERBOSE("%s: mbedtls_asn1_get_alg (%d)\n", __func__, ret); + return -EINVAL; + } + + if (pk_alg != NULL) { + if ((strlen(MBEDTLS_OID_EC_GRP_SECP256R1) == alg_params.len) && + (memcmp(MBEDTLS_OID_EC_GRP_SECP256R1, alg_params.p, alg_params.len) == 0)) { + *pk_alg = BOOT_API_ECDSA_ALGO_TYPE_P256NIST; + } else if ((strlen(OID_EC_GRP_BP256T1) == alg_params.len) && + (memcmp(OID_EC_GRP_BP256T1, alg_params.p, alg_params.len) == 0)) { + *pk_alg = BOOT_API_ECDSA_ALGO_TYPE_BRAINPOOL256; + } else { + ERROR("%s: Algorithm is not supported\n", __func__); + return -EINVAL; + } + } + + ret = mbedtls_asn1_get_bitstring_null(&p, end, len); + if (ret != 0) { + VERBOSE("%s: mbedtls_asn1_get_bitstring_null (%d)\n", __func__, ret); + return -EINVAL; + } + + /* We remove the ident (0x04) first byte. */ + if ((*len < 1U) || (p[0] != MBEDTLS_ASN1_OCTET_STRING)) { + VERBOSE("%s: not expected len or tag\n", __func__); + return -EINVAL; + } + + *len = *len - 1U; + *plain_pk = p + 1U; + + return 0; +} + +#if STM32MP_CRYPTO_ROM_LIB +uint32_t verify_signature(uint8_t *hash_in, uint8_t *pubkey_in, + uint8_t *signature, uint32_t ecc_algo) +{ + int ret; + + ret = mmap_add_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_BASE, + STM32MP_ROM_SIZE_2MB_ALIGNED, MT_CODE | MT_SECURE); + if (ret != 0) { + VERBOSE("%s: mmap_add_dynamic_region (%d)\n", __func__, ret); + return CRYPTO_ERR_SIGNATURE; + } + + ret = auth_ops.verify_signature(hash_in, pubkey_in, signature, ecc_algo); + + if (ret != BOOT_API_RETURN_OK) { + VERBOSE("%s: auth_ops.verify_sign (%d)\n", __func__, ret); + ret = CRYPTO_ERR_SIGNATURE; + } else { + ret = 0; + } + + mmap_remove_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_SIZE_2MB_ALIGNED); + + return ret; +} + +int plat_convert_pk(void *full_pk_ptr, unsigned int full_pk_len, + void **hashed_pk_ptr, unsigned int *hashed_pk_len) +{ + return get_plain_pk_from_asn1(full_pk_ptr, full_pk_len, hashed_pk_ptr, hashed_pk_len, NULL); +} +#else /* STM32MP_CRYPTO_ROM_LIB*/ +static uint32_t verify_signature(uint8_t *hash_in, uint8_t *pubkey_in, + uint8_t *signature, uint32_t ecc_algo) +{ + int ret = -1; + enum stm32_pka_ecdsa_curve_id cid; + + switch (ecc_algo) { + case BOOT_API_ECDSA_ALGO_TYPE_P256NIST: +#if PKA_USE_NIST_P256 + cid = PKA_NIST_P256; + ret = 0; +#else + WARN("%s nist_p256 requested but not included\n", __func__); +#endif + break; + case BOOT_API_ECDSA_ALGO_TYPE_BRAINPOOL256: +#if PKA_USE_BRAINPOOL_P256T1 + cid = PKA_BRAINPOOL_P256T1; + ret = 0; +#else + WARN("%s brainpool_p256t1 requested but not included\n", __func__); +#endif + break; + default: + WARN("%s unexpected ecc_algo(%u)\n", __func__, ecc_algo); + break; + } + + if (ret < 0) { + return CRYPTO_ERR_SIGNATURE; + } + + ret = stm32_pka_ecdsa_verif(hash_in, + BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES, + signature, BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES / 2U, + signature + BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES / 2U, + BOOT_API_ECDSA_SIGNATURE_LEN_IN_BYTES / 2U, + pubkey_in, BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES / 2U, + pubkey_in + BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES / 2U, + BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES / 2U, cid); + if (ret < 0) { + return CRYPTO_ERR_SIGNATURE; + } + + return 0; +} + +int plat_convert_pk(void *full_pk_ptr, unsigned int full_pk_len, + void **hashed_pk_ptr, unsigned int *hashed_pk_len) +{ + static uint8_t st_pk[CRYPTO_PUBKEY_MAX_SIZE + sizeof(uint32_t)]; + int ret; + void *plain_pk; + unsigned int len; + int curve_id; + uint32_t cid; + + ret = get_plain_pk_from_asn1(full_pk_ptr, full_pk_len, &plain_pk, &len, &curve_id); + if ((ret != 0) || (len > CRYPTO_PUBKEY_MAX_SIZE)) { + return -EINVAL; + } + + cid = curve_id; /* we want value of curve_id (1 or 2) in a uint32_t */ + + memcpy(st_pk, &cid, sizeof(cid)); + memcpy(st_pk + sizeof(cid), plain_pk, len); + + *hashed_pk_ptr = st_pk; + *hashed_pk_len = len + sizeof(cid); + + return 0; +} +#endif /* STM32MP_CRYPTO_ROM_LIB */ + +static int get_plain_digest_from_asn1(void *digest_ptr, unsigned int digest_len, + uint8_t **out, size_t *out_len, mbedtls_md_type_t *md_alg) +{ + int ret; + mbedtls_asn1_buf hash_oid, params; + size_t len; + unsigned char *p, *end; + + *out = NULL; + *out_len = 0U; + + /* Digest info should be an MBEDTLS_ASN1_SEQUENCE */ + p = (unsigned char *)digest_ptr; + end = p + digest_len; + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return ret; + } + + /* Get the hash algorithm */ + ret = mbedtls_asn1_get_alg(&p, end, &hash_oid, ¶ms); + if (ret != 0) { + return ret; + } + + ret = mbedtls_oid_get_md_alg(&hash_oid, md_alg); + if (ret != 0) { + return ret; + } + + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_OCTET_STRING); + if (ret != 0) { + return ret; + } + + /* Length of hash must match the algorithm's size */ + if (len != BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES) { + return -1; + } + + *out = p; + *out_len = len; + + return 0; +} + +static int crypto_verify_signature(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len) +{ + uint8_t image_hash[CRYPTO_HASH_MAX_SIZE] = {0}; + uint8_t sig[CRYPTO_SIGN_MAX_SIZE]; + uint8_t my_pk[CRYPTO_PUBKEY_MAX_SIZE]; + int ret; + size_t len; + mbedtls_asn1_sequence seq; + mbedtls_asn1_sequence *cur; + unsigned char *p, *end; + int curve_id; + mbedtls_asn1_buf sig_oid, sig_params; + mbedtls_md_type_t md_alg; + mbedtls_pk_type_t pk_alg; + size_t bignum_len = sizeof(sig) / 2U; + unsigned int seq_num = 0U; + + if (!stm32mp_is_closed_device() && !stm32mp_is_auth_supported()) { + return CRYPTO_SUCCESS; + } + + /* Get pointers to signature OID and parameters */ + p = (unsigned char *)sig_alg; + end = (unsigned char *)(p + sig_alg_len); + ret = mbedtls_asn1_get_alg(&p, end, &sig_oid, &sig_params); + if (ret != 0) { + VERBOSE("%s: mbedtls_asn1_get_alg (%d)\n", __func__, ret); + return CRYPTO_ERR_SIGNATURE; + } + + /* Get the actual signature algorithm (MD + PK) */ + ret = mbedtls_oid_get_sig_alg(&sig_oid, &md_alg, &pk_alg); + if (ret != 0) { + VERBOSE("%s: mbedtls_oid_get_sig_alg (%d)\n", __func__, ret); + return CRYPTO_ERR_SIGNATURE; + } + + if ((md_alg != MBEDTLS_MD_SHA256) || (pk_alg != MBEDTLS_PK_ECDSA)) { + VERBOSE("%s: md_alg=%u pk_alg=%u\n", __func__, md_alg, pk_alg); + return CRYPTO_ERR_SIGNATURE; + } + + ret = get_plain_pk_from_asn1(pk_ptr, pk_len, &pk_ptr, &pk_len, &curve_id); + if (ret != 0) { + VERBOSE("%s: get_plain_pk_from_asn1 (%d)\n", __func__, ret); + return CRYPTO_ERR_SIGNATURE; + } + + /* We expect a known pk_len */ + if (pk_len != sizeof(my_pk)) { + VERBOSE("%s: pk_len=%u sizeof(my_pk)=%zu)\n", __func__, pk_len, sizeof(my_pk)); + return CRYPTO_ERR_SIGNATURE; + } + + /* Need to copy as auth_ops.verify_signature + * expects aligned public key. + */ + memcpy(my_pk, pk_ptr, sizeof(my_pk)); + + /* Get the signature (bitstring) */ + p = (unsigned char *)sig_ptr; + end = (unsigned char *)(p + sig_len); + ret = mbedtls_asn1_get_bitstring_null(&p, end, &len); + if (ret != 0) { + VERBOSE("%s: mbedtls_asn1_get_bitstring_null (%d)\n", __func__, ret); + return CRYPTO_ERR_SIGNATURE; + } + + /* Get r and s from sequence */ + ret = mbedtls_asn1_get_sequence_of(&p, end, &seq, MBEDTLS_ASN1_INTEGER); + if (ret != 0) { + VERBOSE("%s: mbedtls_asn1_get_sequence_of (%d)\n", __func__, ret); + return CRYPTO_ERR_SIGNATURE; + } + + /* We expect only 2 integers (r and s) from the sequence */ + if (seq.next->next != NULL) { + cur = seq.next; + mbedtls_asn1_sequence *next; + + VERBOSE("%s: nb seq != 2\n", __func__); + /* Free all the sequences */ + while (cur != NULL) { + next = cur->next; + mbedtls_free(cur); + cur = next; + } + + return CRYPTO_ERR_SIGNATURE; + } + + /* + * ECDSA signatures are composed of a tuple (R,S) where R and S are between 0 and n. + * This means that the R and S can have a maximum of 32 each, but can also be smaller. + * Also seen the integer sequence may (sometime) start with 0x00 as MSB, but we can only + * manage exactly 2*32 bytes, we remove this higher byte if there are not 00, + * we will fail either. + */ + cur = &seq; + memset(sig, 0U, sizeof(sig)); + + while (cur != NULL) { + size_t skip = 0U; + size_t seek = seq_num * bignum_len; + + if (cur->buf.len > bignum_len) { + /* Remove extra 0x00 bytes */ + skip = cur->buf.len - bignum_len; + } else if (cur->buf.len < bignum_len) { + /* Add padding to match HW required size */ + seek += (bignum_len % cur->buf.len); + } + + if (seek + cur->buf.len > sizeof(sig) + skip) { + panic(); + } + + memcpy(sig + seek, cur->buf.p + skip, cur->buf.len - skip); + cur = cur->next; + seq_num++; + } + + /* Need to free allocated 'next' in mbedtls_asn1_get_sequence_of */ + mbedtls_free(seq.next); + + /* Compute hash for the data covered by the signature */ + stm32_hash_init(HASH_SHA256); + + ret = stm32_hash_final_update((uint8_t *)data_ptr, data_len, image_hash); + if (ret != 0) { + VERBOSE("%s: stm32_hash_final_update (%d)\n", __func__, ret); + return CRYPTO_ERR_SIGNATURE; + } + + return verify_signature(image_hash, my_pk, sig, curve_id); +} + +static int crypto_verify_hash(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, + unsigned int digest_info_len) +{ + int ret; + uint8_t calc_hash[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES]; + unsigned char *p; + mbedtls_md_type_t md_alg; + size_t len; + + /* we receive an asn1 encapsulated digest, we flatten it */ + ret = get_plain_digest_from_asn1(digest_info_ptr, + digest_info_len, &p, &len, + &md_alg); + if ((ret != 0) || (md_alg != MBEDTLS_MD_SHA256) || (len != sizeof(calc_hash))) { + return CRYPTO_ERR_HASH; + } + + digest_info_ptr = p; + digest_info_len = len; + + stm32_hash_init(HASH_SHA256); + + ret = stm32_hash_final_update(data_ptr, data_len, calc_hash); + if (ret != 0) { + VERBOSE("%s: hash failed\n", __func__); + return CRYPTO_ERR_HASH; + } + + ret = memcmp(calc_hash, digest_info_ptr, digest_info_len); + if (ret != 0) { + VERBOSE("%s: not expected digest\n", __func__); + ret = CRYPTO_ERR_HASH; + } + + return ret; +} + +#if !defined(DECRYPTION_SUPPORT_none) +static int derive_key(uint8_t *key, size_t *key_len, size_t len, + unsigned int *flags, const uint8_t *img_id, size_t img_id_len) +{ + size_t i, j; + + assert(*key_len >= 32U); + + /* + * Not a real derivation yet + * + * But we expect a 32 bytes key, and OTP is only 16 bytes + * => duplicate. + */ + for (i = 0U, j = len; j < 32U; + i += sizeof(uint32_t), j += sizeof(uint32_t)) { + memcpy(key + j, key + i, sizeof(uint32_t)); + } + + *key_len = 32U; + /* Variable 'key' store a real key */ + *flags = 0U; + + return 0; +} + +int plat_get_enc_key_info(enum fw_enc_status_t fw_enc_status, uint8_t *key, + size_t *key_len, unsigned int *flags, + const uint8_t *img_id, size_t img_id_len) +{ + uint32_t otp_idx; + uint32_t otp_len; + size_t read_len; + size_t i; + + if (fw_enc_status == FW_ENC_WITH_BSSK) { + return -EINVAL; + } + + if (stm32_get_otp_index(ENCKEY_OTP, &otp_idx, &otp_len) != 0) { + VERBOSE("%s: get %s index error\n", __func__, ENCKEY_OTP); + return -EINVAL; + } + + if (otp_len > (*key_len * CHAR_BIT)) { + VERBOSE("%s: length Error otp_len=%u key_len=%u\n", __func__, + otp_len, *key_len * CHAR_BIT); + return -EINVAL; + } + + read_len = otp_len / CHAR_BIT; + assert(read_len % sizeof(uint32_t) == 0); + + for (i = 0U; i < read_len / sizeof(uint32_t); i++) { + uint32_t tmp; + uint32_t otp_val; + + if (stm32_get_otp_value_from_idx(otp_idx + i, &otp_val) != 0) { + zeromem(key, *key_len); + VERBOSE("%s: unable to read from otp\n", __func__); + return -EINVAL; + } + + tmp = bswap32(otp_val); + memcpy(key + i * sizeof(uint32_t), &tmp, sizeof(tmp)); + } + + /* Now we have the OTP values in key till read_len */ + + if (derive_key(key, key_len, read_len, flags, img_id, + img_id_len) != 0) { + zeromem(key, *key_len); + return -EINVAL; + } + + return 0; +} + +static enum stm32_saes_key_selection select_key(unsigned int key_flags) +{ + if ((key_flags & ENC_KEY_IS_IDENTIFIER) != 0U) { + panic(); + } + + /* Use the provided key buffer */ + return STM32_SAES_KEY_SOFT; +} + +static int stm32_decrypt_aes_gcm(void *data, size_t data_len, + const void *key, unsigned int key_len, + unsigned int key_flags, + const void *iv, unsigned int iv_len, + const void *tag, unsigned int tag_len) +{ + int ret; + struct stm32_saes_context ctx; + unsigned char tag_buf[CRYPTO_MAX_TAG_SIZE]; + enum stm32_saes_key_selection key_mode; + unsigned int diff = 0U; + unsigned int i; + + key_mode = select_key(key_flags); + + ret = stm32_saes_init(&ctx, true, STM32_SAES_MODE_GCM, key_mode, key, + key_len, iv, iv_len); + if (ret != 0) { + return CRYPTO_ERR_INIT; + } + + ret = stm32_saes_update_assodata(&ctx, true, NULL, 0U); + if (ret != 0) { + return CRYPTO_ERR_DECRYPTION; + } + + ret = stm32_saes_update_load(&ctx, true, data, data, data_len); + if (ret != 0) { + return CRYPTO_ERR_DECRYPTION; + } + + ret = stm32_saes_final(&ctx, tag_buf, sizeof(tag_buf)); + if (ret != 0) { + return CRYPTO_ERR_DECRYPTION; + } + + /* Check tag in "constant-time" */ + for (i = 0U; i < tag_len; i++) { + diff |= ((const unsigned char *)tag)[i] ^ tag_buf[i]; + } + + if (diff != 0U) { + return CRYPTO_ERR_DECRYPTION; + } + + return CRYPTO_SUCCESS; +} + +/* + * Authenticated decryption of an image + * + */ +static int crypto_auth_decrypt(enum crypto_dec_algo dec_algo, void *data_ptr, size_t len, + const void *key, unsigned int key_len, unsigned int key_flags, + const void *iv, unsigned int iv_len, const void *tag, + unsigned int tag_len) +{ + int rc = -1; + uint32_t real_iv[4]; + + switch (dec_algo) { + case CRYPTO_GCM_DECRYPT: + /* + * GCM expect a Nonce + * The AES IV is the nonce (a uint32_t[3]) + * then a counter (a uint32_t big endian) + * The counter starts at 2. + */ + memcpy(real_iv, iv, iv_len); + real_iv[3] = htobe32(0x2U); + + rc = stm32_decrypt_aes_gcm(data_ptr, len, key, key_len, key_flags, + real_iv, sizeof(real_iv), tag, tag_len); + break; + default: + rc = CRYPTO_ERR_DECRYPTION; + break; + } + + if (rc != 0) { + return rc; + } + + return CRYPTO_SUCCESS; +} + +REGISTER_CRYPTO_LIB("stm32_crypto_lib", + crypto_lib_init, + crypto_verify_signature, + crypto_verify_hash, + crypto_auth_decrypt); + +#else /* No decryption support */ +REGISTER_CRYPTO_LIB("stm32_crypto_lib", + crypto_lib_init, + crypto_verify_signature, + crypto_verify_hash, + NULL); + +#endif diff --git a/plat/st/common/stm32mp_fconf_io.c b/plat/st/common/stm32mp_fconf_io.c index ca7195854..0b6cc789c 100644 --- a/plat/st/common/stm32mp_fconf_io.c +++ b/plat/st/common/stm32mp_fconf_io.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -42,6 +42,14 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { .img_type_guid = STM32MP_FIP_GUID, .check = open_storage }, +#ifndef DECRYPTION_SUPPORT_none + [ENC_IMAGE_ID] = { + .dev_handle = &fip_dev_handle, + .image_spec = (uintptr_t)NULL, + .img_type_guid = NULL_GUID, + .check = open_fip + }, +#endif #if STM32MP_SDMMC || STM32MP_EMMC [GPT_IMAGE_ID] = { .dev_handle = &storage_dev_handle, @@ -66,7 +74,16 @@ struct plat_io_policy policies[MAX_NUMBER_IDS] = { #endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */ }; -#define FCONF_ST_IO_UUID_NUMBER U(8) +#define DEFAULT_UUID_NUMBER U(7) + +#if TRUSTED_BOARD_BOOT +#define TBBR_UUID_NUMBER U(6) +#else +#define TBBR_UUID_NUMBER U(0) +#endif + +#define FCONF_ST_IO_UUID_NUMBER (DEFAULT_UUID_NUMBER + \ + TBBR_UUID_NUMBER) static io_uuid_spec_t fconf_stm32mp_uuids[FCONF_ST_IO_UUID_NUMBER]; static OBJECT_POOL_ARRAY(fconf_stm32mp_uuids_pool, fconf_stm32mp_uuids); @@ -85,7 +102,14 @@ static const struct policies_load_info load_info[FCONF_ST_IO_UUID_NUMBER] = { {BL33_IMAGE_ID, "bl33_uuid"}, {HW_CONFIG_ID, "hw_cfg_uuid"}, {TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"}, - {NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"}, +#if TRUSTED_BOARD_BOOT + {STM32MP_CONFIG_CERT_ID, "stm32mp_cfg_cert_uuid"}, + {TRUSTED_KEY_CERT_ID, "t_key_cert_uuid"}, + {TRUSTED_OS_FW_KEY_CERT_ID, "tos_fw_key_cert_uuid"}, + {NON_TRUSTED_FW_KEY_CERT_ID, "nt_fw_key_cert_uuid"}, + {TRUSTED_OS_FW_CONTENT_CERT_ID, "tos_fw_content_cert_uuid"}, + {NON_TRUSTED_FW_CONTENT_CERT_ID, "nt_fw_content_cert_uuid"}, +#endif /* TRUSTED_BOARD_BOOT */ }; int fconf_populate_stm32mp_io_policies(uintptr_t config) @@ -135,8 +159,20 @@ int fconf_populate_stm32mp_io_policies(uintptr_t config) uuid_ptr->uuid = uuid_helper.uuid_struct; policies[load_info[i].image_id].image_spec = (uintptr_t)uuid_ptr; - policies[load_info[i].image_id].dev_handle = &fip_dev_handle; - policies[load_info[i].image_id].check = open_fip; + switch (load_info[i].image_id) { +#if ENCRYPT_BL32 && !defined(DECRYPTION_SUPPORT_none) + case BL32_IMAGE_ID: + case BL32_EXTRA1_IMAGE_ID: + case BL32_EXTRA2_IMAGE_ID: + policies[load_info[i].image_id].dev_handle = &enc_dev_handle; + policies[load_info[i].image_id].check = open_enc_fip; + break; +#endif + default: + policies[load_info[i].image_id].dev_handle = &fip_dev_handle; + policies[load_info[i].image_id].check = open_fip; + break; + } } return 0; diff --git a/plat/st/common/stm32mp_trusted_boot.c b/plat/st/common/stm32mp_trusted_boot.c new file mode 100644 index 000000000..051d6fcfb --- /dev/null +++ b/plat/st/common/stm32mp_trusted_boot.c @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <endian.h> +#include <errno.h> +#include <limits.h> + +#include <common/debug.h> +#include <common/tbbr/cot_def.h> +#include <drivers/st/stm32_hash.h> +#include <lib/fconf/fconf.h> +#include <lib/fconf/fconf_dyn_cfg_getter.h> +#include <lib/fconf/fconf_tbbr_getter.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> + +#include <boot_api.h> +#include <platform_def.h> + +#define HEADER_AND_EXT_TOTAL_SIZE 512 + +static uint8_t der_sha256_header[] = {0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20}; +static uint8_t root_pk_hash[HASH_DER_LEN]; + +static int copy_hash_from_otp(const char *otp_name, uint8_t *hash, size_t len) +{ + uint32_t otp_idx; + uint32_t otp_len; + size_t i; + bool valid = false; + + assert(len % sizeof(uint32_t) == 0); + + if (stm32_get_otp_index(otp_name, &otp_idx, &otp_len) != 0) { + VERBOSE("%s: get %s index error\n", __func__, otp_name); + return -EINVAL; + } + if (otp_len != (len * CHAR_BIT)) { + VERBOSE("%s: length Error\n", __func__); + return -EINVAL; + } + + for (i = 0U; i < len / sizeof(uint32_t); i++) { + uint32_t tmp; + uint32_t otp_val; + uint32_t first; + + if (stm32_get_otp_value_from_idx(otp_idx + i, &otp_val) != 0) { + VERBOSE("%s: unable to read from otp\n", __func__); + return -EINVAL; + } + + tmp = bswap32(otp_val); + memcpy(hash + i * sizeof(uint32_t), &tmp, sizeof(tmp)); + + if (i == 0U) { + first = tmp; + } + + /* + * Check if key hash values in OTP are 0 or 0xFFFFFFFFF + * programmed : Invalid Key + */ + if (!stm32mp_is_closed_device() && !valid) { + if ((tmp != 0U) && (tmp != 0xFFFFFFFFU) && (tmp != first)) { + valid = true; + } + } + } + + if (!stm32mp_is_closed_device() && !valid) { + return 0; + } + + return len; +} + +#if STM32_HEADER_VERSION_MAJOR == 1 +static int get_rotpk_hash(void *cookie, uint8_t *hash, size_t len) +{ + if (cookie != NULL) { + return -EINVAL; + } + + return copy_hash_from_otp(PKH_OTP, hash, len); +} +#else +static int get_rotpk_hash(void *cookie, uint8_t *hash, size_t len) +{ + int ret; + uint32_t pk_idx = 0U; + uint8_t calc_hash[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES]; + uint8_t otp_hash[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES]; + boot_api_image_header_t *hdr = (boot_api_image_header_t *)(SRAM3_BASE + SRAM3_SIZE - + HEADER_AND_EXT_TOTAL_SIZE); + boot_extension_header_t *ext_header = (boot_extension_header_t *)hdr->ext_header; + boot_ext_header_params_authentication_t *param; + + if (cookie != NULL) { + return -EINVAL; + } + + if (hdr->header_version != BOOT_API_HEADER_VERSION) { + VERBOSE("%s: unexpected header_version\n", __func__); + return -EINVAL; + } + + param = (boot_ext_header_params_authentication_t *)ext_header->params; + + pk_idx = param->pk_idx; + + stm32_hash_init(HASH_SHA256); + ret = stm32_hash_final_update((uint8_t *)param->pk_hashes, + param->nb_pk * sizeof(boot_api_sha256_t), calc_hash); + if (ret != 0) { + VERBOSE("%s: hash failed\n", __func__); + return -EINVAL; + } + + ret = copy_hash_from_otp(PKH_OTP, otp_hash, len); + if (ret < 0) { + return -EINVAL; + } + + if (ret != 0) { + ret = memcmp(calc_hash, otp_hash, sizeof(calc_hash)); + if (ret != 0) { + VERBOSE("%s: not expected digest\n", __func__); + return -EINVAL; + } + + ret = sizeof(otp_hash); + } + + memcpy(hash, param->pk_hashes[pk_idx], sizeof(otp_hash)); + + return ret; +} +#endif + +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + size_t start_copy_idx = 0U; + int res; + + memcpy(root_pk_hash, der_sha256_header, sizeof(der_sha256_header)); + start_copy_idx = sizeof(der_sha256_header); + + res = get_rotpk_hash(cookie, root_pk_hash + start_copy_idx, + BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES); + if (res < 0) { + return -EINVAL; + } + + *key_len = HASH_DER_LEN; + *key_ptr = &root_pk_hash; + *flags = ROTPK_IS_HASH; + + if ((res == 0) && !stm32mp_is_closed_device()) { + *flags |= ROTPK_NOT_DEPLOYED; + } + + return 0; +} + +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + *nv_ctr = mmio_read_32(TAMP_BASE + TAMP_COUNTR); + + return 0; +} + +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + while (mmio_read_32(TAMP_BASE + TAMP_COUNTR) != nv_ctr) { + mmio_write_32(TAMP_BASE + TAMP_COUNTR, 1U); + } + + return 0; +} + +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + assert(heap_addr != NULL); + assert(heap_size != NULL); + +#if STM32MP_USE_EXTERNAL_HEAP + /* Retrieve the already allocated heap's info from DTB */ + *heap_addr = FCONF_GET_PROPERTY(tbbr, dyn_config, mbedtls_heap_addr); + *heap_size = FCONF_GET_PROPERTY(tbbr, dyn_config, mbedtls_heap_size); + + /* We expect heap already statically mapped */ + + return 0; +#else + return get_mbedtls_heap_helper(heap_addr, heap_size); +#endif +} diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index 6f5fcc78c..4f04a6f03 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -17,6 +17,7 @@ #include <drivers/st/bsec.h> #include <drivers/st/regulator_fixed.h> #include <drivers/st/stm32_iwdg.h> +#include <drivers/st/stm32_rng.h> #include <drivers/st/stm32_uart.h> #include <drivers/st/stm32mp1_clk.h> #include <drivers/st/stm32mp1_pwr.h> @@ -47,10 +48,6 @@ static const char debug_msg[] = { }; #endif -#if STM32MP15 -static struct stm32mp_auth_ops stm32mp1_auth_ops; -#endif - static void print_reset_reason(void) { uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); @@ -167,14 +164,6 @@ void bl2_platform_setup(void) ERROR("DDR mapping: error %d\n", ret); panic(); } - -#if STM32MP_USE_STM32IMAGE -#ifdef AARCH32_SP_OPTEE - INFO("BL2 runs OP-TEE setup\n"); -#else - INFO("BL2 runs SP_MIN setup\n"); -#endif -#endif /* STM32MP_USE_STM32IMAGE */ } #if STM32MP15 @@ -229,19 +218,6 @@ void bl2_el3_plat_arch_setup(void) BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_SECURE); -#if STM32MP_USE_STM32IMAGE -#ifdef AARCH32_SP_OPTEE - mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, - STM32MP_OPTEE_SIZE, - MT_MEMORY | MT_RW | MT_SECURE); -#else - /* Prevent corruption of preloaded BL32 */ - mmap_add_region(BL32_BASE, BL32_BASE, - BL32_LIMIT - BL32_BASE, - MT_RO_DATA | MT_SECURE); -#endif -#endif /* STM32MP_USE_STM32IMAGE */ - /* Prevent corruption of preloaded Device Tree */ mmap_add_region(DTB_BASE, DTB_BASE, DTB_LIMIT - DTB_BASE, @@ -316,6 +292,8 @@ void bl2_el3_plat_arch_setup(void) stm32_save_boot_interface(boot_context->boot_interface_selected, boot_context->boot_interface_instance); + stm32_save_boot_auth(boot_context->auth_status, + boot_context->boot_partition_used_toboot); #if STM32MP_USB_PROGRAMMER && STM32MP15 /* Deconfigure all UART RX pins configured by ROM code */ @@ -342,6 +320,14 @@ void bl2_el3_plat_arch_setup(void) } skip_console_init: +#if !TRUSTED_BOARD_BOOT + if (stm32mp_is_closed_device()) { + /* Closed chip mandates authentication */ + ERROR("Secure chip: TRUSTED_BOARD_BOOT must be enabled\n"); + panic(); + } +#endif + if (fixed_regulator_register() != 0) { panic(); } @@ -373,14 +359,9 @@ skip_console_init: } } -#if STM32MP15 - if (stm32mp_is_auth_supported()) { - stm32mp1_auth_ops.check_key = - boot_context->bootrom_ecdsa_check_key; - stm32mp1_auth_ops.verify_signature = - boot_context->bootrom_ecdsa_verify_signature; - - stm32mp_init_auth(&stm32mp1_auth_ops); +#if STM32MP13 + if (stm32_rng_init() != 0) { + panic(); } #endif @@ -394,9 +375,7 @@ skip_console_init: stm32mp1_syscfg_enable_io_compensation_finish(); -#if !STM32MP_USE_STM32IMAGE fconf_populate("TB_FW", STM32MP_DTB_BASE); -#endif /* !STM32MP_USE_STM32IMAGE */ stm32mp_io_setup(); } @@ -412,7 +391,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) bl_mem_params_node_t *bl32_mem_params; bl_mem_params_node_t *pager_mem_params __unused; bl_mem_params_node_t *paged_mem_params __unused; -#if !STM32MP_USE_STM32IMAGE const struct dyn_cfg_dtb_info_t *config_info; bl_mem_params_node_t *tos_fw_mem_params; unsigned int i; @@ -424,12 +402,10 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) HW_CONFIG_ID, TOS_FW_CONFIG_ID, }; -#endif /* !STM32MP_USE_STM32IMAGE */ assert(bl_mem_params != NULL); switch (image_id) { -#if !STM32MP_USE_STM32IMAGE case FW_CONFIG_ID: /* Set global DTB info for fixed fw_config information */ set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE, @@ -470,11 +446,13 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) /* Init base and size for pager if exist */ paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); - assert(paged_mem_params != NULL); - paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + - (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - - STM32MP_DDR_SHMEM_SIZE); - paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; + if (paged_mem_params != NULL) { + paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + + (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - + STM32MP_DDR_SHMEM_SIZE); + paged_mem_params->image_info.image_max_size = + STM32MP_DDR_S_SIZE; + } break; case BL33_IMAGE_ID: @@ -490,48 +468,45 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) } } break; -#endif /* !STM32MP_USE_STM32IMAGE */ case BL32_IMAGE_ID: if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { + image_info_t *paged_image_info = NULL; + /* BL32 is OP-TEE header */ bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); - paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); - assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); - -#if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) - /* Set OP-TEE extra image load areas at run-time */ - pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; - pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; + assert(pager_mem_params != NULL); - paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + - dt_get_ddr_size() - - STM32MP_DDR_S_SIZE - - STM32MP_DDR_SHMEM_SIZE; - paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; -#endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ + paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); + if (paged_mem_params != NULL) { + paged_image_info = &paged_mem_params->image_info; + } err = parse_optee_header(&bl_mem_params->ep_info, &pager_mem_params->image_info, - &paged_mem_params->image_info); - if (err) { + paged_image_info); + if (err != 0) { ERROR("OPTEE header parse error.\n"); panic(); } /* Set optee boot info from parsed header data */ - bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; - bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ - bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ + if (paged_mem_params != NULL) { + bl_mem_params->ep_info.args.arg0 = + paged_mem_params->image_info.image_base; + } else { + bl_mem_params->ep_info.args.arg0 = 0U; + } + + bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */ + bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */ } else { -#if !STM32MP_USE_STM32IMAGE bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); assert(tos_fw_mem_params != NULL); bl_mem_params->image_info.image_max_size += tos_fw_mem_params->image_info.image_max_size; -#endif /* !STM32MP_USE_STM32IMAGE */ bl_mem_params->ep_info.args.arg0 = 0; } break; @@ -540,9 +515,9 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); assert(bl32_mem_params != NULL); bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; -#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT +#if PSA_FWU_SUPPORT stm32mp1_fwu_set_boot_idx(); -#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ +#endif /* PSA_FWU_SUPPORT */ break; default: diff --git a/plat/st/stm32mp1/cert_create_tbbr.mk b/plat/st/stm32mp1/cert_create_tbbr.mk new file mode 100644 index 000000000..5b1a3ed94 --- /dev/null +++ b/plat/st/stm32mp1/cert_create_tbbr.mk @@ -0,0 +1,19 @@ +# +# Copyright (c) 2022, STMicroelectronics - All Rights Reserved +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Override TBBR Cert to update generic certificate + +$(eval $(call add_define,PDEF_CERTS)) + +PLAT_INCLUDE += -I${PLAT_DIR}include + +src/stm32mp1_tbb_cert.o: ${PLAT_DIR}stm32mp1_tbb_cert.c + ${Q}${HOSTCC} -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@ + +PLAT_OBJECTS = src/stm32mp1_tbb_cert.o + +OBJECTS += $(PLAT_OBJECTS) + diff --git a/plat/st/stm32mp1/include/boot_api.h b/plat/st/stm32mp1/include/boot_api.h index 763841823..1054609a1 100644 --- a/plat/st/stm32mp1/include/boot_api.h +++ b/plat/st/stm32mp1/include/boot_api.h @@ -232,21 +232,14 @@ typedef struct { #if STM32MP15 /* * Pointers to bootROM External Secure Services - * - ECDSA check key * - ECDSA verify signature - * - ECDSA verify signature and go */ - uint32_t (*bootrom_ecdsa_check_key)(uint8_t *pubkey_in, - uint8_t *pubkey_out); + uint32_t reserved3; uint32_t (*bootrom_ecdsa_verify_signature)(uint8_t *hash_in, uint8_t *pubkey_in, uint8_t *signature, uint32_t ecc_algo); - uint32_t (*bootrom_ecdsa_verify_and_go)(uint8_t *hash_in, - uint8_t *pub_key_in, - uint8_t *signature, - uint32_t ecc_algo, - uint32_t *entry_in); + uint32_t reserved4; #endif /* * Information specific to an SD boot @@ -340,6 +333,8 @@ typedef struct { uint32_t binary_type; /* Pad up to 128 byte total size */ uint8_t pad[16]; + /* Followed by extension header */ + uint8_t ext_header[]; #endif #if STM32MP15 /* @@ -370,4 +365,45 @@ typedef struct { #endif } __packed boot_api_image_header_t; +typedef uint8_t boot_api_sha256_t[BOOT_API_SHA256_DIGEST_SIZE_IN_BYTES]; + +typedef struct { + /* Extension header type: + * BOOT_API_FSBL_DECRYPTION_HEADER_MAGIC_NB or + * BOOT_API_AUTHENTICATION_HEADER_MAGIC_NB + * BOOT_API_PADDING_HEADER_MAGIC_NB + */ + uint32_t type; + /* Extension header len in byte */ + uint32_t len; + /* parameters of this extension */ + uint8_t params[]; +} __packed boot_extension_header_t; + +typedef struct { + /* Idx of ECDSA public key to be used in table */ + uint32_t pk_idx; + /* Number of ECDSA public key in table */ + uint32_t nb_pk; + /* + * Type of ECC algorithm to use : + * value 1 : for P-256 NIST algorithm + * value 2 : for Brainpool 256 algorithm + * See definitions 'BOOT_API_ECDSA_ALGO_TYPE_XXX' above. + */ + uint32_t ecc_algo_type; + /* ECDSA public key to be used to check signature. */ + uint8_t ecc_pubk[BOOT_API_ECDSA_PUB_KEY_LEN_IN_BYTES]; + /* table of Hash of Algo+ECDSA public key */ + boot_api_sha256_t pk_hashes[]; +} __packed boot_ext_header_params_authentication_t; + +typedef struct { + /* Size of encryption key (128 or 256) */ + uint32_t key_size; + uint32_t derivation_cont; + /* 128 msb bits of plain payload SHA256 */ + uint32_t hash[4]; +} __packed boot_ext_header_params_encrypted_fsbl_t; + #endif /* BOOT_API_H */ diff --git a/plat/st/stm32mp1/include/plat_def_fip_uuid.h b/plat/st/stm32mp1/include/plat_def_fip_uuid.h new file mode 100644 index 000000000..e5fbc2dfc --- /dev/null +++ b/plat/st/stm32mp1/include/plat_def_fip_uuid.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DEF_FIP_UUID_H +#define PLAT_DEF_FIP_UUID_H + +#define UUID_STM32MP_CONFIG_CERT \ + {{0x50, 0x1d, 0x8d, 0xd2}, {0x8b, 0xce}, {0x49, 0xa5}, 0x84, 0xeb, \ + {0x55, 0x9a, 0x9f, 0x2e, 0xae, 0xaf} } +#endif /* PLAT_DEF_FIP_UUID_H */ + diff --git a/plat/st/stm32mp1/include/plat_tbbr_img_def.h b/plat/st/stm32mp1/include/plat_tbbr_img_def.h new file mode 100644 index 000000000..984aae85b --- /dev/null +++ b/plat/st/stm32mp1/include/plat_tbbr_img_def.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef STM32MP1_IMG_DEF_H +#define STM32MP1_IMG_DEF_H + +#include <export/common/tbbr/tbbr_img_def_exp.h> + +/* Undef the existing values */ +#undef BL32_EXTRA1_IMAGE_ID +#undef BL32_EXTRA2_IMAGE_ID +#undef TOS_FW_CONFIG_ID +#undef TRUSTED_BOOT_FW_CERT_ID +#undef FWU_METADATA_IMAGE_ID +#undef BKUP_FWU_METADATA_IMAGE_ID +#undef FW_CONFIG_ID +#undef HW_CONFIG_ID +#undef GPT_IMAGE_ID +#undef ENC_IMAGE_ID + +/* Define the STM32MP1 used ID */ +#define FW_CONFIG_ID U(1) +#define HW_CONFIG_ID U(2) +#define GPT_IMAGE_ID U(3) +#define ENC_IMAGE_ID U(6) +#define BL32_EXTRA1_IMAGE_ID U(8) +#define BL32_EXTRA2_IMAGE_ID U(9) +#define FWU_METADATA_IMAGE_ID U(12) +#define BKUP_FWU_METADATA_IMAGE_ID U(13) +#define TOS_FW_CONFIG_ID U(16) +#define STM32MP_CONFIG_CERT_ID U(17) + +/* Increase the MAX_NUMBER_IDS to match the authentication pool required */ +#define MAX_NUMBER_IDS U(19) + +#endif /* STM32MP1_IMG_DEF_H */ diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h index 8ecb4c3e4..61b847f6a 100644 --- a/plat/st/stm32mp1/include/platform_def.h +++ b/plat/st/stm32mp1/include/platform_def.h @@ -25,26 +25,10 @@ #define PLATFORM_STACK_SIZE 0xC00 #endif -#if STM32MP_USE_STM32IMAGE -#ifdef AARCH32_SP_OPTEE -#define OPTEE_HEADER_IMAGE_NAME "teeh" -#define OPTEE_CORE_IMAGE_NAME "teex" -#define OPTEE_PAGED_IMAGE_NAME "teed" -#define OPTEE_HEADER_BINARY_TYPE U(0x20) -#define OPTEE_CORE_BINARY_TYPE U(0x21) -#define OPTEE_PAGED_BINARY_TYPE U(0x22) -#endif - -/* SSBL = second stage boot loader */ -#define BL33_IMAGE_NAME "ssbl" -#define BL33_BINARY_TYPE U(0x0) -#else /* STM32MP_USE_STM32IMAGE */ #define FIP_IMAGE_NAME "fip" #define METADATA_PART_1 "metadata1" #define METADATA_PART_2 "metadata2" -#endif /* STM32MP_USE_STM32IMAGE */ - #define STM32MP_PRIMARY_CPU U(0x0) #define STM32MP_SECONDARY_CPU U(0x1) @@ -81,7 +65,7 @@ /******************************************************************************* * BL32 specific defines. ******************************************************************************/ -#if STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) +#if defined(IMAGE_BL32) #if ENABLE_PIE #define BL32_BASE 0 #define BL32_LIMIT STM32MP_BL32_SIZE @@ -90,7 +74,7 @@ #define BL32_LIMIT (STM32MP_BL32_BASE + \ STM32MP_BL32_SIZE) #endif -#endif /* STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) */ +#endif /* defined(IMAGE_BL32) */ /******************************************************************************* * BL33 specific defines. @@ -103,8 +87,7 @@ #define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE /* Needed by STM32CubeProgrammer support */ -#define DWL_BUFFER_BASE (STM32MP_DDR_BASE + U(0x08000000)) -#define DWL_BUFFER_SIZE U(0x08000000) +#define DWL_BUFFER_SIZE U(0x01000000) /* * SSBL offset in case it's stored in eMMC boot partition. diff --git a/plat/st/stm32mp1/include/stm32mp1_mbedtls_config.h b/plat/st/stm32mp1/include/stm32mp1_mbedtls_config.h new file mode 100644 index 000000000..2f07621c3 --- /dev/null +++ b/plat/st/stm32mp1/include/stm32mp1_mbedtls_config.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +/* + * Key algorithms currently supported on mbed TLS libraries + */ +#define TF_MBEDTLS_USE_RSA 0 +#define TF_MBEDTLS_USE_ECDSA 1 + +/* + * Hash algorithms currently supported on mbed TLS libraries + */ +#define TF_MBEDTLS_SHA256 1 +#define TF_MBEDTLS_SHA384 2 +#define TF_MBEDTLS_SHA512 3 + +/* + * Configuration file to build mbed TLS with the required features for + * Trusted Boot + */ + +#define MBEDTLS_PLATFORM_MEMORY +#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS +/* Prevent mbed TLS from using snprintf so that it can use tf_snprintf. */ +#define MBEDTLS_PLATFORM_SNPRINTF_ALT + +#define MBEDTLS_PKCS1_V21 + +#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION +#define MBEDTLS_X509_CHECK_KEY_USAGE +#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE + +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_ASN1_WRITE_C + +#define MBEDTLS_BASE64_C +#define MBEDTLS_BIGNUM_C + +#define MBEDTLS_ERROR_C +#define MBEDTLS_MD_C + +#define MBEDTLS_MEMORY_BUFFER_ALLOC_C +#define MBEDTLS_OID_C + +#define MBEDTLS_PK_C +#define MBEDTLS_PK_PARSE_C +#define MBEDTLS_PK_WRITE_C + +#define MBEDTLS_PLATFORM_C + +#if TF_MBEDTLS_USE_ECDSA +#define MBEDTLS_ECDSA_C +#define MBEDTLS_ECP_C +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECP_NO_INTERNAL_RNG +#endif +#if TF_MBEDTLS_USE_RSA +#define MBEDTLS_RSA_C +#define MBEDTLS_X509_RSASSA_PSS_SUPPORT +#endif + +#define MBEDTLS_SHA256_C +#if (TF_MBEDTLS_HASH_ALG_ID != TF_MBEDTLS_SHA256) +#define MBEDTLS_SHA512_C +#endif + +#define MBEDTLS_VERSION_C + +#define MBEDTLS_X509_USE_C +#define MBEDTLS_X509_CRT_PARSE_C + +#if TF_MBEDTLS_USE_AES_GCM +#define MBEDTLS_AES_C +#define MBEDTLS_CIPHER_C +#define MBEDTLS_GCM_C +#endif + +/* MPI / BIGNUM options */ +#define MBEDTLS_MPI_WINDOW_SIZE 2 + +#if TF_MBEDTLS_USE_RSA +#if TF_MBEDTLS_KEY_SIZE <= 2048 +#define MBEDTLS_MPI_MAX_SIZE 256 +#else +#define MBEDTLS_MPI_MAX_SIZE 512 +#endif +#else +#define MBEDTLS_MPI_MAX_SIZE 256 +#endif + +/* Memory buffer allocator options */ +#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8 + +/* + * Prevent the use of 128-bit division which + * creates dependency on external libraries. + */ +#define MBEDTLS_NO_UDBL_DIVISION + +#ifndef __ASSEMBLER__ +/* System headers required to build mbed TLS with the current configuration */ +#include <stdlib.h> +#include <mbedtls/check_config.h> +#endif + +/* + * Mbed TLS heap size is smal as we only use the asn1 + * parsing functions + * digest, signature and crypto algorithm are done by + * other library. + */ + +#define TF_MBEDTLS_HEAP_SIZE U(5120) +#endif /* MBEDTLS_CONFIG_H */ diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h index 23934e92f..21ef60d0a 100644 --- a/plat/st/stm32mp1/include/stm32mp1_private.h +++ b/plat/st/stm32mp1/include/stm32mp1_private.h @@ -34,9 +34,5 @@ static inline void stm32mp1_syscfg_boot_mode_disable(void){} void stm32mp1_deconfigure_uart_pins(void); -#if STM32MP_USE_STM32IMAGE -uint32_t stm32mp_get_ddr_ns_size(void); -#endif /* STM32MP_USE_STM32IMAGE */ - void stm32mp1_init_scmi_server(void); #endif /* STM32MP1_PRIVATE_H */ diff --git a/plat/st/stm32mp1/include/tbbr/stm32mp1_tbb_cert.h b/plat/st/stm32mp1/include/tbbr/stm32mp1_tbb_cert.h new file mode 100644 index 000000000..2cc1e19e4 --- /dev/null +++ b/plat/st/stm32mp1/include/tbbr/stm32mp1_tbb_cert.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_TBB_CERT_H +#define STM32MP1_TBB_CERT_H + +#include <tbbr/tbb_cert.h> + +/* + * Enumerate the certificates that are used to establish the chain of trust + */ +enum { + STM32MP_CONFIG_CERT = FWU_CERT + 1 +}; + +#endif /* STM32MP1_TBB_CERT_H */ diff --git a/plat/st/stm32mp1/plat_bl2_mem_params_desc.c b/plat/st/stm32mp1/plat_bl2_mem_params_desc.c index 7963c4a97..9ca09307f 100644 --- a/plat/st/stm32mp1/plat_bl2_mem_params_desc.c +++ b/plat/st/stm32mp1/plat_bl2_mem_params_desc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -68,6 +68,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { .next_handoff_image_id = INVALID_IMAGE_ID, }, +#if STM32MP15 /* Fill BL32 external 2 image related information */ { .image_id = BL32_EXTRA2_IMAGE_ID, @@ -82,6 +83,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { .next_handoff_image_id = INVALID_IMAGE_ID, }, +#endif /* Fill HW_CONFIG related information if it exists */ { diff --git a/plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c b/plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c deleted file mode 100644 index 4fce55a9e..000000000 --- a/plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <common/bl_common.h> -#include <common/desc_image_load.h> -#include <plat/common/platform.h> - -#include <platform_def.h> - -/******************************************************************************* - * Following descriptor provides BL image/ep information that gets used - * by BL2 to load the images and also subset of this information is - * passed to next BL image. The image loading sequence is managed by - * populating the images in required loading order. The image execution - * sequence is managed by populating the `next_handoff_image_id` with - * the next executable image id. - ******************************************************************************/ -static bl_mem_params_node_t bl2_mem_params_descs[] = { - /* Fill BL32 related information */ - { - .image_id = BL32_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - - /* Updated at runtime if OP-TEE is loaded */ - .ep_info.pc = STM32MP_BL32_BASE, - - .ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, - SPSR_E_LITTLE, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP), - - /* Updated at runtime if OP-TEE is loaded */ - .image_info.image_base = STM32MP_BL32_BASE, - .image_info.image_max_size = STM32MP_BL32_SIZE, - - .next_handoff_image_id = BL33_IMAGE_ID, - }, - -#if defined(AARCH32_SP_OPTEE) - /* Fill BL32 external 1 image related information */ - { - .image_id = BL32_EXTRA1_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_SKIP_LOADING), - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, - /* Fill BL32 external 2 image related information */ - { - .image_id = BL32_EXTRA2_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_SKIP_LOADING), - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -#endif /* AARCH32_SP_OPTEE */ - - /* Fill BL33 related information */ - { - .image_id = BL33_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - NON_SECURE | EXECUTABLE), - - .ep_info.pc = PLAT_STM32MP_NS_IMAGE_OFFSET, - .ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, - SPSR_E_LITTLE, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0U), - - .image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET, - .image_info.image_max_size = STM32MP_DDR_MAX_SIZE - - (PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_DDR_BASE), - - .next_handoff_image_id = INVALID_IMAGE_ID, - } -}; - -REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/st/stm32mp1/plat_def_uuid_config.c b/plat/st/stm32mp1/plat_def_uuid_config.c new file mode 100644 index 000000000..efaf56701 --- /dev/null +++ b/plat/st/stm32mp1/plat_def_uuid_config.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <firmware_image_package.h> + +#include "tbbr_config.h" + +toc_entry_t plat_def_toc_entries[] = { + { + .name = "STM32MP CONFIG CERT", + .uuid = UUID_STM32MP_CONFIG_CERT, + .cmdline_name = "stm32mp-cfg-cert" + } +}; + diff --git a/plat/st/stm32mp1/plat_fiptool.mk b/plat/st/stm32mp1/plat_fiptool.mk new file mode 100644 index 000000000..00570c2b3 --- /dev/null +++ b/plat/st/stm32mp1/plat_fiptool.mk @@ -0,0 +1,25 @@ +# +# Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Name of the platform defined source file name, +# which contains platform defined UUID entries populated +# in the plat_def_toc_entries[]. +PLAT_DEF_UUID_FILE_NAME := plat_def_uuid_config + +INCLUDE_PATHS += -I${PLAT_DIR}/include -I./ + +PLAT_DEF_UUID := yes + +ifeq (${PLAT_DEF_UUID},yes) +HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID + +${PLAT_DEF_UUID_FILE_NAME}.o: ${PLAT_DIR}${PLAT_DEF_UUID_FILE_NAME}.c + ${HOSTCC} -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@ + +PLAT_OBJECTS += ${PLAT_DEF_UUID_FILE_NAME}.o +endif + +OBJECTS += ${PLAT_OBJECTS} diff --git a/plat/st/stm32mp1/plat_image_load.c b/plat/st/stm32mp1/plat_image_load.c index f68eb3869..c4048fc08 100644 --- a/plat/st/stm32mp1/plat_image_load.c +++ b/plat/st/stm32mp1/plat_image_load.c @@ -4,12 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include <assert.h> - #include <common/desc_image_load.h> -#include <plat/common/platform.h> - -#include <platform_def.h> /******************************************************************************* * This function flushes the data structures so that they are visible @@ -25,17 +20,6 @@ void plat_flush_next_bl_params(void) ******************************************************************************/ bl_load_info_t *plat_get_bl_image_load_info(void) { -#if STM32MP_USE_STM32IMAGE - bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID); - uint32_t ddr_ns_size = stm32mp_get_ddr_ns_size(); - - assert(bl33 != NULL); - - /* Max size is non-secure DDR end address minus image_base */ - bl33->image_info.image_max_size = STM32MP_DDR_BASE + ddr_ns_size - - bl33->image_info.image_base; -#endif /* STM32MP_USE_STM32IMAGE */ - return get_bl_load_info_from_mem_params_desc(); } diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index 127e3183b..7eecf3040 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -10,12 +10,14 @@ BL2_AT_EL3 := 1 USE_COHERENT_MEM := 0 STM32MP_EARLY_CONSOLE ?= 0 +STM32MP_RECONFIGURE_CONSOLE ?= 0 STM32MP_UART_BAUDRATE ?= 115200 -# Allow TF-A to concatenate BL2 & BL32 binaries in a single file, -# share DTB file between BL2 and BL32 -# If it is set to 0, then FIP is used -STM32MP_USE_STM32IMAGE ?= 0 +TRUSTED_BOARD_BOOT ?= 0 +STM32MP_USE_EXTERNAL_HEAP ?= 0 + +# Use secure library from the ROM code for authentication +STM32MP_CRYPTO_ROM_LIB ?= 0 # Please don't increment this value without good understanding of # the monotonic counter @@ -48,10 +50,19 @@ STM32MP15 := 1 endif ifeq ($(STM32MP13),1) +# Will use SRAM2 as mbedtls heap +STM32MP_USE_EXTERNAL_HEAP := 1 + # DDR controller with single AXI port and 16-bit interface STM32MP_DDR_DUAL_AXI_PORT:= 0 STM32MP_DDR_32BIT_INTERFACE:= 0 +ifeq (${TRUSTED_BOARD_BOOT},1) +# PKA algo to include +PKA_USE_NIST_P256 := 1 +PKA_USE_BRAINPOOL_P256T1:= 1 +endif + # STM32 image header version v2.0 STM32_HEADER_VERSION_MAJOR:= 2 STM32_HEADER_VERSION_MINOR:= 0 @@ -65,6 +76,17 @@ STM32MP_DDR_32BIT_INTERFACE:= 1 # STM32 image header version v1.0 STM32_HEADER_VERSION_MAJOR:= 1 STM32_HEADER_VERSION_MINOR:= 0 + +# Add OP-TEE reserved shared memory area in mapping +STM32MP15_OPTEE_RSV_SHM := 1 +$(eval $(call add_defines,STM32MP15_OPTEE_RSV_SHM)) + +STM32MP_CRYPTO_ROM_LIB := 1 + +# Decryption support +ifneq ($(DECRYPTION_SUPPORT),none) +$(error "DECRYPTION_SUPPORT not supported on STM32MP15") +endif endif # STM32 image header binary type for BL2 @@ -82,34 +104,32 @@ TF_CFLAGS += -Wformat-signedness WORKAROUND_CVE_2017_5715:= 0 WORKAROUND_CVE_2022_23960:= 0 +# Number of TF-A copies in the device +STM32_TF_A_COPIES := 2 + +# PLAT_PARTITION_MAX_ENTRIES must take care of STM32_TF-A_COPIES and other partitions +# such as metadata (2) to find all the FIP partitions (default is 2). +PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 4))) + ifeq (${PSA_FWU_SUPPORT},1) -ifneq (${STM32MP_USE_STM32IMAGE},1) # Number of banks of updatable firmware NR_OF_FW_BANKS := 2 NR_OF_IMAGES_IN_FW_BANK := 1 -# Number of TF-A copies in the device -STM32_TF_A_COPIES := 2 -STM32_BL33_PARTS_NUM := 2 -STM32_RUNTIME_PARTS_NUM := 4 -else -$(error FWU Feature enabled only with FIP images) +FWU_MAX_PART = $(shell echo $$(($(STM32_TF_A_COPIES) + 2 + $(NR_OF_FW_BANKS)))) +ifeq ($(shell test $(FWU_MAX_PART) -gt $(PLAT_PARTITION_MAX_ENTRIES); echo $$?),0) +$(error "Required partition number is $(FWU_MAX_PART) where PLAT_PARTITION_MAX_ENTRIES is only \ +$(PLAT_PARTITION_MAX_ENTRIES)") endif -else -# Number of TF-A copies in the device -STM32_TF_A_COPIES := 2 -STM32_BL33_PARTS_NUM := 1 -ifeq ($(AARCH32_SP),optee) -STM32_RUNTIME_PARTS_NUM := 3 -else ifeq ($(STM32MP_USE_STM32IMAGE),1) -STM32_RUNTIME_PARTS_NUM := 0 -else -STM32_RUNTIME_PARTS_NUM := 1 endif + +ifeq ($(STM32MP13),1) +STM32_HASH_VER := 4 +STM32_RNG_VER := 4 +else # Assuming STM32MP15 +STM32_HASH_VER := 2 +STM32_RNG_VER := 2 endif -PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + \ - $(STM32_BL33_PARTS_NUM) + \ - $(STM32_RUNTIME_PARTS_NUM)))) # Boot devices STM32MP_EMMC ?= 0 @@ -123,19 +143,14 @@ STM32MP_EMMC_BOOT ?= 0 STM32MP_USB_PROGRAMMER ?= 0 STM32MP_UART_PROGRAMMER ?= 0 +# Download load address for serial boot devices +DWL_BUFFER_BASE ?= 0xC7000000 + # Device tree ifeq ($(STM32MP13),1) BL2_DTSI := stm32mp13-bl2.dtsi FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) else -ifeq ($(STM32MP_USE_STM32IMAGE),1) -ifeq ($(AARCH32_SP),optee) -BL2_DTSI := stm32mp15-bl2.dtsi -FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) -else -FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(DTB_FILE_NAME))) -endif -else BL2_DTSI := stm32mp15-bl2.dtsi FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) ifeq ($(AARCH32_SP),sp_min) @@ -143,7 +158,6 @@ BL32_DTSI := stm32mp15-bl32.dtsi FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME))) endif endif -endif $(eval DTC_V = $(shell $(DTC) -v | awk '{print $$NF}')) $(eval DTC_VERSION = $(shell printf "%d" $(shell echo ${DTC_V} | cut -d- -f1 | sed "s/\./0/g" | grep -o "[0-9]*"))) @@ -170,7 +184,6 @@ STM32IMAGEPATH ?= tools/stm32image STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT} STM32IMAGE_SRC := ${STM32IMAGEPATH}/stm32image.c -ifneq (${STM32MP_USE_STM32IMAGE},1) FIP_DEPS += dtbs STM32MP_HW_CONFIG := ${BL33_CFG} STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) @@ -182,6 +195,11 @@ endif $(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) # Add the HW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_HW_CONFIG},--hw-config)) +ifeq ($(GENERATE_COT),1) +STM32MP_CFG_CERT := $(BUILD_PLAT)/stm32mp_cfg_cert.crt +# Add the STM32MP_CFG_CERT to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_CFG_CERT},--stm32mp-cfg-cert)) +endif ifeq ($(AARCH32_SP),sp_min) STM32MP_TOS_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dtb,$(DTB_FILE_NAME))) $(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_TOS_FW_CONFIG},--tos-fw-config)) @@ -189,30 +207,34 @@ else # Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images # in the FIP if the platform requires. ifneq ($(BL32_EXTRA1),) -$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1)) +$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1,,$(ENCRYPT_BL32))) endif ifneq ($(BL32_EXTRA2),) -$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2)) -endif +$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2,,$(ENCRYPT_BL32))) endif endif # Enable flags for C files $(eval $(call assert_booleans,\ $(sort \ + PKA_USE_BRAINPOOL_P256T1 \ + PKA_USE_NIST_P256 \ + PLAT_TBBR_IMG_DEF \ PLAT_XLAT_TABLES_DYNAMIC \ + STM32MP_CRYPTO_ROM_LIB \ STM32MP_DDR_32BIT_INTERFACE \ STM32MP_DDR_DUAL_AXI_PORT \ STM32MP_EARLY_CONSOLE \ STM32MP_EMMC \ STM32MP_EMMC_BOOT \ STM32MP_RAW_NAND \ + STM32MP_RECONFIGURE_CONSOLE \ STM32MP_SDMMC \ STM32MP_SPI_NAND \ STM32MP_SPI_NOR \ STM32MP_UART_PROGRAMMER \ STM32MP_USB_PROGRAMMER \ - STM32MP_USE_STM32IMAGE \ + STM32MP_USE_EXTERNAL_HEAP \ STM32MP13 \ STM32MP15 \ ))) @@ -220,6 +242,9 @@ $(eval $(call assert_booleans,\ $(eval $(call assert_numerics,\ $(sort \ PLAT_PARTITION_MAX_ENTRIES \ + STM32_HASH_VER \ + STM32_HEADER_VERSION_MAJOR \ + STM32_RNG_VER \ STM32_TF_A_COPIES \ STM32_TF_VERSION \ STM32MP_UART_BAUDRATE \ @@ -227,23 +252,32 @@ $(eval $(call assert_numerics,\ $(eval $(call add_defines,\ $(sort \ + DWL_BUFFER_BASE \ + PKA_USE_BRAINPOOL_P256T1 \ + PKA_USE_NIST_P256 \ PLAT_PARTITION_MAX_ENTRIES \ + PLAT_TBBR_IMG_DEF \ PLAT_XLAT_TABLES_DYNAMIC \ + STM32_HASH_VER \ + STM32_HEADER_VERSION_MAJOR \ + STM32_RNG_VER \ STM32_TF_A_COPIES \ STM32_TF_VERSION \ + STM32MP_CRYPTO_ROM_LIB \ STM32MP_DDR_32BIT_INTERFACE \ STM32MP_DDR_DUAL_AXI_PORT \ STM32MP_EARLY_CONSOLE \ STM32MP_EMMC \ STM32MP_EMMC_BOOT \ STM32MP_RAW_NAND \ + STM32MP_RECONFIGURE_CONSOLE \ STM32MP_SDMMC \ STM32MP_SPI_NAND \ STM32MP_SPI_NOR \ STM32MP_UART_BAUDRATE \ STM32MP_UART_PROGRAMMER \ STM32MP_USB_PROGRAMMER \ - STM32MP_USE_STM32IMAGE \ + STM32MP_USE_EXTERNAL_HEAP \ STM32MP13 \ STM32MP15 \ ))) @@ -252,11 +286,7 @@ $(eval $(call add_defines,\ PLAT_INCLUDES := -Iplat/st/common/include/ PLAT_INCLUDES += -Iplat/st/stm32mp1/include/ -ifeq (${STM32MP_USE_STM32IMAGE},1) -include common/fdt_wrappers.mk -else include lib/fconf/fconf.mk -endif include lib/libfdt/libfdt.mk PLAT_BL_COMMON_SOURCES := common/uuid.c \ @@ -297,12 +327,12 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \ ifeq ($(STM32MP13),1) PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ - drivers/st/clk/clk-stm32mp13.c + drivers/st/clk/clk-stm32mp13.c \ + drivers/st/crypto/stm32_rng.c else PLAT_BL_COMMON_SOURCES += drivers/st/clk/stm32mp1_clk.c endif -ifneq (${STM32MP_USE_STM32IMAGE},1) BL2_SOURCES += ${FCONF_SOURCES} ${FCONF_DYN_SOURCES} BL2_SOURCES += drivers/io/io_fip.c \ @@ -310,15 +340,6 @@ BL2_SOURCES += drivers/io/io_fip.c \ plat/st/common/stm32mp_fconf_io.c \ plat/st/stm32mp1/plat_bl2_mem_params_desc.c \ plat/st/stm32mp1/stm32mp1_fconf_firewall.c -else -BL2_SOURCES += ${FDT_WRAPPERS_SOURCES} - -BL2_SOURCES += drivers/io/io_dummy.c \ - drivers/st/io/io_stm32image.c \ - plat/st/common/bl2_stm32_io_storage.c \ - plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c \ - plat/st/stm32mp1/stm32mp1_security.c -endif include lib/zlib/zlib.mk @@ -335,9 +356,47 @@ BL2_SOURCES += drivers/io/io_block.c \ drivers/st/crypto/stm32_hash.c \ plat/st/stm32mp1/bl2_plat_setup.c +ifneq (${DECRYPTION_SUPPORT},none) +BL2_SOURCES += drivers/io/io_encrypted.c +endif -ifeq ($(STM32MP15),1) -BL2_SOURCES += plat/st/common/stm32mp_auth.c +ifeq (${TRUSTED_BOARD_BOOT},1) +AUTH_SOURCES := drivers/auth/auth_mod.c \ + drivers/auth/crypto_mod.c \ + drivers/auth/img_parser_mod.c + +ifeq (${GENERATE_COT},1) +TFW_NVCTR_VAL := 0 +NTFW_NVCTR_VAL := 0 +KEY_SIZE := +KEY_ALG := ecdsa +HASH_ALG := sha256 + +ifeq (${SAVE_KEYS},1) +TRUSTED_WORLD_KEY ?= ${BUILD_PLAT}/trusted.pem +NON_TRUSTED_WORLD_KEY ?= ${BUILD_PLAT}/non-trusted.pem +BL32_KEY ?= ${BUILD_PLAT}/trusted_os.pem +BL33_KEY ?= ${BUILD_PLAT}/non-trusted_os.pem +endif + +endif +TF_MBEDTLS_KEY_ALG := ecdsa +MBEDTLS_CONFIG_FILE ?= "<stm32mp1_mbedtls_config.h>" + +include drivers/auth/mbedtls/mbedtls_x509.mk + +COT_DESC_IN_DTB := 1 +AUTH_SOURCES += lib/fconf/fconf_cot_getter.c \ + lib/fconf/fconf_tbbr_getter.c \ + plat/st/common/stm32mp_crypto_lib.c + +ifeq ($(STM32MP13),1) +AUTH_SOURCES += drivers/st/crypto/stm32_pka.c +AUTH_SOURCES += drivers/st/crypto/stm32_saes.c +endif + +BL2_SOURCES += $(AUTH_SOURCES) \ + plat/st/common/stm32mp_trusted_boot.c endif ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) @@ -359,6 +418,9 @@ BL2_SOURCES += drivers/mtd/nand/spi_nand.c endif ifeq (${STM32MP_SPI_NOR},1) +ifneq (${STM32MP_FORCE_MTD_START_OFFSET},) +$(eval $(call add_define_val,STM32MP_NOR_FIP_OFFSET,${STM32MP_FORCE_MTD_START_OFFSET})) +endif BL2_SOURCES += drivers/mtd/nor/spi_nor.c endif @@ -368,6 +430,9 @@ BL2_SOURCES += drivers/mtd/spi-mem/spi_mem.c \ endif ifneq ($(filter 1,${STM32MP_RAW_NAND} ${STM32MP_SPI_NAND}),) +ifneq (${STM32MP_FORCE_MTD_START_OFFSET},) +$(eval $(call add_define_val,STM32MP_NAND_FIP_OFFSET,${STM32MP_FORCE_MTD_START_OFFSET})) +endif BL2_SOURCES += drivers/mtd/nand/core.c endif @@ -440,13 +505,6 @@ check_dtc_version: false; \ fi -ifeq ($(STM32MP_USE_STM32IMAGE)-$(AARCH32_SP),1-sp_min) -${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%.dtb plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP} - @echo " AS stm32mp1.S" - ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \ - -DDTB_BIN_PATH=\"$<\" \ - -c $(word 2,$^) -o $@ -else # Create DTB file for BL2 ${BUILD_PLAT}/fdts/%-bl2.dts: fdts/%.dts fdts/${BL2_DTSI} | ${BUILD_PLAT} fdt_dirs @echo '#include "$(patsubst fdts/%,%,$<)"' > $@ @@ -468,7 +526,6 @@ ${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%-bl2.dtb plat/st/stm32mp1/stm32m ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \ -DDTB_BIN_PATH=\"$<\" \ -c plat/st/stm32mp1/stm32mp1.S -o $@ -endif $(eval $(call MAKE_LD,${STM32_TF_LINKERFILE},plat/st/stm32mp1/stm32mp1.ld.S,bl2)) diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk index c3fc2cb39..1d754d980 100644 --- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk +++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk @@ -10,11 +10,9 @@ endif SP_MIN_WITH_SECURE_FIQ := 1 -ifneq ($(STM32MP_USE_STM32IMAGE),1) override ENABLE_PIE := 1 BL32_CFLAGS += -fpie -DENABLE_PIE BL32_LDFLAGS += $(PIE_LDFLAGS) -endif BL32_CFLAGS += -DSTM32MP_SHARED_RESOURCES diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c index 81067951d..50b079471 100644 --- a/plat/st/stm32mp1/sp_min/sp_min_setup.c +++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,6 +40,8 @@ static entry_point_info_t bl33_image_ep_info; ******************************************************************************/ void sp_min_plat_fiq_handler(uint32_t id) { + (void)plat_crash_console_init(); + switch (id & INT_ID_MASK) { case STM32MP1_IRQ_TZC400: tzc400_init(STM32MP1_TZC_BASE); @@ -51,7 +53,7 @@ void sp_min_plat_fiq_handler(uint32_t id) panic(); break; default: - ERROR("SECURE IT handler not define for it : %u", id); + ERROR("SECURE IT handler not define for it : %u\n", id); break; } } @@ -113,11 +115,9 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { bl_params_t *params_from_bl2 = (bl_params_t *)arg0; -#if STM32MP_USE_STM32IMAGE - uintptr_t dt_addr = STM32MP_DTB_BASE; -#else uintptr_t dt_addr = arg1; -#endif + + stm32mp_setup_early_console(); /* Imprecise aborts can be masked in NonSecure */ write_scr(read_scr() | SCR_AW_BIT); diff --git a/plat/st/stm32mp1/stm32mp1.S b/plat/st/stm32mp1/stm32mp1.S index 85caa0a80..aee4f0ec2 100644 --- a/plat/st/stm32mp1/stm32mp1.S +++ b/plat/st/stm32mp1/stm32mp1.S @@ -1,16 +1,9 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#if STM32MP_USE_STM32IMAGE -#ifdef BL32_BIN_PATH -.section .bl32_image -.incbin BL32_BIN_PATH -#endif -#endif /* STM32MP_USE_STM32IMAGE */ - .section .bl2_image .incbin BL2_BIN_PATH diff --git a/plat/st/stm32mp1/stm32mp1.ld.S b/plat/st/stm32mp1/stm32mp1.ld.S index 2254feead..1be82193b 100644 --- a/plat/st/stm32mp1/stm32mp1.ld.S +++ b/plat/st/stm32mp1/stm32mp1.ld.S @@ -43,11 +43,7 @@ SECTIONS * The strongest and only alignment contraint is MMU 4K page. * Indeed as images below will be removed, 4K pages will be re-used. */ -#if STM32MP_USE_STM32IMAGE - . = ( STM32MP_DTB_BASE - STM32MP_BINARY_BASE ); -#else . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE ); -#endif /* STM32MP_USE_STM32IMAGE */ __DTB_IMAGE_START__ = .; *(.dtb_image*) __DTB_IMAGE_END__ = .; @@ -66,18 +62,6 @@ SECTIONS *(.bl2_image*) __BL2_IMAGE_END__ = .; -#if STM32MP_USE_STM32IMAGE && !defined(AARCH32_SP_OPTEE) - /* - * bl32 will be settled by bl2. - * The strongest and only alignment constraint is 8 words to simplify - * memraise8 assembly code. - */ - . = ( STM32MP_BL32_BASE - STM32MP_BINARY_BASE ); - __BL32_IMAGE_START__ = .; - *(.bl32_image*) - __BL32_IMAGE_END__ = .; -#endif /* STM32MP_USE_STM32IMAGE && !defined(AARCH32_SP_OPTEE) */ - __DATA_END__ = .; } >RAM diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c index b05de1cb8..3a8a27ac9 100644 --- a/plat/st/stm32mp1/stm32mp1_boot_device.c +++ b/plat/st/stm32mp1/stm32mp1_boot_device.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <assert.h> #include <errno.h> #include <common/debug.h> @@ -15,9 +16,21 @@ #include <plat/common/platform.h> #if STM32MP_RAW_NAND || STM32MP_SPI_NAND +#if STM32MP13 +void plat_get_scratch_buffer(void **buffer_addr, size_t *buf_size) +{ + assert(buffer_addr != NULL); + assert(buf_size != NULL); + + *buffer_addr = (void *)STM32MP_MTD_BUFFER; + *buf_size = PLATFORM_MTD_MAX_PAGE_SIZE; +} +#endif + static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc) { uint32_t nand_param; + uint32_t nand2_param __maybe_unused; /* Check if NAND parameters are stored in OTP */ if (stm32_get_otp_value(NAND_OTP, &nand_param) != 0) { @@ -26,13 +39,40 @@ static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc) } if (nand_param == 0U) { +#if STM32MP13 + if (is_slc) { + return 0; + } +#endif +#if STM32MP15 return 0; +#endif } if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) { +#if STM32MP13 + if (is_slc) { + goto ecc; + } +#endif +#if STM32MP15 goto ecc; +#endif } +#if STM32MP13 + if (stm32_get_otp_value(NAND2_OTP, &nand2_param) != 0) { + ERROR("BSEC: NAND_OTP Error\n"); + return -EACCES; + } + + /* Check OTP configuration for this device */ + if ((((nand2_param & NAND2_CONFIG_DISTRIB) == NAND2_PNAND_NAND1_SNAND_NAND2) && !is_slc) || + (((nand2_param & NAND2_CONFIG_DISTRIB) == NAND2_PNAND_NAND2_SNAND_NAND1) && is_slc)) { + nand_param = nand2_param << (NAND_PAGE_SIZE_SHIFT - NAND2_PAGE_SIZE_SHIFT); + } +#endif + /* NAND parameter shall be read from OTP */ if ((nand_param & NAND_WIDTH_MASK) != 0U) { nand_dev->buswidth = NAND_BUS_WIDTH_16; diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 7e0745a8e..f0d85263e 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -19,7 +19,6 @@ #include <drivers/st/stm32mp1_clk.h> #include <boot_api.h> -#include <stm32mp_auth.h> #include <stm32mp_common.h> #include <stm32mp_dt.h> #include <stm32mp1_dbgmcu.h> @@ -27,11 +26,7 @@ #include <stm32mp1_shared_resources.h> #endif -#if !STM32MP_USE_STM32IMAGE #include "stm32mp1_fip_def.h" -#else /* STM32MP_USE_STM32IMAGE */ -#include "stm32mp1_stm32image_def.h" -#endif /* STM32MP_USE_STM32IMAGE */ /******************************************************************************* * CHIP ID @@ -71,6 +66,7 @@ #define STM32MP1_REV_B U(0x2000) #if STM32MP13 +#define STM32MP1_REV_Y U(0x1003) #define STM32MP1_REV_Z U(0x1001) #endif #if STM32MP15 @@ -182,12 +178,23 @@ enum ddr_type { #endif #endif +#if STM32MP13 +#define STM32MP_BL33_BASE STM32MP_DDR_BASE +#endif +#if STM32MP15 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) +#endif #define STM32MP_BL33_MAX_SIZE U(0x400000) /* Define maximum page size for NAND devices */ #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) +/* Define location for the MTD scratch buffer */ +#if STM32MP13 +#define STM32MP_MTD_BUFFER (SRAM1_BASE + \ + SRAM1_SIZE - \ + PLATFORM_MTD_MAX_PAGE_SIZE) +#endif /******************************************************************************* * STM32MP1 device/io map related constants (used for MMU) ******************************************************************************/ @@ -247,8 +254,14 @@ enum ddr_type { /******************************************************************************* * STM32MP1 UART ******************************************************************************/ +#if STM32MP13 +#define USART1_BASE U(0x4C000000) +#define USART2_BASE U(0x4C001000) +#endif +#if STM32MP15 #define USART1_BASE U(0x5C000000) #define USART2_BASE U(0x4000E000) +#endif #define USART3_BASE U(0x4000F000) #define UART4_BASE U(0x40010000) #define UART5_BASE U(0x40011000) @@ -424,9 +437,17 @@ enum ddr_type { #define PACKAGE_OTP "package_otp" #endif #define HW2_OTP "hw2_otp" +#if STM32MP13 +#define NAND_OTP "cfg9_otp" +#define NAND2_OTP "cfg10_otp" +#endif +#if STM32MP15 #define NAND_OTP "nand_otp" +#endif #define MONOTONIC_OTP "monotonic_otp" #define UID_OTP "uid_otp" +#define PKH_OTP "pkh_otp" +#define ENCKEY_OTP "enckey_otp" #define BOARD_ID_OTP "board_id" /* OTP mask */ @@ -484,7 +505,7 @@ enum ddr_type { #define NAND_BLOCK_SIZE_128_PAGES U(1) #define NAND_BLOCK_SIZE_256_PAGES U(2) -/* NAND number of block (in unit of 256 blocs) */ +/* NAND number of block (in unit of 256 blocks) */ #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) #define NAND_BLOCK_NB_SHIFT 19 #define NAND_BLOCK_NB_UNIT U(256) @@ -505,6 +526,14 @@ enum ddr_type { /* NAND number of planes */ #define NAND_PLANE_BIT_NB_MASK BIT(14) +/* NAND2 OTP */ +#define NAND2_PAGE_SIZE_SHIFT 16 + +/* NAND2 config distribution */ +#define NAND2_CONFIG_DISTRIB BIT(0) +#define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) +#define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) + /* MONOTONIC OTP */ #define MAX_MONOTONIC_VALUE 32 @@ -519,6 +548,7 @@ enum ddr_type { ******************************************************************************/ #define TAMP_BASE U(0x5C00A000) #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) +#define TAMP_COUNTR U(0x40) #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) static inline uintptr_t tamp_bkpr(uint32_t idx) @@ -634,5 +664,6 @@ static inline uintptr_t tamp_bkpr(uint32_t idx) #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure" #endif #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" +#define DT_UART_COMPAT "st,stm32h7-uart" #endif /* STM32MP1_DEF_H */ diff --git a/plat/st/stm32mp1/stm32mp1_fip_def.h b/plat/st/stm32mp1/stm32mp1_fip_def.h index 7a277fdcb..4098386fd 100644 --- a/plat/st/stm32mp1/stm32mp1_fip_def.h +++ b/plat/st/stm32mp1/stm32mp1_fip_def.h @@ -7,17 +7,44 @@ #ifndef STM32MP1_FIP_DEF_H #define STM32MP1_FIP_DEF_H +#if STM32MP15_OPTEE_RSV_SHM #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ +#else +#define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */ +#define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */ +#endif +#if TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP +#if STM32MP15 +#define STM32MP_BL2_RO_SIZE U(0x00014000) /* 80 KB */ +#define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */ +#endif /* STM32MP15 */ +#else /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */ #if STM32MP13 +#if BL2_IN_XIP_MEM #define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */ #define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */ -#define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */ +#else +/* STM32MP_BL2_RO_SIZE not used if !BL2_IN_XIP_MEM */ +#define STM32MP_BL2_SIZE U(0x0001B000) /* 108KB for BL2 */ + /* with 20KB for DTB, SYSRAM is full */ +#endif #endif /* STM32MP13 */ #if STM32MP15 #define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */ #define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */ +#endif /* STM32MP15 */ +#endif /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */ + +#if STM32MP13 +#if TRUSTED_BOARD_BOOT +#define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ +#else /* TRUSTED_BOARD_BOOT */ +#define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */ +#endif /* TRUSTED_BOARD_BOOT */ +#endif /* STM32MP13 */ +#if STM32MP15 #define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */ #endif /* STM32MP15 */ #define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */ @@ -98,9 +125,14 @@ #endif /******************************************************************************* - * STM32MP1 RAW partition offset for MTD devices + * STM32MP1 RAW partition offset for devices without GPT ******************************************************************************/ +#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000) +#ifndef STM32MP_NOR_FIP_OFFSET #define STM32MP_NOR_FIP_OFFSET U(0x00080000) +#endif +#ifndef STM32MP_NAND_FIP_OFFSET #define STM32MP_NAND_FIP_OFFSET U(0x00200000) +#endif #endif /* STM32MP1_FIP_DEF_H */ diff --git a/plat/st/stm32mp1/stm32mp1_helper.S b/plat/st/stm32mp1/stm32mp1_helper.S index cac9752e2..eb8823b02 100644 --- a/plat/st/stm32mp1/stm32mp1_helper.S +++ b/plat/st/stm32mp1/stm32mp1_helper.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,6 +15,8 @@ .globl platform_mem_init .globl plat_report_exception + .globl plat_report_prefetch_abort + .globl plat_report_data_abort .globl plat_get_my_entrypoint .globl plat_secondary_cold_boot_setup .globl plat_reset_handler @@ -30,20 +32,18 @@ func platform_mem_init bx lr endfunc platform_mem_init -func plat_report_exception #if DEBUG +func plat_report_exception mov r8, lr - /* Test if an abort occurred */ + /* + * Test if an abort occurred + * In this case the error message has already been displayed + * by dedicated functions + */ cmp r0, #MODE32_abt - bne undef_inst_lbl - ldr r4, =abort_str - bl asm_print_str - mrs r4, lr_abt - sub r4, r4, #4 - b print_exception_info + beq 1f -undef_inst_lbl: /* Test for an undefined instruction */ cmp r0, #MODE32_und bne other_exception_lbl @@ -69,12 +69,69 @@ print_exception_info: ldr r4, =end_error_str bl asm_print_str +1: bx r8 -#else - bx lr -#endif endfunc plat_report_exception +func plat_report_prefetch_abort + mov r8, lr + mov r9, r0 + + ldr r4, =prefetch_abort_str + bl asm_print_str + + mov r4, r9 + sub r4, r4, #4 + bl asm_print_hex + + ldr r4, =ifsr_str + bl asm_print_str + + ldcopr r4, IFSR + bl asm_print_hex + + ldr r4, =ifar_str + bl asm_print_str + + ldcopr r4, IFAR + bl asm_print_hex + + ldr r4, =end_error_str + bl asm_print_str + + bx r8 +endfunc plat_report_prefetch_abort + +func plat_report_data_abort + mov r8, lr + mov r9, r0 + + ldr r4, =data_abort_str + bl asm_print_str + + mov r4, r9 + sub r4, r4, #8 + bl asm_print_hex + + ldr r4, =dfsr_str + bl asm_print_str + + ldcopr r4, DFSR + bl asm_print_hex + + ldr r4, =dfar_str + bl asm_print_str + + ldcopr r4, DFAR + bl asm_print_hex + + ldr r4, =end_error_str + bl asm_print_str + + bx r8 +endfunc plat_report_data_abort +#endif /* DEBUG */ + func plat_reset_handler bx lr endfunc plat_reset_handler @@ -256,14 +313,24 @@ endfunc plat_panic_handler #if DEBUG .section .rodata.rev_err_str, "aS" -abort_str: - .asciz "\nAbort at: 0x" +prefetch_abort_str: + .asciz "\nPrefetch Abort at: 0x" +data_abort_str: + .asciz "\nData Abort at: 0x" undefined_str: .asciz "\nUndefined instruction at: 0x" exception_start_str: .asciz "\nException mode=0x" exception_end_str: .asciz " at: 0x" +dfsr_str: + .asciz " DFSR = 0x" +dfar_str: + .asciz " DFAR = 0x" +ifsr_str: + .asciz " IFSR = 0x" +ifar_str: + .asciz " IFAR = 0x" end_error_str: .asciz "\n\r" #endif diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c index 389215129..6e438c44e 100644 --- a/plat/st/stm32mp1/stm32mp1_pm.c +++ b/plat/st/stm32mp1/stm32mp1_pm.c @@ -87,7 +87,7 @@ static int stm32_pwr_domain_on(u_register_t mpidr) clk_disable(RTCAPB); /* Generate an IT to core 1 */ - gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP_SECONDARY_CPU); + gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, false, STM32MP_SECONDARY_CPU); return PSCI_E_SUCCESS; } diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index 1617afd04..9bdb07552 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -43,8 +43,10 @@ #if STM32MP15 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) #endif -#define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00) +#define TAMP_BOOT_MODE_ITF_MASK GENMASK(15, 8) #define TAMP_BOOT_MODE_ITF_SHIFT 8 +#define TAMP_BOOT_MODE_AUTH_MASK GENMASK(23, 16) +#define TAMP_BOOT_MODE_AUTH_SHIFT 16 /* * Backup register to store fwu update information. @@ -52,9 +54,9 @@ * (so it should be in Zone 2). */ #define TAMP_BOOT_FWU_INFO_REG_ID U(10) -#define TAMP_BOOT_FWU_INFO_IDX_MSK U(0xF) +#define TAMP_BOOT_FWU_INFO_IDX_MSK GENMASK(3, 0) #define TAMP_BOOT_FWU_INFO_IDX_OFF U(0) -#define TAMP_BOOT_FWU_INFO_CNT_MSK U(0xF0) +#define TAMP_BOOT_FWU_INFO_CNT_MSK GENMASK(7, 4) #define TAMP_BOOT_FWU_INFO_CNT_OFF U(4) #if defined(IMAGE_BL2) @@ -199,6 +201,8 @@ unsigned long stm32_get_gpio_bank_clock(unsigned int bank) int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) { + const char *node_compatible = NULL; + switch (bank) { case GPIO_BANK_A: case GPIO_BANK_B: @@ -209,18 +213,24 @@ int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) case GPIO_BANK_G: case GPIO_BANK_H: case GPIO_BANK_I: +#if STM32MP13 + node_compatible = "st,stm32mp135-pinctrl"; + break; +#endif #if STM32MP15 case GPIO_BANK_J: case GPIO_BANK_K: -#endif - return fdt_path_offset(fdt, "/soc/pin-controller"); -#if STM32MP15 + node_compatible = "st,stm32mp157-pinctrl"; + break; case GPIO_BANK_Z: - return fdt_path_offset(fdt, "/soc/pin-controller-z"); + node_compatible = "st,stm32mp157-z-pinctrl"; + break; #endif default: panic(); } + + return fdt_node_offset_by_compatible(fdt, -1, node_compatible); } #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) @@ -483,6 +493,11 @@ void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) case STM32MP1_REV_B: cpu_r = "B"; break; +#if STM32MP13 + case STM32MP1_REV_Y: + cpu_r = "Y"; + break; +#endif case STM32MP1_REV_Z: cpu_r = "Z"; break; @@ -682,29 +697,6 @@ uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) } #endif -#if STM32MP_USE_STM32IMAGE -/* Get the non-secure DDR size */ -uint32_t stm32mp_get_ddr_ns_size(void) -{ - static uint32_t ddr_ns_size; - uint32_t ddr_size; - - if (ddr_ns_size != 0U) { - return ddr_ns_size; - } - - ddr_size = dt_get_ddr_size(); - if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || - (ddr_size > STM32MP_DDR_MAX_SIZE)) { - panic(); - } - - ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); - - return ddr_ns_size; -} -#endif /* STM32MP_USE_STM32IMAGE */ - void stm32_save_boot_interface(uint32_t interface, uint32_t instance) { uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); @@ -738,7 +730,21 @@ void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) *instance = itf & 0xFU; } -#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT +void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition) +{ + uint32_t boot_status = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); + + clk_enable(RTCAPB); + + mmio_clrsetbits_32(boot_status, + TAMP_BOOT_MODE_AUTH_MASK, + ((auth_status << 4) | (boot_partition & 0xFU)) << + TAMP_BOOT_MODE_AUTH_SHIFT); + + clk_disable(RTCAPB); +} + +#if PSA_FWU_SUPPORT void stm32mp1_fwu_set_boot_idx(void) { clk_enable(RTCAPB); @@ -779,4 +785,4 @@ void stm32_set_max_fwu_trial_boot_cnt(void) TAMP_BOOT_FWU_INFO_CNT_MSK); clk_disable(RTCAPB); } -#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ +#endif /* PSA_FWU_SUPPORT */ diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c deleted file mode 100644 index c84bffcf9..000000000 --- a/plat/st/stm32mp1/stm32mp1_security.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <stdint.h> - -#include <platform_def.h> - -#include <common/debug.h> -#include <drivers/arm/tzc400.h> -#include <drivers/clk.h> -#include <drivers/st/stm32mp1_clk.h> -#include <dt-bindings/clock/stm32mp1-clks.h> -#include <dt-bindings/soc/stm32mp15-tzc400.h> -#include <lib/mmio.h> - -static unsigned int region_nb; - -static void init_tzc400_begin(unsigned int region0_attr) -{ - tzc400_init(STM32MP1_TZC_BASE); - tzc400_disable_filters(); - - /* Region 0 set to cover all DRAM at 0xC000_0000 */ - tzc400_configure_region0(region0_attr, 0); - - region_nb = 1U; -} - -static void init_tzc400_end(unsigned int action) -{ - tzc400_set_action(action); - tzc400_enable_filters(); -} - -static void tzc400_add_region(unsigned long long region_base, - unsigned long long region_top, bool sec) -{ - unsigned int sec_attr; - unsigned int nsaid_permissions; - - if (sec) { - sec_attr = TZC_REGION_S_RDWR; - nsaid_permissions = 0; - } else { - sec_attr = TZC_REGION_S_NONE; - nsaid_permissions = TZC_REGION_NSEC_ALL_ACCESS_RDWR; - } - - tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, region_nb, region_base, - region_top, sec_attr, nsaid_permissions); - - region_nb++; -} - -/******************************************************************************* - * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access - * and allow Non-Secure masters full access. - ******************************************************************************/ -static void init_tzc400(void) -{ - unsigned long long region_base, region_top; - unsigned long long ddr_base = STM32MP_DDR_BASE; - unsigned long long ddr_ns_size = - (unsigned long long)stm32mp_get_ddr_ns_size(); - unsigned long long ddr_ns_top = ddr_base + (ddr_ns_size - 1U); - unsigned long long ddr_top __unused; - - init_tzc400_begin(TZC_REGION_S_NONE); - - /* - * Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the - * same configuration to all filters in the TZC. - */ - region_base = ddr_base; - region_top = ddr_ns_top; - tzc400_add_region(region_base, region_top, false); - -#ifdef AARCH32_SP_OPTEE - /* Region 2 set to cover all secure DRAM. */ - region_base = region_top + 1U; - region_top += STM32MP_DDR_S_SIZE; - tzc400_add_region(region_base, region_top, true); - - ddr_top = STM32MP_DDR_BASE + dt_get_ddr_size() - 1U; - if (region_top < ddr_top) { - /* Region 3 set to cover non-secure memory DRAM after BL32. */ - region_base = region_top + 1U; - region_top = ddr_top; - tzc400_add_region(region_base, region_top, false); - } -#endif - - /* - * Raise an interrupt (secure FIQ) if a NS device tries to access - * secure memory - */ - init_tzc400_end(TZC_ACTION_INT); -} - -/******************************************************************************* - * Initialize the TrustZone Controller. - * Early initialization create only one region with full access to secure. - * This setting is used before and during DDR initialization. - ******************************************************************************/ -static void early_init_tzc400(void) -{ - clk_enable(TZC1); - clk_enable(TZC2); - - /* Region 0 set to cover all DRAM secure at 0xC000_0000 */ - init_tzc400_begin(TZC_REGION_S_RDWR); - - /* Raise an exception if a NS device tries to access secure memory */ - init_tzc400_end(TZC_ACTION_ERR); -} - -/******************************************************************************* - * Initialize the secure environment. At this moment only the TrustZone - * Controller is initialized. - ******************************************************************************/ -void stm32mp1_arch_security_setup(void) -{ - early_init_tzc400(); -} - -/******************************************************************************* - * Initialize the secure environment. At this moment only the TrustZone - * Controller is initialized. - ******************************************************************************/ -void stm32mp1_security_setup(void) -{ - init_tzc400(); -} diff --git a/plat/st/stm32mp1/stm32mp1_stm32image_def.h b/plat/st/stm32mp1/stm32mp1_stm32image_def.h deleted file mode 100644 index 8efa342c1..000000000 --- a/plat/st/stm32mp1/stm32mp1_stm32image_def.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2021, STMicroelectronics - All Rights Reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STM32MP1_STM32IMAGE_DEF_H -#define STM32MP1_STM32IMAGE_DEF_H - -#ifdef AARCH32_SP_OPTEE -#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ -#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ -#else -#define STM32MP_DDR_S_SIZE U(0) -#define STM32MP_DDR_SHMEM_SIZE U(0) -#endif - -#define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */ -#define STM32MP_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ - -#ifdef AARCH32_SP_OPTEE -#define STM32MP_BL32_BASE STM32MP_SEC_SYSRAM_BASE - -#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ - STM32MP_SEC_SYSRAM_SIZE - \ - STM32MP_BL2_SIZE) - -/* OP-TEE loads from SYSRAM base to BL2 DTB start address */ -#define STM32MP_OPTEE_BASE STM32MP_BL32_BASE -#define STM32MP_OPTEE_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ - STM32MP_BL2_SIZE - STM32MP_DTB_SIZE) -#define STM32MP_BL32_SIZE STM32MP_OPTEE_SIZE -#else /* AARCH32_SP_OPTEE */ -#define STM32MP_BL32_SIZE U(0x00019000) /* 96 KB for BL32 */ - -#define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \ - STM32MP_SEC_SYSRAM_SIZE - \ - STM32MP_BL32_SIZE) - -#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ - STM32MP_BL2_SIZE) -#endif /* AARCH32_SP_OPTEE */ - -/* DTB initialization value */ -#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ - STM32MP_DTB_SIZE) - -/* - * MAX_MMAP_REGIONS is usually: - * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup - */ -#if defined(IMAGE_BL32) -#define MAX_MMAP_REGIONS 6 -#endif - -/******************************************************************************* - * STM32MP1 RAW partition offset for MTD devices - ******************************************************************************/ -#define STM32MP_NOR_BL33_OFFSET U(0x00080000) -#ifdef AARCH32_SP_OPTEE -#define STM32MP_NOR_TEEH_OFFSET U(0x00280000) -#define STM32MP_NOR_TEED_OFFSET U(0x002C0000) -#define STM32MP_NOR_TEEX_OFFSET U(0x00300000) -#endif - -#define STM32MP_NAND_BL33_OFFSET U(0x00200000) -#ifdef AARCH32_SP_OPTEE -#define STM32MP_NAND_TEEH_OFFSET U(0x00600000) -#define STM32MP_NAND_TEED_OFFSET U(0x00680000) -#define STM32MP_NAND_TEEX_OFFSET U(0x00700000) -#endif - -#endif /* STM32MP1_STM32IMAGE_DEF_H */ diff --git a/plat/st/stm32mp1/stm32mp1_tbb_cert.c b/plat/st/stm32mp1/stm32mp1_tbb_cert.c new file mode 100644 index 000000000..0e77397c8 --- /dev/null +++ b/plat/st/stm32mp1/stm32mp1_tbb_cert.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "tbbr/tbb_ext.h" +#include "tbbr/tbb_key.h" + +#include "tbbr/stm32mp1_tbb_cert.h" + +/* + * Certificates used in the chain of trust + * + * The order of the certificates must follow the enumeration specified in + * stm32mp1_tbb_cert.h. All certificates are self-signed, so the issuer certificate + * field points to itself. + */ +static cert_t stm32mp1_tbb_certs[] = { + [0] = { + .id = STM32MP_CONFIG_CERT, + .opt = "stm32mp-cfg-cert", + .help_msg = "STM32MP Config Certificate (output file)", + .fn = NULL, + .cn = "STM32MP config FW Certificate", + .key = ROT_KEY, + .issuer = STM32MP_CONFIG_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + HW_CONFIG_HASH_EXT, + FW_CONFIG_HASH_EXT + }, + .num_ext = 3 + }, +}; + +PLAT_REGISTER_COT(stm32mp1_tbb_certs); diff --git a/plat/ti/k3/board/j784s4/board.mk b/plat/ti/k3/board/j784s4/board.mk new file mode 100644 index 000000000..92433ab65 --- /dev/null +++ b/plat/ti/k3/board/j784s4/board.mk @@ -0,0 +1,24 @@ +# +# Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BL32_BASE ?= 0x9e800000 +$(eval $(call add_define,BL32_BASE)) + +PRELOADED_BL33_BASE ?= 0x80080000 +$(eval $(call add_define,PRELOADED_BL33_BASE)) + +K3_HW_CONFIG_BASE ?= 0x82000000 +$(eval $(call add_define,K3_HW_CONFIG_BASE)) + +# Define sec_proxy usage as the full prioritized communication scheme +K3_SEC_PROXY_LITE := 0 +$(eval $(call add_define,K3_SEC_PROXY_LITE)) + +# System coherency is managed in hardware +USE_COHERENT_MEM := 1 + +PLAT_INCLUDES += \ + -Iplat/ti/k3/board/j784s4/include \ diff --git a/plat/ti/k3/board/j784s4/include/board_def.h b/plat/ti/k3/board/j784s4/include/board_def.h new file mode 100644 index 000000000..c2debc70e --- /dev/null +++ b/plat/ti/k3/board/j784s4/include/board_def.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOARD_DEF_H +#define BOARD_DEF_H + +#include <lib/utils_def.h> + +/* The ports must be in order and contiguous */ +#define K3_CLUSTER0_CORE_COUNT U(4) +#define K3_CLUSTER1_CORE_COUNT U(4) +#define K3_CLUSTER2_CORE_COUNT U(0) +#define K3_CLUSTER3_CORE_COUNT U(0) +/* + * This RAM will be used for the bootloader including code, bss, and stacks. + * It may need to be increased if BL31 grows in size. + * + * The link addresses are determined by SEC_SRAM_BASE + offset. + * When ENABLE_PIE is set, the TF images can be loaded anywhere, so + * SEC_SRAM_BASE is really arbitrary. + * + * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that + * it matches to the physical address where BL31 is loaded, that is, + * SEC_SRAM_BASE should be the base address of the RAM region. + * + * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is + * defined as default for our platform. + */ +#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */ +#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */ + +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) + +#define PLAT_PROC_START_ID U(32) + +#define PLAT_PROC_DEVICE_START_ID U(202) +#define PLAT_CLUSTER_DEVICE_START_ID U(198) + +#endif /* BOARD_DEF_H */ diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk index e299c30cc..026d6a3f2 100644 --- a/plat/ti/k3/common/plat_common.mk +++ b/plat/ti/k3/common/plat_common.mk @@ -27,7 +27,7 @@ ERRATA_A72_859971 := 1 ERRATA_A72_1319367 := 1 CRASH_REPORTING := 1 -HANDLE_EA_EL3_FIRST := 1 +HANDLE_EA_EL3_FIRST_NS := 1 # Split out RO data into a non-executable section SEPARATE_CODE_AND_RODATA := 1 diff --git a/plat/xilinx/common/include/ipi.h b/plat/xilinx/common/include/ipi.h index ac76bf06c..1d62f3e4a 100644 --- a/plat/xilinx/common/include/ipi.h +++ b/plat/xilinx/common/include/ipi.h @@ -14,20 +14,20 @@ /********************************************************************* * IPI mailbox status macros ********************************************************************/ -#define IPI_MB_STATUS_IDLE 0 -#define IPI_MB_STATUS_SEND_PENDING 1 -#define IPI_MB_STATUS_RECV_PENDING 2 +#define IPI_MB_STATUS_IDLE (0U) +#define IPI_MB_STATUS_SEND_PENDING (1U) +#define IPI_MB_STATUS_RECV_PENDING (2U) /********************************************************************* * IPI mailbox call is secure or not macros ********************************************************************/ -#define IPI_MB_CALL_NOTSECURE 0 -#define IPI_MB_CALL_SECURE 1 +#define IPI_MB_CALL_NOTSECURE (0U) +#define IPI_MB_CALL_SECURE (1U) /********************************************************************* * IPI secure check ********************************************************************/ -#define IPI_SECURE_MASK 0x1U +#define IPI_SECURE_MASK (0x1U) #define IPI_IS_SECURE(I) ((ipi_table[(I)].secure_only & \ IPI_SECURE_MASK) ? 1 : 0) diff --git a/plat/xilinx/common/include/plat_startup.h b/plat/xilinx/common/include/plat_startup.h index 6799e2181..1733930c9 100644 --- a/plat/xilinx/common/include/plat_startup.h +++ b/plat/xilinx/common/include/plat_startup.h @@ -7,6 +7,8 @@ #ifndef PLAT_STARTUP_H #define PLAT_STARTUP_H +#include <common/bl_common.h> + /* For FSBL handover */ enum fsbl_handoff { FSBL_HANDOFF_SUCCESS = 0, @@ -15,6 +17,23 @@ enum fsbl_handoff { FSBL_HANDOFF_TOO_MANY_PARTS }; +#define FSBL_MAX_PARTITIONS 8U + +/* Structure corresponding to each partition entry */ +struct xfsbl_partition { + uint64_t entry_point; + uint64_t flags; +}; + +/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */ +struct xfsbl_atf_handoff_params { + uint8_t magic[4]; + uint32_t num_entries; + struct xfsbl_partition partition[FSBL_MAX_PARTITIONS]; +}; + +#define ATF_HANDOFF_PARAMS_MAX_SIZE sizeof(struct xfsbl_atf_handoff_params) + enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32, entry_point_info_t *bl33, uint64_t atf_handoff_addr); diff --git a/plat/xilinx/common/include/pm_client.h b/plat/xilinx/common/include/pm_client.h index e91bb8f6c..eae1d9860 100644 --- a/plat/xilinx/common/include/pm_client.h +++ b/plat/xilinx/common/include/pm_client.h @@ -1,5 +1,7 @@ /* * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,17 +18,16 @@ #include "pm_defs.h" /* Functions to be implemented by each PU */ -void pm_client_suspend(const struct pm_proc *proc, unsigned int state); +void pm_client_suspend(const struct pm_proc *proc, uint32_t state); void pm_client_abort_suspend(void); void pm_client_wakeup(const struct pm_proc *proc); /* Global variables to be set in pm_client.c */ extern const struct pm_proc *primary_proc; -#ifndef VERSAL_PLATFORM -enum pm_ret_status set_ocm_retention(void); +#if defined(PLAT_zynqmp) enum pm_ret_status pm_set_suspend_mode(uint32_t mode); const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid); -#endif +#endif /* PLAT_zynqmp */ #endif /* PM_CLIENT_H */ diff --git a/plat/xilinx/common/include/pm_common.h b/plat/xilinx/common/include/pm_common.h index 0c24a3665..89626e5f2 100644 --- a/plat/xilinx/common/include/pm_common.h +++ b/plat/xilinx/common/include/pm_common.h @@ -27,6 +27,11 @@ #endif #define PAYLOAD_ARG_SIZE 4U /* size in bytes */ +#define TZ_VERSION_MAJOR 1 +#define TZ_VERSION_MINOR 0 +#define TZ_VERSION ((TZ_VERSION_MAJOR << 16) | \ + TZ_VERSION_MINOR) + /** * pm_ipi - struct for capturing IPI-channel specific info * @local_ipi_id Local IPI agent ID @@ -48,10 +53,10 @@ struct pm_ipi { */ struct pm_proc { const uint32_t node_id; - const unsigned int pwrdn_mask; + const uint32_t pwrdn_mask; const struct pm_ipi *ipi; }; -const struct pm_proc *pm_get_proc(unsigned int cpuid); +const struct pm_proc *pm_get_proc(uint32_t cpuid); #endif /* PM_COMMON_H */ diff --git a/plat/xilinx/common/include/pm_ipi.h b/plat/xilinx/common/include/pm_ipi.h index 8c7738d71..52dfc4766 100644 --- a/plat/xilinx/common/include/pm_ipi.h +++ b/plat/xilinx/common/include/pm_ipi.h @@ -1,5 +1,7 @@ /* * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,12 +10,13 @@ #define PM_IPI_H #include <plat_ipi.h> +#include <stddef.h> #include "pm_common.h" #define IPI_BLOCKING 1 #define IPI_NON_BLOCKING 0 -int pm_ipi_init(const struct pm_proc *proc); +void pm_ipi_init(const struct pm_proc *proc); enum pm_ret_status pm_ipi_send(const struct pm_proc *proc, uint32_t payload[PAYLOAD_ARG_CNT]); @@ -21,8 +24,8 @@ enum pm_ret_status pm_ipi_send_non_blocking(const struct pm_proc *proc, uint32_t payload[PAYLOAD_ARG_CNT]); enum pm_ret_status pm_ipi_send_sync(const struct pm_proc *proc, uint32_t payload[PAYLOAD_ARG_CNT], - unsigned int *value, size_t count); -void pm_ipi_buff_read_callb(unsigned int *value, size_t count); + uint32_t *value, size_t count); +void pm_ipi_buff_read_callb(uint32_t *value, size_t count); void pm_ipi_irq_enable(const struct pm_proc *proc); void pm_ipi_irq_clear(const struct pm_proc *proc); uint32_t pm_ipi_irq_status(const struct pm_proc *proc); diff --git a/plat/xilinx/common/ipi.c b/plat/xilinx/common/ipi.c index 2f52f38f3..643889647 100644 --- a/plat/xilinx/common/ipi.c +++ b/plat/xilinx/common/ipi.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, Xilinx, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +18,6 @@ #include <lib/mmio.h> #include <ipi.h> -#include <plat_ipi.h> #include <plat_private.h> /********************************************************************* @@ -141,7 +141,7 @@ void ipi_mb_release(uint32_t local, uint32_t remote) */ int ipi_mb_enquire_status(uint32_t local, uint32_t remote) { - int ret = 0; + int ret = 0U; uint32_t status; status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET); diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c index f53115885..cb6aaa5df 100644 --- a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c +++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c @@ -64,13 +64,13 @@ * function with rt_svc_handle signature */ uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, - uint64_t x3, uint64_t x4, void *cookie, + uint64_t x3, uint64_t x4, const void *cookie, void *handle, uint64_t flags) { - int ret; + int32_t ret; uint32_t ipi_local_id; uint32_t ipi_remote_id; - unsigned int is_secure; + uint32_t is_secure; ipi_local_id = x1 & UNSIGNED32_MASK; ipi_remote_id = x2 & UNSIGNED32_MASK; @@ -94,7 +94,7 @@ uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, SMC_RET1(handle, 0); case IPI_MAILBOX_STATUS_ENQUIRY: { - int disable_irq; + int32_t disable_irq; disable_irq = (x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) ? 1 : 0; ret = ipi_mb_enquire_status(ipi_local_id, ipi_remote_id); @@ -112,7 +112,7 @@ uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, } case IPI_MAILBOX_ACK: { - int enable_irq; + int32_t enable_irq; enable_irq = (x3 & IPI_SMC_ACK_EIRQ_MASK) ? 1 : 0; ipi_mb_ack(ipi_local_id, ipi_remote_id); diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.h b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.h index 10682d835..af13db97a 100644 --- a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.h +++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.h @@ -33,7 +33,7 @@ enum ipi_api_id { /* IPI SMC handler */ uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, - uint64_t x3, uint64_t x4, void *cookie, void *handle, + uint64_t x3, uint64_t x4, const void *cookie, void *handle, uint64_t flags); #endif /* IPI_MAILBOX_SVC_H */ diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c index b8f88c46c..de9cf4d01 100644 --- a/plat/xilinx/common/plat_startup.c +++ b/plat/xilinx/common/plat_startup.c @@ -24,49 +24,34 @@ * CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3 */ -#define FSBL_FLAGS_ESTATE_SHIFT 0 -#define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT) -#define FSBL_FLAGS_ESTATE_A64 0 -#define FSBL_FLAGS_ESTATE_A32 1 - -#define FSBL_FLAGS_ENDIAN_SHIFT 1 -#define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT) -#define FSBL_FLAGS_ENDIAN_LE 0 -#define FSBL_FLAGS_ENDIAN_BE 1 - -#define FSBL_FLAGS_TZ_SHIFT 2 -#define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT) -#define FSBL_FLAGS_NON_SECURE 0 -#define FSBL_FLAGS_SECURE 1 - -#define FSBL_FLAGS_EL_SHIFT 3 -#define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT) -#define FSBL_FLAGS_EL0 0 -#define FSBL_FLAGS_EL1 1 -#define FSBL_FLAGS_EL2 2 -#define FSBL_FLAGS_EL3 3 - -#define FSBL_FLAGS_CPU_SHIFT 5 -#define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT) -#define FSBL_FLAGS_A53_0 0 -#define FSBL_FLAGS_A53_1 1 -#define FSBL_FLAGS_A53_2 2 -#define FSBL_FLAGS_A53_3 3 - -#define FSBL_MAX_PARTITIONS 8 - -/* Structure corresponding to each partition entry */ -struct xfsbl_partition { - uint64_t entry_point; - uint64_t flags; -}; - -/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */ -struct xfsbl_atf_handoff_params { - uint8_t magic[4]; - uint32_t num_entries; - struct xfsbl_partition partition[FSBL_MAX_PARTITIONS]; -}; +#define FSBL_FLAGS_ESTATE_SHIFT 0U +#define FSBL_FLAGS_ESTATE_MASK (1U << FSBL_FLAGS_ESTATE_SHIFT) +#define FSBL_FLAGS_ESTATE_A64 0U +#define FSBL_FLAGS_ESTATE_A32 1U + +#define FSBL_FLAGS_ENDIAN_SHIFT 1U +#define FSBL_FLAGS_ENDIAN_MASK (1U << FSBL_FLAGS_ENDIAN_SHIFT) +#define FSBL_FLAGS_ENDIAN_LE 0U +#define FSBL_FLAGS_ENDIAN_BE 1U + +#define FSBL_FLAGS_TZ_SHIFT 2U +#define FSBL_FLAGS_TZ_MASK (1U << FSBL_FLAGS_TZ_SHIFT) +#define FSBL_FLAGS_NON_SECURE 0U +#define FSBL_FLAGS_SECURE 1U + +#define FSBL_FLAGS_EL_SHIFT 3U +#define FSBL_FLAGS_EL_MASK (3U << FSBL_FLAGS_EL_SHIFT) +#define FSBL_FLAGS_EL0 0U +#define FSBL_FLAGS_EL1 1U +#define FSBL_FLAGS_EL2 2U +#define FSBL_FLAGS_EL3 3U + +#define FSBL_FLAGS_CPU_SHIFT 5U +#define FSBL_FLAGS_CPU_MASK (3U << FSBL_FLAGS_CPU_SHIFT) +#define FSBL_FLAGS_A53_0 0U +#define FSBL_FLAGS_A53_1 1U +#define FSBL_FLAGS_A53_2 2U +#define FSBL_FLAGS_A53_3 3U /** * @partition: Pointer to partition struct @@ -75,7 +60,7 @@ struct xfsbl_atf_handoff_params { * * Return: FSBL_FLAGS_A53_0, FSBL_FLAGS_A53_1, FSBL_FLAGS_A53_2 or FSBL_FLAGS_A53_3 */ -static int get_fsbl_cpu(const struct xfsbl_partition *partition) +static int32_t get_fsbl_cpu(const struct xfsbl_partition *partition) { uint64_t flags = partition->flags & FSBL_FLAGS_CPU_MASK; @@ -89,7 +74,7 @@ static int get_fsbl_cpu(const struct xfsbl_partition *partition) * * Return: FSBL_FLAGS_EL0, FSBL_FLAGS_EL1, FSBL_FLAGS_EL2 or FSBL_FLAGS_EL3 */ -static int get_fsbl_el(const struct xfsbl_partition *partition) +static int32_t get_fsbl_el(const struct xfsbl_partition *partition) { uint64_t flags = partition->flags & FSBL_FLAGS_EL_MASK; @@ -103,7 +88,7 @@ static int get_fsbl_el(const struct xfsbl_partition *partition) * * Return: FSBL_FLAGS_NON_SECURE or FSBL_FLAGS_SECURE */ -static int get_fsbl_ss(const struct xfsbl_partition *partition) +static int32_t get_fsbl_ss(const struct xfsbl_partition *partition) { uint64_t flags = partition->flags & FSBL_FLAGS_TZ_MASK; @@ -117,7 +102,7 @@ static int get_fsbl_ss(const struct xfsbl_partition *partition) * * Return: SPSR_E_LITTLE or SPSR_E_BIG */ -static int get_fsbl_endian(const struct xfsbl_partition *partition) +static int32_t get_fsbl_endian(const struct xfsbl_partition *partition) { uint64_t flags = partition->flags & FSBL_FLAGS_ENDIAN_MASK; @@ -137,7 +122,7 @@ static int get_fsbl_endian(const struct xfsbl_partition *partition) * * Return: FSBL_FLAGS_ESTATE_A32 or FSBL_FLAGS_ESTATE_A64 */ -static int get_fsbl_estate(const struct xfsbl_partition *partition) +static int32_t get_fsbl_estate(const struct xfsbl_partition *partition) { uint64_t flags = partition->flags & FSBL_FLAGS_ESTATE_MASK; @@ -161,8 +146,6 @@ enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32, uint64_t atf_handoff_addr) { const struct xfsbl_atf_handoff_params *ATFHandoffParams; - assert((atf_handoff_addr < BL31_BASE) || - (atf_handoff_addr > (uint64_t)&__BL31_END__)); if (!atf_handoff_addr) { WARN("BL31: No ATF handoff structure passed\n"); return FSBL_HANDOFF_NO_STRUCT; @@ -193,8 +176,8 @@ enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32, */ for (size_t i = 0; i < ATFHandoffParams->num_entries; i++) { entry_point_info_t *image; - int target_estate, target_secure; - int target_cpu, target_endianness, target_el; + int32_t target_estate, target_secure, target_cpu; + uint32_t target_endianness, target_el; VERBOSE("BL31: %zd: entry:0x%" PRIx64 ", flags:0x%" PRIx64 "\n", i, ATFHandoffParams->partition[i].entry_point, diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c index 1d1ba852f..513d6be0a 100644 --- a/plat/xilinx/common/pm_service/pm_ipi.c +++ b/plat/xilinx/common/pm_service/pm_ipi.c @@ -1,5 +1,7 @@ /* * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,9 +15,11 @@ #include <plat_private.h> #include <plat/common/platform.h> +#include "pm_defs.h" #include "pm_ipi.h" -#define ERROR_CODE_MASK 0xFFFFU +#define ERROR_CODE_MASK (0xFFFFU) +#define PM_OFFSET (0U) DEFINE_BAKERY_LOCK(pm_secure_lock); @@ -30,12 +34,10 @@ DEFINE_BAKERY_LOCK(pm_secure_lock); * * Called from pm_setup initialization function */ -int pm_ipi_init(const struct pm_proc *proc) +void pm_ipi_init(const struct pm_proc *proc) { bakery_lock_init(&pm_secure_lock); ipi_mb_open(proc->ipi->local_ipi_id, proc->ipi->remote_ipi_id); - - return 0; } /** @@ -52,7 +54,7 @@ static enum pm_ret_status pm_ipi_send_common(const struct pm_proc *proc, uint32_t payload[PAYLOAD_ARG_CNT], uint32_t is_blocking) { - unsigned int offset = 0; + uint32_t offset = PM_OFFSET; uintptr_t buffer_base = proc->ipi->buffer_base + IPI_BUFFER_TARGET_REMOTE_OFFSET + IPI_BUFFER_REQ_OFFSET; @@ -131,12 +133,12 @@ enum pm_ret_status pm_ipi_send(const struct pm_proc *proc, * @return Returns status, either success or error+reason */ static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc, - unsigned int *value, size_t count) + uint32_t *value, size_t count) { size_t i; #if IPI_CRC_CHECK size_t j; - unsigned int response_payload[PAYLOAD_ARG_CNT]; + uint32_t response_payload[PAYLOAD_ARG_CNT]; #endif uintptr_t buffer_base = proc->ipi->buffer_base + IPI_BUFFER_TARGET_REMOTE_OFFSET + @@ -177,12 +179,12 @@ static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc, * * @return Returns status, either success or error+reason */ -void pm_ipi_buff_read_callb(unsigned int *value, size_t count) +void pm_ipi_buff_read_callb(uint32_t *value, size_t count) { size_t i; #if IPI_CRC_CHECK size_t j; - unsigned int response_payload[PAYLOAD_ARG_CNT]; + unsigned int response_payload[PAYLOAD_ARG_CNT] = {0}; #endif uintptr_t buffer_base = IPI_BUFFER_REMOTE_BASE + IPI_BUFFER_TARGET_LOCAL_OFFSET + @@ -224,7 +226,7 @@ void pm_ipi_buff_read_callb(unsigned int *value, size_t count) */ enum pm_ret_status pm_ipi_send_sync(const struct pm_proc *proc, uint32_t payload[PAYLOAD_ARG_CNT], - unsigned int *value, size_t count) + uint32_t *value, size_t count) { enum pm_ret_status ret; @@ -255,7 +257,7 @@ void pm_ipi_irq_clear(const struct pm_proc *proc) uint32_t pm_ipi_irq_status(const struct pm_proc *proc) { - int ret; + int32_t ret; ret = ipi_mb_enquire_status(proc->ipi->local_ipi_id, proc->ipi->remote_ipi_id); diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c index 897ed59ec..f55cde961 100644 --- a/plat/xilinx/versal/aarch64/versal_common.c +++ b/plat/xilinx/versal/aarch64/versal_common.c @@ -47,7 +47,7 @@ void versal_config_setup(void) generic_delay_timer_init(); } -unsigned int plat_get_syscnt_freq2(void) +uint32_t plat_get_syscnt_freq2(void) { return VERSAL_CPU_CLOCK; } diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c index 78bfc2978..9b3620839 100644 --- a/plat/xilinx/versal/bl31_versal_setup.c +++ b/plat/xilinx/versal/bl31_versal_setup.c @@ -1,5 +1,7 @@ /* * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,6 +22,9 @@ #include <versal_def.h> #include <plat_private.h> #include <plat_startup.h> +#include <pm_ipi.h> +#include "pm_client.h" +#include "pm_api_sys.h" static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -63,23 +68,26 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { uint64_t atf_handoff_addr; + uint32_t payload[PAYLOAD_ARG_CNT], max_size = ATF_HANDOFF_PARAMS_MAX_SIZE; + enum pm_ret_status ret_status; + uint64_t addr[ATF_HANDOFF_PARAMS_MAX_SIZE]; if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) { static console_t versal_runtime_console; /* Initialize the console to provide early debug support */ - int rc = console_pl011_register((unsigned long)VERSAL_UART_BASE, - (unsigned int)VERSAL_UART_CLOCK, - (unsigned int)VERSAL_UART_BAUDRATE, + int32_t rc = console_pl011_register((uintptr_t)VERSAL_UART_BASE, + (uint32_t)VERSAL_UART_CLOCK, + (uint32_t)VERSAL_UART_BAUDRATE, &versal_runtime_console); if (rc == 0) { panic(); } - console_set_scope(&versal_runtime_console, (unsigned int)(CONSOLE_FLAG_BOOT | + console_set_scope(&versal_runtime_console, (uint32_t)(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME)); } else if (VERSAL_CONSOLE_IS(dcc)) { /* Initialize the dcc console for debug */ - int rc = console_dcc_register(); + int32_t rc = console_dcc_register(); if (rc == 0) { panic(); } @@ -106,7 +114,17 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); - atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); + PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, + (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size); + ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); + if (ret_status == PM_RET_SUCCESS) { + INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status); + atf_handoff_addr = (uintptr_t)&addr; + } else { + ERROR("BL31: GET_HANDOFF_PARAMS Failed, read atf_handoff_addr from reg\n"); + atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); + } + enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, &bl33_image_ep_info, atf_handoff_addr); @@ -124,16 +142,29 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); } -static interrupt_type_handler_t type_el3_interrupt_handler; +static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) { - /* Validate 'handler'*/ - if (handler == NULL) { + static uint32_t index; + uint32_t i; + + /* Validate 'handler' and 'id' parameters */ + if (handler == NULL || index >= MAX_INTR_EL3) { return -EINVAL; } - type_el3_interrupt_handler = handler; + /* Check if a handler has already been registered */ + for (i = 0; i < index; i++) { + if (id == type_el3_interrupt_table[i].id) { + return -EALREADY; + } + } + + type_el3_interrupt_table[index].id = id; + type_el3_interrupt_table[index].handler = handler; + + index++; return 0; } @@ -142,16 +173,17 @@ static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, void *handle, void *cookie) { uint32_t intr_id; - interrupt_type_handler_t handler; + uint32_t i; + interrupt_type_handler_t handler = NULL; intr_id = plat_ic_get_pending_interrupt_id(); - /* Currently we support one interrupt */ - if (intr_id != PLAT_VERSAL_IPI_IRQ) { - WARN("Unexpected interrupt call: 0x%x\n", intr_id); - return 0; + + for (i = 0; i < MAX_INTR_EL3; i++) { + if (intr_id == type_el3_interrupt_table[i].id) { + handler = type_el3_interrupt_table[i].handler; + } } - handler = type_el3_interrupt_handler; if (handler != NULL) { return handler(intr_id, flags, handle, cookie); } diff --git a/plat/xilinx/versal/include/plat_pm_common.h b/plat/xilinx/versal/include/plat_pm_common.h index 22c9d1182..4c057b832 100644 --- a/plat/xilinx/versal/include/plat_pm_common.h +++ b/plat/xilinx/versal/include/plat_pm_common.h @@ -19,8 +19,4 @@ #define NON_SECURE_FLAG 1U #define SECURE_FLAG 0U -#define VERSAL_TZ_VERSION_MAJOR 1 -#define VERSAL_TZ_VERSION_MINOR 0 -#define VERSAL_TZ_VERSION ((VERSAL_TZ_VERSION_MAJOR << 16) | \ - VERSAL_TZ_VERSION_MINOR) #endif /* PLAT_PM_COMMON_H */ diff --git a/plat/xilinx/versal/include/plat_private.h b/plat/xilinx/versal/include/plat_private.h index d12d13af8..818797d2d 100644 --- a/plat/xilinx/versal/include/plat_private.h +++ b/plat/xilinx/versal/include/plat_private.h @@ -1,5 +1,7 @@ /* * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +12,11 @@ #include <lib/xlat_tables/xlat_tables.h> #include <bl31/interrupt_mgmt.h> +typedef struct versal_intr_info_type_el3 { + uint32_t id; + interrupt_type_handler_t handler; +} versal_intr_info_type_el3_t; + void versal_config_setup(void); const mmap_region_t *plat_versal_get_mmap(void); @@ -22,11 +29,11 @@ void plat_versal_gic_pcpu_init(void); void plat_versal_gic_save(void); void plat_versal_gic_resume(void); -unsigned int versal_calc_core_pos(u_register_t mpidr); +uint32_t versal_calc_core_pos(u_register_t mpidr); /* * Register handler to specific GIC entrance * for INTR_TYPE_EL3 type of interrupt */ -int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler); +int32_t request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler); #endif /* PLAT_PRIVATE_H */ diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h index 83e508392..6d95fdc5f 100644 --- a/plat/xilinx/versal/include/platform_def.h +++ b/plat/xilinx/versal/include/platform_def.h @@ -15,7 +15,7 @@ ******************************************************************************/ /* Size of cacheable stacks */ -#define PLATFORM_STACK_SIZE 0x440 +#define PLATFORM_STACK_SIZE U(0x440) #define PLATFORM_CORE_COUNT U(2) #define PLAT_MAX_PWR_LVL U(1) diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h index 731742da8..60431a59f 100644 --- a/plat/xilinx/versal/include/versal_def.h +++ b/plat/xilinx/versal/include/versal_def.h @@ -1,5 +1,7 @@ /* * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +12,8 @@ #include <plat/arm/common/smccc_def.h> #include <plat/common/common_def.h> +/* number of interrupt handlers. increase as required */ +#define MAX_INTR_EL3 2 /* List all consoles */ #define VERSAL_CONSOLE_ID_pl011 1 #define VERSAL_CONSOLE_ID_pl011_0 1 @@ -37,20 +41,6 @@ #define DEVICE1_BASE 0xF9000000 #define DEVICE1_SIZE 0x00800000 -/* CRL */ -#define VERSAL_CRL 0xFF5E0000 -#define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C) -#define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348) - -#define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25) - -/* IOU SCNTRS */ -#define VERSAL_IOU_SCNTRS 0xFF140000 -#define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0) -#define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20) - -#define VERSAL_IOU_SCNTRS_CONTROL_EN 1 - /******************************************************************************* * IRQ constants ******************************************************************************/ @@ -95,15 +85,15 @@ # define VERSAL_UART_BAUDRATE 115200 # define VERSAL_CPU_CLOCK 100000000 #elif VERSAL_PLATFORM_IS(spp_itr6) -# define PLATFORM_NAME "SPP ITR6" -# define VERSAL_UART_CLOCK 25000000 -# define VERSAL_UART_BAUDRATE 115200 -# define VERSAL_CPU_CLOCK 2720000 +# define PLATFORM_NAME "SPP ITR6" +# define VERSAL_UART_CLOCK 25000000 +# define VERSAL_UART_BAUDRATE 115200 +# define VERSAL_CPU_CLOCK 2720000 #elif VERSAL_PLATFORM_IS(emu_itr6) -# define PLATFORM_NAME "EMU ITR6" -# define VERSAL_UART_CLOCK 212000 -# define VERSAL_UART_BAUDRATE 9600 -# define VERSAL_CPU_CLOCK 212000 +# define PLATFORM_NAME "EMU ITR6" +# define VERSAL_UART_CLOCK 212000 +# define VERSAL_UART_BAUDRATE 9600 +# define VERSAL_CPU_CLOCK 212000 #endif /* Access control register defines */ diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c index eb05e5857..6787f31b4 100644 --- a/plat/xilinx/versal/plat_psci.c +++ b/plat/xilinx/versal/plat_psci.c @@ -19,9 +19,9 @@ static uintptr_t versal_sec_entry; -static int versal_pwr_domain_on(u_register_t mpidr) +static int32_t versal_pwr_domain_on(u_register_t mpidr) { - int cpu_id = plat_core_pos_by_mpidr(mpidr); + int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); const struct pm_proc *proc; VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); @@ -30,7 +30,7 @@ static int versal_pwr_domain_on(u_register_t mpidr) return PSCI_E_INTERN_FAIL; } - proc = pm_get_proc((unsigned int)cpu_id); + proc = pm_get_proc((uint32_t)cpu_id); /* Send request to PMC to wake up selected ACPU core */ (void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U, @@ -50,8 +50,8 @@ static int versal_pwr_domain_on(u_register_t mpidr) */ static void versal_pwr_domain_suspend(const psci_power_state_t *target_state) { - unsigned int state; - unsigned int cpu_id = plat_my_core_pos(); + uint32_t state; + uint32_t cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { @@ -88,7 +88,7 @@ static void versal_pwr_domain_suspend(const psci_power_state_t *target_state) static void versal_pwr_domain_suspend_finish( const psci_power_state_t *target_state) { - unsigned int cpu_id = plat_my_core_pos(); + uint32_t cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { @@ -156,7 +156,7 @@ static void __dead2 versal_system_reset(void) */ static void versal_pwr_domain_off(const psci_power_state_t *target_state) { - unsigned int cpu_id = plat_my_core_pos(); + uint32_t cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { @@ -188,12 +188,12 @@ static void versal_pwr_domain_off(const psci_power_state_t *target_state) * * @return Returns status, either success or reason */ -static int versal_validate_power_state(unsigned int power_state, +static int32_t versal_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) { VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); - unsigned int pstate = psci_get_pstate_type(power_state); + uint32_t pstate = psci_get_pstate_type(power_state); assert(req_state); @@ -238,7 +238,7 @@ static const struct plat_psci_ops versal_nopmc_psci_ops = { /******************************************************************************* * Export the platform specific power ops. ******************************************************************************/ -int plat_setup_psci_ops(uintptr_t sec_entrypoint, +int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, const struct plat_psci_ops **psci_ops) { versal_sec_entry = sec_entrypoint; diff --git a/plat/xilinx/versal/plat_topology.c b/plat/xilinx/versal/plat_topology.c index 66d4fae39..6a94544e0 100644 --- a/plat/xilinx/versal/plat_topology.c +++ b/plat/xilinx/versal/plat_topology.c @@ -6,9 +6,9 @@ #include <platform_def.h> -static const unsigned char plat_power_domain_tree_desc[] = {1, PLATFORM_CORE_COUNT}; +static const uint8_t plat_power_domain_tree_desc[] = {1, PLATFORM_CORE_COUNT}; -const unsigned char *plat_get_power_domain_tree_desc(void) +const uint8_t *plat_get_power_domain_tree_desc(void) { return plat_power_domain_tree_desc; } diff --git a/plat/xilinx/versal/plat_versal.c b/plat/xilinx/versal/plat_versal.c index 54c35b630..132c7b78f 100644 --- a/plat/xilinx/versal/plat_versal.c +++ b/plat/xilinx/versal/plat_versal.c @@ -7,7 +7,7 @@ #include <plat_private.h> #include <plat/common/platform.h> -int plat_core_pos_by_mpidr(u_register_t mpidr) +int32_t plat_core_pos_by_mpidr(u_register_t mpidr) { if ((mpidr & MPIDR_CLUSTER_MASK) != 0U) { return -1; @@ -17,5 +17,5 @@ int plat_core_pos_by_mpidr(u_register_t mpidr) return -1; } - return (int)versal_calc_core_pos(mpidr); + return (int32_t)versal_calc_core_pos(mpidr); } diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk index a8b2c948a..8087297a2 100644 --- a/plat/xilinx/versal/platform.mk +++ b/plat/xilinx/versal/platform.mk @@ -11,6 +11,10 @@ PL011_GENERIC_UART := 1 IPI_CRC_CHECK := 0 HARDEN_SLS_ALL := 0 +# A72 Erratum for SoC +ERRATA_A72_859971 := 1 +ERRATA_A72_1319367 := 1 + ifdef VERSAL_ATF_MEM_BASE $(eval $(call add_define,VERSAL_ATF_MEM_BASE)) diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c index 04258cc0a..db9fae433 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.c +++ b/plat/xilinx/versal/pm_service/pm_api_sys.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,62 +17,20 @@ #include "pm_client.h" #include "pm_defs.h" #include "pm_svc_main.h" -#include "../drivers/arm/gic/v3/gicv3_private.h" - -/********************************************************************* - * Target module IDs macros - ********************************************************************/ -#define LIBPM_MODULE_ID 0x2U -#define LOADER_MODULE_ID 0x7U - -#define MODE 0x80000000U -#define MODULE_ID_MASK 0x0000ff00 /* default shutdown/reboot scope is system(2) */ -static unsigned int pm_shutdown_scope = XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM; +static uint32_t pm_shutdown_scope = XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM; /** * pm_get_shutdown_scope() - Get the currently set shutdown scope * * @return Shutdown scope value */ -unsigned int pm_get_shutdown_scope(void) +uint32_t pm_get_shutdown_scope(void) { return pm_shutdown_scope; } -/** - * Assigning of argument values into array elements. - */ -#define PM_PACK_PAYLOAD1(pl, mid, flag, arg0) { \ - pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | ((mid) << 8U) | ((flag) << 24U)); \ -} - -#define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) { \ - pl[1] = (uint32_t)(arg1); \ - PM_PACK_PAYLOAD1(pl, (mid), (flag), (arg0)); \ -} - -#define PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2) { \ - pl[2] = (uint32_t)(arg2); \ - PM_PACK_PAYLOAD2(pl, (mid), (flag), (arg0), (arg1)); \ -} - -#define PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3) { \ - pl[3] = (uint32_t)(arg3); \ - PM_PACK_PAYLOAD3(pl, (mid), (flag), (arg0), (arg1), (arg2)); \ -} - -#define PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4) { \ - pl[4] = (uint32_t)(arg4); \ - PM_PACK_PAYLOAD4(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3)); \ -} - -#define PM_PACK_PAYLOAD6(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \ - pl[5] = (uint32_t)(arg5); \ - PM_PACK_PAYLOAD5(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3), (arg4)); \ -} - /* PM API functions */ /** @@ -90,11 +49,12 @@ enum pm_ret_status pm_handle_eemi_call(uint32_t flag, uint32_t x0, uint32_t x1, uint32_t payload[PAYLOAD_ARG_CNT] = {0}; uint32_t module_id; - module_id = (x0 & MODULE_ID_MASK) >> 8; + module_id = (x0 & MODULE_ID_MASK) >> 8U; //default module id is for LIBPM - if (module_id == 0) + if (module_id == 0) { module_id = LIBPM_MODULE_ID; + } PM_PACK_PAYLOAD6(payload, module_id, flag, x0, x1, x2, x3, x4, x5); return pm_ipi_send_sync(primary_proc, payload, (uint32_t *)result, PAYLOAD_ARG_CNT); @@ -115,12 +75,12 @@ enum pm_ret_status pm_handle_eemi_call(uint32_t flag, uint32_t x0, uint32_t x1, * @return Returns status, either success or error+reason */ enum pm_ret_status pm_self_suspend(uint32_t nid, - unsigned int latency, - unsigned int state, + uint32_t latency, + uint32_t state, uintptr_t address, uint32_t flag) { uint32_t payload[PAYLOAD_ARG_CNT]; - unsigned int cpuid = plat_my_core_pos(); + uint32_t cpuid = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpuid); if (proc == NULL) { @@ -182,7 +142,7 @@ enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason, uint32_t flag) * @return Returns status, either success or error+reason */ enum pm_ret_status pm_req_suspend(uint32_t target, uint8_t ack, - unsigned int latency, unsigned int state, + uint32_t latency, uint32_t state, uint32_t flag) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -232,10 +192,12 @@ enum pm_ret_status pm_req_wakeup(uint32_t target, uint32_t set_address, * @data - array of PAYLOAD_ARG_CNT elements * @flag - 0 - Call from secure source * 1 - Call from non-secure source + * @ack - 0 - Do not ack IPI after reading payload + * 1 - Ack IPI after reading payload * * Read value from ipi buffer response buffer. */ -void pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag) +void pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag, uint32_t ack) { /* Return if interrupt is not from PMU */ if (pm_ipi_irq_status(primary_proc) == 0) { @@ -243,7 +205,10 @@ void pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag) } pm_ipi_buff_read_callb(data, count); - pm_ipi_irq_clear(primary_proc); + + if (ack != 0U) { + pm_ipi_irq_clear(primary_proc); + } } /** @@ -437,7 +402,7 @@ enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2, ret = pm_feature_check(PM_QUERY_DATA, &version[0], flag); if (ret == PM_RET_SUCCESS) { - fw_api_version = version[0] & 0xFFFF; + fw_api_version = version[0] & 0xFFFFU; if ((fw_api_version == 2U) && ((qid == XPM_QID_CLOCK_GET_NAME) || (qid == XPM_QID_PINCTRL_GET_FUNCTION_NAME))) { @@ -500,9 +465,7 @@ enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id, if (ret != 0) { return PM_RET_ERROR_ARGS; } - gicd_write_irouter(gicv3_driver_data->gicd_base, - (unsigned int)PLAT_VERSAL_IPI_IRQ, MODE); - ret = PM_RET_SUCCESS; + ret = PM_RET_SUCCESS; break; default: return PM_RET_ERROR_NOTSUPPORTED; @@ -554,14 +517,14 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *ret_payload, case PM_GET_TRUSTZONE_VERSION: ret_payload[0] = PM_API_VERSION_2; return PM_RET_SUCCESS; - case PM_LOAD_PDI: + case TF_A_PM_REGISTER_SGI: ret_payload[0] = PM_API_BASE_VERSION; return PM_RET_SUCCESS; default: break; } - module_id = (api_id & MODULE_ID_MASK) >> 8; + module_id = (api_id & MODULE_ID_MASK) >> 8U; /* * feature check should be done only for LIBPM module diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h index 86a46d01e..c539aa743 100644 --- a/plat/xilinx/versal/pm_service/pm_api_sys.h +++ b/plat/xilinx/versal/pm_service/pm_api_sys.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +11,13 @@ #include <stdint.h> #include "pm_defs.h" +/********************************************************************* + * Target module IDs macros + ********************************************************************/ +#define LIBPM_MODULE_ID 0x2U +#define LOADER_MODULE_ID 0x7U + +#define MODULE_ID_MASK 0x0000ff00U /********************************************************** * PM API function declarations **********************************************************/ @@ -18,19 +26,20 @@ enum pm_ret_status pm_handle_eemi_call(uint32_t flag, uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3, uint32_t x4, uint32_t x5, uint64_t *result); enum pm_ret_status pm_self_suspend(uint32_t nid, - unsigned int latency, - unsigned int state, + uint32_t latency, + uint32_t state, uintptr_t address, uint32_t flag); enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason, uint32_t flag); enum pm_ret_status pm_req_suspend(uint32_t target, uint8_t ack, - unsigned int latency, - unsigned int state, uint32_t flag); + uint32_t latency, + uint32_t state, uint32_t flag); enum pm_ret_status pm_req_wakeup(uint32_t target, uint32_t set_address, uintptr_t address, uint8_t ack, uint32_t flag); enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t device_id, uint8_t enable, uint32_t flag); -void pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag); +void pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag, + uint32_t ack); enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param, uint32_t value, uint32_t flag); enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param, @@ -48,7 +57,7 @@ enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id, uint32_t *value, uint32_t flag); enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t *data, uint32_t flag); -unsigned int pm_get_shutdown_scope(void); +uint32_t pm_get_shutdown_scope(void); enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *ret_payload, uint32_t flag); enum pm_ret_status pm_load_pdi(uint32_t src, uint32_t address_low, @@ -56,4 +65,37 @@ enum pm_ret_status pm_load_pdi(uint32_t src, uint32_t address_low, enum pm_ret_status pm_register_notifier(uint32_t device_id, uint32_t event, uint32_t wake, uint32_t enable, uint32_t flag); + +/** + * Assigning of argument values into array elements. + */ +#define PM_PACK_PAYLOAD1(pl, mid, flag, arg0) { \ + pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | ((mid) << 8U) | ((flag) << 24U)); \ +} + +#define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) { \ + pl[1] = (uint32_t)(arg1); \ + PM_PACK_PAYLOAD1(pl, (mid), (flag), (arg0)); \ +} + +#define PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2) { \ + pl[2] = (uint32_t)(arg2); \ + PM_PACK_PAYLOAD2(pl, (mid), (flag), (arg0), (arg1)); \ +} + +#define PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3) { \ + pl[3] = (uint32_t)(arg3); \ + PM_PACK_PAYLOAD3(pl, (mid), (flag), (arg0), (arg1), (arg2)); \ +} + +#define PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4) { \ + pl[4] = (uint32_t)(arg4); \ + PM_PACK_PAYLOAD4(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3)); \ +} + +#define PM_PACK_PAYLOAD6(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \ + pl[5] = (uint32_t)(arg5); \ + PM_PACK_PAYLOAD5(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3), (arg4)); \ +} + #endif /* PM_API_SYS_H */ diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c index 4012f32c6..ce5e53384 100644 --- a/plat/xilinx/versal/pm_service/pm_client.c +++ b/plat/xilinx/versal/pm_service/pm_client.c @@ -105,7 +105,7 @@ static enum pm_device_node_idx irq_node_map[IRQ_MAX + 1] = { * * Return: PM node index corresponding to the specified interrupt */ -static enum pm_device_node_idx irq_to_pm_node_idx(unsigned int irq) +static enum pm_device_node_idx irq_to_pm_node_idx(uint32_t irq) { assert(irq <= IRQ_MAX); return irq_node_map[irq]; @@ -170,7 +170,7 @@ static void pm_client_set_wakeup_sources(uint32_t node_id) * required prior to sending suspend request to PMU * Actions taken depend on the state system is suspending to. */ -void pm_client_suspend(const struct pm_proc *proc, unsigned int state) +void pm_client_suspend(const struct pm_proc *proc, uint32_t state) { bakery_lock_get(&pm_client_secure_lock); @@ -211,7 +211,7 @@ void pm_client_abort_suspend(void) * * Return: the cpu ID (starting from 0) for the subsystem */ -static unsigned int pm_get_cpuid(uint32_t nid) +static uint32_t pm_get_cpuid(uint32_t nid) { for (size_t i = 0U; i < ARRAY_SIZE(pm_procs_all); i++) { if (pm_procs_all[i].node_id == nid) { @@ -229,7 +229,7 @@ static unsigned int pm_get_cpuid(uint32_t nid) */ void pm_client_wakeup(const struct pm_proc *proc) { - unsigned int cpuid = pm_get_cpuid(proc->node_id); + uint32_t cpuid = pm_get_cpuid(proc->node_id); if (cpuid == UNDEFINED_CPUID) { return; @@ -251,7 +251,7 @@ void pm_client_wakeup(const struct pm_proc *proc) * * Return: pointer to a proc structure if proc is found, otherwise NULL */ -const struct pm_proc *pm_get_proc(unsigned int cpuid) +const struct pm_proc *pm_get_proc(uint32_t cpuid) { if (cpuid < ARRAY_SIZE(pm_procs_all)) { return &pm_procs_all[cpuid]; diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h index 92061208b..2922b5dd0 100644 --- a/plat/xilinx/versal/pm_service/pm_defs.h +++ b/plat/xilinx/versal/pm_service/pm_defs.h @@ -39,9 +39,7 @@ /* PM API Versions */ #define PM_API_BASE_VERSION 1U -#define PM_API_VERSION_2 2U - -#define PM_API_QUERY_DATA_VERSION 2U +#define PM_API_VERSION_2 2U /* PM API ids */ #define PM_REGISTER_NOTIFIER 5U @@ -62,6 +60,7 @@ /* Loader API ids */ #define PM_LOAD_PDI 0x701U +#define PM_LOAD_GET_HANDOFF_PARAMS 0x70BU /* IOCTL IDs for clock driver */ #define IOCTL_SET_PLL_FRAC_MODE 8U diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c index 24b68e7ef..9eb426a37 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.c +++ b/plat/xilinx/versal/pm_service/pm_svc_main.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,27 +19,52 @@ #include "pm_client.h" #include "pm_ipi.h" #include <drivers/arm/gicv3.h> +#include "../drivers/arm/gic/v3/gicv3_private.h" + +#define MODE 0x80000000U #define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U #define INVALID_SGI 0xFFU +#define PM_INIT_SUSPEND_CB (30U) +#define PM_NOTIFY_CB (32U) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r_el1, S3_0_C12_C11_6) /* pm_up = true - UP, pm_up = false - DOWN */ static bool pm_up; -static unsigned int sgi = (unsigned int)INVALID_SGI; +static uint32_t sgi = (uint32_t)INVALID_SGI; + +static void notify_os(void) +{ + int32_t cpu; + uint32_t reg; + + cpu = plat_my_core_pos() + 1U; + + reg = (cpu | (sgi << XSCUGIC_SGIR_EL1_INITID_SHIFT)); + write_icc_asgi1r_el1(reg); +} static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle, void *cookie) { - unsigned int cpu; - unsigned int reg; + uint32_t payload[4] = {0}; + + VERBOSE("Received IPI FIQ from firmware\n"); (void)plat_ic_acknowledge_interrupt(); - cpu = plat_my_core_pos() + 1U; - if ((unsigned int)sgi != (unsigned int)INVALID_SGI) { - reg = (cpu | ((unsigned int)sgi << (unsigned int)XSCUGIC_SGIR_EL1_INITID_SHIFT)); - write_icc_asgi1r_el1(reg); + pm_get_callbackdata(payload, ARRAY_SIZE(payload), 0, 0); + switch (payload[0]) { + case PM_INIT_SUSPEND_CB: + case PM_NOTIFY_CB: + if (sgi != INVALID_SGI) { + notify_os(); + } + break; + default: + pm_ipi_irq_clear(primary_proc); + WARN("Invalid IPI payload\n"); + break; } /* Clear FIQ */ @@ -59,7 +85,7 @@ static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle, * Update the SGI number to be used. * */ -int pm_register_sgi(unsigned int sgi_num, unsigned int reset) +int32_t pm_register_sgi(uint32_t sgi_num, uint32_t reset) { if (reset == 1U) { sgi = INVALID_SGI; @@ -74,7 +100,7 @@ int pm_register_sgi(unsigned int sgi_num, unsigned int reset) return -EINVAL; } - sgi = (unsigned int)sgi_num; + sgi = (uint32_t)sgi_num; return 0; } @@ -91,18 +117,12 @@ int pm_register_sgi(unsigned int sgi_num, unsigned int reset) * Called from sip_svc_setup initialization function with the * rt_svc_init signature. */ -int pm_setup(void) +int32_t pm_setup(void) { - int status, ret = 0; + int32_t ret = 0; - status = pm_ipi_init(primary_proc); - - if (status < 0) { - INFO("BL31: PM Service Init Failed, Error Code %d!\n", status); - ret = status; - } else { - pm_up = true; - } + pm_ipi_init(primary_proc); + pm_up = true; /* * Enable IPI IRQ @@ -116,6 +136,8 @@ int pm_setup(void) if (ret != 0) { WARN("BL31: registering IPI interrupt failed\n"); } + + gicd_write_irouter(gicv3_driver_data->gicd_base, PLAT_VERSAL_IPI_IRQ, MODE); return ret; } @@ -146,7 +168,7 @@ static uintptr_t eemi_for_compatibility(uint32_t api_id, uint32_t *pm_arg, if (ret == PM_RET_ERROR_NOTSUPPORTED) return (uintptr_t)0; - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); } case PM_QUERY_DATA: @@ -154,10 +176,10 @@ static uintptr_t eemi_for_compatibility(uint32_t api_id, uint32_t *pm_arg, uint32_t data[PAYLOAD_ARG_CNT] = { 0 }; ret = pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2], - pm_arg[3], data, security_flag); + pm_arg[3], data, security_flag); - SMC_RET2(handle, (uint64_t)ret | ((uint64_t)data[0] << 32), - (uint64_t)data[1] | ((uint64_t)data[2] << 32)); + SMC_RET2(handle, (uint64_t)ret | ((uint64_t)data[0] << 32U), + (uint64_t)data[1] | ((uint64_t)data[2] << 32U)); } case PM_FEATURE_CHECK: @@ -165,8 +187,8 @@ static uintptr_t eemi_for_compatibility(uint32_t api_id, uint32_t *pm_arg, uint32_t result[PAYLOAD_ARG_CNT] = {0U}; ret = pm_feature_check(pm_arg[0], result, security_flag); - SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32), - (uint64_t)result[1] | ((uint64_t)result[2] << 32)); + SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U), + (uint64_t)result[1] | ((uint64_t)result[2] << 32U)); } case PM_LOAD_PDI: @@ -201,24 +223,24 @@ static uintptr_t eemi_psci_debugfs_handler(uint32_t api_id, uint32_t *pm_arg, case PM_SELF_SUSPEND: ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], security_flag); - SMC_RET1(handle, (uint64_t)ret); + SMC_RET1(handle, (u_register_t)ret); case PM_FORCE_POWERDOWN: ret = pm_force_powerdown(pm_arg[0], pm_arg[1], security_flag); - SMC_RET1(handle, (uint64_t)ret); + SMC_RET1(handle, (u_register_t)ret); case PM_REQ_SUSPEND: ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], security_flag); - SMC_RET1(handle, (uint64_t)ret); + SMC_RET1(handle, (u_register_t)ret); case PM_ABORT_SUSPEND: ret = pm_abort_suspend(pm_arg[0], security_flag); - SMC_RET1(handle, (uint64_t)ret); + SMC_RET1(handle, (u_register_t)ret); case PM_SYSTEM_SHUTDOWN: ret = pm_system_shutdown(pm_arg[0], pm_arg[1], security_flag); - SMC_RET1(handle, (uint64_t)ret); + SMC_RET1(handle, (u_register_t)ret); default: return (uintptr_t)0; @@ -230,7 +252,7 @@ static uintptr_t eemi_psci_debugfs_handler(uint32_t api_id, uint32_t *pm_arg, * * These EEMI calls performs functionality that does not require * IPI transaction. The handler ends in TF-A and returns requested data to - * kernel from TF-A + * kernel from TF-A. */ static uintptr_t TF_A_specific_handler(uint32_t api_id, uint32_t *pm_arg, void *handle, uint32_t security_flag) @@ -239,7 +261,7 @@ static uintptr_t TF_A_specific_handler(uint32_t api_id, uint32_t *pm_arg, case TF_A_PM_REGISTER_SGI: { - int ret; + int32_t ret; ret = pm_register_sgi(pm_arg[0], pm_arg[1]); if (ret != 0) { @@ -253,15 +275,15 @@ static uintptr_t TF_A_specific_handler(uint32_t api_id, uint32_t *pm_arg, { uint32_t result[4] = {0}; - pm_get_callbackdata(result, ARRAY_SIZE(result), security_flag); + pm_get_callbackdata(result, ARRAY_SIZE(result), security_flag, 1U); SMC_RET2(handle, - (uint64_t)result[0] | ((uint64_t)result[1] << 32), - (uint64_t)result[2] | ((uint64_t)result[3] << 32)); + (uint64_t)result[0] | ((uint64_t)result[1] << 32U), + (uint64_t)result[2] | ((uint64_t)result[3] << 32U)); } case PM_GET_TRUSTZONE_VERSION: SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | - ((uint64_t)VERSAL_TZ_VERSION << 32)); + ((uint64_t)TZ_VERSION << 32U)); default: return (uintptr_t)0; @@ -297,13 +319,13 @@ static uintptr_t eemi_handler(uint32_t api_id, uint32_t *pm_arg, if ((pm_arg[0] == XPM_QID_CLOCK_GET_NAME || pm_arg[0] == XPM_QID_PINCTRL_GET_FUNCTION_NAME) && ret == PM_RET_SUCCESS) { - SMC_RET2(handle, (uint64_t)buf[0] | ((uint64_t)buf[1] << 32), - (uint64_t)buf[2] | ((uint64_t)buf[3] << 32)); + SMC_RET2(handle, (uint64_t)buf[0] | ((uint64_t)buf[1] << 32U), + (uint64_t)buf[2] | ((uint64_t)buf[3] << 32U)); } } - SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buf[0] << 32), - (uint64_t)buf[1] | ((uint64_t)buf[2] << 32)); + SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buf[0] << 32U), + (uint64_t)buf[1] | ((uint64_t)buf[2] << 32U)); } /** @@ -324,7 +346,7 @@ static uintptr_t eemi_handler(uint32_t api_id, uint32_t *pm_arg, * function with rt_svc_handle signature */ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, - uint64_t x4, void *cookie, void *handle, uint64_t flags) + uint64_t x4, const void *cookie, void *handle, uint64_t flags) { uintptr_t ret; uint32_t pm_arg[PAYLOAD_ARG_CNT] = {0}; @@ -332,36 +354,40 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t api_id; /* Handle case where PM wasn't initialized properly */ - if (!pm_up) + if (pm_up == false) { SMC_RET1(handle, SMC_UNK); + } /* * Mark BIT24 payload (i.e 1st bit of pm_arg[3] ) as non-secure (1) * if smc called is non secure */ - if (is_caller_non_secure(flags)) { + if (is_caller_non_secure(flags) != 0) { security_flag = NON_SECURE_FLAG; } pm_arg[0] = (uint32_t)x1; - pm_arg[1] = (uint32_t)(x1 >> 32); + pm_arg[1] = (uint32_t)(x1 >> 32U); pm_arg[2] = (uint32_t)x2; - pm_arg[3] = (uint32_t)(x2 >> 32); + pm_arg[3] = (uint32_t)(x2 >> 32U); pm_arg[4] = (uint32_t)x3; (void)(x4); api_id = smc_fid & FUNCID_NUM_MASK; ret = eemi_for_compatibility(api_id, pm_arg, handle, security_flag); - if (ret != (uintptr_t)0) + if (ret != (uintptr_t)0) { return ret; + } ret = eemi_psci_debugfs_handler(api_id, pm_arg, handle, flags); - if (ret != (uintptr_t)0) + if (ret != (uintptr_t)0) { return ret; + } ret = TF_A_specific_handler(api_id, pm_arg, handle, security_flag); - if (ret != (uintptr_t)0) + if (ret != (uintptr_t)0) { return ret; + } ret = eemi_handler(api_id, pm_arg, handle, security_flag); diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.h b/plat/xilinx/versal/pm_service/pm_svc_main.h index 2dff5b296..b6e764f2c 100644 --- a/plat/xilinx/versal/pm_service/pm_svc_main.h +++ b/plat/xilinx/versal/pm_service/pm_svc_main.h @@ -9,10 +9,10 @@ #include <pm_common.h> -int pm_setup(void); +int32_t pm_setup(void); uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, - uint64_t x4, void *cookie, void *handle, + uint64_t x4, const void *cookie, void *handle, uint64_t flags); -int pm_register_sgi(unsigned int sgi_num, unsigned int reset); +int32_t pm_register_sgi(uint32_t sgi_num, uint32_t reset); #endif /* PM_SVC_MAIN_H */ diff --git a/plat/xilinx/versal/versal_gicv3.c b/plat/xilinx/versal/versal_gicv3.c index 08e7cf95a..d41090699 100644 --- a/plat/xilinx/versal/versal_gicv3.c +++ b/plat/xilinx/versal/versal_gicv3.c @@ -53,7 +53,7 @@ static gicv3_dist_ctx_t dist_ctx __section("versal_el3_tzc_dram"); * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; * - No CPUs implemented in the system use affinity level 3. */ -static unsigned int versal_gicv3_mpidr_hash(u_register_t mpidr) +static uint32_t versal_gicv3_mpidr_hash(u_register_t mpidr) { mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); return versal_calc_core_pos(mpidr); diff --git a/plat/xilinx/versal_net/aarch64/versal_net_common.c b/plat/xilinx/versal_net/aarch64/versal_net_common.c new file mode 100644 index 000000000..c78b5d02e --- /dev/null +++ b/plat/xilinx/versal_net/aarch64/versal_net_common.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <drivers/generic_delay_timer.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> +#include <plat_ipi.h> + +#include <plat_private.h> +#include <versal_net_def.h> + +uint32_t platform_id, platform_version; + +/* + * Table of regions to map using the MMU. + * This doesn't include TZRAM as the 'mem_layout' argument passed to + * configure_mmu_elx() will give the available subset of that, + */ +const mmap_region_t plat_versal_net_mmap[] = { + MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; + +const mmap_region_t *plat_versal_net_get_mmap(void) +{ + return plat_versal_net_mmap; +} + +/* For saving cpu clock for certain platform */ +uint32_t cpu_clock; + +char *board_name_decode(void) +{ + switch (platform_id) { + case VERSAL_NET_SPP: + return "IPP"; + case VERSAL_NET_EMU: + return "EMU"; + case VERSAL_NET_SILICON: + return "Silicon"; + case VERSAL_NET_QEMU: + return "QEMU"; + default: + return "Unknown"; + } +} + +void board_detection(void) +{ + uint32_t version; + + version = mmio_read_32(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + if (platform_id == VERSAL_NET_QEMU_COSIM) { + platform_id = VERSAL_NET_QEMU; + } + + if ((platform_id == VERSAL_NET_SPP) || + (platform_id == VERSAL_NET_EMU) || + (platform_id == VERSAL_NET_QEMU)) { + /* + * 9 is diff for + * 0 means 0.9 version + * 1 means 1.0 version + * 2 means 1.1 version + * etc, + */ + platform_version += 9U; + } + + /* Make sure that console is setup to see this message */ + VERBOSE("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10U, platform_version % 10U); +} + +void versal_net_config_setup(void) +{ + uint32_t val; + uintptr_t crl_base, iou_scntrs_base, psx_base; + + crl_base = VERSAL_NET_CRL; + iou_scntrs_base = VERSAL_NET_IOU_SCNTRS; + psx_base = PSX_CRF; + + /* Reset for system timestamp generator in FPX */ + mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0); + + /* Global timer init - Program time stamp reference clk */ + val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET); + val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val); + + /* Clear reset of timestamp reg */ + mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0); + + /* Program freq register in System counter and enable system counter. */ + mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET, + cpu_clock); + mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET, + VERSAL_NET_IOU_SCNTRS_CONTROL_EN); + + generic_delay_timer_init(); + +#if (TFA_NO_PM == 0) + /* Configure IPI data for versal_net */ + versal_net_ipi_config_table_init(); +#endif +} + +uint32_t plat_get_syscnt_freq2(void) +{ + return cpu_clock; +} diff --git a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S new file mode 100644 index 000000000..48082a68b --- /dev/null +++ b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <drivers/arm/gicv3.h> +#include <platform_def.h> + + .globl plat_secondary_cold_boot_setup + .globl plat_is_my_cpu_primary + .globl platform_mem_init + .globl plat_my_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * TODO: Should we read the PSYS register to make sure + * that the request has gone through. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + mrs x0, mpidr_el1 + + /* + * There is no sane reason to come out of this wfi. This + * cpu will be powered on and reset by the cpu_on pm api + */ + dsb sy + bl plat_panic_handler +endfunc plat_secondary_cold_boot_setup + +func plat_is_my_cpu_primary + mov x9, x30 + bl plat_my_core_pos + cmp x0, #VERSAL_NET_PRIMARY_CPU + cset x0, eq + ret x9 +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_core_pos_by_mpidr() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_core_pos_by_mpidr +endfunc plat_my_core_pos + + /* --------------------------------------------------------------------- + * We don't need to carry out any memory initialization on Versal NET + * platform. The Secure RAM is accessible straight away. + * --------------------------------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init +/* mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE + mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ + mov_imm x2, VERSAL_NET_CONSOLE_BAUDRATE + b console_pl011_core_init */ +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_BASE + b console_pl011_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * void plat_crash_console_flush() + * Function to force a write of all buffered + * data that hasn't been output. + * Out : void. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE + b console_pl011_core_flush +endfunc plat_crash_console_flush diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c new file mode 100644 index 000000000..c9942d6a5 --- /dev/null +++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> + +#include <bl31/bl31.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <common/fdt_fixup.h> +#include <common/fdt_wrappers.h> +#include <drivers/arm/pl011.h> +#include <drivers/console.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <libfdt.h> +#include <plat/common/platform.h> +#include <plat_arm.h> + +#include <plat_private.h> +#include <plat_startup.h> +#include <versal_net_def.h> + +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; +static console_t versal_net_runtime_console; + +/* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + */ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + assert(sec_state_is_valid(type)); + + if (type == NON_SECURE) { + return &bl33_image_ep_info; + } + + return &bl32_image_ep_info; +} + +/* + * Set the build time defaults,if we can't find any config data. + */ +static inline void bl31_set_default_config(void) +{ + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); +} + +/* + * Perform any BL31 specific platform actions. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. + */ +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + uint32_t uart_clock; + int32_t rc; + + board_detection(); + + switch (platform_id) { + case VERSAL_NET_SPP: + cpu_clock = 1000000; + uart_clock = 1000000; + break; + case VERSAL_NET_EMU: + cpu_clock = 3660000; + uart_clock = 25000000; + break; + case VERSAL_NET_QEMU: + /* Random values now */ + cpu_clock = 100000000; + uart_clock = 25000000; + break; + case VERSAL_NET_SILICON: + cpu_clock = 100000000; + uart_clock = 100000000; + break; + default: + panic(); + } + + /* Initialize the console to provide early debug support */ + rc = console_pl011_register(VERSAL_NET_UART_BASE, uart_clock, + VERSAL_NET_UART_BAUDRATE, + &versal_net_runtime_console); + if (rc == 0) { + panic(); + } + + console_set_scope(&versal_net_runtime_console, CONSOLE_FLAG_BOOT | + CONSOLE_FLAG_RUNTIME); + + NOTICE("TF-A running on Xilinx %s %d.%d\n", board_name_decode(), + platform_version / 10U, platform_version % 10U); + + /* Initialize the platform config for future decision making */ + versal_net_config_setup(); + /* There are no parameters from BL2 if BL31 is a reset vector */ + assert(arg0 == 0U); + assert(arg1 == 0U); + + /* + * Do initial security configuration to allow DRAM/device access. On + * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but + * other platforms might have more programmable security devices + * present. + */ + + /* Populate common information for BL32 and BL33 */ + SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + + bl31_set_default_config(); + + NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); + NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); +} + +static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; + +int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) +{ + static uint32_t index; + uint32_t i; + + /* Validate 'handler' and 'id' parameters */ + if (handler == NULL || index >= MAX_INTR_EL3) { + return -EINVAL; + } + + /* Check if a handler has already been registered */ + for (i = 0; i < index; i++) { + if (id == type_el3_interrupt_table[i].id) { + return -EALREADY; + } + } + + type_el3_interrupt_table[index].id = id; + type_el3_interrupt_table[index].handler = handler; + + index++; + + return 0; +} + +static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, + void *handle, void *cookie) +{ + uint32_t intr_id; + uint32_t i; + interrupt_type_handler_t handler = NULL; + + intr_id = plat_ic_get_pending_interrupt_id(); + + for (i = 0; i < MAX_INTR_EL3; i++) { + if (intr_id == type_el3_interrupt_table[i].id) { + handler = type_el3_interrupt_table[i].handler; + } + } + + if (handler != NULL) { + handler(intr_id, flags, handle, cookie); + } + + return 0; +} + +void bl31_platform_setup(void) +{ + /* Initialize the gic cpu and distributor interfaces */ + plat_versal_net_gic_driver_init(); + plat_versal_net_gic_init(); +} + +void bl31_plat_runtime_setup(void) +{ + uint64_t flags = 0; + int32_t rc; + + set_interrupt_rm_flag(flags, NON_SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_EL3, + rdo_el3_interrupt_handler, flags); + if (rc != 0) { + panic(); + } +} + +/* + * Perform the very early platform specific architectural setup here. + */ +void bl31_plat_arch_setup(void) +{ + const mmap_region_t bl_regions[] = { + MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE), + MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, + MT_RO_DATA | MT_SECURE), + {0} + }; + + setup_page_tables(bl_regions, plat_versal_net_get_mmap()); + enable_mmu(0); +} diff --git a/plat/xilinx/versal_net/include/plat_ipi.h b/plat/xilinx/versal_net/include/plat_ipi.h new file mode 100644 index 000000000..5255f8f56 --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_ipi.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Versal IPI management enums and defines */ + +#ifndef PLAT_IPI_H +#define PLAT_IPI_H + +#include <stdint.h> + +#include <ipi.h> + +/********************************************************************* + * IPI agent IDs macros + ********************************************************************/ +#define IPI_ID_PMC 1U +#define IPI_ID_APU 2U +#define IPI_ID_RPU0 3U +#define IPI_ID_RPU1 4U +#define IPI_ID_3 5U +#define IPI_ID_4 6U +#define IPI_ID_5 7U +#define IPI_ID_MAX 8U + +/********************************************************************* + * IPI message buffers + ********************************************************************/ +#define IPI_BUFFER_BASEADDR (0xEB3F0000U) + +#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U) +#define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U) + +#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U +#define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U + +#define IPI_BUFFER_LOCAL_BASE IPI_BUFFER_APU_BASE +#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMC_BASE + +#define IPI_BUFFER_TARGET_LOCAL_OFFSET IPI_BUFFER_TARGET_APU_OFFSET +#define IPI_BUFFER_TARGET_REMOTE_OFFSET IPI_BUFFER_TARGET_PMC_OFFSET + +#define IPI_BUFFER_MAX_WORDS 8 + +#define IPI_BUFFER_REQ_OFFSET 0x0U +#define IPI_BUFFER_RESP_OFFSET 0x20U + +/********************************************************************* + * Platform specific IPI API declarations + ********************************************************************/ + +/* Configure IPI table for versal_net */ +void versal_net_ipi_config_table_init(void); + +#endif /* PLAT_IPI_H */ diff --git a/plat/xilinx/versal_net/include/plat_macros.S b/plat/xilinx/versal_net/include/plat_macros.S new file mode 100644 index 000000000..fb108b67c --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_macros.S @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <drivers/arm/gic_common.h> +#include <drivers/arm/gicv2.h> +#include <drivers/arm/gicv3.h> + +#include "../include/platform_def.h" + +.section .rodata.gic_reg_name, "aS" +/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" + +/* Applicable only to GICv3 with SRE enabled */ +icc_regs: + .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" + +/* Registers common to both GICv2 and GICv3 */ +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below utility macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL31 on Versal NET platform. + * Expects: GICD base in x16, GICC base in x17 + * Clobbers: x0 - x10, sp + * --------------------------------------------- + */ + .macro versal_net_print_gic_regs + /* Check for GICv3 system register access */ + mrs x7, id_aa64pfr0_el1 + ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH + cmp x7, #1 + b.ne print_gicv2 + + /* Check for SRE enable */ + mrs x8, ICC_SRE_EL3 + tst x8, #ICC_SRE_SRE_BIT + b.eq print_gicv2 + + /* Load the icc reg list to x6 */ + adr x6, icc_regs + /* Load the icc regs to gp regs used by str_in_crash_buf_print */ + mrs x8, ICC_HPPIR0_EL1 + mrs x9, ICC_HPPIR1_EL1 + mrs x10, ICC_CTLR_EL3 + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + b print_gic_common + +print_gicv2: + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + +print_gic_common: + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + /* + * Empty for now to handle more platforms variant. + * Uncomment it when versions are stable + */ + /* + mov_imm x17, PLAT_VERSAL_NET_GICD_BASE + mov_imm x16, PLAT_VERSAL_NET_GICR_BASE + versal_net_print_gic_regs + */ + .endm + +#endif /* PLAT_MACROS_S */ diff --git a/plat/xilinx/versal_net/include/plat_pm_common.h b/plat/xilinx/versal_net/include/plat_pm_common.h new file mode 100644 index 000000000..ad7b40f6d --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_pm_common.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Contains platform specific definitions of commonly used macros data types + * for PU Power Management. This file should be common for all PU's. + */ + +#ifndef PLAT_PM_COMMON_H +#define PLAT_PM_COMMON_H + +#include <stdint.h> + +#include <common/debug.h> + +#include "pm_defs.h" + +#define NON_SECURE_FLAG 1U +#define SECURE_FLAG 0U + +#endif /* PLAT_PM_COMMON_H */ diff --git a/plat/xilinx/versal_net/include/plat_private.h b/plat/xilinx/versal_net/include/plat_private.h new file mode 100644 index 000000000..6a3bc19d0 --- /dev/null +++ b/plat/xilinx/versal_net/include/plat_private.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_PRIVATE_H +#define PLAT_PRIVATE_H + +#include <bl31/interrupt_mgmt.h> +#include <lib/xlat_tables/xlat_tables_v2.h> + +typedef struct versal_intr_info_type_el3 { + uint32_t id; + interrupt_type_handler_t handler; +} versal_intr_info_type_el3_t; + +void versal_net_config_setup(void); + +const mmap_region_t *plat_versal_net_get_mmap(void); + +void plat_versal_net_gic_driver_init(void); +void plat_versal_net_gic_init(void); +void plat_versal_net_gic_cpuif_enable(void); +void plat_versal_net_gic_cpuif_disable(void); +void plat_versal_net_gic_pcpu_init(void); +void plat_versal_net_gic_save(void); +void plat_versal_net_gic_resume(void); +void plat_versal_net_gic_redistif_on(void); +void plat_versal_net_gic_redistif_off(void); + +extern uint32_t cpu_clock, platform_id, platform_version; +void board_detection(void); +char *board_name_decode(void); +uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, void *handle, uint64_t flags); +int32_t sip_svc_setup_init(void); +/* + * Register handler to specific GIC entrance + * for INTR_TYPE_EL3 type of interrupt + */ +int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler); + +#define PM_GET_CHIPID (24U) +#define IOCTL_OSPI_MUX_SELECT (21U) + +#endif /* PLAT_PRIVATE_H */ diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h new file mode 100644 index 000000000..696771f46 --- /dev/null +++ b/plat/xilinx/versal_net/include/platform_def.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include "versal_net_def.h" + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#define PLATFORM_STACK_SIZE U(0x440) + +#define PLATFORM_CLUSTER_COUNT U(4) +#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) /* 4 CPUs per cluster */ + +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) + +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#ifndef VERSAL_NET_ATF_MEM_BASE +# define BL31_BASE U(0xBBF00000) +# define BL31_LIMIT U(0xBBFFFFFF) +#else +# define BL31_BASE U(VERSAL_NET_ATF_MEM_BASE) +# define BL31_LIMIT U(VERSAL_NET_ATF_MEM_BASE + VERSAL_NET_ATF_MEM_SIZE - 1) +# ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE +# define BL31_PROGBITS_LIMIT U(VERSAL_NET_ATF_MEM_BASE + \ + VERSAL_NET_ATF_MEM_PROGBITS_SIZE - 1) +# endif +#endif + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#ifndef VERSAL_NET_BL32_MEM_BASE +# define BL32_BASE U(0x60000000) +# define BL32_LIMIT U(0x7FFFFFFF) +#else +# define BL32_BASE U(VERSAL_NET_BL32_MEM_BASE) +# define BL32_LIMIT U(VERSAL_NET_BL32_MEM_BASE + VERSAL_NET_BL32_MEM_SIZE - 1) +#endif + +/******************************************************************************* + * BL33 specific defines. + ******************************************************************************/ +#ifndef PRELOADED_BL33_BASE +# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) +#else +# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) +#endif + +/******************************************************************************* + * TSP specific defines. + ******************************************************************************/ +#define TSP_SEC_MEM_BASE BL32_BASE +#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1U) + +/* ID of the secure physical generic timer interrupt used by the TSP */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_DDR_LOWMEM_MAX U(0x80000000) + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) +#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#define MAX_MMAP_REGIONS U(10) +#else +#define MAX_MMAP_REGIONS U(9) +#endif + +#define MAX_XLAT_TABLES U(8) + +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#define PLAT_VERSAL_NET_GICD_BASE U(0xE2000000) +#define PLAT_VERSAL_NET_GICR_BASE U(0xE2060000) + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_VERSAL_IPI_IRQ 62 + +#define PLAT_VERSAL_NET_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#define PLAT_VERSAL_NET_G0_IRQ_PROPS(grp) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h new file mode 100644 index 000000000..8cb5bf3a3 --- /dev/null +++ b/plat/xilinx/versal_net/include/versal_net_def.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef VERSAL_NET_DEF_H +#define VERSAL_NET_DEF_H + +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +#define MAX_INTR_EL3 2 +/* This part is taken from U-Boot project under GPL that's why dual license above */ +#define __bf_shf(x) (__builtin_ffsll(x) - 1U) +#define FIELD_GET(_mask, _reg) \ + ({ \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + +/* List all consoles */ +#define VERSAL_NET_CONSOLE_ID_pl011 U(1) +#define VERSAL_NET_CONSOLE_ID_pl011_0 U(1) +#define VERSAL_NET_CONSOLE_ID_pl011_1 U(2) + +#define VERSAL_NET_CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE) + +/* List all platforms */ +#define VERSAL_NET_SILICON U(0) +#define VERSAL_NET_SPP U(1) +#define VERSAL_NET_EMU U(2) +#define VERSAL_NET_QEMU U(3) +#define VERSAL_NET_QEMU_COSIM U(7) + +/* For platform detection */ +#define PMC_TAP U(0xF11A0000) +#define PMC_TAP_VERSION (PMC_TAP + 0x4U) +# define PLATFORM_MASK GENMASK(27U, 24U) +# define PLATFORM_VERSION_MASK GENMASK(31U, 28U) + +/* Global timer reset */ +#define PSX_CRF U(0xEC200000) +#define ACPU0_CLK_CTRL U(0x10C) +#define ACPU_CLK_CTRL_CLKACT BIT(25) + +#define RST_APU0_OFFSET U(0x300) +#define RST_APU_COLD_RESET BIT(0) +#define RST_APU_WARN_RESET BIT(4) +#define RST_APU_CLUSTER_COLD_RESET BIT(8) +#define RST_APU_CLUSTER_WARM_RESET BIT(9) + +#define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) + +#define APU_PCLI U(0xECB10000) +#define APU_PCLI_CPU_STEP U(0x30) +#define APU_PCLI_CLUSTER_CPU_STEP (4U * APU_PCLI_CPU_STEP) +#define APU_PCLI_CLUSTER_OFFSET U(0x8000) +#define APU_PCLI_CLUSTER_STEP U(0x1000) +#define PCLI_PREQ_OFFSET U(0x4) +#define PREQ_CHANGE_REQUEST BIT(0) +#define PCLI_PSTATE_OFFSET U(0x8) +#define PCLI_PSTATE_VAL_SET U(0x48) +#define PCLI_PSTATE_VAL_CLEAR U(0x38) + +/* Firmware Image Package */ +#define VERSAL_NET_PRIMARY_CPU U(0) + +#define CORE_0_IEN_POWER_OFFSET (0x00000018U) +#define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ + (0x30 * cpu_id))) +#define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) +#define CORE_0_IDS_POWER_OFFSET (0x0000001CU) +#define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ + (0x30 * cpu_id))) +#define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) +#define CORE_PWRDN_EN_BIT_MASK (0x1U) + +/******************************************************************************* + * memory map related constants + ******************************************************************************/ +/* IPP 1.2/SPP 0.9 mapping */ +#define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ +#define DEVICE0_SIZE U(0x08000000) +#define DEVICE1_BASE U(0xE2000000) /* gic */ +#define DEVICE1_SIZE U(0x00800000) +#define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ +#define DEVICE2_SIZE U(0x01000000) +#define CRF_BASE U(0xFD1A0000) +#define CRF_SIZE U(0x00600000) +#define IPI_BASE U(0xEB300000) +#define IPI_SIZE U(0x00100000) + +/* CRL */ +#define VERSAL_NET_CRL U(0xEB5E0000) +#define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) +#define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348) + +#define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) + +/* IOU SCNTRS */ +#define VERSAL_NET_IOU_SCNTRS U(0xEC920000) +#define VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) +#define VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) + +#define VERSAL_NET_IOU_SCNTRS_CONTROL_EN U(1) + +#define APU_CLUSTER0 U(0xECC00000) +#define APU_RVBAR_L_0 U(0x40) +#define APU_RVBAR_H_0 U(0x44) +#define APU_CLUSTER_STEP U(0x100000) + +#define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) + +/******************************************************************************* + * IRQ constants + ******************************************************************************/ +#define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define VERSAL_NET_UART0_BASE U(0xF1920000) +#define VERSAL_NET_UART_BAUDRATE 115200 + +#define VERSAL_NET_UART_BASE VERSAL_NET_UART0_BASE + +#define PLAT_VERSAL_NET_CRASH_UART_BASE VERSAL_NET_UART_BASE +#define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ VERSAL_NET_UART_CLOCK +#define VERSAL_NET_CONSOLE_BAUDRATE VERSAL_NET_UART_BAUDRATE + +/******************************************************************************* + * IPI registers and bitfields + ******************************************************************************/ +#define IPI0_REG_BASE (0xEB330000U) +#define IPI0_TRIG_BIT (1 << 2) +#define PMC_IPI_TRIG_BIT (1 << 1) +#define IPI1_REG_BASE (0xEB340000U) +#define IPI1_TRIG_BIT (1 << 3) +#define IPI2_REG_BASE (0xEB350000U) +#define IPI2_TRIG_BIT (1 << 4) +#define IPI3_REG_BASE (0xEB360000U) +#define IPI3_TRIG_BIT (1 << 5) +#define IPI4_REG_BASE (0xEB370000U) +#define IPI4_TRIG_BIT (1 << 6) +#define IPI5_REG_BASE (0xEB380000U) +#define IPI5_TRIG_BIT (1 << 7) + +/* Processor core device IDs */ +#define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU) +#define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U) +#define PM_DEV_CLUSTER0_ACPU_2 (0x1810C0B1U) +#define PM_DEV_CLUSTER0_ACPU_3 (0x1810C0B2U) + +#define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U) +#define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U) +#define PM_DEV_CLUSTER1_ACPU_2 (0x1810C0B5U) +#define PM_DEV_CLUSTER1_ACPU_3 (0x1810C0B6U) + +#define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U) +#define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U) +#define PM_DEV_CLUSTER2_ACPU_2 (0x1810C0B9U) +#define PM_DEV_CLUSTER2_ACPU_3 (0x1810C0BAU) + +#define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU) +#define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU) +#define PM_DEV_CLUSTER3_ACPU_2 (0x1810C0BDU) +#define PM_DEV_CLUSTER3_ACPU_3 (0x1810C0BEU) + +#endif /* VERSAL_NET_DEF_H */ diff --git a/plat/xilinx/versal_net/plat_psci.c b/plat/xilinx/versal_net/plat_psci.c new file mode 100644 index 000000000..c5833a9ae --- /dev/null +++ b/plat/xilinx/versal_net/plat_psci.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <lib/mmio.h> +#include <lib/psci/psci.h> +#include <plat/arm/common/plat_arm.h> +#include <plat/common/platform.h> +#include <plat_arm.h> + +#include <plat_private.h> + +#define PM_RET_ERROR_NOFEATURE U(19) + +#define PM_IOCTL 34U + +static uintptr_t versal_net_sec_entry; + +static void zynqmp_cpu_standby(plat_local_state_t cpu_state) +{ + dsb(); + wfi(); +} + +static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr) +{ + uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); + uint32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER; + uint32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER; + uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0; + uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + (cluster * 0x4); + + VERBOSE("%s: mpidr: 0x%lx, cpuid: %x, cpu: %x, cluster: %x\n", + __func__, mpidr, cpu_id, cpu, cluster); + + if (cpu_id == -1) { + return PSCI_E_INTERN_FAIL; + } + + if (platform_id == VERSAL_NET_SPP && cluster > 1) { + panic(); + } + + if (cluster > 3) { + panic(); + } + + apu_pcli_cluster = APU_PCLI + APU_PCLI_CLUSTER_OFFSET + (cluster * APU_PCLI_CLUSTER_STEP); + apu_cluster_base = APU_CLUSTER0 + (cluster * APU_CLUSTER_STEP); + + /* Enable clock */ + mmio_setbits_32(PSX_CRF + ACPU0_CLK_CTRL + (cluster * 0x4), ACPU_CLK_CTRL_CLKACT); + + /* Enable cluster states */ + mmio_setbits_32(apu_pcli_cluster + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_SET); + mmio_setbits_32(apu_pcli_cluster + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST); + + /* assert core reset */ + mmio_setbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); + + /* program RVBAR */ + mmio_write_32(apu_cluster_base + APU_RVBAR_L_0 + (cpu << 3), + (uint32_t)versal_net_sec_entry); + mmio_write_32(apu_cluster_base + APU_RVBAR_H_0 + (cpu << 3), + versal_net_sec_entry >> 32); + + /* de-assert core reset */ + mmio_clrbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); + + /* clear cluster resets */ + mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_WARM_RESET); + mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_COLD_RESET); + + apu_pcli_base = APU_PCLI + (APU_PCLI_CPU_STEP * cpu) + + (APU_PCLI_CLUSTER_CPU_STEP * cluster); + + mmio_write_32(apu_pcli_base + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_CLEAR); + mmio_write_32(apu_pcli_base + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST); + + return PSCI_E_SUCCESS; +} + +static void zynqmp_nopmu_pwr_domain_off(const psci_power_state_t *target_state) +{ +} + +static void __dead2 zynqmp_nopmu_system_reset(void) +{ + while (1) + wfi(); +} + +static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint) +{ + return PSCI_E_SUCCESS; +} + +static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) +{ +} + +static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + plat_versal_net_gic_pcpu_init(); + plat_versal_net_gic_cpuif_enable(); +} + +static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ +} + +static void __dead2 zynqmp_system_off(void) +{ + while (1) + wfi(); +} + +static int32_t zynqmp_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) +{ + return PSCI_E_SUCCESS; +} + +static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; + req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; +} + +static const struct plat_psci_ops versal_net_nopmc_psci_ops = { + .cpu_standby = zynqmp_cpu_standby, + .pwr_domain_on = zynqmp_nopmu_pwr_domain_on, + .pwr_domain_off = zynqmp_nopmu_pwr_domain_off, + .system_reset = zynqmp_nopmu_system_reset, + .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint, + .pwr_domain_suspend = zynqmp_pwr_domain_suspend, + .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, + .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, + .system_off = zynqmp_system_off, + .validate_power_state = zynqmp_validate_power_state, + .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, +}; + +/******************************************************************************* + * Export the platform specific power ops. + ******************************************************************************/ +int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, + const struct plat_psci_ops **psci_ops) +{ + versal_net_sec_entry = sec_entrypoint; + + VERBOSE("Setting up entry point %lx\n", versal_net_sec_entry); + + *psci_ops = &versal_net_nopmc_psci_ops; + + return 0; +} + +int sip_svc_setup_init(void) +{ + return 0; +} + +static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id, + uint32_t arg1, uint32_t arg2) +{ + VERBOSE("%s: ioctl_id: %x, arg1: %x\n", __func__, ioctl_id, arg1); + if (ioctl_id == IOCTL_OSPI_MUX_SELECT) { + mmio_write_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, arg1); + return 0; + } + return PM_RET_ERROR_NOFEATURE; +} + +static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, void *handle, uint64_t flags) +{ + int32_t ret; + uint32_t arg[4], api_id; + + arg[0] = (uint32_t)x1; + arg[1] = (uint32_t)(x1 >> 32); + arg[2] = (uint32_t)x2; + arg[3] = (uint32_t)(x2 >> 32); + + api_id = smc_fid & FUNCID_NUM_MASK; + VERBOSE("%s: smc_fid: %x, api_id=0x%x\n", __func__, smc_fid, api_id); + + switch (api_id) { + case PM_IOCTL: + { + ret = no_pm_ioctl(arg[0], arg[1], arg[2], arg[3]); + SMC_RET1(handle, (uint64_t)ret); + } + case PM_GET_CHIPID: + { + uint32_t idcode, version; + + idcode = mmio_read_32(PMC_TAP); + version = mmio_read_32(PMC_TAP_VERSION); + SMC_RET2(handle, ((uint64_t)idcode << 32), version); + } + default: + WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} + +uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, + void *cookie, void *handle, uint64_t flags) +{ + return no_pm_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); +} diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c new file mode 100644 index 000000000..8beaa9a57 --- /dev/null +++ b/plat/xilinx/versal_net/plat_psci_pm.c @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <common/debug.h> +#include <lib/mmio.h> +#include <lib/psci/psci.h> +#include <plat/arm/common/plat_arm.h> +#include <plat/common/platform.h> +#include <plat_arm.h> + +#include <plat_private.h> +#include "pm_api_sys.h" +#include "pm_client.h" +#include <pm_common.h> +#include "pm_svc_main.h" +#include "versal_net_def.h" + +static uintptr_t versal_net_sec_entry; + +static int32_t versal_net_pwr_domain_on(u_register_t mpidr) +{ + uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); + const struct pm_proc *proc; + + VERBOSE("%s: mpidr: 0x%lx, cpuid: %x\n", + __func__, mpidr, cpu_id); + + if (cpu_id == -1) { + return PSCI_E_INTERN_FAIL; + } + + proc = pm_get_proc(cpu_id); + if (!proc) { + return PSCI_E_INTERN_FAIL; + } + + pm_req_wakeup(proc->node_id, (versal_net_sec_entry & 0xFFFFFFFFU) | 0x1U, + versal_net_sec_entry >> 32, 0, 0); + + /* Clear power down request */ + pm_client_wakeup(proc); + + return PSCI_E_SUCCESS; +} + +/** + * versal_net_pwr_domain_off() - This function performs actions to turn off core + * + * @param target_state Targeted state + */ +static void versal_net_pwr_domain_off(const psci_power_state_t *target_state) +{ + uint32_t cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + } + + /* Prevent interrupts from spuriously waking up this cpu */ + plat_versal_net_gic_cpuif_disable(); + + /* + * Send request to PMC to power down the appropriate APU CPU + * core. + * According to PSCI specification, CPU_off function does not + * have resume address and CPU core can only be woken up + * invoking CPU_on function, during which resume address will + * be set. + */ + pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0, + SECURE_FLAG); +} + +/** + * versal_net_system_reset() - This function sends the reset request + * to firmware for the system to reset. This function does not return. + */ +static void __dead2 versal_net_system_reset(void) +{ + /* Send the system reset request to the PMC */ + pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, + pm_get_shutdown_scope(), SECURE_FLAG); + + while (1) { + wfi(); + } +} + +/** + * versal_net_pwr_domain_suspend() - This function sends request to PMC to suspend + * core. + * + * @param target_state Targeted state + */ +static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + uint32_t state; + uint32_t cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + } + + plat_versal_net_gic_cpuif_disable(); + + if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { + plat_versal_net_gic_save(); + } + + state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? + PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; + + /* Send request to PMC to suspend this core */ + pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_net_sec_entry, + SECURE_FLAG); + + /* TODO: disable coherency */ +} + +static void versal_net_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + (void)target_state; + + /* Enable the gic cpu interface */ + plat_versal_net_gic_pcpu_init(); + + /* Program the gic per-cpu distributor or re-distributor interface */ + plat_versal_net_gic_cpuif_enable(); +} + +/** + * versal_net_pwr_domain_suspend_finish() - This function performs actions to finish + * suspend procedure. + * + * @param target_state Targeted state + */ +static void versal_net_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + uint32_t cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* Clear the APU power control register for this cpu */ + pm_client_wakeup(proc); + + /* TODO: enable coherency */ + + /* APU was turned off, so restore GIC context */ + if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { + plat_versal_net_gic_resume(); + } + + plat_versal_net_gic_cpuif_enable(); +} + +/** + * versal_net_system_off() - This function sends the system off request + * to firmware. This function does not return. + */ +static void __dead2 versal_net_system_off(void) +{ + /* Send the power down request to the PMC */ + pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, + pm_get_shutdown_scope(), SECURE_FLAG); + + while (1) { + wfi(); + } +} + +/** + * versal_net_validate_power_state() - This function ensures that the power state + * parameter in request is valid. + * + * @param power_state Power state of core + * @param req_state Requested state + * + * @return Returns status, either PSCI_E_SUCCESS or reason + */ +static int32_t versal_net_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); + + int32_t pstate = psci_get_pstate_type(power_state); + + assert(req_state); + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) { + req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; + } else { + req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; + } + + /* We expect the 'state id' to be zero */ + if (psci_get_pstate_id(power_state)) { + return PSCI_E_INVALID_PARAMS; + } + + return PSCI_E_SUCCESS; +} + +/** + * versal_net_get_sys_suspend_power_state() - Get power state for system suspend + * + * @param req_state Requested state + */ +static void versal_net_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; + req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; +} + +static const struct plat_psci_ops versal_net_nopmc_psci_ops = { + .pwr_domain_on = versal_net_pwr_domain_on, + .pwr_domain_off = versal_net_pwr_domain_off, + .pwr_domain_on_finish = versal_net_pwr_domain_on_finish, + .pwr_domain_suspend = versal_net_pwr_domain_suspend, + .pwr_domain_suspend_finish = versal_net_pwr_domain_suspend_finish, + .system_off = versal_net_system_off, + .system_reset = versal_net_system_reset, + .validate_power_state = versal_net_validate_power_state, + .get_sys_suspend_power_state = versal_net_get_sys_suspend_power_state, +}; + +/******************************************************************************* + * Export the platform specific power ops. + ******************************************************************************/ +int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, + const struct plat_psci_ops **psci_ops) +{ + versal_net_sec_entry = sec_entrypoint; + + VERBOSE("Setting up entry point %lx\n", versal_net_sec_entry); + + *psci_ops = &versal_net_nopmc_psci_ops; + + return 0; +} + +int32_t sip_svc_setup_init(void) +{ + return pm_setup(); +} + +uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, + void *cookie, void *handle, uint64_t flags) +{ + return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); +} diff --git a/plat/xilinx/versal_net/plat_topology.c b/plat/xilinx/versal_net/plat_topology.c new file mode 100644 index 000000000..7f985b0a5 --- /dev/null +++ b/plat/xilinx/versal_net/plat_topology.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <plat/common/platform.h> + +#include <plat_private.h> +#include <platform_def.h> + +static const uint8_t plat_power_domain_tree_desc[] = { + /* Number of root nodes */ + 1, + /* Number of clusters */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, + /* Number of children for the second cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, + /* Number of children for the third cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, + /* Number of children for the fourth cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, +}; + +const uint8_t *plat_get_power_domain_tree_desc(void) +{ + return plat_power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int32_t plat_core_pos_by_mpidr(u_register_t mpidr) +{ + uint32_t cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + + cluster_id = MPIDR_AFFLVL2_VAL(mpidr); + cpu_id = MPIDR_AFFLVL1_VAL(mpidr); + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) { + return -3; + } + + /* + * Validate cpu_id by checking whether it represents a CPU in + * one of the two clusters present on the platform. + */ + if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) { + return -1; + } + + return (cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER)); +} diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk new file mode 100644 index 000000000..b3d56bcc4 --- /dev/null +++ b/plat/xilinx/versal_net/platform.mk @@ -0,0 +1,102 @@ +# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. +# Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +PLAT_PATH := plat/xilinx/versal_net + +# A78 Erratum for SoC +ERRATA_A78_AE_1941500 := 1 +ERRATA_A78_AE_1951502 := 1 +ERRATA_A78_AE_2376748 := 1 +ERRATA_A78_AE_2395408 := 1 + +override PROGRAMMABLE_RESET_ADDRESS := 1 +PSCI_EXTENDED_STATE_ID := 1 +SEPARATE_CODE_AND_RODATA := 1 +override RESET_TO_BL31 := 1 +PL011_GENERIC_UART := 1 +GIC_ENABLE_V4_EXTN := 0 +GICV3_SUPPORT_GIC600 := 1 +TFA_NO_PM := 0 + +override CTX_INCLUDE_AARCH32_REGS := 0 + +ifdef TFA_NO_PM + $(eval $(call add_define,TFA_NO_PM)) +endif + +ifdef VERSAL_NET_ATF_MEM_BASE + $(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE)) + + ifndef VERSAL_NET_ATF_MEM_SIZE + $(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE") + endif + $(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE)) + + ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE + $(eval $(call add_define,VERSAL_NET_ATF_MEM_PROGBITS_SIZE)) + endif +endif + +ifdef VERSAL_NET_BL32_MEM_BASE + $(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE)) + + ifndef VERSAL_NET_BL32_MEM_SIZE + $(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE") + endif + $(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE)) +endif + +USE_COHERENT_MEM := 0 +HW_ASSISTED_COHERENCY := 1 + +VERSAL_NET_CONSOLE ?= pl011 +$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE})) + +PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ + -Iplat/xilinx/common/include/ \ + -Iplat/xilinx/common/ipi_mailbox_service/ \ + -I${PLAT_PATH}/include/ \ + -Iplat/xilinx/versal/pm_service/ + +# Include GICv3 driver files +include drivers/arm/gic/v3/gicv3.mk +include lib/xlat_tables_v2/xlat_tables.mk +include lib/libfdt/libfdt.mk + +PLAT_BL_COMMON_SOURCES := \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + ${GICV3_SOURCES} \ + drivers/arm/pl011/aarch64/pl011_console.S \ + plat/arm/common/arm_common.c \ + plat/common/plat_gicv3.c \ + ${PLAT_PATH}/aarch64/versal_net_helpers.S \ + ${PLAT_PATH}/aarch64/versal_net_common.c + +BL31_SOURCES += drivers/arm/cci/cci.c \ + lib/cpus/aarch64/cortex_a78_ae.S \ + lib/cpus/aarch64/cortex_a78.S \ + plat/common/plat_psci_common.c +ifeq ($(TFA_NO_PM), 0) +BL31_SOURCES += plat/xilinx/versal/pm_service/pm_api_sys.c \ + plat/xilinx/common/pm_service/pm_ipi.c \ + ${PLAT_PATH}/plat_psci_pm.c \ + plat/xilinx/versal/pm_service/pm_svc_main.c \ + ${PLAT_PATH}/pm_service/pm_client.c \ + ${PLAT_PATH}/versal_net_ipi.c +else +BL31_SOURCES += ${PLAT_PATH}/plat_psci.c +endif +BL31_SOURCES += plat/xilinx/common/plat_startup.c \ + plat/xilinx/common/ipi.c \ + plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ + ${PLAT_PATH}/bl31_versal_net_setup.c \ + ${PLAT_PATH}/plat_topology.c \ + common/fdt_fixup.c \ + ${LIBFDT_SRCS} \ + ${PLAT_PATH}/sip_svc_setup.c \ + ${PLAT_PATH}/versal_net_gicv3.c \ + ${XLAT_TABLES_LIB_SRCS} diff --git a/plat/xilinx/versal_net/pm_service/pm_client.c b/plat/xilinx/versal_net/pm_service/pm_client.c new file mode 100644 index 000000000..648732415 --- /dev/null +++ b/plat/xilinx/versal_net/pm_service/pm_client.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * APU specific definition of processors in the subsystem as well as functions + * for getting information about and changing state of the APU. + */ + +#include <assert.h> + +#include <drivers/arm/gic_common.h> +#include <drivers/arm/gicv3.h> +#include <lib/bakery_lock.h> +#include <lib/mmio.h> +#include <lib/mmio.h> +#include <lib/utils.h> +#include <plat/common/platform.h> + +#include <plat_ipi.h> +#include <platform_def.h> +#include "pm_api_sys.h" +#include "pm_client.h" +#include <versal_net_def.h> + +#define UNDEFINED_CPUID (~0) + +DEFINE_RENAME_SYSREG_RW_FUNCS(cpu_pwrctrl_val, S3_0_C15_C2_7) +DEFINE_BAKERY_LOCK(pm_client_secure_lock); + +static const struct pm_ipi apu_ipi = { + .local_ipi_id = IPI_ID_APU, + .remote_ipi_id = IPI_ID_PMC, + .buffer_base = IPI_BUFFER_APU_BASE, +}; + +/* Order in pm_procs_all array must match cpu ids */ +static const struct pm_proc pm_procs_all[] = { + { + .node_id = PM_DEV_CLUSTER0_ACPU_0, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER0_ACPU_1, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER0_ACPU_2, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER0_ACPU_3, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER1_ACPU_0, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER1_ACPU_1, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER1_ACPU_2, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER1_ACPU_3, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER2_ACPU_0, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER2_ACPU_1, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER2_ACPU_2, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER2_ACPU_3, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER3_ACPU_0, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER3_ACPU_1, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER3_ACPU_2, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + }, + { + .node_id = PM_DEV_CLUSTER3_ACPU_3, + .ipi = &apu_ipi, + .pwrdn_mask = 0, + } +}; + +const struct pm_proc *primary_proc = &pm_procs_all[0]; + +/** + * pm_get_proc() - returns pointer to the proc structure + * @param cpuid id of the cpu whose proc struct pointer should be returned + * + * @return pointer to a proc structure if proc is found, otherwise NULL + */ +const struct pm_proc *pm_get_proc(uint32_t cpuid) +{ + if (cpuid < ARRAY_SIZE(pm_procs_all)) { + return &pm_procs_all[cpuid]; + } + + NOTICE("ERROR: cpuid: %d proc NULL\n", cpuid); + return NULL; +} + +/** + * pm_client_suspend() - Client-specific suspend actions + * + * This function should contain any PU-specific actions + * required prior to sending suspend request to PMU + * Actions taken depend on the state system is suspending to. + * + * @param proc processor which need to suspend + * @param state desired suspend state + */ +void pm_client_suspend(const struct pm_proc *proc, uint32_t state) +{ + uint32_t cpu_id = plat_my_core_pos(); + uintptr_t val; + + bakery_lock_get(&pm_client_secure_lock); + + /* TODO: Set wakeup source */ + + val = read_cpu_pwrctrl_val(); + val |= CORE_PWRDN_EN_BIT_MASK; + write_cpu_pwrctrl_val(val); + + isb(); + + mmio_write_32(APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id), + APU_PCIL_CORE_X_IEN_POWER_MASK); + + bakery_lock_release(&pm_client_secure_lock); +} + +/** + * pm_get_cpuid() - get the local cpu ID for a global node ID + * @param nid node id of the processor + * + * @return the cpu ID (starting from 0) for the subsystem + */ +static uint32_t pm_get_cpuid(uint32_t nid) +{ + for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) { + if (pm_procs_all[i].node_id == nid) { + return i; + } + } + return UNDEFINED_CPUID; +} + +/** + * pm_client_wakeup() - Client-specific wakeup actions + * + * This function should contain any PU-specific actions + * required for waking up another APU core + * + * @param proc Processor which need to wakeup + */ +void pm_client_wakeup(const struct pm_proc *proc) +{ + uint32_t cpuid = pm_get_cpuid(proc->node_id); + + if (cpuid == UNDEFINED_CPUID) { + return; + } + + bakery_lock_get(&pm_client_secure_lock); + + /* TODO: clear powerdown bit for affected cpu */ + + bakery_lock_release(&pm_client_secure_lock); +} + +/** + * pm_client_abort_suspend() - Client-specific abort-suspend actions + * + * This function should contain any PU-specific actions + * required for aborting a prior suspend request + */ +void pm_client_abort_suspend(void) +{ + uint32_t cpu_id = plat_my_core_pos(); + uintptr_t val; + + /* Enable interrupts at processor level (for current cpu) */ + gicv3_cpuif_enable(plat_my_core_pos()); + + bakery_lock_get(&pm_client_secure_lock); + + /* Clear powerdown request */ + val = read_cpu_pwrctrl_val(); + val &= ~CORE_PWRDN_EN_BIT_MASK; + write_cpu_pwrctrl_val(val); + + isb(); + + /* Disabled power down interrupt */ + mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id), + APU_PCIL_CORE_X_IDS_POWER_MASK); + + bakery_lock_release(&pm_client_secure_lock); +} diff --git a/plat/xilinx/versal_net/sip_svc_setup.c b/plat/xilinx/versal_net/sip_svc_setup.c new file mode 100644 index 000000000..0e3940fee --- /dev/null +++ b/plat/xilinx/versal_net/sip_svc_setup.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Top level SMC handler for SiP calls. Dispatch PM calls to PM SMC handler. */ + +#include <errno.h> + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <tools_share/uuid.h> + +#include "ipi_mailbox_svc.h" +#include "plat_private.h" +#include "pm_svc_main.h" + +/* SMC function IDs for SiP Service queries */ +#define VERSAL_NET_SIP_SVC_CALL_COUNT (0x8200ff00U) +#define VERSAL_NET_SIP_SVC_UID (0x8200ff01U) +#define VERSAL_NET_SIP_SVC_VERSION (0x8200ff03U) + +/* SiP Service Calls version numbers */ +#define SIP_SVC_VERSION_MAJOR (0U) +#define SIP_SVC_VERSION_MINOR (1U) + +/* These macros are used to identify PM calls from the SMC function ID */ +#define PM_FID_MASK 0xf000u +#define PM_FID_VALUE 0u +#define IPI_FID_VALUE 0x1000u +#define is_pm_fid(_fid) (((_fid) & PM_FID_MASK) == PM_FID_VALUE) +#define is_ipi_fid(_fid) (((_fid) & PM_FID_MASK) == IPI_FID_VALUE) + +/* SiP Service UUID */ +DEFINE_SVC_UUID2(versal_net_sip_uuid, + 0x80d4c25a, 0xebaf, 0x11eb, 0x94, 0x68, + 0x0b, 0x4e, 0x3b, 0x8f, 0xc3, 0x60); + +/** + * sip_svc_setup() - Setup SiP Service + */ +static int32_t sip_svc_setup(void) +{ + return sip_svc_setup_init(); +} + +/* + * sip_svc_smc_handler() - Top-level SiP Service SMC handler + * + * Handler for all SiP SMC calls. Handles standard SIP requests + * and calls PM SMC handler if the call is for a PM-API function. + */ +static uintptr_t sip_svc_smc_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + /* Let PM SMC handler deal with PM-related requests */ + if (is_pm_fid(smc_fid)) { + return smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, + flags); + } + + /* Let IPI SMC handler deal with IPI-related requests if platform */ + if (is_ipi_fid(smc_fid)) { + return ipi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); + } + + /* Let PM SMC handler deal with PM-related requests */ + switch (smc_fid) { + case VERSAL_NET_SIP_SVC_CALL_COUNT: + /* PM functions + default functions */ + SMC_RET1(handle, 2); + + case VERSAL_NET_SIP_SVC_UID: + SMC_UUID_RET(handle, versal_net_sip_uuid); + + case VERSAL_NET_SIP_SVC_VERSION: + SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR); + + default: + WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} + +/* Register PM Service Calls as runtime service */ +DECLARE_RT_SVC( + sip_svc, + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + sip_svc_setup, + sip_svc_smc_handler); diff --git a/plat/xilinx/versal_net/versal_net_gicv3.c b/plat/xilinx/versal_net/versal_net_gicv3.c new file mode 100644 index 000000000..b7ac6abbc --- /dev/null +++ b/plat/xilinx/versal_net/versal_net_gicv3.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common/debug.h> +#include <common/interrupt_props.h> +#include <drivers/arm/gicv3.h> +#include <lib/utils.h> +#include <plat/common/platform.h> + +#include <plat_private.h> +#include <platform_def.h> + +/****************************************************************************** + * The following functions are defined as weak to allow a platform to override + * the way the GICv3 driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_versal_net_gic_driver_init +#pragma weak plat_versal_net_gic_init +#pragma weak plat_versal_net_gic_cpuif_enable +#pragma weak plat_versal_net_gic_cpuif_disable +#pragma weak plat_versal_net_gic_pcpu_init +#pragma weak plat_versal_net_gic_redistif_on +#pragma weak plat_versal_net_gic_redistif_off + +/* The GICv3 driver only needs to be initialized in EL3 */ +static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +static const uintptr_t gicr_base_addrs[2] = { + PLAT_VERSAL_NET_GICR_BASE, /* GICR Base address of the primary CPU */ + 0U /* Zero Termination */ +}; + +/* List of zero terminated GICR frame addresses which CPUs will probe */ +static const uintptr_t *gicr_frames; + +static const interrupt_prop_t versal_net_interrupt_props[] = { + PLAT_VERSAL_NET_G1S_IRQ_PROPS(INTR_GROUP1S), + PLAT_VERSAL_NET_G0_IRQ_PROPS(INTR_GROUP0) +}; + +/* + * We save and restore the GICv3 context on system suspend. Allocate the + * data in the designated EL3 Secure carve-out memory. + */ +static gicv3_redist_ctx_t rdist_ctx __section("versal_net_el3_tzc_dram"); +static gicv3_dist_ctx_t dist_ctx __section("versal_net_el3_tzc_dram"); + +/* + * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register + * to core position. + * + * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity + * values read from GICR_TYPER don't have an MT field. To reuse the same + * translation used for CPUs, we insert MT bit read from the PE's MPIDR into + * that read from GICR_TYPER. + * + * Assumptions: + * + * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; + * - No CPUs implemented in the system use affinity level 3. + */ +static uint32_t versal_net_gicv3_mpidr_hash(u_register_t mpidr) +{ + mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); + return plat_core_pos_by_mpidr(mpidr); +} + +static const gicv3_driver_data_t versal_net_gic_data __unused = { + .gicd_base = PLAT_VERSAL_NET_GICD_BASE, + .gicr_base = 0U, + .interrupt_props = versal_net_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(versal_net_interrupt_props), + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = rdistif_base_addrs, + .mpidr_to_core_pos = versal_net_gicv3_mpidr_hash +}; + +void __init plat_versal_net_gic_driver_init(void) +{ + /* + * The GICv3 driver is initialized in EL3 and does not need + * to be initialized again in SEL1. This is because the S-EL1 + * can use GIC system registers to manage interrupts and does + * not need GIC interface base addresses to be configured. + */ +#if IMAGE_BL31 + gicv3_driver_init(&versal_net_gic_data); + gicr_frames = gicr_base_addrs; + + if (gicv3_rdistif_probe(gicr_frames[0]) == -1) { + ERROR("No GICR base frame found for Primary CPU\n"); + panic(); + } +#endif +} + +/****************************************************************************** + * Versal NET common helper to initialize the GIC. Only invoked by BL31 + *****************************************************************************/ +void __init plat_versal_net_gic_init(void) +{ + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/****************************************************************************** + * Versal NET common helper to enable the GIC CPU interface + *****************************************************************************/ +void plat_versal_net_gic_cpuif_enable(void) +{ + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/****************************************************************************** + * Versal NET common helper to disable the GIC CPU interface + *****************************************************************************/ +void plat_versal_net_gic_cpuif_disable(void) +{ + gicv3_cpuif_disable(plat_my_core_pos()); +} + +/****************************************************************************** + * Versal NET common helper to initialize the per-cpu redistributor interface in + * GICv3 + *****************************************************************************/ +void plat_versal_net_gic_pcpu_init(void) +{ + int32_t result; + const uintptr_t *plat_gicr_frames = gicr_frames; + + do { + result = gicv3_rdistif_probe(*plat_gicr_frames); + + /* If the probe is successful, no need to proceed further */ + if (result == 0) { + break; + } + + plat_gicr_frames++; + } while (*plat_gicr_frames != 0U); + + if (result == -1) { + ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); + panic(); + } + + gicv3_rdistif_init(plat_my_core_pos()); +} + +/****************************************************************************** + * Versal NET common helpers to power GIC redistributor interface + *****************************************************************************/ +void plat_versal_net_gic_redistif_on(void) +{ + gicv3_rdistif_on(plat_my_core_pos()); +} + +void plat_versal_net_gic_redistif_off(void) +{ + gicv3_rdistif_off(plat_my_core_pos()); +} + +/****************************************************************************** + * Versal NET common helper to save & restore the GICv3 on resume from system + * suspend + *****************************************************************************/ +void plat_versal_net_gic_save(void) +{ + /* + * If an ITS is available, save its context before + * the Redistributor using: + * gicv3_its_save_disable(gits_base, &its_ctx[i]) + * Additionnaly, an implementation-defined sequence may + * be required to save the whole ITS state. + */ + + /* + * Save the GIC Redistributors and ITS contexts before the + * Distributor context. As we only handle SYSTEM SUSPEND API, + * we only need to save the context of the CPU that is issuing + * the SYSTEM SUSPEND call, i.e. the current CPU. + */ + gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx); + + /* Save the GIC Distributor context */ + gicv3_distif_save(&dist_ctx); + + /* + * From here, all the components of the GIC can be safely powered down + * as long as there is an alternate way to handle wakeup interrupt + * sources. + */ +} + +void plat_versal_net_gic_resume(void) +{ + /* Restore the GIC Distributor context */ + gicv3_distif_init_restore(&dist_ctx); + + /* + * Restore the GIC Redistributor and ITS contexts after the + * Distributor context. As we only handle SYSTEM SUSPEND API, + * we only need to restore the context of the CPU that issued + * the SYSTEM SUSPEND call. + */ + gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx); + + /* + * If an ITS is available, restore its context after + * the Redistributor using: + * gicv3_its_restore(gits_base, &its_ctx[i]) + * An implementation-defined sequence may be required to + * restore the whole ITS state. The ITS must also be + * re-enabled after this sequence has been executed. + */ +} diff --git a/plat/xilinx/versal_net/versal_net_ipi.c b/plat/xilinx/versal_net/versal_net_ipi.c new file mode 100644 index 000000000..26ded890e --- /dev/null +++ b/plat/xilinx/versal_net/versal_net_ipi.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2022, Xilinx, Inc. All rights reserved. + * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * Versal NET IPI agent registers access management + */ + +#include <errno.h> +#include <string.h> + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <lib/bakery_lock.h> +#include <lib/mmio.h> + +#include <ipi.h> +#include <plat_ipi.h> +#include <plat_private.h> + +/* versal_net ipi configuration table */ +static const struct ipi_config versal_net_ipi_table[IPI_ID_MAX] = { + /* A72 IPI */ + [IPI_ID_APU] = { + .ipi_bit_mask = IPI0_TRIG_BIT, + .ipi_reg_base = IPI0_REG_BASE, + .secure_only = 0, + }, + + /* PMC IPI */ + [IPI_ID_PMC] = { + .ipi_bit_mask = PMC_IPI_TRIG_BIT, + .ipi_reg_base = IPI0_REG_BASE, + .secure_only = 0, + }, + + /* RPU0 IPI */ + [IPI_ID_RPU0] = { + .ipi_bit_mask = IPI1_TRIG_BIT, + .ipi_reg_base = IPI1_REG_BASE, + .secure_only = 0, + }, + + /* RPU1 IPI */ + [IPI_ID_RPU1] = { + .ipi_bit_mask = IPI2_TRIG_BIT, + .ipi_reg_base = IPI2_REG_BASE, + .secure_only = 0, + }, + + /* IPI3 IPI */ + [IPI_ID_3] = { + .ipi_bit_mask = IPI3_TRIG_BIT, + .ipi_reg_base = IPI3_REG_BASE, + .secure_only = 0, + }, + + /* IPI4 IPI */ + [IPI_ID_4] = { + .ipi_bit_mask = IPI4_TRIG_BIT, + .ipi_reg_base = IPI4_REG_BASE, + .secure_only = 0, + }, + + /* IPI5 IPI */ + [IPI_ID_5] = { + .ipi_bit_mask = IPI5_TRIG_BIT, + .ipi_reg_base = IPI5_REG_BASE, + .secure_only = 0, + }, +}; + +/* versal_net_ipi_config_table_init() - Initialize versal_net IPI configuration data + * + * @ipi_config_table - IPI configuration table + * @ipi_total - Total number of IPI available + * + */ +void versal_net_ipi_config_table_init(void) +{ + ipi_config_table_init(versal_net_ipi_table, ARRAY_SIZE(versal_net_ipi_table)); +} diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c index 32b01231f..3946e9b62 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -29,7 +29,7 @@ const mmap_region_t plat_arm_mmap[] = { {0} }; -static unsigned int zynqmp_get_silicon_ver(void) +static uint32_t zynqmp_get_silicon_ver(void) { static unsigned int ver; @@ -43,7 +43,7 @@ static unsigned int zynqmp_get_silicon_ver(void) return ver; } -unsigned int zynqmp_get_uart_clk(void) +uint32_t zynqmp_get_uart_clk(void) { unsigned int ver = zynqmp_get_silicon_ver(); @@ -56,8 +56,8 @@ unsigned int zynqmp_get_uart_clk(void) #if LOG_LEVEL >= LOG_LEVEL_NOTICE static const struct { - unsigned int id; - unsigned int ver; + uint32_t id; + uint32_t ver; char *name; bool evexists; } zynqmp_devices[] = { @@ -215,7 +215,8 @@ static const struct { #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT) #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK) -#define SILICON_ID_XCK26 0x4724093 +#define SILICON_ID_XCK24 0x4714093U +#define SILICON_ID_XCK26 0x4724093U static char *zynqmp_get_silicon_idcode_name(void) { @@ -251,9 +252,12 @@ static char *zynqmp_get_silicon_idcode_name(void) } if (i >= ARRAY_SIZE(zynqmp_devices)) { - if (chipid[0] == SILICON_ID_XCK26) { + switch (chipid[0]) { + case SILICON_ID_XCK24: + return "XCK24"; + case SILICON_ID_XCK26: return "XCK26"; - } else { + default: return "XCZUUNKN"; } } @@ -306,20 +310,20 @@ static char *zynqmp_print_silicon_idcode(void) return zynqmp_get_silicon_idcode_name(); } -static unsigned int zynqmp_get_ps_ver(void) +static uint32_t zynqmp_get_ps_ver(void) { uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); ver &= ZYNQMP_PS_VER_MASK; ver >>= ZYNQMP_PS_VER_SHIFT; - return ver + 1; + return ver + 1U; } static void zynqmp_print_platform_name(void) { - unsigned int ver = zynqmp_get_silicon_ver(); - unsigned int rtl = zynqmp_get_rtl_ver(); + uint32_t ver = zynqmp_get_silicon_ver(); + uint32_t rtl = zynqmp_get_rtl_ver(); char *label = "Unknown"; switch (ver) { @@ -343,7 +347,7 @@ static void zynqmp_print_platform_name(void) static inline void zynqmp_print_platform_name(void) { } #endif -unsigned int zynqmp_get_bootmode(void) +uint32_t zynqmp_get_bootmode(void) { uint32_t r; unsigned int ret; @@ -375,9 +379,9 @@ void zynqmp_config_setup(void) generic_delay_timer_init(); } -unsigned int plat_get_syscnt_freq2(void) +uint32_t plat_get_syscnt_freq2(void) { - unsigned int ver = zynqmp_get_silicon_ver(); + uint32_t ver = zynqmp_get_silicon_ver(); if (ver == ZYNQMP_CSU_VERSION_QEMU) { return 65000000; diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 6ded2e20b..1d59537d5 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -82,7 +82,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); } else if (ZYNQMP_CONSOLE_IS(dcc)) { /* Initialize the dcc console for debug */ - int rc = console_dcc_register(); + int32_t rc = console_dcc_register(); if (rc == 0) { panic(); } @@ -176,7 +176,7 @@ static void prepare_dtb(void) /* Return if no device tree is detected */ if (fdt_check_header(dtb) != 0) { - NOTICE("Can't read DT at 0x%p\n", dtb); + NOTICE("Can't read DT at %p\n", dtb); return; } diff --git a/plat/xilinx/zynqmp/include/plat_ipi.h b/plat/xilinx/zynqmp/include/plat_ipi.h index bccd2f194..a78f93a18 100644 --- a/plat/xilinx/zynqmp/include/plat_ipi.h +++ b/plat/xilinx/zynqmp/include/plat_ipi.h @@ -41,7 +41,7 @@ #define IPI_BUFFER_TARGET_LOCAL_OFFSET 0x80U #define IPI_BUFFER_TARGET_REMOTE_OFFSET 0x1C0U -#define IPI_BUFFER_MAX_WORDS 8 +#define IPI_BUFFER_MAX_WORDS 8U #define IPI_BUFFER_REQ_OFFSET 0x0U #define IPI_BUFFER_RESP_OFFSET 0x20U diff --git a/plat/xilinx/zynqmp/include/plat_private.h b/plat/xilinx/zynqmp/include/plat_private.h index 288cc5301..534777b11 100644 --- a/plat/xilinx/zynqmp/include/plat_private.h +++ b/plat/xilinx/zynqmp/include/plat_private.h @@ -15,11 +15,11 @@ void zynqmp_config_setup(void); -unsigned int zynqmp_calc_core_pos(u_register_t mpidr); +uint32_t zynqmp_calc_core_pos(u_register_t mpidr); /* ZynqMP specific functions */ -unsigned int zynqmp_get_uart_clk(void); -unsigned int zynqmp_get_bootmode(void); +uint32_t zynqmp_get_uart_clk(void); +uint32_t zynqmp_get_bootmode(void); #if ZYNQMP_WDT_RESTART diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index 9c1600a7b..c2d22c20c 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -40,8 +40,8 @@ # define BL31_BASE U(0xfffea000) # define BL31_LIMIT U(0x100000000) #else -# define BL31_BASE U(0x1000) -# define BL31_LIMIT U(0x7ffff) +# define BL31_BASE U(0xfffe5000) +# define BL31_LIMIT U(0x100000000) #endif #else # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h index 19b6937cb..428bed500 100644 --- a/plat/xilinx/zynqmp/include/zynqmp_def.h +++ b/plat/xilinx/zynqmp/include/zynqmp_def.h @@ -163,40 +163,40 @@ #define ZYNQMP_CSU_VERSION_SILICON 0 #define ZYNQMP_CSU_VERSION_QEMU 3 -#define ZYNQMP_RTL_VER_MASK 0xFF0 +#define ZYNQMP_RTL_VER_MASK 0xFF0U #define ZYNQMP_RTL_VER_SHIFT 4 -#define ZYNQMP_PS_VER_MASK 0xF +#define ZYNQMP_PS_VER_MASK 0xFU #define ZYNQMP_PS_VER_SHIFT 0 #define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) -#define ZYNQMP_CSU_IDCODE_OFFSET 0x40 +#define ZYNQMP_CSU_IDCODE_OFFSET 0x40U -#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0 -#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFF << \ +#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U +#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \ ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) #define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 -#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 -#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << \ +#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U +#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \ ZYNQMP_CSU_IDCODE_SVD_SHIFT) -#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 -#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xF << \ +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \ ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) -#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19 -#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3 << \ +#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U +#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \ ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) -#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21 -#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7F << \ +#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U +#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \ ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) #define ZYNQMP_CSU_IDCODE_FAMILY 0x23 -#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28 -#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xF << \ +#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U +#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \ ZYNQMP_CSU_IDCODE_REVISION_SHIFT) -#define ZYNQMP_CSU_IDCODE_REVISION 0 +#define ZYNQMP_CSU_IDCODE_REVISION 0U -#define ZYNQMP_CSU_VERSION_OFFSET 0x44 +#define ZYNQMP_CSU_VERSION_OFFSET 0x44U /* Efuse */ #define EFUSE_BASEADDR U(0xFFCC0000) @@ -352,7 +352,7 @@ #define RESTART_SCOPE_SHIFT (3) #define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) -/*AFI registers */ +/* AFI registers */ #define AFIFM6_WRCTRL U(13) #define FABRIC_WIDTH U(3) diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c index f337cf502..b7408b1da 100644 --- a/plat/xilinx/zynqmp/plat_psci.c +++ b/plat/xilinx/zynqmp/plat_psci.c @@ -29,9 +29,9 @@ static void zynqmp_cpu_standby(plat_local_state_t cpu_state) wfi(); } -static int zynqmp_pwr_domain_on(u_register_t mpidr) +static int32_t zynqmp_pwr_domain_on(u_register_t mpidr) { - unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); + uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); const struct pm_proc *proc; uint32_t buff[3]; enum pm_ret_status ret; @@ -60,7 +60,7 @@ static int zynqmp_pwr_domain_on(u_register_t mpidr) static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state) { - unsigned int cpu_id = plat_my_core_pos(); + uint32_t cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { @@ -84,8 +84,8 @@ static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state) static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) { - unsigned int state; - unsigned int cpu_id = plat_my_core_pos(); + uint32_t state; + uint32_t cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) @@ -117,7 +117,7 @@ static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) { - unsigned int cpu_id = plat_my_core_pos(); + uint32_t cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { @@ -171,12 +171,12 @@ static void __dead2 zynqmp_system_reset(void) } } -static int zynqmp_validate_power_state(unsigned int power_state, +static int32_t zynqmp_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) { VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); - int pstate = psci_get_pstate_type(power_state); + uint32_t pstate = psci_get_pstate_type(power_state); assert(req_state); diff --git a/plat/xilinx/zynqmp/plat_topology.c b/plat/xilinx/zynqmp/plat_topology.c index aab24aa07..41add9fd4 100644 --- a/plat/xilinx/zynqmp/plat_topology.c +++ b/plat/xilinx/zynqmp/plat_topology.c @@ -3,10 +3,11 @@ * * SPDX-License-Identifier: BSD-3-Clause */ +#include <stdint.h> -static const unsigned char plat_power_domain_tree_desc[] = {1, 4}; +static const uint8_t plat_power_domain_tree_desc[] = {1, 4}; -const unsigned char *plat_get_power_domain_tree_desc(void) +const uint8_t *plat_get_power_domain_tree_desc(void) { return plat_power_domain_tree_desc; } diff --git a/plat/xilinx/zynqmp/plat_zynqmp.c b/plat/xilinx/zynqmp/plat_zynqmp.c index 58a52a3bf..25ebac6b9 100644 --- a/plat/xilinx/zynqmp/plat_zynqmp.c +++ b/plat/xilinx/zynqmp/plat_zynqmp.c @@ -7,7 +7,7 @@ #include <plat_private.h> #include <plat/common/platform.h> -int plat_core_pos_by_mpidr(u_register_t mpidr) +int32_t plat_core_pos_by_mpidr(u_register_t mpidr) { if (mpidr & MPIDR_CLUSTER_MASK) { return -1; diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index ea8a5d1db..05adbd07c 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -1,5 +1,6 @@ # # Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. +# Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -11,17 +12,26 @@ SEPARATE_CODE_AND_RODATA := 1 ZYNQMP_WDT_RESTART := 0 IPI_CRC_CHECK := 0 override RESET_TO_BL31 := 1 -override GICV2_G0_FOR_EL3 := 1 override WARMBOOT_ENABLE_DCACHE_EARLY := 1 EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT) +# pncd SPD requires secure SGI to be handled at EL1 +ifeq (${SPD},pncd) +ifeq (${ZYNQMP_WDT_RESTART},1) +$(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible") +endif +override GICV2_G0_FOR_EL3 := 0 +else +override GICV2_G0_FOR_EL3 := 1 +endif + # Do not enable SVE ENABLE_SVE_FOR_NS := 0 WORKAROUND_CVE_2017_5715 := 0 -ARM_XLAT_TABLES_LIB_V1 := 1 +ARM_XLAT_TABLES_LIB_V1 := 1 $(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1)) $(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1)) @@ -60,6 +70,10 @@ ifdef IPI_CRC_CHECK $(eval $(call add_define,IPI_CRC_CHECK)) endif +ifdef ZYNQMP_SECURE_EFUSES + $(eval $(call add_define,ZYNQMP_SECURE_EFUSES)) +endif + PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ -Iinclude/plat/arm/common/aarch64/ \ -Iplat/xilinx/common/include/ \ diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index 1ea741cc3..e61310aad 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -21,51 +21,51 @@ #include "pm_common.h" #include "pm_ipi.h" -#define CLK_NODE_MAX U(6) - -#define CLK_PARENTS_ID_LEN U(16) -#define CLK_TOPOLOGY_NODE_OFFSET U(16) -#define CLK_TOPOLOGY_PAYLOAD_LEN U(12) -#define CLK_PARENTS_PAYLOAD_LEN U(12) -#define CLK_TYPE_SHIFT U(2) -#define CLK_CLKFLAGS_SHIFT U(8) -#define CLK_TYPEFLAGS_SHIFT U(24) -#define CLK_TYPEFLAGS2_SHIFT U(4) -#define CLK_TYPEFLAGS_BITS_MASK U(0xFF) -#define CLK_TYPEFLAGS2_BITS_MASK U(0x0F00) -#define CLK_TYPEFLAGS_BITS U(8) +#define CLK_NODE_MAX (6U) + +#define CLK_PARENTS_ID_LEN (16U) +#define CLK_TOPOLOGY_NODE_OFFSET (16U) +#define CLK_TOPOLOGY_PAYLOAD_LEN (12U) +#define CLK_PARENTS_PAYLOAD_LEN (12U) +#define CLK_TYPE_SHIFT (2U) +#define CLK_CLKFLAGS_SHIFT (8U) +#define CLK_TYPEFLAGS_SHIFT (24U) +#define CLK_TYPEFLAGS2_SHIFT (4U) +#define CLK_TYPEFLAGS_BITS_MASK (0xFFU) +#define CLK_TYPEFLAGS2_BITS_MASK (0x0F00U) +#define CLK_TYPEFLAGS_BITS (8U) #define CLK_EXTERNAL_PARENT (PARENT_CLK_EXTERNAL << CLK_PARENTS_ID_LEN) -#define NA_MULT U(0) -#define NA_DIV U(0) -#define NA_SHIFT U(0) -#define NA_WIDTH U(0) -#define NA_CLK_FLAGS U(0) -#define NA_TYPE_FLAGS U(0) +#define NA_MULT (0U) +#define NA_DIV (0U) +#define NA_SHIFT (0U) +#define NA_WIDTH (0U) +#define NA_CLK_FLAGS (0U) +#define NA_TYPE_FLAGS (0U) /* PLL nodes related definitions */ -#define PLL_PRESRC_MUX_SHIFT U(20) -#define PLL_PRESRC_MUX_WIDTH U(3) -#define PLL_POSTSRC_MUX_SHIFT U(24) -#define PLL_POSTSRC_MUX_WIDTH U(3) -#define PLL_DIV2_MUX_SHIFT U(16) -#define PLL_DIV2_MUX_WIDTH U(1) -#define PLL_BYPASS_MUX_SHIFT U(3) -#define PLL_BYPASS_MUX_WIDTH U(1) +#define PLL_PRESRC_MUX_SHIFT (20U) +#define PLL_PRESRC_MUX_WIDTH (3U) +#define PLL_POSTSRC_MUX_SHIFT (24U) +#define PLL_POSTSRC_MUX_WIDTH (3U) +#define PLL_DIV2_MUX_SHIFT (16U) +#define PLL_DIV2_MUX_WIDTH (1U) +#define PLL_BYPASS_MUX_SHIFT (3U) +#define PLL_BYPASS_MUX_WIDTH (1U) /* Peripheral nodes related definitions */ /* Peripheral Clocks */ -#define PERIPH_MUX_SHIFT U(0) -#define PERIPH_MUX_WIDTH U(3) -#define PERIPH_DIV1_SHIFT U(8) -#define PERIPH_DIV1_WIDTH U(6) -#define PERIPH_DIV2_SHIFT U(16) -#define PERIPH_DIV2_WIDTH U(6) -#define PERIPH_GATE_SHIFT U(24) -#define PERIPH_GATE_WIDTH U(1) +#define PERIPH_MUX_SHIFT (0U) +#define PERIPH_MUX_WIDTH (3U) +#define PERIPH_DIV1_SHIFT (8U) +#define PERIPH_DIV1_WIDTH (6U) +#define PERIPH_DIV2_SHIFT (16U) +#define PERIPH_DIV2_WIDTH (6U) +#define PERIPH_GATE_SHIFT (24U) +#define PERIPH_GATE_WIDTH (1U) -#define USB_GATE_SHIFT U(25) +#define USB_GATE_SHIFT (25U) /* External clock related definitions */ @@ -87,20 +87,20 @@ #define PLLCTRL_BP_MASK BIT(3) -#define PLLCTRL_RESET_MASK U(1) -#define PLL_FRAC_OFFSET U(8) -#define PLL_FRAC_MODE U(1) -#define PLL_INT_MODE U(0) -#define PLL_FRAC_MODE_MASK U(0x80000000) -#define PLL_FRAC_MODE_SHIFT U(31) -#define PLL_FRAC_DATA_MASK U(0xFFFF) -#define PLL_FRAC_DATA_SHIFT U(0) -#define PLL_FBDIV_MASK U(0x7F00) -#define PLL_FBDIV_WIDTH U(7) -#define PLL_FBDIV_SHIFT U(8) - -#define CLK_PLL_RESET_ASSERT U(1) -#define CLK_PLL_RESET_RELEASE U(2) +#define PLLCTRL_RESET_MASK (1U) +#define PLL_FRAC_OFFSET (8U) +#define PLL_FRAC_MODE (1U) +#define PLL_INT_MODE (0U) +#define PLL_FRAC_MODE_MASK (0x80000000U) +#define PLL_FRAC_MODE_SHIFT (31U) +#define PLL_FRAC_DATA_MASK (0xFFFFU) +#define PLL_FRAC_DATA_SHIFT (0U) +#define PLL_FBDIV_MASK (0x7F00U) +#define PLL_FBDIV_WIDTH (7U) +#define PLL_FBDIV_SHIFT (8U) + +#define CLK_PLL_RESET_ASSERT (1U) +#define CLK_PLL_RESET_RELEASE (2U) #define CLK_PLL_RESET_PULSE (CLK_PLL_RESET_ASSERT | CLK_PLL_RESET_RELEASE) /* Common topology definitions */ @@ -228,8 +228,8 @@ struct pm_clock_node { struct pm_clock { char name[CLK_NAME_LEN]; uint8_t num_nodes; - unsigned int control_reg; - unsigned int status_reg; + uint32_t control_reg; + uint32_t status_reg; int32_t (*parents)[]; struct pm_clock_node(*nodes)[]; }; @@ -2396,11 +2396,11 @@ static uint32_t pm_clk_invalid_list[] = {CLK_USB0, CLK_USB1, CLK_CSU_SPB, * * Return: Returns 1 if clock is valid else 0. */ -static bool pm_clock_valid(unsigned int clock_id) +static bool pm_clock_valid(uint32_t clock_id) { unsigned int i; - for (i = 0; i < ARRAY_SIZE(pm_clk_invalid_list); i++) + for (i = 0U; i < ARRAY_SIZE(pm_clk_invalid_list); i++) if (pm_clk_invalid_list[i] == clock_id) return 0; @@ -2415,7 +2415,7 @@ static bool pm_clock_valid(unsigned int clock_id) * * Return: Returns type of clock (OUTPUT/EXTERNAL). */ -static unsigned int pm_clock_type(unsigned int clock_id) +static uint32_t pm_clock_type(uint32_t clock_id) { return (clock_id < CLK_MAX_OUTPUT_CLK) ? CLK_TYPE_OUTPUT : CLK_TYPE_EXTERNAL; @@ -2429,7 +2429,7 @@ static unsigned int pm_clock_type(unsigned int clock_id) * * @return Returns success. */ -enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks) +enum pm_ret_status pm_api_clock_get_num_clocks(uint32_t *nclocks) { *nclocks = CLK_MAX; @@ -2444,7 +2444,7 @@ enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks) * This function is used by master to get nmae of clock specified * by given clock ID. */ -void pm_api_clock_get_name(unsigned int clock_id, char *name) +void pm_api_clock_get_name(uint32_t clock_id, char *name) { if (clock_id == CLK_MAX) { memcpy(name, END_OF_CLK, sizeof(END_OF_CLK) > CLK_NAME_LEN ? @@ -2472,13 +2472,13 @@ void pm_api_clock_get_name(unsigned int clock_id, char *name) * * @return Returns status, either success or error+reason */ -enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id, - unsigned int index, +enum pm_ret_status pm_api_clock_get_topology(uint32_t clock_id, + uint32_t index, uint32_t *topology) { struct pm_clock_node *clock_nodes; uint8_t num_nodes; - unsigned int i; + uint32_t i; uint16_t typeflags; if (!pm_clock_valid(clock_id)) { @@ -2528,13 +2528,13 @@ enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id, * * @return Returns status, either success or error+reason */ -enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id, +enum pm_ret_status pm_api_clock_get_fixedfactor_params(uint32_t clock_id, uint32_t *mul, uint32_t *div) { struct pm_clock_node *clock_nodes; uint8_t num_nodes; - unsigned int type, i; + uint32_t type, i; if (!pm_clock_valid(clock_id)) { return PM_RET_ERROR_ARGS; @@ -2581,11 +2581,11 @@ enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id, * * @return Returns status, either success or error+reason */ -enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id, - unsigned int index, +enum pm_ret_status pm_api_clock_get_parents(uint32_t clock_id, + uint32_t index, uint32_t *parents) { - unsigned int i; + uint32_t i; int32_t *clk_parents; if (!pm_clock_valid(clock_id)) { @@ -2610,7 +2610,7 @@ enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id, } } - for (i = 0; i < 3; i++) { + for (i = 0; i < 3U; i++) { parents[i] = clk_parents[index + i]; if (clk_parents[index + i] == CLK_NA_PARENT) { break; @@ -2630,7 +2630,7 @@ enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id, * * @return Returns status, either success or error+reason */ -enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id, +enum pm_ret_status pm_api_clock_get_attributes(uint32_t clock_id, uint32_t *attr) { if (clock_id >= CLK_MAX) { @@ -2672,9 +2672,9 @@ enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id, if (nodes[i].type == div_type) { if (CLK_DIVIDER_POWER_OF_TWO & nodes[i].typeflags) { - *max_div = (1 << (BIT(nodes[i].width) - 1)); + *max_div = (1U << (BIT(nodes[i].width) - 1U)); } else { - *max_div = BIT(nodes[i].width) - 1; + *max_div = BIT(nodes[i].width) - 1U; } return PM_RET_SUCCESS; } @@ -2815,7 +2815,7 @@ struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id) */ enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll) { - if (!pll) { + if (pll == NULL) { return PM_RET_ERROR_ARGS; } @@ -2838,7 +2838,7 @@ enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll) */ enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll) { - if (!pll) { + if (pll == NULL) { return PM_RET_ERROR_ARGS; } @@ -2857,12 +2857,12 @@ enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll) * returned state value is valid or an error if returned by PMU */ enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll, - unsigned int *state) + uint32_t *state) { enum pm_ret_status status; enum pm_pll_mode mode; - if (!pll || !state) { + if ((pll == NULL) || !state) { return PM_RET_ERROR_ARGS; } @@ -2894,9 +2894,9 @@ enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll, */ enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll, enum clock_id clock_id, - unsigned int parent_index) + uint32_t parent_index) { - if (!pll) { + if (pll == NULL) { return PM_RET_ERROR_ARGS; } if (pll->pre_src == clock_id) { @@ -2927,9 +2927,9 @@ enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll, */ enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll, enum clock_id clock_id, - unsigned int *parent_index) + uint32_t *parent_index) { - if (!pll) { + if (pll == NULL) { return PM_RET_ERROR_ARGS; } if (pll->pre_src == clock_id) { @@ -2962,11 +2962,11 @@ enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll, * @return Success if mode is buffered or error if an argument is invalid */ enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id, - unsigned int mode) + uint32_t mode) { struct pm_pll *pll = pm_clock_get_pll(clock_id); - if (!pll || (mode != PLL_FRAC_MODE && mode != PLL_INT_MODE)) { + if ((pll == NULL) || (mode != PLL_FRAC_MODE && mode != PLL_INT_MODE)) { return PM_RET_ERROR_ARGS; } pll->mode = mode; @@ -2984,11 +2984,11 @@ enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id, * @return Success if mode is stored or error if an argument is invalid */ enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id, - unsigned int *mode) + uint32_t *mode) { struct pm_pll *pll = pm_clock_get_pll(clock_id); - if (!pll || !mode) { + if ((pll == NULL) || !mode) { return PM_RET_ERROR_ARGS; } *mode = pll->mode; @@ -3002,7 +3002,7 @@ enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id, * * @return Returns success if clock_id is valid, otherwise an error */ -enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id) +enum pm_ret_status pm_clock_id_is_valid(uint32_t clock_id) { if (!pm_clock_valid(clock_id)) { return PM_RET_ERROR_ARGS; @@ -3022,7 +3022,7 @@ enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id) * * @return True(1)=clock has the divider, false(0)=otherwise */ -uint8_t pm_clock_has_div(unsigned int clock_id, enum pm_clock_div_id div_id) +uint8_t pm_clock_has_div(uint32_t clock_id, enum pm_clock_div_id div_id) { uint32_t i; struct pm_clock_node *nodes; diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h index 5efd63ff5..cc0daccdf 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h @@ -15,19 +15,19 @@ #include "pm_common.h" -#define CLK_NAME_LEN U(15) -#define MAX_PARENTS U(100) +#define CLK_NAME_LEN (15U) +#define MAX_PARENTS (100U) #define CLK_NA_PARENT -1 #define CLK_DUMMY_PARENT -2 /* Flags for parent id */ -#define PARENT_CLK_SELF U(0) -#define PARENT_CLK_NODE1 U(1) -#define PARENT_CLK_NODE2 U(2) -#define PARENT_CLK_NODE3 U(3) -#define PARENT_CLK_NODE4 U(4) -#define PARENT_CLK_EXTERNAL U(5) -#define PARENT_CLK_MIO0_MIO77 U(6) +#define PARENT_CLK_SELF (0U) +#define PARENT_CLK_NODE1 (1U) +#define PARENT_CLK_NODE2 (2U) +#define PARENT_CLK_NODE3 (3U) +#define PARENT_CLK_NODE4 (4U) +#define PARENT_CLK_EXTERNAL (5U) +#define PARENT_CLK_MIO0_MIO77 (6U) #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ @@ -57,224 +57,224 @@ //CLock Ids enum clock_id { - CLK_IOPLL, - CLK_RPLL, - CLK_APLL, - CLK_DPLL, - CLK_VPLL, - CLK_IOPLL_TO_FPD, - CLK_RPLL_TO_FPD, - CLK_APLL_TO_LPD, - CLK_DPLL_TO_LPD, - CLK_VPLL_TO_LPD, - CLK_ACPU, - CLK_ACPU_HALF, - CLK_DBG_FPD, - CLK_DBG_LPD, - CLK_DBG_TRACE, - CLK_DBG_TSTMP, - CLK_DP_VIDEO_REF, - CLK_DP_AUDIO_REF, - CLK_DP_STC_REF, - CLK_GDMA_REF, - CLK_DPDMA_REF, - CLK_DDR_REF, - CLK_SATA_REF, - CLK_PCIE_REF, - CLK_GPU_REF, - CLK_GPU_PP0_REF, - CLK_GPU_PP1_REF, - CLK_TOPSW_MAIN, - CLK_TOPSW_LSBUS, - CLK_GTGREF0_REF, - CLK_LPD_SWITCH, - CLK_LPD_LSBUS, - CLK_USB0_BUS_REF, - CLK_USB1_BUS_REF, - CLK_USB3_DUAL_REF, - CLK_USB0, - CLK_USB1, - CLK_CPU_R5, - CLK_CPU_R5_CORE, - CLK_CSU_SPB, - CLK_CSU_PLL, - CLK_PCAP, - CLK_IOU_SWITCH, - CLK_GEM_TSU_REF, - CLK_GEM_TSU, - CLK_GEM0_TX, - CLK_GEM1_TX, - CLK_GEM2_TX, - CLK_GEM3_TX, - CLK_GEM0_RX, - CLK_GEM1_RX, - CLK_GEM2_RX, - CLK_GEM3_RX, - CLK_QSPI_REF, - CLK_SDIO0_REF, - CLK_SDIO1_REF, - CLK_UART0_REF, - CLK_UART1_REF, - CLK_SPI0_REF, - CLK_SPI1_REF, - CLK_NAND_REF, - CLK_I2C0_REF, - CLK_I2C1_REF, - CLK_CAN0_REF, - CLK_CAN1_REF, - CLK_CAN0, - CLK_CAN1, - CLK_DLL_REF, - CLK_ADMA_REF, - CLK_TIMESTAMP_REF, - CLK_AMS_REF, - CLK_PL0_REF, - CLK_PL1_REF, - CLK_PL2_REF, - CLK_PL3_REF, - CLK_FPD_WDT, - CLK_IOPLL_INT, - CLK_IOPLL_PRE_SRC, - CLK_IOPLL_HALF, - CLK_IOPLL_INT_MUX, - CLK_IOPLL_POST_SRC, - CLK_RPLL_INT, - CLK_RPLL_PRE_SRC, - CLK_RPLL_HALF, - CLK_RPLL_INT_MUX, - CLK_RPLL_POST_SRC, - CLK_APLL_INT, - CLK_APLL_PRE_SRC, - CLK_APLL_HALF, - CLK_APLL_INT_MUX, - CLK_APLL_POST_SRC, - CLK_DPLL_INT, - CLK_DPLL_PRE_SRC, - CLK_DPLL_HALF, - CLK_DPLL_INT_MUX, - CLK_DPLL_POST_SRC, - CLK_VPLL_INT, - CLK_VPLL_PRE_SRC, - CLK_VPLL_HALF, - CLK_VPLL_INT_MUX, - CLK_VPLL_POST_SRC, - CLK_CAN0_MIO, - CLK_CAN1_MIO, - CLK_ACPU_FULL, - CLK_GEM0_REF, - CLK_GEM1_REF, - CLK_GEM2_REF, - CLK_GEM3_REF, - CLK_GEM0_REF_UNGATED, - CLK_GEM1_REF_UNGATED, - CLK_GEM2_REF_UNGATED, - CLK_GEM3_REF_UNGATED, - CLK_LPD_WDT, - END_OF_OUTPUT_CLKS, + CLK_IOPLL = (0U), + CLK_RPLL = (1U), + CLK_APLL = (2U), + CLK_DPLL = (3U), + CLK_VPLL = (4U), + CLK_IOPLL_TO_FPD = (5U), + CLK_RPLL_TO_FPD = (6U), + CLK_APLL_TO_LPD = (7U), + CLK_DPLL_TO_LPD = (8U), + CLK_VPLL_TO_LPD = (9U), + CLK_ACPU = (10U), + CLK_ACPU_HALF = (11U), + CLK_DBG_FPD = (12U), + CLK_DBG_LPD = (13U), + CLK_DBG_TRACE = (14U), + CLK_DBG_TSTMP = (15U), + CLK_DP_VIDEO_REF = (16U), + CLK_DP_AUDIO_REF = (17U), + CLK_DP_STC_REF = (18U), + CLK_GDMA_REF = (19U), + CLK_DPDMA_REF = (20U), + CLK_DDR_REF = (21U), + CLK_SATA_REF = (22U), + CLK_PCIE_REF = (23U), + CLK_GPU_REF = (24U), + CLK_GPU_PP0_REF = (25U), + CLK_GPU_PP1_REF = (26U), + CLK_TOPSW_MAIN = (27U), + CLK_TOPSW_LSBUS = (28U), + CLK_GTGREF0_REF = (29U), + CLK_LPD_SWITCH = (30U), + CLK_LPD_LSBUS = (31U), + CLK_USB0_BUS_REF = (32U), + CLK_USB1_BUS_REF = (33U), + CLK_USB3_DUAL_REF = (34U), + CLK_USB0 = (35U), + CLK_USB1 = (36U), + CLK_CPU_R5 = (37U), + CLK_CPU_R5_CORE = (38U), + CLK_CSU_SPB = (39U), + CLK_CSU_PLL = (40U), + CLK_PCAP = (41U), + CLK_IOU_SWITCH = (42U), + CLK_GEM_TSU_REF = (43U), + CLK_GEM_TSU = (44U), + CLK_GEM0_TX = (45U), + CLK_GEM1_TX = (46U), + CLK_GEM2_TX = (47U), + CLK_GEM3_TX = (48U), + CLK_GEM0_RX = (49U), + CLK_GEM1_RX = (50U), + CLK_GEM2_RX = (51U), + CLK_GEM3_RX = (52U), + CLK_QSPI_REF = (53U), + CLK_SDIO0_REF = (54U), + CLK_SDIO1_REF = (55U), + CLK_UART0_REF = (56U), + CLK_UART1_REF = (57U), + CLK_SPI0_REF = (58U), + CLK_SPI1_REF = (59U), + CLK_NAND_REF = (60U), + CLK_I2C0_REF = (61U), + CLK_I2C1_REF = (62U), + CLK_CAN0_REF = (63U), + CLK_CAN1_REF = (64U), + CLK_CAN0 = (65U), + CLK_CAN1 = (66U), + CLK_DLL_REF = (67U), + CLK_ADMA_REF = (68U), + CLK_TIMESTAMP_REF = (69U), + CLK_AMS_REF = (70U), + CLK_PL0_REF = (71U), + CLK_PL1_REF = (72U), + CLK_PL2_REF = (73U), + CLK_PL3_REF = (74U), + CLK_FPD_WDT = (75U), + CLK_IOPLL_INT = (76U), + CLK_IOPLL_PRE_SRC = (77U), + CLK_IOPLL_HALF = (78U), + CLK_IOPLL_INT_MUX = (79U), + CLK_IOPLL_POST_SRC = (80U), + CLK_RPLL_INT = (81U), + CLK_RPLL_PRE_SRC = (82U), + CLK_RPLL_HALF = (83U), + CLK_RPLL_INT_MUX = (84U), + CLK_RPLL_POST_SRC = (85U), + CLK_APLL_INT = (86U), + CLK_APLL_PRE_SRC = (87U), + CLK_APLL_HALF = (88U), + CLK_APLL_INT_MUX = (89U), + CLK_APLL_POST_SRC = (90U), + CLK_DPLL_INT = (91U), + CLK_DPLL_PRE_SRC = (92U), + CLK_DPLL_HALF = (93U), + CLK_DPLL_INT_MUX = (94U), + CLK_DPLL_POST_SRC = (95U), + CLK_VPLL_INT = (96U), + CLK_VPLL_PRE_SRC = (97U), + CLK_VPLL_HALF = (98U), + CLK_VPLL_INT_MUX = (99U), + CLK_VPLL_POST_SRC = (100U), + CLK_CAN0_MIO = (101U), + CLK_CAN1_MIO = (102U), + CLK_ACPU_FULL = (103U), + CLK_GEM0_REF = (104U), + CLK_GEM1_REF = (105U), + CLK_GEM2_REF = (106U), + CLK_GEM3_REF = (107U), + CLK_GEM0_REF_UNGATED = (108U), + CLK_GEM1_REF_UNGATED = (109U), + CLK_GEM2_REF_UNGATED = (110U), + CLK_GEM3_REF_UNGATED = (111U), + CLK_LPD_WDT = (112U), + END_OF_OUTPUT_CLKS = (113U), }; -#define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS) +#define CLK_MAX_OUTPUT_CLK END_OF_OUTPUT_CLKS //External clock ids enum { EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS, - EXT_CLK_VIDEO, - EXT_CLK_PSS_ALT_REF, - EXT_CLK_AUX_REF, - EXT_CLK_GT_CRX_REF, - EXT_CLK_SWDT0, - EXT_CLK_SWDT1, - EXT_CLK_GEM0_TX_EMIO, - EXT_CLK_GEM1_TX_EMIO, - EXT_CLK_GEM2_TX_EMIO, - EXT_CLK_GEM3_TX_EMIO, - EXT_CLK_GEM0_RX_EMIO, - EXT_CLK_GEM1_RX_EMIO, - EXT_CLK_GEM2_RX_EMIO, - EXT_CLK_GEM3_RX_EMIO, - EXT_CLK_MIO50_OR_MIO51, - EXT_CLK_MIO0, - EXT_CLK_MIO1, - EXT_CLK_MIO2, - EXT_CLK_MIO3, - EXT_CLK_MIO4, - EXT_CLK_MIO5, - EXT_CLK_MIO6, - EXT_CLK_MIO7, - EXT_CLK_MIO8, - EXT_CLK_MIO9, - EXT_CLK_MIO10, - EXT_CLK_MIO11, - EXT_CLK_MIO12, - EXT_CLK_MIO13, - EXT_CLK_MIO14, - EXT_CLK_MIO15, - EXT_CLK_MIO16, - EXT_CLK_MIO17, - EXT_CLK_MIO18, - EXT_CLK_MIO19, - EXT_CLK_MIO20, - EXT_CLK_MIO21, - EXT_CLK_MIO22, - EXT_CLK_MIO23, - EXT_CLK_MIO24, - EXT_CLK_MIO25, - EXT_CLK_MIO26, - EXT_CLK_MIO27, - EXT_CLK_MIO28, - EXT_CLK_MIO29, - EXT_CLK_MIO30, - EXT_CLK_MIO31, - EXT_CLK_MIO32, - EXT_CLK_MIO33, - EXT_CLK_MIO34, - EXT_CLK_MIO35, - EXT_CLK_MIO36, - EXT_CLK_MIO37, - EXT_CLK_MIO38, - EXT_CLK_MIO39, - EXT_CLK_MIO40, - EXT_CLK_MIO41, - EXT_CLK_MIO42, - EXT_CLK_MIO43, - EXT_CLK_MIO44, - EXT_CLK_MIO45, - EXT_CLK_MIO46, - EXT_CLK_MIO47, - EXT_CLK_MIO48, - EXT_CLK_MIO49, - EXT_CLK_MIO50, - EXT_CLK_MIO51, - EXT_CLK_MIO52, - EXT_CLK_MIO53, - EXT_CLK_MIO54, - EXT_CLK_MIO55, - EXT_CLK_MIO56, - EXT_CLK_MIO57, - EXT_CLK_MIO58, - EXT_CLK_MIO59, - EXT_CLK_MIO60, - EXT_CLK_MIO61, - EXT_CLK_MIO62, - EXT_CLK_MIO63, - EXT_CLK_MIO64, - EXT_CLK_MIO65, - EXT_CLK_MIO66, - EXT_CLK_MIO67, - EXT_CLK_MIO68, - EXT_CLK_MIO69, - EXT_CLK_MIO70, - EXT_CLK_MIO71, - EXT_CLK_MIO72, - EXT_CLK_MIO73, - EXT_CLK_MIO74, - EXT_CLK_MIO75, - EXT_CLK_MIO76, - EXT_CLK_MIO77, - END_OF_CLKS, + EXT_CLK_VIDEO = (114U), + EXT_CLK_PSS_ALT_REF = (115U), + EXT_CLK_AUX_REF = (116U), + EXT_CLK_GT_CRX_REF = (117U), + EXT_CLK_SWDT0 = (118U), + EXT_CLK_SWDT1 = (119U), + EXT_CLK_GEM0_TX_EMIO = (120U), + EXT_CLK_GEM1_TX_EMIO = (121U), + EXT_CLK_GEM2_TX_EMIO = (122U), + EXT_CLK_GEM3_TX_EMIO = (123U), + EXT_CLK_GEM0_RX_EMIO = (124U), + EXT_CLK_GEM1_RX_EMIO = (125U), + EXT_CLK_GEM2_RX_EMIO = (126U), + EXT_CLK_GEM3_RX_EMIO = (127U), + EXT_CLK_MIO50_OR_MIO51 = (128U), + EXT_CLK_MIO0 = (129U), + EXT_CLK_MIO1 = (130U), + EXT_CLK_MIO2 = (131U), + EXT_CLK_MIO3 = (132U), + EXT_CLK_MIO4 = (133U), + EXT_CLK_MIO5 = (134U), + EXT_CLK_MIO6 = (135U), + EXT_CLK_MIO7 = (136U), + EXT_CLK_MIO8 = (137U), + EXT_CLK_MIO9 = (138U), + EXT_CLK_MIO10 = (139U), + EXT_CLK_MIO11 = (140U), + EXT_CLK_MIO12 = (141U), + EXT_CLK_MIO13 = (142U), + EXT_CLK_MIO14 = (143U), + EXT_CLK_MIO15 = (144U), + EXT_CLK_MIO16 = (145U), + EXT_CLK_MIO17 = (146U), + EXT_CLK_MIO18 = (147U), + EXT_CLK_MIO19 = (148U), + EXT_CLK_MIO20 = (149U), + EXT_CLK_MIO21 = (150U), + EXT_CLK_MIO22 = (151U), + EXT_CLK_MIO23 = (152U), + EXT_CLK_MIO24 = (153U), + EXT_CLK_MIO25 = (154U), + EXT_CLK_MIO26 = (155U), + EXT_CLK_MIO27 = (156U), + EXT_CLK_MIO28 = (157U), + EXT_CLK_MIO29 = (158U), + EXT_CLK_MIO30 = (159U), + EXT_CLK_MIO31 = (160U), + EXT_CLK_MIO32 = (161U), + EXT_CLK_MIO33 = (162U), + EXT_CLK_MIO34 = (163U), + EXT_CLK_MIO35 = (164U), + EXT_CLK_MIO36 = (165U), + EXT_CLK_MIO37 = (166U), + EXT_CLK_MIO38 = (167U), + EXT_CLK_MIO39 = (168U), + EXT_CLK_MIO40 = (169U), + EXT_CLK_MIO41 = (170U), + EXT_CLK_MIO42 = (171U), + EXT_CLK_MIO43 = (172U), + EXT_CLK_MIO44 = (173U), + EXT_CLK_MIO45 = (174U), + EXT_CLK_MIO46 = (175U), + EXT_CLK_MIO47 = (176U), + EXT_CLK_MIO48 = (177U), + EXT_CLK_MIO49 = (178U), + EXT_CLK_MIO50 = (179U), + EXT_CLK_MIO51 = (180U), + EXT_CLK_MIO52 = (181U), + EXT_CLK_MIO53 = (182U), + EXT_CLK_MIO54 = (183U), + EXT_CLK_MIO55 = (184U), + EXT_CLK_MIO56 = (185U), + EXT_CLK_MIO57 = (186U), + EXT_CLK_MIO58 = (187U), + EXT_CLK_MIO59 = (188U), + EXT_CLK_MIO60 = (189U), + EXT_CLK_MIO61 = (190U), + EXT_CLK_MIO62 = (191U), + EXT_CLK_MIO63 = (192U), + EXT_CLK_MIO64 = (193U), + EXT_CLK_MIO65 = (194U), + EXT_CLK_MIO66 = (195U), + EXT_CLK_MIO67 = (196U), + EXT_CLK_MIO68 = (197U), + EXT_CLK_MIO69 = (198U), + EXT_CLK_MIO70 = (199U), + EXT_CLK_MIO71 = (200U), + EXT_CLK_MIO72 = (201U), + EXT_CLK_MIO73 = (202U), + EXT_CLK_MIO74 = (203U), + EXT_CLK_MIO75 = (204U), + EXT_CLK_MIO76 = (205U), + EXT_CLK_MIO77 = (206U), + END_OF_CLKS = (207U), }; -#define CLK_MAX (unsigned int)(END_OF_CLKS) +#define CLK_MAX END_OF_CLKS //CLock types #define CLK_TYPE_OUTPUT 0U @@ -292,20 +292,20 @@ enum { struct pm_pll; struct pm_pll *pm_clock_get_pll(enum clock_id clock_id); struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id); -uint8_t pm_clock_has_div(unsigned int clock_id, enum pm_clock_div_id div_id); +uint8_t pm_clock_has_div(uint32_t clock_id, enum pm_clock_div_id div_id); -void pm_api_clock_get_name(unsigned int clock_id, char *name); -enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks); -enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id, - unsigned int index, +void pm_api_clock_get_name(uint32_t clock_id, char *name); +enum pm_ret_status pm_api_clock_get_num_clocks(uint32_t *nclocks); +enum pm_ret_status pm_api_clock_get_topology(uint32_t clock_id, + uint32_t index, uint32_t *topology); -enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id, +enum pm_ret_status pm_api_clock_get_fixedfactor_params(uint32_t clock_id, uint32_t *mul, uint32_t *div); -enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id, - unsigned int index, +enum pm_ret_status pm_api_clock_get_parents(uint32_t clock_id, + uint32_t index, uint32_t *parents); -enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id, +enum pm_ret_status pm_api_clock_get_attributes(uint32_t clock_id, uint32_t *attr); enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id, uint8_t div_type, @@ -313,21 +313,21 @@ enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id, enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id, enum pm_node_id *node_id); -enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id); +enum pm_ret_status pm_clock_id_is_valid(uint32_t clock_id); enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll); enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll); enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll, - unsigned int *state); + uint32_t *state); enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll, enum clock_id clock_id, - unsigned int parent_index); + uint32_t parent_index); enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll, enum clock_id clock_id, - unsigned int *parent_index); + uint32_t *parent_index); enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id, - unsigned int mode); + uint32_t mode); enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id, - unsigned int *mode); + uint32_t *mode); #endif /* PM_API_CLOCK_H */ diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c index f12143a37..c0bfd51e7 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c @@ -29,13 +29,13 @@ * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_ioctl_get_rpu_oper_mode(unsigned int *mode) +static enum pm_ret_status pm_ioctl_get_rpu_oper_mode(uint32_t *mode) { - unsigned int val; + uint32_t val; val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL); val &= ZYNQMP_SLSPLIT_MASK; - if (val == 0) { + if (val == 0U) { *mode = PM_RPU_MODE_LOCKSTEP; } else { *mode = PM_RPU_MODE_SPLIT; @@ -55,9 +55,9 @@ static enum pm_ret_status pm_ioctl_get_rpu_oper_mode(unsigned int *mode) * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_ioctl_set_rpu_oper_mode(unsigned int mode) +static enum pm_ret_status pm_ioctl_set_rpu_oper_mode(uint32_t mode) { - unsigned int val; + uint32_t val; if (mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET) { return PM_RET_ERROR_ACCESS; @@ -92,9 +92,9 @@ static enum pm_ret_status pm_ioctl_set_rpu_oper_mode(unsigned int mode) * @return Returns status, either success or error+reason */ static enum pm_ret_status pm_ioctl_config_boot_addr(enum pm_node_id nid, - unsigned int value) + uint32_t value) { - unsigned int rpu_cfg_addr, val; + uint32_t rpu_cfg_addr, val; if (nid == NODE_RPU_0) { rpu_cfg_addr = ZYNQMP_RPU0_CFG; @@ -128,9 +128,9 @@ static enum pm_ret_status pm_ioctl_config_boot_addr(enum pm_node_id nid, * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_ioctl_config_tcm_comb(unsigned int value) +static enum pm_ret_status pm_ioctl_config_tcm_comb(uint32_t value) { - unsigned int val; + uint32_t val; val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL); @@ -156,8 +156,8 @@ static enum pm_ret_status pm_ioctl_config_tcm_comb(unsigned int value) * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_ioctl_set_tapdelay_bypass(unsigned int type, - unsigned int value) +static enum pm_ret_status pm_ioctl_set_tapdelay_bypass(uint32_t type, + uint32_t value) { if ((value != PM_TAPDELAY_BYPASS_ENABLE && value != PM_TAPDELAY_BYPASS_DISABLE) || type >= PM_TAPDELAY_MAX) { @@ -179,9 +179,9 @@ static enum pm_ret_status pm_ioctl_set_tapdelay_bypass(unsigned int type, * @return Returns status, either success or error+reason */ static enum pm_ret_status pm_ioctl_set_sgmii_mode(enum pm_node_id nid, - unsigned int value) + uint32_t value) { - unsigned int val, mask, shift; + uint32_t val, mask, shift; enum pm_ret_status ret; if (value != PM_SGMII_DISABLE && value != PM_SGMII_ENABLE) { @@ -237,9 +237,9 @@ static enum pm_ret_status pm_ioctl_set_sgmii_mode(enum pm_node_id nid, * @return Returns status, either success or error+reason */ static enum pm_ret_status pm_ioctl_sd_dll_reset(enum pm_node_id nid, - unsigned int type) + uint32_t type) { - unsigned int mask, val; + uint32_t mask, val; enum pm_ret_status ret; if (nid == NODE_SD_0) { @@ -288,11 +288,11 @@ static enum pm_ret_status pm_ioctl_sd_dll_reset(enum pm_node_id nid, */ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid, enum tap_delay_type type, - unsigned int value) + uint32_t value) { - unsigned int shift; + uint32_t shift; enum pm_ret_status ret; - unsigned int val, mask; + uint32_t val, mask; if (nid == NODE_SD_0) { shift = 0; @@ -309,7 +309,7 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid, return ret; } - if ((val & mask) == 0) { + if ((val & mask) == 0U) { ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT); if (ret != PM_RET_SUCCESS) { return ret; @@ -325,7 +325,7 @@ static enum pm_ret_status pm_ioctl_sd_set_tapdelay(enum pm_node_id nid, goto reset_release; } - if (value == 0) { + if (value == 0U) { ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY, (ZYNQMP_SD_ITAPDLYENA_MASK << shift), 0); @@ -384,7 +384,7 @@ reset_release: * @return Returns status, either success or error+reason */ static enum pm_ret_status pm_ioctl_set_pll_frac_mode - (unsigned int pll, unsigned int mode) + (uint32_t pll, uint32_t mode) { return pm_clock_set_pll_mode(pll, mode); } @@ -400,7 +400,7 @@ static enum pm_ret_status pm_ioctl_set_pll_frac_mode * @return Returns status, either success or error+reason */ static enum pm_ret_status pm_ioctl_get_pll_frac_mode - (unsigned int pll, unsigned int *mode) + (uint32_t pll, uint32_t *mode) { return pm_clock_get_pll_mode(pll, mode); } @@ -417,7 +417,7 @@ static enum pm_ret_status pm_ioctl_get_pll_frac_mode * @return Returns status, either success or error+reason */ static enum pm_ret_status pm_ioctl_set_pll_frac_data - (unsigned int pll, unsigned int data) + (uint32_t pll, uint32_t data) { enum pm_node_id pll_nid; enum pm_ret_status status; @@ -442,7 +442,7 @@ static enum pm_ret_status pm_ioctl_set_pll_frac_data * @return Returns status, either success or error+reason */ static enum pm_ret_status pm_ioctl_get_pll_frac_data - (unsigned int pll, unsigned int *data) + (uint32_t pll, uint32_t *data) { enum pm_node_id pll_nid; enum pm_ret_status status; @@ -466,8 +466,8 @@ static enum pm_ret_status pm_ioctl_get_pll_frac_data * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_ioctl_write_ggs(unsigned int index, - unsigned int value) +static enum pm_ret_status pm_ioctl_write_ggs(uint32_t index, + uint32_t value) { if (index >= GGS_NUM_REGS) { return PM_RET_ERROR_ARGS; @@ -487,8 +487,8 @@ static enum pm_ret_status pm_ioctl_write_ggs(unsigned int index, * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_ioctl_read_ggs(unsigned int index, - unsigned int *value) +static enum pm_ret_status pm_ioctl_read_ggs(uint32_t index, + uint32_t *value) { if (index >= GGS_NUM_REGS) { return PM_RET_ERROR_ARGS; @@ -507,8 +507,8 @@ static enum pm_ret_status pm_ioctl_read_ggs(unsigned int index, * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_ioctl_write_pggs(unsigned int index, - unsigned int value) +static enum pm_ret_status pm_ioctl_write_pggs(uint32_t index, + uint32_t value) { if (index >= PGGS_NUM_REGS) { return PM_RET_ERROR_ARGS; @@ -527,11 +527,11 @@ static enum pm_ret_status pm_ioctl_write_pggs(unsigned int index, * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_ioctl_afi(unsigned int index, - unsigned int value) +static enum pm_ret_status pm_ioctl_afi(uint32_t index, + uint32_t value) { - unsigned int mask; - unsigned int regarr[] = {0xFD360000U, + uint32_t mask; + uint32_t regarr[] = {0xFD360000U, 0xFD360014U, 0xFD370000U, 0xFD370014U, @@ -553,7 +553,7 @@ static enum pm_ret_status pm_ioctl_afi(unsigned int index, return PM_RET_ERROR_ARGS; } - if (index < AFIFM6_WRCTRL) { + if (index <= AFIFM6_WRCTRL) { mask = FABRIC_WIDTH; } else { mask = 0xf00; @@ -572,8 +572,8 @@ static enum pm_ret_status pm_ioctl_afi(unsigned int index, * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_ioctl_read_pggs(unsigned int index, - unsigned int *value) +static enum pm_ret_status pm_ioctl_read_pggs(uint32_t index, + uint32_t *value) { if (index >= PGGS_NUM_REGS) { return PM_RET_ERROR_ARGS; @@ -626,7 +626,7 @@ static enum pm_ret_status pm_ioctl_ulpi_reset(void) * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_ioctl_set_boot_health_status(unsigned int value) +static enum pm_ret_status pm_ioctl_set_boot_health_status(uint32_t value) { return pm_mmio_write(PMU_GLOBAL_GEN_STORAGE4, PM_BOOT_HEALTH_STATUS_MASK, value); @@ -645,10 +645,10 @@ static enum pm_ret_status pm_ioctl_set_boot_health_status(unsigned int value) * @return Returns status, either success or error+reason */ enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, - unsigned int ioctl_id, - unsigned int arg1, - unsigned int arg2, - unsigned int *value) + uint32_t ioctl_id, + uint32_t arg1, + uint32_t arg2, + uint32_t *value) { enum pm_ret_status ret; uint32_t payload[PAYLOAD_ARG_CNT]; @@ -750,7 +750,7 @@ enum pm_ret_status atf_ioctl_bitmask(uint32_t *bit_mask) IOCTL_AFI, }; uint8_t i, ioctl_id; - int ret; + int32_t ret; for (i = 0U; i < ARRAY_SIZE(supported_ids); i++) { ioctl_id = supported_ids[i]; @@ -759,7 +759,7 @@ enum pm_ret_status atf_ioctl_bitmask(uint32_t *bit_mask) } ret = check_api_dependency(ioctl_id); if (ret == PM_RET_SUCCESS) { - bit_mask[ioctl_id / 32] |= BIT(ioctl_id % 32); + bit_mask[ioctl_id / 32U] |= BIT(ioctl_id % 32U); } } diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h index 0c5f33fa6..3b0d6ee37 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h @@ -88,9 +88,9 @@ enum tap_delay_type { #define PM_DLL_RESET_PULSE 2U enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, - unsigned int ioctl_id, - unsigned int arg1, - unsigned int arg2, - unsigned int *value); + uint32_t ioctl_id, + uint32_t arg1, + uint32_t arg2, + uint32_t *value); enum pm_ret_status atf_ioctl_bitmask(uint32_t *bit_mask); #endif /* PM_API_IOCTL_H */ diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c index 75e0499f4..8f373418c 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c @@ -21,12 +21,13 @@ struct pinctrl_function { char name[FUNCTION_NAME_LEN]; - uint16_t (*groups)[]; + uint16_t group_base; + uint8_t group_size; uint8_t regval; }; /* Max groups for one pin */ -#define MAX_PIN_GROUPS U(13) +#define MAX_PIN_GROUPS (13U) struct zynqmp_pin_group { uint16_t (*groups)[]; @@ -36,904 +37,344 @@ static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = { [PINCTRL_FUNC_CAN0] = { .name = "can0", .regval = 0x20, - .groups = &((uint16_t []) { - PINCTRL_GRP_CAN0_0, - PINCTRL_GRP_CAN0_1, - PINCTRL_GRP_CAN0_2, - PINCTRL_GRP_CAN0_3, - PINCTRL_GRP_CAN0_4, - PINCTRL_GRP_CAN0_5, - PINCTRL_GRP_CAN0_6, - PINCTRL_GRP_CAN0_7, - PINCTRL_GRP_CAN0_8, - PINCTRL_GRP_CAN0_9, - PINCTRL_GRP_CAN0_10, - PINCTRL_GRP_CAN0_11, - PINCTRL_GRP_CAN0_12, - PINCTRL_GRP_CAN0_13, - PINCTRL_GRP_CAN0_14, - PINCTRL_GRP_CAN0_15, - PINCTRL_GRP_CAN0_16, - PINCTRL_GRP_CAN0_17, - PINCTRL_GRP_CAN0_18, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_CAN0_0, + .group_size = PINCTRL_GRP_CAN0_18 - PINCTRL_GRP_CAN0_0 + 1U, }, [PINCTRL_FUNC_CAN1] = { .name = "can1", .regval = 0x20, - .groups = &((uint16_t []) { - PINCTRL_GRP_CAN1_0, - PINCTRL_GRP_CAN1_1, - PINCTRL_GRP_CAN1_2, - PINCTRL_GRP_CAN1_3, - PINCTRL_GRP_CAN1_4, - PINCTRL_GRP_CAN1_5, - PINCTRL_GRP_CAN1_6, - PINCTRL_GRP_CAN1_7, - PINCTRL_GRP_CAN1_8, - PINCTRL_GRP_CAN1_9, - PINCTRL_GRP_CAN1_10, - PINCTRL_GRP_CAN1_11, - PINCTRL_GRP_CAN1_12, - PINCTRL_GRP_CAN1_13, - PINCTRL_GRP_CAN1_14, - PINCTRL_GRP_CAN1_15, - PINCTRL_GRP_CAN1_16, - PINCTRL_GRP_CAN1_17, - PINCTRL_GRP_CAN1_18, - PINCTRL_GRP_CAN1_19, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_CAN1_0, + .group_size = PINCTRL_GRP_CAN1_19 - PINCTRL_GRP_CAN1_0 + 1U, }, [PINCTRL_FUNC_ETHERNET0] = { .name = "ethernet0", .regval = 0x02, - .groups = &((uint16_t []) { - PINCTRL_GRP_ETHERNET0_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_ETHERNET0_0, + .group_size = PINCTRL_GRP_ETHERNET0_0 - PINCTRL_GRP_ETHERNET0_0 + 1U, }, [PINCTRL_FUNC_ETHERNET1] = { .name = "ethernet1", .regval = 0x02, - .groups = &((uint16_t []) { - PINCTRL_GRP_ETHERNET1_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_ETHERNET1_0, + .group_size = PINCTRL_GRP_ETHERNET1_0 - PINCTRL_GRP_ETHERNET1_0 + 1U, }, [PINCTRL_FUNC_ETHERNET2] = { .name = "ethernet2", .regval = 0x02, - .groups = &((uint16_t []) { - PINCTRL_GRP_ETHERNET2_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_ETHERNET2_0, + .group_size = PINCTRL_GRP_ETHERNET2_0 - PINCTRL_GRP_ETHERNET2_0 + 1U, }, [PINCTRL_FUNC_ETHERNET3] = { .name = "ethernet3", .regval = 0x02, - .groups = &((uint16_t []) { - PINCTRL_GRP_ETHERNET3_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_ETHERNET3_0, + .group_size = PINCTRL_GRP_ETHERNET3_0 - PINCTRL_GRP_ETHERNET3_0 + 1U, }, [PINCTRL_FUNC_GEMTSU0] = { .name = "gemtsu0", .regval = 0x02, - .groups = &((uint16_t []) { - PINCTRL_GRP_GEMTSU0_0, - PINCTRL_GRP_GEMTSU0_1, - PINCTRL_GRP_GEMTSU0_2, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_GEMTSU0_0, + .group_size = PINCTRL_GRP_GEMTSU0_2 - PINCTRL_GRP_GEMTSU0_0 + 1U, }, [PINCTRL_FUNC_GPIO0] = { .name = "gpio0", .regval = 0x00, - .groups = &((uint16_t []) { - PINCTRL_GRP_GPIO0_0, - PINCTRL_GRP_GPIO0_1, - PINCTRL_GRP_GPIO0_2, - PINCTRL_GRP_GPIO0_3, - PINCTRL_GRP_GPIO0_4, - PINCTRL_GRP_GPIO0_5, - PINCTRL_GRP_GPIO0_6, - PINCTRL_GRP_GPIO0_7, - PINCTRL_GRP_GPIO0_8, - PINCTRL_GRP_GPIO0_9, - PINCTRL_GRP_GPIO0_10, - PINCTRL_GRP_GPIO0_11, - PINCTRL_GRP_GPIO0_12, - PINCTRL_GRP_GPIO0_13, - PINCTRL_GRP_GPIO0_14, - PINCTRL_GRP_GPIO0_15, - PINCTRL_GRP_GPIO0_16, - PINCTRL_GRP_GPIO0_17, - PINCTRL_GRP_GPIO0_18, - PINCTRL_GRP_GPIO0_19, - PINCTRL_GRP_GPIO0_20, - PINCTRL_GRP_GPIO0_21, - PINCTRL_GRP_GPIO0_22, - PINCTRL_GRP_GPIO0_23, - PINCTRL_GRP_GPIO0_24, - PINCTRL_GRP_GPIO0_25, - PINCTRL_GRP_GPIO0_26, - PINCTRL_GRP_GPIO0_27, - PINCTRL_GRP_GPIO0_28, - PINCTRL_GRP_GPIO0_29, - PINCTRL_GRP_GPIO0_30, - PINCTRL_GRP_GPIO0_31, - PINCTRL_GRP_GPIO0_32, - PINCTRL_GRP_GPIO0_33, - PINCTRL_GRP_GPIO0_34, - PINCTRL_GRP_GPIO0_35, - PINCTRL_GRP_GPIO0_36, - PINCTRL_GRP_GPIO0_37, - PINCTRL_GRP_GPIO0_38, - PINCTRL_GRP_GPIO0_39, - PINCTRL_GRP_GPIO0_40, - PINCTRL_GRP_GPIO0_41, - PINCTRL_GRP_GPIO0_42, - PINCTRL_GRP_GPIO0_43, - PINCTRL_GRP_GPIO0_44, - PINCTRL_GRP_GPIO0_45, - PINCTRL_GRP_GPIO0_46, - PINCTRL_GRP_GPIO0_47, - PINCTRL_GRP_GPIO0_48, - PINCTRL_GRP_GPIO0_49, - PINCTRL_GRP_GPIO0_50, - PINCTRL_GRP_GPIO0_51, - PINCTRL_GRP_GPIO0_52, - PINCTRL_GRP_GPIO0_53, - PINCTRL_GRP_GPIO0_54, - PINCTRL_GRP_GPIO0_55, - PINCTRL_GRP_GPIO0_56, - PINCTRL_GRP_GPIO0_57, - PINCTRL_GRP_GPIO0_58, - PINCTRL_GRP_GPIO0_59, - PINCTRL_GRP_GPIO0_60, - PINCTRL_GRP_GPIO0_61, - PINCTRL_GRP_GPIO0_62, - PINCTRL_GRP_GPIO0_63, - PINCTRL_GRP_GPIO0_64, - PINCTRL_GRP_GPIO0_65, - PINCTRL_GRP_GPIO0_66, - PINCTRL_GRP_GPIO0_67, - PINCTRL_GRP_GPIO0_68, - PINCTRL_GRP_GPIO0_69, - PINCTRL_GRP_GPIO0_70, - PINCTRL_GRP_GPIO0_71, - PINCTRL_GRP_GPIO0_72, - PINCTRL_GRP_GPIO0_73, - PINCTRL_GRP_GPIO0_74, - PINCTRL_GRP_GPIO0_75, - PINCTRL_GRP_GPIO0_76, - PINCTRL_GRP_GPIO0_77, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_GPIO0_0, + .group_size = PINCTRL_GRP_GPIO0_77 - PINCTRL_GRP_GPIO0_0 + 1U, }, [PINCTRL_FUNC_I2C0] = { .name = "i2c0", .regval = 0x40, - .groups = &((uint16_t []) { - PINCTRL_GRP_I2C0_0, - PINCTRL_GRP_I2C0_1, - PINCTRL_GRP_I2C0_2, - PINCTRL_GRP_I2C0_3, - PINCTRL_GRP_I2C0_4, - PINCTRL_GRP_I2C0_5, - PINCTRL_GRP_I2C0_6, - PINCTRL_GRP_I2C0_7, - PINCTRL_GRP_I2C0_8, - PINCTRL_GRP_I2C0_9, - PINCTRL_GRP_I2C0_10, - PINCTRL_GRP_I2C0_11, - PINCTRL_GRP_I2C0_12, - PINCTRL_GRP_I2C0_13, - PINCTRL_GRP_I2C0_14, - PINCTRL_GRP_I2C0_15, - PINCTRL_GRP_I2C0_16, - PINCTRL_GRP_I2C0_17, - PINCTRL_GRP_I2C0_18, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_I2C0_0, + .group_size = PINCTRL_GRP_I2C0_18 - PINCTRL_GRP_I2C0_0 + 1U, }, [PINCTRL_FUNC_I2C1] = { .name = "i2c1", .regval = 0x40, - .groups = &((uint16_t []) { - PINCTRL_GRP_I2C1_0, - PINCTRL_GRP_I2C1_1, - PINCTRL_GRP_I2C1_2, - PINCTRL_GRP_I2C1_3, - PINCTRL_GRP_I2C1_4, - PINCTRL_GRP_I2C1_5, - PINCTRL_GRP_I2C1_6, - PINCTRL_GRP_I2C1_7, - PINCTRL_GRP_I2C1_8, - PINCTRL_GRP_I2C1_9, - PINCTRL_GRP_I2C1_10, - PINCTRL_GRP_I2C1_11, - PINCTRL_GRP_I2C1_12, - PINCTRL_GRP_I2C1_13, - PINCTRL_GRP_I2C1_14, - PINCTRL_GRP_I2C1_15, - PINCTRL_GRP_I2C1_16, - PINCTRL_GRP_I2C1_17, - PINCTRL_GRP_I2C1_18, - PINCTRL_GRP_I2C1_19, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_I2C1_0, + .group_size = PINCTRL_GRP_I2C1_19 - PINCTRL_GRP_I2C1_0 + 1U, }, [PINCTRL_FUNC_MDIO0] = { .name = "mdio0", .regval = 0x60, - .groups = &((uint16_t []) { - PINCTRL_GRP_MDIO0_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_MDIO0_0, + .group_size = PINCTRL_GRP_MDIO0_0 - PINCTRL_GRP_MDIO0_0 + 1U, }, [PINCTRL_FUNC_MDIO1] = { .name = "mdio1", .regval = 0x80, - .groups = &((uint16_t []) { - PINCTRL_GRP_MDIO1_0, - PINCTRL_GRP_MDIO1_1, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_MDIO1_0, + .group_size = PINCTRL_GRP_MDIO1_1 - PINCTRL_GRP_MDIO1_0 + 1U, }, [PINCTRL_FUNC_MDIO2] = { .name = "mdio2", .regval = 0xa0, - .groups = &((uint16_t []) { - PINCTRL_GRP_MDIO2_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_MDIO2_0, + .group_size = PINCTRL_GRP_MDIO2_0 - PINCTRL_GRP_MDIO2_0 + 1U, }, [PINCTRL_FUNC_MDIO3] = { .name = "mdio3", .regval = 0xc0, - .groups = &((uint16_t []) { - PINCTRL_GRP_MDIO3_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_MDIO3_0, + .group_size = PINCTRL_GRP_MDIO3_0 - PINCTRL_GRP_MDIO3_0 + 1U, }, [PINCTRL_FUNC_QSPI0] = { .name = "qspi0", .regval = 0x02, - .groups = &((uint16_t []) { - PINCTRL_GRP_QSPI0_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_QSPI0_0, + .group_size = PINCTRL_GRP_QSPI0_0 - PINCTRL_GRP_QSPI0_0 + 1U, }, [PINCTRL_FUNC_QSPI_FBCLK] = { .name = "qspi_fbclk", .regval = 0x02, - .groups = &((uint16_t []) { - PINCTRL_GRP_QSPI_FBCLK, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_QSPI_FBCLK, + .group_size = PINCTRL_GRP_QSPI_FBCLK - PINCTRL_GRP_QSPI_FBCLK + 1U, }, [PINCTRL_FUNC_QSPI_SS] = { .name = "qspi_ss", .regval = 0x02, - .groups = &((uint16_t []) { - PINCTRL_GRP_QSPI_SS, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_QSPI_SS, + .group_size = PINCTRL_GRP_QSPI_SS - PINCTRL_GRP_QSPI_SS + 1U, }, [PINCTRL_FUNC_SPI0] = { .name = "spi0", .regval = 0x80, - .groups = &((uint16_t []) { - PINCTRL_GRP_SPI0_0, - PINCTRL_GRP_SPI0_1, - PINCTRL_GRP_SPI0_2, - PINCTRL_GRP_SPI0_3, - PINCTRL_GRP_SPI0_4, - PINCTRL_GRP_SPI0_5, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SPI0_0, + .group_size = PINCTRL_GRP_SPI0_5 - PINCTRL_GRP_SPI0_0 + 1U, }, [PINCTRL_FUNC_SPI1] = { .name = "spi1", .regval = 0x80, - .groups = &((uint16_t []) { - PINCTRL_GRP_SPI1_0, - PINCTRL_GRP_SPI1_1, - PINCTRL_GRP_SPI1_2, - PINCTRL_GRP_SPI1_3, - PINCTRL_GRP_SPI1_4, - PINCTRL_GRP_SPI1_5, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SPI1_0, + .group_size = PINCTRL_GRP_SPI1_5 - PINCTRL_GRP_SPI1_0 + 1U, }, [PINCTRL_FUNC_SPI0_SS] = { .name = "spi0_ss", .regval = 0x80, - .groups = &((uint16_t []) { - PINCTRL_GRP_SPI0_0_SS0, - PINCTRL_GRP_SPI0_0_SS1, - PINCTRL_GRP_SPI0_0_SS2, - PINCTRL_GRP_SPI0_1_SS0, - PINCTRL_GRP_SPI0_1_SS1, - PINCTRL_GRP_SPI0_1_SS2, - PINCTRL_GRP_SPI0_2_SS0, - PINCTRL_GRP_SPI0_2_SS1, - PINCTRL_GRP_SPI0_2_SS2, - PINCTRL_GRP_SPI0_3_SS0, - PINCTRL_GRP_SPI0_3_SS1, - PINCTRL_GRP_SPI0_3_SS2, - PINCTRL_GRP_SPI0_4_SS0, - PINCTRL_GRP_SPI0_4_SS1, - PINCTRL_GRP_SPI0_4_SS2, - PINCTRL_GRP_SPI0_5_SS0, - PINCTRL_GRP_SPI0_5_SS1, - PINCTRL_GRP_SPI0_5_SS2, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SPI0_0_SS0, + .group_size = PINCTRL_GRP_SPI0_5_SS2 - PINCTRL_GRP_SPI0_0_SS0 + 1U, }, [PINCTRL_FUNC_SPI1_SS] = { .name = "spi1_ss", .regval = 0x80, - .groups = &((uint16_t []) { - PINCTRL_GRP_SPI1_0_SS0, - PINCTRL_GRP_SPI1_0_SS1, - PINCTRL_GRP_SPI1_0_SS2, - PINCTRL_GRP_SPI1_1_SS0, - PINCTRL_GRP_SPI1_1_SS1, - PINCTRL_GRP_SPI1_1_SS2, - PINCTRL_GRP_SPI1_2_SS0, - PINCTRL_GRP_SPI1_2_SS1, - PINCTRL_GRP_SPI1_2_SS2, - PINCTRL_GRP_SPI1_3_SS0, - PINCTRL_GRP_SPI1_3_SS1, - PINCTRL_GRP_SPI1_3_SS2, - PINCTRL_GRP_SPI1_4_SS0, - PINCTRL_GRP_SPI1_4_SS1, - PINCTRL_GRP_SPI1_4_SS2, - PINCTRL_GRP_SPI1_5_SS0, - PINCTRL_GRP_SPI1_5_SS1, - PINCTRL_GRP_SPI1_5_SS2, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SPI1_0_SS0, + .group_size = PINCTRL_GRP_SPI1_5_SS2 - PINCTRL_GRP_SPI1_0_SS0 + 1U, }, [PINCTRL_FUNC_SDIO0] = { .name = "sdio0", .regval = 0x08, - .groups = &((uint16_t []) { - PINCTRL_GRP_SDIO0_0, - PINCTRL_GRP_SDIO0_1, - PINCTRL_GRP_SDIO0_2, - PINCTRL_GRP_SDIO0_4BIT_0_0, - PINCTRL_GRP_SDIO0_4BIT_0_1, - PINCTRL_GRP_SDIO0_4BIT_1_0, - PINCTRL_GRP_SDIO0_4BIT_1_1, - PINCTRL_GRP_SDIO0_4BIT_2_0, - PINCTRL_GRP_SDIO0_4BIT_2_1, - PINCTRL_GRP_SDIO0_1BIT_0_0, - PINCTRL_GRP_SDIO0_1BIT_0_1, - PINCTRL_GRP_SDIO0_1BIT_0_2, - PINCTRL_GRP_SDIO0_1BIT_0_3, - PINCTRL_GRP_SDIO0_1BIT_0_4, - PINCTRL_GRP_SDIO0_1BIT_0_5, - PINCTRL_GRP_SDIO0_1BIT_0_6, - PINCTRL_GRP_SDIO0_1BIT_0_7, - PINCTRL_GRP_SDIO0_1BIT_1_0, - PINCTRL_GRP_SDIO0_1BIT_1_1, - PINCTRL_GRP_SDIO0_1BIT_1_2, - PINCTRL_GRP_SDIO0_1BIT_1_3, - PINCTRL_GRP_SDIO0_1BIT_1_4, - PINCTRL_GRP_SDIO0_1BIT_1_5, - PINCTRL_GRP_SDIO0_1BIT_1_6, - PINCTRL_GRP_SDIO0_1BIT_1_7, - PINCTRL_GRP_SDIO0_1BIT_2_0, - PINCTRL_GRP_SDIO0_1BIT_2_1, - PINCTRL_GRP_SDIO0_1BIT_2_2, - PINCTRL_GRP_SDIO0_1BIT_2_3, - PINCTRL_GRP_SDIO0_1BIT_2_4, - PINCTRL_GRP_SDIO0_1BIT_2_5, - PINCTRL_GRP_SDIO0_1BIT_2_6, - PINCTRL_GRP_SDIO0_1BIT_2_7, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SDIO0_0, + .group_size = PINCTRL_GRP_SDIO0_1BIT_2_7 - PINCTRL_GRP_SDIO0_0 + 1U, }, [PINCTRL_FUNC_SDIO0_PC] = { .name = "sdio0_pc", .regval = 0x08, - .groups = &((uint16_t []) { - PINCTRL_GRP_SDIO0_0_PC, - PINCTRL_GRP_SDIO0_1_PC, - PINCTRL_GRP_SDIO0_2_PC, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SDIO0_0_PC, + .group_size = PINCTRL_GRP_SDIO0_2_PC - PINCTRL_GRP_SDIO0_0_PC + 1U, }, [PINCTRL_FUNC_SDIO0_CD] = { .name = "sdio0_cd", .regval = 0x08, - .groups = &((uint16_t []) { - PINCTRL_GRP_SDIO0_0_CD, - PINCTRL_GRP_SDIO0_1_CD, - PINCTRL_GRP_SDIO0_2_CD, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SDIO0_0_CD, + .group_size = PINCTRL_GRP_SDIO0_2_CD - PINCTRL_GRP_SDIO0_0_CD + 1U, }, [PINCTRL_FUNC_SDIO0_WP] = { .name = "sdio0_wp", .regval = 0x08, - .groups = &((uint16_t []) { - PINCTRL_GRP_SDIO0_0_WP, - PINCTRL_GRP_SDIO0_1_WP, - PINCTRL_GRP_SDIO0_2_WP, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SDIO0_0_WP, + .group_size = PINCTRL_GRP_SDIO0_2_WP - PINCTRL_GRP_SDIO0_0_WP + 1U, }, [PINCTRL_FUNC_SDIO1] = { .name = "sdio1", .regval = 0x10, - .groups = &((uint16_t []) { - PINCTRL_GRP_SDIO1_0, - PINCTRL_GRP_SDIO1_4BIT_0_0, - PINCTRL_GRP_SDIO1_4BIT_0_1, - PINCTRL_GRP_SDIO1_4BIT_1_0, - PINCTRL_GRP_SDIO1_1BIT_0_0, - PINCTRL_GRP_SDIO1_1BIT_0_1, - PINCTRL_GRP_SDIO1_1BIT_0_2, - PINCTRL_GRP_SDIO1_1BIT_0_3, - PINCTRL_GRP_SDIO1_1BIT_0_4, - PINCTRL_GRP_SDIO1_1BIT_0_5, - PINCTRL_GRP_SDIO1_1BIT_0_6, - PINCTRL_GRP_SDIO1_1BIT_0_7, - PINCTRL_GRP_SDIO1_1BIT_1_0, - PINCTRL_GRP_SDIO1_1BIT_1_1, - PINCTRL_GRP_SDIO1_1BIT_1_2, - PINCTRL_GRP_SDIO1_1BIT_1_3, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SDIO1_0, + .group_size = PINCTRL_GRP_SDIO1_1BIT_1_3 - PINCTRL_GRP_SDIO1_0 + 1U, }, [PINCTRL_FUNC_SDIO1_PC] = { .name = "sdio1_pc", .regval = 0x10, - .groups = &((uint16_t []) { - PINCTRL_GRP_SDIO1_0_PC, - PINCTRL_GRP_SDIO1_1_PC, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SDIO1_0_PC, + .group_size = PINCTRL_GRP_SDIO1_1_PC - PINCTRL_GRP_SDIO1_0_PC + 1U, }, [PINCTRL_FUNC_SDIO1_CD] = { .name = "sdio1_cd", .regval = 0x10, - .groups = &((uint16_t []) { - PINCTRL_GRP_SDIO1_0_CD, - PINCTRL_GRP_SDIO1_1_CD, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SDIO1_0_CD, + .group_size = PINCTRL_GRP_SDIO1_1_CD - PINCTRL_GRP_SDIO1_0_CD + 1U, }, [PINCTRL_FUNC_SDIO1_WP] = { .name = "sdio1_wp", .regval = 0x10, - .groups = &((uint16_t []) { - PINCTRL_GRP_SDIO1_0_WP, - PINCTRL_GRP_SDIO1_1_WP, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SDIO1_0_WP, + .group_size = PINCTRL_GRP_SDIO1_1_WP - PINCTRL_GRP_SDIO1_0_WP + 1U, }, [PINCTRL_FUNC_NAND0] = { .name = "nand0", .regval = 0x04, - .groups = &((uint16_t []) { - PINCTRL_GRP_NAND0_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_NAND0_0, + .group_size = PINCTRL_GRP_NAND0_0 - PINCTRL_GRP_NAND0_0 + 1U, }, [PINCTRL_FUNC_NAND0_CE] = { .name = "nand0_ce", .regval = 0x04, - .groups = &((uint16_t []) { - PINCTRL_GRP_NAND0_0_CE, - PINCTRL_GRP_NAND0_1_CE, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_NAND0_0_CE, + .group_size = PINCTRL_GRP_NAND0_1_CE - PINCTRL_GRP_NAND0_0_CE + 1U, }, [PINCTRL_FUNC_NAND0_RB] = { .name = "nand0_rb", .regval = 0x04, - .groups = &((uint16_t []) { - PINCTRL_GRP_NAND0_0_RB, - PINCTRL_GRP_NAND0_1_RB, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_NAND0_0_RB, + .group_size = PINCTRL_GRP_NAND0_1_RB - PINCTRL_GRP_NAND0_0_RB + 1U, }, [PINCTRL_FUNC_NAND0_DQS] = { .name = "nand0_dqs", .regval = 0x04, - .groups = &((uint16_t []) { - PINCTRL_GRP_NAND0_0_DQS, - PINCTRL_GRP_NAND0_1_DQS, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_NAND0_0_DQS, + .group_size = PINCTRL_GRP_NAND0_1_DQS - PINCTRL_GRP_NAND0_0_DQS + 1U, }, [PINCTRL_FUNC_TTC0_CLK] = { .name = "ttc0_clk", .regval = 0xa0, - .groups = &((uint16_t []) { - PINCTRL_GRP_TTC0_0_CLK, - PINCTRL_GRP_TTC0_1_CLK, - PINCTRL_GRP_TTC0_2_CLK, - PINCTRL_GRP_TTC0_3_CLK, - PINCTRL_GRP_TTC0_4_CLK, - PINCTRL_GRP_TTC0_5_CLK, - PINCTRL_GRP_TTC0_6_CLK, - PINCTRL_GRP_TTC0_7_CLK, - PINCTRL_GRP_TTC0_8_CLK, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TTC0_0_CLK, + .group_size = PINCTRL_GRP_TTC0_8_CLK - PINCTRL_GRP_TTC0_0_CLK + 1U, }, [PINCTRL_FUNC_TTC0_WAV] = { .name = "ttc0_wav", .regval = 0xa0, - .groups = &((uint16_t []) { - PINCTRL_GRP_TTC0_0_WAV, - PINCTRL_GRP_TTC0_1_WAV, - PINCTRL_GRP_TTC0_2_WAV, - PINCTRL_GRP_TTC0_3_WAV, - PINCTRL_GRP_TTC0_4_WAV, - PINCTRL_GRP_TTC0_5_WAV, - PINCTRL_GRP_TTC0_6_WAV, - PINCTRL_GRP_TTC0_7_WAV, - PINCTRL_GRP_TTC0_8_WAV, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TTC0_0_WAV, + .group_size = PINCTRL_GRP_TTC0_8_WAV - PINCTRL_GRP_TTC0_0_WAV + 1U, }, [PINCTRL_FUNC_TTC1_CLK] = { .name = "ttc1_clk", .regval = 0xa0, - .groups = &((uint16_t []) { - PINCTRL_GRP_TTC1_0_CLK, - PINCTRL_GRP_TTC1_1_CLK, - PINCTRL_GRP_TTC1_2_CLK, - PINCTRL_GRP_TTC1_3_CLK, - PINCTRL_GRP_TTC1_4_CLK, - PINCTRL_GRP_TTC1_5_CLK, - PINCTRL_GRP_TTC1_6_CLK, - PINCTRL_GRP_TTC1_7_CLK, - PINCTRL_GRP_TTC1_8_CLK, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TTC1_0_CLK, + .group_size = PINCTRL_GRP_TTC1_8_CLK - PINCTRL_GRP_TTC1_0_CLK + 1U, }, [PINCTRL_FUNC_TTC1_WAV] = { .name = "ttc1_wav", .regval = 0xa0, - .groups = &((uint16_t []) { - PINCTRL_GRP_TTC1_0_WAV, - PINCTRL_GRP_TTC1_1_WAV, - PINCTRL_GRP_TTC1_2_WAV, - PINCTRL_GRP_TTC1_3_WAV, - PINCTRL_GRP_TTC1_4_WAV, - PINCTRL_GRP_TTC1_5_WAV, - PINCTRL_GRP_TTC1_6_WAV, - PINCTRL_GRP_TTC1_7_WAV, - PINCTRL_GRP_TTC1_8_WAV, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TTC1_0_WAV, + .group_size = PINCTRL_GRP_TTC1_8_WAV - PINCTRL_GRP_TTC1_0_WAV + 1U, }, [PINCTRL_FUNC_TTC2_CLK] = { .name = "ttc2_clk", .regval = 0xa0, - .groups = &((uint16_t []) { - PINCTRL_GRP_TTC2_0_CLK, - PINCTRL_GRP_TTC2_1_CLK, - PINCTRL_GRP_TTC2_2_CLK, - PINCTRL_GRP_TTC2_3_CLK, - PINCTRL_GRP_TTC2_4_CLK, - PINCTRL_GRP_TTC2_5_CLK, - PINCTRL_GRP_TTC2_6_CLK, - PINCTRL_GRP_TTC2_7_CLK, - PINCTRL_GRP_TTC2_8_CLK, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TTC2_0_CLK, + .group_size = PINCTRL_GRP_TTC2_8_CLK - PINCTRL_GRP_TTC2_0_CLK + 1U, }, [PINCTRL_FUNC_TTC2_WAV] = { .name = "ttc2_wav", .regval = 0xa0, - .groups = &((uint16_t []) { - PINCTRL_GRP_TTC2_0_WAV, - PINCTRL_GRP_TTC2_1_WAV, - PINCTRL_GRP_TTC2_2_WAV, - PINCTRL_GRP_TTC2_3_WAV, - PINCTRL_GRP_TTC2_4_WAV, - PINCTRL_GRP_TTC2_5_WAV, - PINCTRL_GRP_TTC2_6_WAV, - PINCTRL_GRP_TTC2_7_WAV, - PINCTRL_GRP_TTC2_8_WAV, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TTC2_0_WAV, + .group_size = PINCTRL_GRP_TTC2_8_WAV - PINCTRL_GRP_TTC2_0_WAV + 1U, }, [PINCTRL_FUNC_TTC3_CLK] = { .name = "ttc3_clk", .regval = 0xa0, - .groups = &((uint16_t []) { - PINCTRL_GRP_TTC3_0_CLK, - PINCTRL_GRP_TTC3_1_CLK, - PINCTRL_GRP_TTC3_2_CLK, - PINCTRL_GRP_TTC3_3_CLK, - PINCTRL_GRP_TTC3_4_CLK, - PINCTRL_GRP_TTC3_5_CLK, - PINCTRL_GRP_TTC3_6_CLK, - PINCTRL_GRP_TTC3_7_CLK, - PINCTRL_GRP_TTC3_8_CLK, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TTC3_0_CLK, + .group_size = PINCTRL_GRP_TTC3_8_CLK - PINCTRL_GRP_TTC3_0_CLK + 1U, }, [PINCTRL_FUNC_TTC3_WAV] = { .name = "ttc3_wav", .regval = 0xa0, - .groups = &((uint16_t []) { - PINCTRL_GRP_TTC3_0_WAV, - PINCTRL_GRP_TTC3_1_WAV, - PINCTRL_GRP_TTC3_2_WAV, - PINCTRL_GRP_TTC3_3_WAV, - PINCTRL_GRP_TTC3_4_WAV, - PINCTRL_GRP_TTC3_5_WAV, - PINCTRL_GRP_TTC3_6_WAV, - PINCTRL_GRP_TTC3_7_WAV, - PINCTRL_GRP_TTC3_8_WAV, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TTC3_0_WAV, + .group_size = PINCTRL_GRP_TTC3_8_WAV - PINCTRL_GRP_TTC3_0_WAV + 1U, }, [PINCTRL_FUNC_UART0] = { .name = "uart0", .regval = 0xc0, - .groups = &((uint16_t []) { - PINCTRL_GRP_UART0_0, - PINCTRL_GRP_UART0_1, - PINCTRL_GRP_UART0_2, - PINCTRL_GRP_UART0_3, - PINCTRL_GRP_UART0_4, - PINCTRL_GRP_UART0_5, - PINCTRL_GRP_UART0_6, - PINCTRL_GRP_UART0_7, - PINCTRL_GRP_UART0_8, - PINCTRL_GRP_UART0_9, - PINCTRL_GRP_UART0_10, - PINCTRL_GRP_UART0_11, - PINCTRL_GRP_UART0_12, - PINCTRL_GRP_UART0_13, - PINCTRL_GRP_UART0_14, - PINCTRL_GRP_UART0_15, - PINCTRL_GRP_UART0_16, - PINCTRL_GRP_UART0_17, - PINCTRL_GRP_UART0_18, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_UART0_0, + .group_size = PINCTRL_GRP_UART0_18 - PINCTRL_GRP_UART0_0 + 1U, }, [PINCTRL_FUNC_UART1] = { .name = "uart1", .regval = 0xc0, - .groups = &((uint16_t []) { - PINCTRL_GRP_UART1_0, - PINCTRL_GRP_UART1_1, - PINCTRL_GRP_UART1_2, - PINCTRL_GRP_UART1_3, - PINCTRL_GRP_UART1_4, - PINCTRL_GRP_UART1_5, - PINCTRL_GRP_UART1_6, - PINCTRL_GRP_UART1_7, - PINCTRL_GRP_UART1_8, - PINCTRL_GRP_UART1_9, - PINCTRL_GRP_UART1_10, - PINCTRL_GRP_UART1_11, - PINCTRL_GRP_UART1_12, - PINCTRL_GRP_UART1_13, - PINCTRL_GRP_UART1_14, - PINCTRL_GRP_UART1_15, - PINCTRL_GRP_UART1_16, - PINCTRL_GRP_UART1_17, - PINCTRL_GRP_UART1_18, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_UART1_0, + .group_size = PINCTRL_GRP_UART1_18 - PINCTRL_GRP_UART1_0 + 1U, }, [PINCTRL_FUNC_USB0] = { .name = "usb0", .regval = 0x04, - .groups = &((uint16_t []) { - PINCTRL_GRP_USB0_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_USB0_0, + .group_size = PINCTRL_GRP_USB0_0 - PINCTRL_GRP_USB0_0 + 1U, }, [PINCTRL_FUNC_USB1] = { .name = "usb1", .regval = 0x04, - .groups = &((uint16_t []) { - PINCTRL_GRP_USB1_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_USB1_0, + .group_size = PINCTRL_GRP_USB1_0 - PINCTRL_GRP_USB1_0 + 1U, }, [PINCTRL_FUNC_SWDT0_CLK] = { .name = "swdt0_clk", .regval = 0x60, - .groups = &((uint16_t []) { - PINCTRL_GRP_SWDT0_0_CLK, - PINCTRL_GRP_SWDT0_1_CLK, - PINCTRL_GRP_SWDT0_2_CLK, - PINCTRL_GRP_SWDT0_3_CLK, - PINCTRL_GRP_SWDT0_4_CLK, - PINCTRL_GRP_SWDT0_5_CLK, - PINCTRL_GRP_SWDT0_6_CLK, - PINCTRL_GRP_SWDT0_7_CLK, - PINCTRL_GRP_SWDT0_8_CLK, - PINCTRL_GRP_SWDT0_9_CLK, - PINCTRL_GRP_SWDT0_10_CLK, - PINCTRL_GRP_SWDT0_11_CLK, - PINCTRL_GRP_SWDT0_12_CLK, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SWDT0_0_CLK, + .group_size = PINCTRL_GRP_SWDT0_12_CLK - PINCTRL_GRP_SWDT0_0_CLK + 1U, }, [PINCTRL_FUNC_SWDT0_RST] = { .name = "swdt0_rst", .regval = 0x60, - .groups = &((uint16_t []) { - PINCTRL_GRP_SWDT0_0_RST, - PINCTRL_GRP_SWDT0_1_RST, - PINCTRL_GRP_SWDT0_2_RST, - PINCTRL_GRP_SWDT0_3_RST, - PINCTRL_GRP_SWDT0_4_RST, - PINCTRL_GRP_SWDT0_5_RST, - PINCTRL_GRP_SWDT0_6_RST, - PINCTRL_GRP_SWDT0_7_RST, - PINCTRL_GRP_SWDT0_8_RST, - PINCTRL_GRP_SWDT0_9_RST, - PINCTRL_GRP_SWDT0_10_RST, - PINCTRL_GRP_SWDT0_11_RST, - PINCTRL_GRP_SWDT0_12_RST, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SWDT0_0_RST, + .group_size = PINCTRL_GRP_SWDT0_12_RST - PINCTRL_GRP_SWDT0_0_RST + 1U, }, [PINCTRL_FUNC_SWDT1_CLK] = { .name = "swdt1_clk", .regval = 0x60, - .groups = &((uint16_t []) { - PINCTRL_GRP_SWDT1_0_CLK, - PINCTRL_GRP_SWDT1_1_CLK, - PINCTRL_GRP_SWDT1_2_CLK, - PINCTRL_GRP_SWDT1_3_CLK, - PINCTRL_GRP_SWDT1_4_CLK, - PINCTRL_GRP_SWDT1_5_CLK, - PINCTRL_GRP_SWDT1_6_CLK, - PINCTRL_GRP_SWDT1_7_CLK, - PINCTRL_GRP_SWDT1_8_CLK, - PINCTRL_GRP_SWDT1_9_CLK, - PINCTRL_GRP_SWDT1_10_CLK, - PINCTRL_GRP_SWDT1_11_CLK, - PINCTRL_GRP_SWDT1_12_CLK, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SWDT1_0_CLK, + .group_size = PINCTRL_GRP_SWDT1_12_CLK - PINCTRL_GRP_SWDT1_0_CLK + 1U, }, [PINCTRL_FUNC_SWDT1_RST] = { .name = "swdt1_rst", .regval = 0x60, - .groups = &((uint16_t []) { - PINCTRL_GRP_SWDT1_0_RST, - PINCTRL_GRP_SWDT1_1_RST, - PINCTRL_GRP_SWDT1_2_RST, - PINCTRL_GRP_SWDT1_3_RST, - PINCTRL_GRP_SWDT1_4_RST, - PINCTRL_GRP_SWDT1_5_RST, - PINCTRL_GRP_SWDT1_6_RST, - PINCTRL_GRP_SWDT1_7_RST, - PINCTRL_GRP_SWDT1_8_RST, - PINCTRL_GRP_SWDT1_9_RST, - PINCTRL_GRP_SWDT1_10_RST, - PINCTRL_GRP_SWDT1_11_RST, - PINCTRL_GRP_SWDT1_12_RST, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_SWDT1_0_RST, + .group_size = PINCTRL_GRP_SWDT1_12_RST - PINCTRL_GRP_SWDT1_0_RST + 1U, }, [PINCTRL_FUNC_PMU0] = { .name = "pmu0", .regval = 0x08, - .groups = &((uint16_t []) { - PINCTRL_GRP_PMU0_0, - PINCTRL_GRP_PMU0_1, - PINCTRL_GRP_PMU0_2, - PINCTRL_GRP_PMU0_3, - PINCTRL_GRP_PMU0_4, - PINCTRL_GRP_PMU0_5, - PINCTRL_GRP_PMU0_6, - PINCTRL_GRP_PMU0_7, - PINCTRL_GRP_PMU0_8, - PINCTRL_GRP_PMU0_9, - PINCTRL_GRP_PMU0_10, - PINCTRL_GRP_PMU0_11, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_PMU0_0, + .group_size = PINCTRL_GRP_PMU0_11 - PINCTRL_GRP_PMU0_0 + 1U, }, [PINCTRL_FUNC_PCIE0] = { .name = "pcie0", .regval = 0x04, - .groups = &((uint16_t []) { - PINCTRL_GRP_PCIE0_0, - PINCTRL_GRP_PCIE0_1, - PINCTRL_GRP_PCIE0_2, - PINCTRL_GRP_PCIE0_3, - PINCTRL_GRP_PCIE0_4, - PINCTRL_GRP_PCIE0_5, - PINCTRL_GRP_PCIE0_6, - PINCTRL_GRP_PCIE0_7, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_PCIE0_0, + .group_size = PINCTRL_GRP_PCIE0_7 - PINCTRL_GRP_PCIE0_0 + 1U, }, [PINCTRL_FUNC_CSU0] = { .name = "csu0", .regval = 0x18, - .groups = &((uint16_t []) { - PINCTRL_GRP_CSU0_0, - PINCTRL_GRP_CSU0_1, - PINCTRL_GRP_CSU0_2, - PINCTRL_GRP_CSU0_3, - PINCTRL_GRP_CSU0_4, - PINCTRL_GRP_CSU0_5, - PINCTRL_GRP_CSU0_6, - PINCTRL_GRP_CSU0_7, - PINCTRL_GRP_CSU0_8, - PINCTRL_GRP_CSU0_9, - PINCTRL_GRP_CSU0_10, - PINCTRL_GRP_CSU0_11, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_CSU0_0, + .group_size = PINCTRL_GRP_CSU0_11 - PINCTRL_GRP_CSU0_0 + 1U, }, [PINCTRL_FUNC_DPAUX0] = { .name = "dpaux0", .regval = 0x18, - .groups = &((uint16_t []) { - PINCTRL_GRP_DPAUX0_0, - PINCTRL_GRP_DPAUX0_1, - PINCTRL_GRP_DPAUX0_2, - PINCTRL_GRP_DPAUX0_3, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_DPAUX0_0, + .group_size = PINCTRL_GRP_DPAUX0_3 - PINCTRL_GRP_DPAUX0_0 + 1U, }, [PINCTRL_FUNC_PJTAG0] = { .name = "pjtag0", .regval = 0x60, - .groups = &((uint16_t []) { - PINCTRL_GRP_PJTAG0_0, - PINCTRL_GRP_PJTAG0_1, - PINCTRL_GRP_PJTAG0_2, - PINCTRL_GRP_PJTAG0_3, - PINCTRL_GRP_PJTAG0_4, - PINCTRL_GRP_PJTAG0_5, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_PJTAG0_0, + .group_size = PINCTRL_GRP_PJTAG0_5 - PINCTRL_GRP_PJTAG0_0 + 1U, }, [PINCTRL_FUNC_TRACE0] = { .name = "trace0", .regval = 0xe0, - .groups = &((uint16_t []) { - PINCTRL_GRP_TRACE0_0, - PINCTRL_GRP_TRACE0_1, - PINCTRL_GRP_TRACE0_2, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TRACE0_0, + .group_size = PINCTRL_GRP_TRACE0_2 - PINCTRL_GRP_TRACE0_0 + 1U, }, [PINCTRL_FUNC_TRACE0_CLK] = { .name = "trace0_clk", .regval = 0xe0, - .groups = &((uint16_t []) { - PINCTRL_GRP_TRACE0_0_CLK, - PINCTRL_GRP_TRACE0_1_CLK, - PINCTRL_GRP_TRACE0_2_CLK, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TRACE0_0_CLK, + .group_size = PINCTRL_GRP_TRACE0_2_CLK - PINCTRL_GRP_TRACE0_0_CLK + 1U, }, [PINCTRL_FUNC_TESTSCAN0] = { .name = "testscan0", .regval = 0x10, - .groups = &((uint16_t []) { - PINCTRL_GRP_TESTSCAN0_0, - END_OF_GROUPS, - }), + .group_base = PINCTRL_GRP_TESTSCAN0_0, + .group_size = PINCTRL_GRP_TESTSCAN0_0 - PINCTRL_GRP_TESTSCAN0_0 + 1U, }, }; @@ -2511,7 +1952,7 @@ static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = { * * @return Returns success. */ -enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins) +enum pm_ret_status pm_api_pinctrl_get_num_pins(uint32_t *npins) { *npins = MAX_PIN; @@ -2526,7 +1967,7 @@ enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins) * * @return Returns success. */ -enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs) +enum pm_ret_status pm_api_pinctrl_get_num_functions(uint32_t *nfuncs) { *nfuncs = MAX_FUNCTION; @@ -2543,26 +1984,14 @@ enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs) * * @return Returns success. */ -enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid, - unsigned int *ngroups) +enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid, + uint32_t *ngroups) { - int i = 0; - uint16_t *grps; - if (fid >= MAX_FUNCTION) { return PM_RET_ERROR_ARGS; } - *ngroups = 0; - - grps = *pinctrl_functions[fid].groups; - if (grps == NULL) { - return PM_RET_SUCCESS; - } - - while (grps[i++] != (uint16_t)END_OF_GROUPS) { - (*ngroups)++; - } + *ngroups = pinctrl_functions[fid].group_size; return PM_RET_SUCCESS; } @@ -2575,7 +2004,7 @@ enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid, * This function is used by master to get name of function specified * by given function ID. */ -void pm_api_pinctrl_get_function_name(unsigned int fid, char *name) +void pm_api_pinctrl_get_function_name(uint32_t fid, char *name) { if (fid >= MAX_FUNCTION) { memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN); @@ -2602,12 +2031,13 @@ void pm_api_pinctrl_get_function_name(unsigned int fid, char *name) * * Return: Returns status, either success or error+reason. */ -enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid, - unsigned int index, +enum pm_ret_status pm_api_pinctrl_get_function_groups(uint32_t fid, + uint32_t index, uint16_t *groups) { - unsigned int i; - uint16_t *grps; + uint16_t grps; + uint16_t end_of_grp_offset; + uint16_t i; if (fid >= MAX_FUNCTION) { return PM_RET_ERROR_ARGS; @@ -2615,23 +2045,14 @@ enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid, memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); - grps = *pinctrl_functions[fid].groups; - if (grps == NULL) { - return PM_RET_SUCCESS; - } + grps = pinctrl_functions[fid].group_base; + end_of_grp_offset = grps + pinctrl_functions[fid].group_size; - /* Skip groups till index */ - for (i = 0; i < index; i++) { - if (grps[i] == (uint16_t)END_OF_GROUPS) { - return PM_RET_SUCCESS; - } - } - - for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { - groups[i] = grps[index + i]; - if (groups[i] == (uint16_t)END_OF_GROUPS) { + for (i = 0U; i < NUM_GROUPS_PER_RESP; i++) { + if ((grps + index + i) >= end_of_grp_offset) { break; } + groups[i] = (grps + index + i); } return PM_RET_SUCCESS; @@ -2655,11 +2076,11 @@ enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid, * * Return: Returns status, either success or error+reason. */ -enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin, - unsigned int index, +enum pm_ret_status pm_api_pinctrl_get_pin_groups(uint32_t pin, + uint32_t index, uint16_t *groups) { - unsigned int i; + uint32_t i; uint16_t *grps; if (pin >= MAX_PIN) { diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h index 2b8fca3cd..5c4cb4504 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h @@ -13,76 +13,76 @@ #include "pm_common.h" -#define FUNCTION_NAME_LEN U(16) -#define GROUPS_PAYLOAD_LEN U(12) -#define NUM_GROUPS_PER_RESP U(6) +#define FUNCTION_NAME_LEN (16U) +#define GROUPS_PAYLOAD_LEN (12U) +#define NUM_GROUPS_PER_RESP (6U) #define END_OF_FUNCTION "END_OF_FUNCTION" #define END_OF_GROUPS -1 #define PINCTRL_GRP_RESERVED -2 //pinctrl function ids enum { - PINCTRL_FUNC_CAN0, - PINCTRL_FUNC_CAN1, - PINCTRL_FUNC_ETHERNET0, - PINCTRL_FUNC_ETHERNET1, - PINCTRL_FUNC_ETHERNET2, - PINCTRL_FUNC_ETHERNET3, - PINCTRL_FUNC_GEMTSU0, - PINCTRL_FUNC_GPIO0, - PINCTRL_FUNC_I2C0, - PINCTRL_FUNC_I2C1, - PINCTRL_FUNC_MDIO0, - PINCTRL_FUNC_MDIO1, - PINCTRL_FUNC_MDIO2, - PINCTRL_FUNC_MDIO3, - PINCTRL_FUNC_QSPI0, - PINCTRL_FUNC_QSPI_FBCLK, - PINCTRL_FUNC_QSPI_SS, - PINCTRL_FUNC_SPI0, - PINCTRL_FUNC_SPI1, - PINCTRL_FUNC_SPI0_SS, - PINCTRL_FUNC_SPI1_SS, - PINCTRL_FUNC_SDIO0, - PINCTRL_FUNC_SDIO0_PC, - PINCTRL_FUNC_SDIO0_CD, - PINCTRL_FUNC_SDIO0_WP, - PINCTRL_FUNC_SDIO1, - PINCTRL_FUNC_SDIO1_PC, - PINCTRL_FUNC_SDIO1_CD, - PINCTRL_FUNC_SDIO1_WP, - PINCTRL_FUNC_NAND0, - PINCTRL_FUNC_NAND0_CE, - PINCTRL_FUNC_NAND0_RB, - PINCTRL_FUNC_NAND0_DQS, - PINCTRL_FUNC_TTC0_CLK, - PINCTRL_FUNC_TTC0_WAV, - PINCTRL_FUNC_TTC1_CLK, - PINCTRL_FUNC_TTC1_WAV, - PINCTRL_FUNC_TTC2_CLK, - PINCTRL_FUNC_TTC2_WAV, - PINCTRL_FUNC_TTC3_CLK, - PINCTRL_FUNC_TTC3_WAV, - PINCTRL_FUNC_UART0, - PINCTRL_FUNC_UART1, - PINCTRL_FUNC_USB0, - PINCTRL_FUNC_USB1, - PINCTRL_FUNC_SWDT0_CLK, - PINCTRL_FUNC_SWDT0_RST, - PINCTRL_FUNC_SWDT1_CLK, - PINCTRL_FUNC_SWDT1_RST, - PINCTRL_FUNC_PMU0, - PINCTRL_FUNC_PCIE0, - PINCTRL_FUNC_CSU0, - PINCTRL_FUNC_DPAUX0, - PINCTRL_FUNC_PJTAG0, - PINCTRL_FUNC_TRACE0, - PINCTRL_FUNC_TRACE0_CLK, - PINCTRL_FUNC_TESTSCAN0, - END_FUNCTION, + PINCTRL_FUNC_CAN0 = (0U), + PINCTRL_FUNC_CAN1 = (1U), + PINCTRL_FUNC_ETHERNET0 = (2U), + PINCTRL_FUNC_ETHERNET1 = (3U), + PINCTRL_FUNC_ETHERNET2 = (4U), + PINCTRL_FUNC_ETHERNET3 = (5U), + PINCTRL_FUNC_GEMTSU0 = (6U), + PINCTRL_FUNC_GPIO0 = (7U), + PINCTRL_FUNC_I2C0 = (8U), + PINCTRL_FUNC_I2C1 = (9U), + PINCTRL_FUNC_MDIO0 = (10U), + PINCTRL_FUNC_MDIO1 = (11U), + PINCTRL_FUNC_MDIO2 = (12U), + PINCTRL_FUNC_MDIO3 = (13U), + PINCTRL_FUNC_QSPI0 = (14U), + PINCTRL_FUNC_QSPI_FBCLK = (15U), + PINCTRL_FUNC_QSPI_SS = (16U), + PINCTRL_FUNC_SPI0 = (17U), + PINCTRL_FUNC_SPI1 = (18U), + PINCTRL_FUNC_SPI0_SS = (19U), + PINCTRL_FUNC_SPI1_SS = (20U), + PINCTRL_FUNC_SDIO0 = (21U), + PINCTRL_FUNC_SDIO0_PC = (22U), + PINCTRL_FUNC_SDIO0_CD = (23U), + PINCTRL_FUNC_SDIO0_WP = (24U), + PINCTRL_FUNC_SDIO1 = (25U), + PINCTRL_FUNC_SDIO1_PC = (26U), + PINCTRL_FUNC_SDIO1_CD = (27U), + PINCTRL_FUNC_SDIO1_WP = (28U), + PINCTRL_FUNC_NAND0 = (29U), + PINCTRL_FUNC_NAND0_CE = (30U), + PINCTRL_FUNC_NAND0_RB = (31U), + PINCTRL_FUNC_NAND0_DQS = (32U), + PINCTRL_FUNC_TTC0_CLK = (33U), + PINCTRL_FUNC_TTC0_WAV = (34U), + PINCTRL_FUNC_TTC1_CLK = (35U), + PINCTRL_FUNC_TTC1_WAV = (36U), + PINCTRL_FUNC_TTC2_CLK = (37U), + PINCTRL_FUNC_TTC2_WAV = (38U), + PINCTRL_FUNC_TTC3_CLK = (39U), + PINCTRL_FUNC_TTC3_WAV = (40U), + PINCTRL_FUNC_UART0 = (41U), + PINCTRL_FUNC_UART1 = (42U), + PINCTRL_FUNC_USB0 = (43U), + PINCTRL_FUNC_USB1 = (44U), + PINCTRL_FUNC_SWDT0_CLK = (45U), + PINCTRL_FUNC_SWDT0_RST = (46U), + PINCTRL_FUNC_SWDT1_CLK = (47U), + PINCTRL_FUNC_SWDT1_RST = (48U), + PINCTRL_FUNC_PMU0 = (49U), + PINCTRL_FUNC_PCIE0 = (50U), + PINCTRL_FUNC_CSU0 = (51U), + PINCTRL_FUNC_DPAUX0 = (52U), + PINCTRL_FUNC_PJTAG0 = (53U), + PINCTRL_FUNC_TRACE0 = (54U), + PINCTRL_FUNC_TRACE0_CLK = (55U), + PINCTRL_FUNC_TESTSCAN0 = (56U), + END_FUNCTION = (57U), }; -#define MAX_FUNCTION (unsigned int)(END_FUNCTION) +#define MAX_FUNCTION END_FUNCTION // pinctrl pin numbers enum { @@ -164,10 +164,10 @@ enum { PINCTRL_PIN_75, PINCTRL_PIN_76, PINCTRL_PIN_77, - END_PINS, + END_PINS = (78U), }; -#define MAX_PIN (unsigned int)(END_PINS) +#define MAX_PIN END_PINS // pinctrl group ids enum { @@ -187,50 +187,50 @@ enum { PINCTRL_GRP_QSPI_SS, PINCTRL_GRP_QSPI_FBCLK, PINCTRL_GRP_SPI0_0, + PINCTRL_GRP_SPI0_1, + PINCTRL_GRP_SPI0_2, + PINCTRL_GRP_SPI0_3, + PINCTRL_GRP_SPI0_4, + PINCTRL_GRP_SPI0_5, PINCTRL_GRP_SPI0_0_SS0, PINCTRL_GRP_SPI0_0_SS1, PINCTRL_GRP_SPI0_0_SS2, - PINCTRL_GRP_SPI0_1, PINCTRL_GRP_SPI0_1_SS0, PINCTRL_GRP_SPI0_1_SS1, PINCTRL_GRP_SPI0_1_SS2, - PINCTRL_GRP_SPI0_2, PINCTRL_GRP_SPI0_2_SS0, PINCTRL_GRP_SPI0_2_SS1, PINCTRL_GRP_SPI0_2_SS2, - PINCTRL_GRP_SPI0_3, PINCTRL_GRP_SPI0_3_SS0, PINCTRL_GRP_SPI0_3_SS1, PINCTRL_GRP_SPI0_3_SS2, - PINCTRL_GRP_SPI0_4, PINCTRL_GRP_SPI0_4_SS0, PINCTRL_GRP_SPI0_4_SS1, PINCTRL_GRP_SPI0_4_SS2, - PINCTRL_GRP_SPI0_5, PINCTRL_GRP_SPI0_5_SS0, PINCTRL_GRP_SPI0_5_SS1, PINCTRL_GRP_SPI0_5_SS2, PINCTRL_GRP_SPI1_0, + PINCTRL_GRP_SPI1_1, + PINCTRL_GRP_SPI1_2, + PINCTRL_GRP_SPI1_3, + PINCTRL_GRP_SPI1_4, + PINCTRL_GRP_SPI1_5, PINCTRL_GRP_SPI1_0_SS0, PINCTRL_GRP_SPI1_0_SS1, PINCTRL_GRP_SPI1_0_SS2, - PINCTRL_GRP_SPI1_1, PINCTRL_GRP_SPI1_1_SS0, PINCTRL_GRP_SPI1_1_SS1, PINCTRL_GRP_SPI1_1_SS2, - PINCTRL_GRP_SPI1_2, PINCTRL_GRP_SPI1_2_SS0, PINCTRL_GRP_SPI1_2_SS1, PINCTRL_GRP_SPI1_2_SS2, - PINCTRL_GRP_SPI1_3, PINCTRL_GRP_SPI1_3_SS0, PINCTRL_GRP_SPI1_3_SS1, PINCTRL_GRP_SPI1_3_SS2, - PINCTRL_GRP_SPI1_4, PINCTRL_GRP_SPI1_4_SS0, PINCTRL_GRP_SPI1_4_SS1, PINCTRL_GRP_SPI1_4_SS2, - PINCTRL_GRP_SPI1_5, PINCTRL_GRP_SPI1_5_SS0, PINCTRL_GRP_SPI1_5_SS1, PINCTRL_GRP_SPI1_5_SS2, @@ -268,13 +268,13 @@ enum { PINCTRL_GRP_SDIO0_1BIT_2_6, PINCTRL_GRP_SDIO0_1BIT_2_7, PINCTRL_GRP_SDIO0_0_PC, - PINCTRL_GRP_SDIO0_0_CD, - PINCTRL_GRP_SDIO0_0_WP, PINCTRL_GRP_SDIO0_1_PC, - PINCTRL_GRP_SDIO0_1_CD, - PINCTRL_GRP_SDIO0_1_WP, PINCTRL_GRP_SDIO0_2_PC, + PINCTRL_GRP_SDIO0_0_CD, + PINCTRL_GRP_SDIO0_1_CD, PINCTRL_GRP_SDIO0_2_CD, + PINCTRL_GRP_SDIO0_0_WP, + PINCTRL_GRP_SDIO0_1_WP, PINCTRL_GRP_SDIO0_2_WP, PINCTRL_GRP_SDIO1_0, PINCTRL_GRP_SDIO1_4BIT_0_0, @@ -293,17 +293,17 @@ enum { PINCTRL_GRP_SDIO1_1BIT_1_2, PINCTRL_GRP_SDIO1_1BIT_1_3, PINCTRL_GRP_SDIO1_0_PC, - PINCTRL_GRP_SDIO1_0_CD, - PINCTRL_GRP_SDIO1_0_WP, PINCTRL_GRP_SDIO1_1_PC, + PINCTRL_GRP_SDIO1_0_CD, PINCTRL_GRP_SDIO1_1_CD, + PINCTRL_GRP_SDIO1_0_WP, PINCTRL_GRP_SDIO1_1_WP, PINCTRL_GRP_NAND0_0, PINCTRL_GRP_NAND0_0_CE, - PINCTRL_GRP_NAND0_0_RB, - PINCTRL_GRP_NAND0_0_DQS, PINCTRL_GRP_NAND0_1_CE, + PINCTRL_GRP_NAND0_0_RB, PINCTRL_GRP_NAND0_1_RB, + PINCTRL_GRP_NAND0_0_DQS, PINCTRL_GRP_NAND0_1_DQS, PINCTRL_GRP_CAN0_0, PINCTRL_GRP_CAN0_1, @@ -422,128 +422,128 @@ enum { PINCTRL_GRP_I2C1_18, PINCTRL_GRP_I2C1_19, PINCTRL_GRP_TTC0_0_CLK, - PINCTRL_GRP_TTC0_0_WAV, PINCTRL_GRP_TTC0_1_CLK, - PINCTRL_GRP_TTC0_1_WAV, PINCTRL_GRP_TTC0_2_CLK, - PINCTRL_GRP_TTC0_2_WAV, PINCTRL_GRP_TTC0_3_CLK, - PINCTRL_GRP_TTC0_3_WAV, PINCTRL_GRP_TTC0_4_CLK, - PINCTRL_GRP_TTC0_4_WAV, PINCTRL_GRP_TTC0_5_CLK, - PINCTRL_GRP_TTC0_5_WAV, PINCTRL_GRP_TTC0_6_CLK, - PINCTRL_GRP_TTC0_6_WAV, PINCTRL_GRP_TTC0_7_CLK, - PINCTRL_GRP_TTC0_7_WAV, PINCTRL_GRP_TTC0_8_CLK, + PINCTRL_GRP_TTC0_0_WAV, + PINCTRL_GRP_TTC0_1_WAV, + PINCTRL_GRP_TTC0_2_WAV, + PINCTRL_GRP_TTC0_3_WAV, + PINCTRL_GRP_TTC0_4_WAV, + PINCTRL_GRP_TTC0_5_WAV, + PINCTRL_GRP_TTC0_6_WAV, + PINCTRL_GRP_TTC0_7_WAV, PINCTRL_GRP_TTC0_8_WAV, PINCTRL_GRP_TTC1_0_CLK, - PINCTRL_GRP_TTC1_0_WAV, PINCTRL_GRP_TTC1_1_CLK, - PINCTRL_GRP_TTC1_1_WAV, PINCTRL_GRP_TTC1_2_CLK, - PINCTRL_GRP_TTC1_2_WAV, PINCTRL_GRP_TTC1_3_CLK, - PINCTRL_GRP_TTC1_3_WAV, PINCTRL_GRP_TTC1_4_CLK, - PINCTRL_GRP_TTC1_4_WAV, PINCTRL_GRP_TTC1_5_CLK, - PINCTRL_GRP_TTC1_5_WAV, PINCTRL_GRP_TTC1_6_CLK, - PINCTRL_GRP_TTC1_6_WAV, PINCTRL_GRP_TTC1_7_CLK, - PINCTRL_GRP_TTC1_7_WAV, PINCTRL_GRP_TTC1_8_CLK, + PINCTRL_GRP_TTC1_0_WAV, + PINCTRL_GRP_TTC1_1_WAV, + PINCTRL_GRP_TTC1_2_WAV, + PINCTRL_GRP_TTC1_3_WAV, + PINCTRL_GRP_TTC1_4_WAV, + PINCTRL_GRP_TTC1_5_WAV, + PINCTRL_GRP_TTC1_6_WAV, + PINCTRL_GRP_TTC1_7_WAV, PINCTRL_GRP_TTC1_8_WAV, PINCTRL_GRP_TTC2_0_CLK, - PINCTRL_GRP_TTC2_0_WAV, PINCTRL_GRP_TTC2_1_CLK, - PINCTRL_GRP_TTC2_1_WAV, PINCTRL_GRP_TTC2_2_CLK, - PINCTRL_GRP_TTC2_2_WAV, PINCTRL_GRP_TTC2_3_CLK, - PINCTRL_GRP_TTC2_3_WAV, PINCTRL_GRP_TTC2_4_CLK, - PINCTRL_GRP_TTC2_4_WAV, PINCTRL_GRP_TTC2_5_CLK, - PINCTRL_GRP_TTC2_5_WAV, PINCTRL_GRP_TTC2_6_CLK, - PINCTRL_GRP_TTC2_6_WAV, PINCTRL_GRP_TTC2_7_CLK, - PINCTRL_GRP_TTC2_7_WAV, PINCTRL_GRP_TTC2_8_CLK, + PINCTRL_GRP_TTC2_0_WAV, + PINCTRL_GRP_TTC2_1_WAV, + PINCTRL_GRP_TTC2_2_WAV, + PINCTRL_GRP_TTC2_3_WAV, + PINCTRL_GRP_TTC2_4_WAV, + PINCTRL_GRP_TTC2_5_WAV, + PINCTRL_GRP_TTC2_6_WAV, + PINCTRL_GRP_TTC2_7_WAV, PINCTRL_GRP_TTC2_8_WAV, PINCTRL_GRP_TTC3_0_CLK, - PINCTRL_GRP_TTC3_0_WAV, PINCTRL_GRP_TTC3_1_CLK, - PINCTRL_GRP_TTC3_1_WAV, PINCTRL_GRP_TTC3_2_CLK, - PINCTRL_GRP_TTC3_2_WAV, PINCTRL_GRP_TTC3_3_CLK, - PINCTRL_GRP_TTC3_3_WAV, PINCTRL_GRP_TTC3_4_CLK, - PINCTRL_GRP_TTC3_4_WAV, PINCTRL_GRP_TTC3_5_CLK, - PINCTRL_GRP_TTC3_5_WAV, PINCTRL_GRP_TTC3_6_CLK, - PINCTRL_GRP_TTC3_6_WAV, PINCTRL_GRP_TTC3_7_CLK, - PINCTRL_GRP_TTC3_7_WAV, PINCTRL_GRP_TTC3_8_CLK, + PINCTRL_GRP_TTC3_0_WAV, + PINCTRL_GRP_TTC3_1_WAV, + PINCTRL_GRP_TTC3_2_WAV, + PINCTRL_GRP_TTC3_3_WAV, + PINCTRL_GRP_TTC3_4_WAV, + PINCTRL_GRP_TTC3_5_WAV, + PINCTRL_GRP_TTC3_6_WAV, + PINCTRL_GRP_TTC3_7_WAV, PINCTRL_GRP_TTC3_8_WAV, PINCTRL_GRP_SWDT0_0_CLK, - PINCTRL_GRP_SWDT0_0_RST, PINCTRL_GRP_SWDT0_1_CLK, - PINCTRL_GRP_SWDT0_1_RST, PINCTRL_GRP_SWDT0_2_CLK, - PINCTRL_GRP_SWDT0_2_RST, PINCTRL_GRP_SWDT0_3_CLK, - PINCTRL_GRP_SWDT0_3_RST, PINCTRL_GRP_SWDT0_4_CLK, - PINCTRL_GRP_SWDT0_4_RST, PINCTRL_GRP_SWDT0_5_CLK, - PINCTRL_GRP_SWDT0_5_RST, PINCTRL_GRP_SWDT0_6_CLK, - PINCTRL_GRP_SWDT0_6_RST, PINCTRL_GRP_SWDT0_7_CLK, - PINCTRL_GRP_SWDT0_7_RST, PINCTRL_GRP_SWDT0_8_CLK, - PINCTRL_GRP_SWDT0_8_RST, PINCTRL_GRP_SWDT0_9_CLK, - PINCTRL_GRP_SWDT0_9_RST, PINCTRL_GRP_SWDT0_10_CLK, - PINCTRL_GRP_SWDT0_10_RST, PINCTRL_GRP_SWDT0_11_CLK, - PINCTRL_GRP_SWDT0_11_RST, PINCTRL_GRP_SWDT0_12_CLK, + PINCTRL_GRP_SWDT0_0_RST, + PINCTRL_GRP_SWDT0_1_RST, + PINCTRL_GRP_SWDT0_2_RST, + PINCTRL_GRP_SWDT0_3_RST, + PINCTRL_GRP_SWDT0_4_RST, + PINCTRL_GRP_SWDT0_5_RST, + PINCTRL_GRP_SWDT0_6_RST, + PINCTRL_GRP_SWDT0_7_RST, + PINCTRL_GRP_SWDT0_8_RST, + PINCTRL_GRP_SWDT0_9_RST, + PINCTRL_GRP_SWDT0_10_RST, + PINCTRL_GRP_SWDT0_11_RST, PINCTRL_GRP_SWDT0_12_RST, PINCTRL_GRP_SWDT1_0_CLK, - PINCTRL_GRP_SWDT1_0_RST, PINCTRL_GRP_SWDT1_1_CLK, - PINCTRL_GRP_SWDT1_1_RST, PINCTRL_GRP_SWDT1_2_CLK, - PINCTRL_GRP_SWDT1_2_RST, PINCTRL_GRP_SWDT1_3_CLK, - PINCTRL_GRP_SWDT1_3_RST, PINCTRL_GRP_SWDT1_4_CLK, - PINCTRL_GRP_SWDT1_4_RST, PINCTRL_GRP_SWDT1_5_CLK, - PINCTRL_GRP_SWDT1_5_RST, PINCTRL_GRP_SWDT1_6_CLK, - PINCTRL_GRP_SWDT1_6_RST, PINCTRL_GRP_SWDT1_7_CLK, - PINCTRL_GRP_SWDT1_7_RST, PINCTRL_GRP_SWDT1_8_CLK, - PINCTRL_GRP_SWDT1_8_RST, PINCTRL_GRP_SWDT1_9_CLK, - PINCTRL_GRP_SWDT1_9_RST, PINCTRL_GRP_SWDT1_10_CLK, - PINCTRL_GRP_SWDT1_10_RST, PINCTRL_GRP_SWDT1_11_CLK, - PINCTRL_GRP_SWDT1_11_RST, PINCTRL_GRP_SWDT1_12_CLK, + PINCTRL_GRP_SWDT1_0_RST, + PINCTRL_GRP_SWDT1_1_RST, + PINCTRL_GRP_SWDT1_2_RST, + PINCTRL_GRP_SWDT1_3_RST, + PINCTRL_GRP_SWDT1_4_RST, + PINCTRL_GRP_SWDT1_5_RST, + PINCTRL_GRP_SWDT1_6_RST, + PINCTRL_GRP_SWDT1_7_RST, + PINCTRL_GRP_SWDT1_8_RST, + PINCTRL_GRP_SWDT1_9_RST, + PINCTRL_GRP_SWDT1_10_RST, + PINCTRL_GRP_SWDT1_11_RST, PINCTRL_GRP_SWDT1_12_RST, PINCTRL_GRP_GPIO0_0, PINCTRL_GRP_GPIO0_1, @@ -668,10 +668,10 @@ enum { PINCTRL_GRP_PJTAG0_4, PINCTRL_GRP_PJTAG0_5, PINCTRL_GRP_TRACE0_0, - PINCTRL_GRP_TRACE0_0_CLK, PINCTRL_GRP_TRACE0_1, - PINCTRL_GRP_TRACE0_1_CLK, PINCTRL_GRP_TRACE0_2, + PINCTRL_GRP_TRACE0_0_CLK, + PINCTRL_GRP_TRACE0_1_CLK, PINCTRL_GRP_TRACE0_2_CLK, PINCTRL_GRP_TESTSCAN0_0, }; @@ -709,15 +709,15 @@ enum { #define PINCTRL_DRIVE_STRENGTH_8MA 2U #define PINCTRL_DRIVE_STRENGTH_12MA 3U -void pm_api_pinctrl_get_function_name(unsigned int fid, char *name); -enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid, - unsigned int index, +void pm_api_pinctrl_get_function_name(uint32_t fid, char *name); +enum pm_ret_status pm_api_pinctrl_get_function_groups(uint32_t fid, + uint32_t index, uint16_t *groups); -enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin, - unsigned int index, +enum pm_ret_status pm_api_pinctrl_get_pin_groups(uint32_t pin, + uint32_t index, uint16_t *groups); -enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins); -enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs); -enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid, - unsigned int *ngroups); +enum pm_ret_status pm_api_pinctrl_get_num_pins(uint32_t *npins); +enum pm_ret_status pm_api_pinctrl_get_num_functions(uint32_t *nfuncs); +enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid, + uint32_t *ngroups); #endif /* PM_API_PINCTRL_H */ diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c index e524ba5d3..a17b6c550 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c @@ -240,14 +240,14 @@ static const uint8_t atf_expected_ver_id[] = { }; /* default shutdown/reboot scope is system(2) */ -static unsigned int pm_shutdown_scope = PMF_SHUTDOWN_SUBTYPE_SYSTEM; +static uint32_t pm_shutdown_scope = PMF_SHUTDOWN_SUBTYPE_SYSTEM; /** * pm_get_shutdown_scope() - Get the currently set shutdown scope * * @return Shutdown scope value */ -unsigned int pm_get_shutdown_scope(void) +uint32_t pm_get_shutdown_scope(void) { return pm_shutdown_scope; } @@ -269,12 +269,12 @@ unsigned int pm_get_shutdown_scope(void) * @return Returns status, either success or error+reason */ enum pm_ret_status pm_self_suspend(enum pm_node_id nid, - unsigned int latency, - unsigned int state, + uint32_t latency, + uint32_t state, uintptr_t address) { uint32_t payload[PAYLOAD_ARG_CNT]; - unsigned int cpuid = plat_my_core_pos(); + uint32_t cpuid = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpuid); /* @@ -300,7 +300,7 @@ enum pm_ret_status pm_self_suspend(enum pm_node_id nid, */ enum pm_ret_status pm_req_suspend(enum pm_node_id target, enum pm_request_ack ack, - unsigned int latency, unsigned int state) + uint32_t latency, uint32_t state) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -330,7 +330,7 @@ enum pm_ret_status pm_req_suspend(enum pm_node_id target, * @return Returns status, either success or error+reason */ enum pm_ret_status pm_req_wakeup(enum pm_node_id target, - unsigned int set_address, + uint32_t set_address, uintptr_t address, enum pm_request_ack ack) { @@ -412,7 +412,7 @@ enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason) */ enum pm_ret_status pm_set_wakeup_source(enum pm_node_id target, enum pm_node_id wkup_node, - unsigned int enable) + uint32_t enable) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -428,7 +428,7 @@ enum pm_ret_status pm_set_wakeup_source(enum pm_node_id target, * * @return Returns status, either success or error+reason */ -enum pm_ret_status pm_system_shutdown(unsigned int type, unsigned int subtype) +enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -454,8 +454,8 @@ enum pm_ret_status pm_system_shutdown(unsigned int type, unsigned int subtype) * @return Returns status, either success or error+reason */ enum pm_ret_status pm_req_node(enum pm_node_id nid, - unsigned int capabilities, - unsigned int qos, + uint32_t capabilities, + uint32_t qos, enum pm_request_ack ack) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -481,8 +481,8 @@ enum pm_ret_status pm_req_node(enum pm_node_id nid, * @return Returns status, either success or error+reason */ enum pm_ret_status pm_set_requirement(enum pm_node_id nid, - unsigned int capabilities, - unsigned int qos, + uint32_t capabilities, + uint32_t qos, enum pm_request_ack ack) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -505,7 +505,7 @@ enum pm_ret_status pm_set_requirement(enum pm_node_id nid, * * @return Returns status, either success or error+reason */ -enum pm_ret_status pm_get_api_version(unsigned int *version) +enum pm_ret_status pm_get_api_version(uint32_t *version) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -545,8 +545,8 @@ enum pm_ret_status pm_get_node_status(enum pm_node_id nid, * @return Returns status, either success or error+reason */ enum pm_ret_status pm_mmio_write(uintptr_t address, - unsigned int mask, - unsigned int value) + uint32_t mask, + uint32_t value) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -565,7 +565,7 @@ enum pm_ret_status pm_mmio_write(uintptr_t address, * * @return Returns status, either success or error+reason */ -enum pm_ret_status pm_mmio_read(uintptr_t address, unsigned int *value) +enum pm_ret_status pm_mmio_read(uintptr_t address, uint32_t *value) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -609,7 +609,7 @@ enum pm_ret_status pm_fpga_load(uint32_t address_low, * the fpga status * @return Returns status, either success or error+reason */ -enum pm_ret_status pm_fpga_get_status(unsigned int *value) +enum pm_ret_status pm_fpga_get_status(uint32_t *value) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -715,10 +715,10 @@ void pm_get_callbackdata(uint32_t *data, size_t count) * @return Returns status, either success or error+reason */ enum pm_ret_status pm_ioctl(enum pm_node_id nid, - unsigned int ioctl_id, - unsigned int arg1, - unsigned int arg2, - unsigned int *value) + uint32_t ioctl_id, + uint32_t arg1, + uint32_t arg2, + uint32_t *value) { return pm_api_ioctl(nid, ioctl_id, arg1, arg2, value); } @@ -947,7 +947,7 @@ enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *version, * * Return: Returns status, either success or error+reason. */ -static enum pm_ret_status pm_clock_get_max_divisor(unsigned int clock_id, +static enum pm_ret_status pm_clock_get_max_divisor(uint32_t clock_id, uint8_t div_type, uint32_t *max_div) { @@ -975,7 +975,7 @@ static enum pm_ret_status pm_clock_get_num_clocks(uint32_t *nclocks) * This function is used by master to get nmae of clock specified * by given clock ID. */ -static void pm_clock_get_name(unsigned int clock_id, char *name) +static void pm_clock_get_name(uint32_t clock_id, char *name) { pm_api_clock_get_name(clock_id, name); } @@ -993,8 +993,8 @@ static void pm_clock_get_name(unsigned int clock_id, char *name) * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_clock_get_topology(unsigned int clock_id, - unsigned int index, +static enum pm_ret_status pm_clock_get_topology(uint32_t clock_id, + uint32_t index, uint32_t *topology) { return pm_api_clock_get_topology(clock_id, index, topology); @@ -1012,7 +1012,7 @@ static enum pm_ret_status pm_clock_get_topology(unsigned int clock_id, * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_clock_get_fixedfactor_params(unsigned int clock_id, +static enum pm_ret_status pm_clock_get_fixedfactor_params(uint32_t clock_id, uint32_t *mul, uint32_t *div) { @@ -1036,8 +1036,8 @@ static enum pm_ret_status pm_clock_get_fixedfactor_params(unsigned int clock_id, * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_clock_get_parents(unsigned int clock_id, - unsigned int index, +static enum pm_ret_status pm_clock_get_parents(uint32_t clock_id, + uint32_t index, uint32_t *parents) { return pm_api_clock_get_parents(clock_id, index, parents); @@ -1053,7 +1053,7 @@ static enum pm_ret_status pm_clock_get_parents(unsigned int clock_id, * * @return Returns status, either success or error+reason */ -static enum pm_ret_status pm_clock_get_attributes(unsigned int clock_id, +static enum pm_ret_status pm_clock_get_attributes(uint32_t clock_id, uint32_t *attr) { return pm_api_clock_get_attributes(clock_id, attr); @@ -1067,8 +1067,8 @@ static enum pm_ret_status pm_clock_get_attributes(unsigned int clock_id, * @return Error if an argument is not valid or status as returned by the * PM controller (PMU) */ -static enum pm_ret_status pm_clock_gate(unsigned int clock_id, - unsigned char enable) +static enum pm_ret_status pm_clock_gate(uint32_t clock_id, + uint8_t enable) { uint32_t payload[PAYLOAD_ARG_CNT]; enum pm_ret_status status; @@ -1108,7 +1108,7 @@ static enum pm_ret_status pm_clock_gate(unsigned int clock_id, * @return: Error if an argument is not valid or status as returned by the * pm_clock_gate */ -enum pm_ret_status pm_clock_enable(unsigned int clock_id) +enum pm_ret_status pm_clock_enable(uint32_t clock_id) { struct pm_pll *pll; @@ -1132,7 +1132,7 @@ enum pm_ret_status pm_clock_enable(unsigned int clock_id) * @return: Error if an argument is not valid or status as returned by the * pm_clock_gate */ -enum pm_ret_status pm_clock_disable(unsigned int clock_id) +enum pm_ret_status pm_clock_disable(uint32_t clock_id) { struct pm_pll *pll; @@ -1156,8 +1156,8 @@ enum pm_ret_status pm_clock_disable(unsigned int clock_id) * * Return: Returns status, either success or error+reason. */ -enum pm_ret_status pm_clock_getstate(unsigned int clock_id, - unsigned int *state) +enum pm_ret_status pm_clock_getstate(uint32_t clock_id, + uint32_t *state) { struct pm_pll *pll; uint32_t payload[PAYLOAD_ARG_CNT]; @@ -1189,8 +1189,8 @@ enum pm_ret_status pm_clock_getstate(unsigned int clock_id, * * Return: Returns status, either success or error+reason. */ -enum pm_ret_status pm_clock_setdivider(unsigned int clock_id, - unsigned int divider) +enum pm_ret_status pm_clock_setdivider(uint32_t clock_id, + uint32_t divider) { enum pm_ret_status status; enum pm_node_id nid; @@ -1237,8 +1237,8 @@ enum pm_ret_status pm_clock_setdivider(unsigned int clock_id, * * Return: Returns status, either success or error+reason. */ -enum pm_ret_status pm_clock_getdivider(unsigned int clock_id, - unsigned int *divider) +enum pm_ret_status pm_clock_getdivider(uint32_t clock_id, + uint32_t *divider) { enum pm_ret_status status; enum pm_node_id nid; @@ -1291,7 +1291,7 @@ enum pm_ret_status pm_clock_getdivider(unsigned int clock_id, * * Return: Returns status, either success or error+reason. */ -enum pm_ret_status pm_clock_setrate(unsigned int clock_id, +enum pm_ret_status pm_clock_setrate(uint32_t clock_id, uint64_t rate) { return PM_RET_ERROR_NOTSUPPORTED; @@ -1307,7 +1307,7 @@ enum pm_ret_status pm_clock_setrate(unsigned int clock_id, * * Return: Returns status, either success or error+reason. */ -enum pm_ret_status pm_clock_getrate(unsigned int clock_id, +enum pm_ret_status pm_clock_getrate(uint32_t clock_id, uint64_t *rate) { return PM_RET_ERROR_NOTSUPPORTED; @@ -1322,8 +1322,8 @@ enum pm_ret_status pm_clock_getrate(unsigned int clock_id, * * Return: Returns status, either success or error+reason. */ -enum pm_ret_status pm_clock_setparent(unsigned int clock_id, - unsigned int parent_index) +enum pm_ret_status pm_clock_setparent(uint32_t clock_id, + uint32_t parent_index) { struct pm_pll *pll; uint32_t payload[PAYLOAD_ARG_CNT]; @@ -1356,8 +1356,8 @@ enum pm_ret_status pm_clock_setparent(unsigned int clock_id, * * Return: Returns status, either success or error+reason. */ -enum pm_ret_status pm_clock_getparent(unsigned int clock_id, - unsigned int *parent_index) +enum pm_ret_status pm_clock_getparent(uint32_t clock_id, + uint32_t *parent_index) { struct pm_pll *pll; uint32_t payload[PAYLOAD_ARG_CNT]; @@ -1417,7 +1417,7 @@ static enum pm_ret_status pm_pinctrl_get_num_functions(uint32_t *nfuncs) * * Return: Returns status, either success or error+reason. */ -static enum pm_ret_status pm_pinctrl_get_num_function_groups(unsigned int fid, +static enum pm_ret_status pm_pinctrl_get_num_function_groups(uint32_t fid, uint32_t *ngroups) { return pm_api_pinctrl_get_num_func_groups(fid, ngroups); @@ -1431,7 +1431,7 @@ static enum pm_ret_status pm_pinctrl_get_num_function_groups(unsigned int fid, * This function is used by master to get name of function specified * by given function Id */ -static void pm_pinctrl_get_function_name(unsigned int fid, char *name) +static void pm_pinctrl_get_function_name(uint32_t fid, char *name) { pm_api_pinctrl_get_function_name(fid, name); } @@ -1453,8 +1453,8 @@ static void pm_pinctrl_get_function_name(unsigned int fid, char *name) * * Return: Returns status, either success or error+reason. */ -static enum pm_ret_status pm_pinctrl_get_function_groups(unsigned int fid, - unsigned int index, +static enum pm_ret_status pm_pinctrl_get_function_groups(uint32_t fid, + uint32_t index, uint16_t *groups) { return pm_api_pinctrl_get_function_groups(fid, index, groups); @@ -1477,8 +1477,8 @@ static enum pm_ret_status pm_pinctrl_get_function_groups(unsigned int fid, * * Return: Returns status, either success or error+reason. */ -static enum pm_ret_status pm_pinctrl_get_pin_groups(unsigned int pin_id, - unsigned int index, +static enum pm_ret_status pm_pinctrl_get_pin_groups(uint32_t pin_id, + uint32_t index, uint16_t *groups) { return pm_api_pinctrl_get_pin_groups(pin_id, index, groups); @@ -1494,8 +1494,8 @@ static enum pm_ret_status pm_pinctrl_get_pin_groups(unsigned int pin_id, * * This function returns requested data. */ -void pm_query_data(enum pm_query_id qid, unsigned int arg1, unsigned int arg2, - unsigned int arg3, unsigned int *data) +void pm_query_data(enum pm_query_id qid, uint32_t arg1, uint32_t arg2, + uint32_t arg3, uint32_t *data) { switch (qid) { case PM_QID_CLOCK_GET_NAME: @@ -1632,7 +1632,7 @@ enum pm_ret_status pm_fpga_read(uint32_t reg_numframes, */ enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid, enum pm_pll_param param_id, - unsigned int value) + uint32_t value) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -1662,7 +1662,7 @@ enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid, */ enum pm_ret_status pm_pll_get_parameter(enum pm_node_id nid, enum pm_pll_param param_id, - unsigned int *value) + uint32_t *value) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -1752,11 +1752,11 @@ enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode) * * @return Returns status, either success or error+reason */ -enum pm_ret_status pm_register_access(unsigned int register_access_id, - unsigned int address, - unsigned int mask, - unsigned int value, - unsigned int *out) +enum pm_ret_status pm_register_access(uint32_t register_access_id, + uint32_t address, + uint32_t mask, + uint32_t value, + uint32_t *out) { enum pm_ret_status ret; @@ -1808,7 +1808,7 @@ enum pm_ret_status pm_efuse_access(uint32_t address_high, return pm_ipi_send_sync(primary_proc, payload, value, 1); } -enum pm_ret_status em_set_action(unsigned int *value) +enum pm_ret_status em_set_action(uint32_t *value) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -1817,7 +1817,7 @@ enum pm_ret_status em_set_action(unsigned int *value) return pm_ipi_send_sync(primary_proc, payload, value, 1); } -enum pm_ret_status em_remove_action(unsigned int *value) +enum pm_ret_status em_remove_action(uint32_t *value) { uint32_t payload[PAYLOAD_ARG_CNT]; @@ -1826,7 +1826,7 @@ enum pm_ret_status em_remove_action(unsigned int *value) return pm_ipi_send_sync(primary_proc, payload, value, 1); } -enum pm_ret_status em_send_errors(unsigned int *value) +enum pm_ret_status em_send_errors(uint32_t *value) { uint32_t payload[PAYLOAD_ARG_CNT]; diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h index 84b239c67..9ba9475d4 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h @@ -70,12 +70,12 @@ enum pm_register_access_id { **********************************************************/ enum pm_ret_status pm_req_suspend(enum pm_node_id target, enum pm_request_ack ack, - unsigned int latency, - unsigned int state); + uint32_t latency, + uint32_t state); enum pm_ret_status pm_self_suspend(enum pm_node_id nid, - unsigned int latency, - unsigned int state, + uint32_t latency, + uint32_t state, uintptr_t address); enum pm_ret_status pm_force_powerdown(enum pm_node_id target, @@ -84,84 +84,73 @@ enum pm_ret_status pm_force_powerdown(enum pm_node_id target, enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason); enum pm_ret_status pm_req_wakeup(enum pm_node_id target, - unsigned int set_address, + uint32_t set_address, uintptr_t address, enum pm_request_ack ack); enum pm_ret_status pm_set_wakeup_source(enum pm_node_id target, enum pm_node_id wkup_node, - unsigned int enable); + uint32_t enable); -enum pm_ret_status pm_system_shutdown(unsigned int type, unsigned int subtype); - -enum pm_ret_status pm_init_suspend_cb(enum pm_suspend_reason reason, - unsigned int latency, - unsigned int state, - unsigned int timeout); +enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype); /* API functions for managing PM Slaves */ enum pm_ret_status pm_req_node(enum pm_node_id nid, - unsigned int capabilities, - unsigned int qos, + uint32_t capabilities, + uint32_t qos, enum pm_request_ack ack); enum pm_ret_status pm_set_requirement(enum pm_node_id nid, - unsigned int capabilities, - unsigned int qos, + uint32_t capabilities, + uint32_t qos, enum pm_request_ack ack); /* Miscellaneous API functions */ -enum pm_ret_status pm_get_api_version(unsigned int *version); +enum pm_ret_status pm_get_api_version(uint32_t *version); enum pm_ret_status pm_get_node_status(enum pm_node_id nid, uint32_t *ret_buff); -enum pm_ret_status pm_acknowledge_cb(enum pm_node_id nid, - enum pm_ret_status status, - unsigned int oppoint); -enum pm_ret_status pm_notify_cb(enum pm_node_id nid, - unsigned int event, - unsigned int oppoint); /* Direct-Control API functions */ enum pm_ret_status pm_mmio_write(uintptr_t address, - unsigned int mask, - unsigned int value); -enum pm_ret_status pm_mmio_read(uintptr_t address, unsigned int *value); + uint32_t mask, + uint32_t value); +enum pm_ret_status pm_mmio_read(uintptr_t address, uint32_t *value); enum pm_ret_status pm_fpga_load(uint32_t address_low, uint32_t address_high, uint32_t size, uint32_t flags); -enum pm_ret_status pm_fpga_get_status(unsigned int *value); +enum pm_ret_status pm_fpga_get_status(uint32_t *value); enum pm_ret_status pm_get_chipid(uint32_t *value); enum pm_ret_status pm_secure_rsaaes(uint32_t address_low, uint32_t address_high, uint32_t size, uint32_t flags); -unsigned int pm_get_shutdown_scope(void); +uint32_t pm_get_shutdown_scope(void); void pm_get_callbackdata(uint32_t *data, size_t count); enum pm_ret_status pm_ioctl(enum pm_node_id nid, - unsigned int ioctl_id, - unsigned int arg1, - unsigned int arg2, - unsigned int *value); -enum pm_ret_status pm_clock_enable(unsigned int clock_id); -enum pm_ret_status pm_clock_disable(unsigned int clock_id); -enum pm_ret_status pm_clock_getstate(unsigned int clock_id, - unsigned int *state); -enum pm_ret_status pm_clock_setdivider(unsigned int clock_id, - unsigned int divider); -enum pm_ret_status pm_clock_getdivider(unsigned int clock_id, - unsigned int *divider); -enum pm_ret_status pm_clock_setrate(unsigned int clock_id, + uint32_t ioctl_id, + uint32_t arg1, + uint32_t arg2, + uint32_t *value); +enum pm_ret_status pm_clock_enable(uint32_t clock_id); +enum pm_ret_status pm_clock_disable(uint32_t clock_id); +enum pm_ret_status pm_clock_getstate(uint32_t clock_id, + uint32_t *state); +enum pm_ret_status pm_clock_setdivider(uint32_t clock_id, + uint32_t divider); +enum pm_ret_status pm_clock_getdivider(uint32_t clock_id, + uint32_t *divider); +enum pm_ret_status pm_clock_setrate(uint32_t clock_id, uint64_t rate); -enum pm_ret_status pm_clock_getrate(unsigned int clock_id, +enum pm_ret_status pm_clock_getrate(uint32_t clock_id, uint64_t *rate); -enum pm_ret_status pm_clock_setparent(unsigned int clock_id, - unsigned int parent_index); -enum pm_ret_status pm_clock_getparent(unsigned int clock_id, - unsigned int *parent_index); -void pm_query_data(enum pm_query_id qid, unsigned int arg1, unsigned int arg2, - unsigned int arg3, unsigned int *data); +enum pm_ret_status pm_clock_setparent(uint32_t clock_id, + uint32_t parent_index); +enum pm_ret_status pm_clock_getparent(uint32_t clock_id, + uint32_t *parent_index); +void pm_query_data(enum pm_query_id qid, uint32_t arg1, uint32_t arg2, + uint32_t arg3, uint32_t *data); enum pm_ret_status pm_sha_hash(uint32_t address_high, uint32_t address_low, uint32_t size, @@ -183,28 +172,24 @@ enum pm_ret_status pm_fpga_read(uint32_t reg_numframes, enum pm_ret_status pm_aes_engine(uint32_t address_high, uint32_t address_low, uint32_t *value); -enum pm_ret_status pm_register_access(unsigned int register_access_id, - unsigned int address, - unsigned int mask, - unsigned int value, - unsigned int *out); +enum pm_ret_status pm_register_access(uint32_t register_access_id, + uint32_t address, + uint32_t mask, + uint32_t value, + uint32_t *out); enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid, enum pm_pll_param param_id, - unsigned int value); + uint32_t value); enum pm_ret_status pm_pll_get_parameter(enum pm_node_id nid, enum pm_pll_param param_id, - unsigned int *value); + uint32_t *value); enum pm_ret_status pm_pll_set_mode(enum pm_node_id nid, enum pm_pll_mode mode); enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode); enum pm_ret_status pm_efuse_access(uint32_t address_high, uint32_t address_low, uint32_t *value); -enum pm_ret_status em_set_action(unsigned int *value); -enum pm_ret_status em_remove_action(unsigned int *value); -enum pm_ret_status em_send_errors(unsigned int *value); -enum pm_ret_status pm_feature_config(unsigned int ioctl_id, - unsigned int config_id, - unsigned int value, - unsigned int *response); +enum pm_ret_status em_set_action(uint32_t *value); +enum pm_ret_status em_remove_action(uint32_t *value); +enum pm_ret_status em_send_errors(uint32_t *value); enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *version, uint32_t *bit_mask, uint8_t len); enum pm_ret_status check_api_dependency(uint8_t id); diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c index 1f5443044..7217fa145 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_client.c +++ b/plat/xilinx/zynqmp/pm_service/pm_client.c @@ -25,12 +25,12 @@ #include "pm_client.h" #include "pm_ipi.h" -#define IRQ_MAX 84 -#define NUM_GICD_ISENABLER ((IRQ_MAX >> 5) + 1) -#define UNDEFINED_CPUID (~0) +#define IRQ_MAX 84U +#define NUM_GICD_ISENABLER ((IRQ_MAX >> 5U) + 1U) +#define UNDEFINED_CPUID (~0U) -#define PM_SUSPEND_MODE_STD 0 -#define PM_SUSPEND_MODE_POWER_OFF 1 +#define PM_SUSPEND_MODE_STD 0U +#define PM_SUSPEND_MODE_POWER_OFF 1U DEFINE_BAKERY_LOCK(pm_client_secure_lock); @@ -69,7 +69,7 @@ static const struct pm_proc pm_procs_all[] = { }; /* Interrupt to PM node ID map */ -static enum pm_node_id irq_node_map[IRQ_MAX + 1] = { +static enum pm_node_id irq_node_map[IRQ_MAX + 1U] = { NODE_UNKNOWN, NODE_UNKNOWN, NODE_UNKNOWN, @@ -163,7 +163,7 @@ static enum pm_node_id irq_node_map[IRQ_MAX + 1] = { * * Return: PM node ID corresponding to the specified interrupt */ -static enum pm_node_id irq_to_pm_node(unsigned int irq) +static enum pm_node_id irq_to_pm_node(uint32_t irq) { assert(irq <= IRQ_MAX); return irq_node_map[irq]; @@ -176,14 +176,14 @@ static enum pm_node_id irq_to_pm_node(unsigned int irq) static void pm_client_set_wakeup_sources(void) { uint32_t reg_num; - uint8_t pm_wakeup_nodes_set[NODE_MAX]; - uintptr_t isenabler1 = BASE_GICD_BASE + GICD_ISENABLER + 4; + uint8_t pm_wakeup_nodes_set[NODE_MAX] = { 0 }; + uintptr_t isenabler1 = BASE_GICD_BASE + GICD_ISENABLER + 4U; /* In case of power-off suspend, only NODE_EXTERN must be set */ if (suspend_mode == PM_SUSPEND_MODE_POWER_OFF) { enum pm_ret_status ret; - ret = pm_set_wakeup_source(NODE_APU, NODE_EXTERN, 1); + ret = pm_set_wakeup_source(NODE_APU, NODE_EXTERN, 1U); /** * If NODE_EXTERN could not be set as wake source, proceed with * standard suspend (no one will wake the system otherwise) @@ -195,11 +195,11 @@ static void pm_client_set_wakeup_sources(void) zeromem(&pm_wakeup_nodes_set, sizeof(pm_wakeup_nodes_set)); - for (reg_num = 0; reg_num < NUM_GICD_ISENABLER; reg_num++) { + for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) { uint32_t base_irq = reg_num << ISENABLER_SHIFT; - uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2)); + uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2U)); - if (!reg) { + if (reg == 0) { continue; } @@ -217,10 +217,11 @@ static void pm_client_set_wakeup_sources(void) node = irq_to_pm_node(irq); reg &= ~lowest_set; - if ((node != NODE_UNKNOWN) && - (!pm_wakeup_nodes_set[node])) { - ret = pm_set_wakeup_source(NODE_APU, node, 1); - pm_wakeup_nodes_set[node] = !ret; + if (node > NODE_UNKNOWN && node < NODE_MAX) { + if (pm_wakeup_nodes_set[node] == 0U) { + ret = pm_set_wakeup_source(NODE_APU, node, 1U); + pm_wakeup_nodes_set[node] = (ret == PM_RET_SUCCESS) ? 1U : 0U; + } } } } @@ -232,7 +233,7 @@ static void pm_client_set_wakeup_sources(void) * * Return: pointer to a proc structure if proc is found, otherwise NULL */ -const struct pm_proc *pm_get_proc(unsigned int cpuid) +const struct pm_proc *pm_get_proc(uint32_t cpuid) { if (cpuid < ARRAY_SIZE(pm_procs_all)) { return &pm_procs_all[cpuid]; @@ -263,7 +264,7 @@ const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid) * * Return: the cpu ID (starting from 0) for the subsystem */ -static unsigned int pm_get_cpuid(enum pm_node_id nid) +static uint32_t pm_get_cpuid(enum pm_node_id nid) { for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) { if (pm_procs_all[i].node_id == nid) { @@ -282,7 +283,7 @@ const struct pm_proc *primary_proc = &pm_procs_all[0]; * required prior to sending suspend request to PMU * Actions taken depend on the state system is suspending to. */ -void pm_client_suspend(const struct pm_proc *proc, unsigned int state) +void pm_client_suspend(const struct pm_proc *proc, uint32_t state) { bakery_lock_get(&pm_client_secure_lock); @@ -325,7 +326,7 @@ void pm_client_abort_suspend(void) */ void pm_client_wakeup(const struct pm_proc *proc) { - unsigned int cpuid = pm_get_cpuid(proc->node_id); + uint32_t cpuid = pm_get_cpuid(proc->node_id); if (cpuid == UNDEFINED_CPUID) { return; diff --git a/plat/xilinx/zynqmp/pm_service/pm_defs.h b/plat/xilinx/zynqmp/pm_service/pm_defs.h index 8eb197a4a..e335b9443 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_defs.h +++ b/plat/xilinx/zynqmp/pm_service/pm_defs.h @@ -17,10 +17,10 @@ * Version number is a 32bit value, like: * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR */ -#define PM_VERSION_MAJOR 1 -#define PM_VERSION_MINOR 1 +#define PM_VERSION_MAJOR 1U +#define PM_VERSION_MINOR 1U -#define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR) +#define PM_VERSION ((PM_VERSION_MAJOR << 16U) | PM_VERSION_MINOR) /** * PM API versions @@ -245,6 +245,7 @@ enum pm_opchar_type { * @PM_RET_SUCCESS: success * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated) * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated) + * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled * @PM_RET_ERROR_INTERNAL: internal error * @PM_RET_ERROR_CONFLICT: conflict * @PM_RET_ERROR_ACCESS: access rights violation @@ -255,18 +256,19 @@ enum pm_opchar_type { * @PM_RET_ERROR_NODE_USED: node is already in use */ enum pm_ret_status { - PM_RET_SUCCESS, - PM_RET_ERROR_ARGS = 1, - PM_RET_ERROR_NOTSUPPORTED = 4, - PM_RET_ERROR_INTERNAL = 2000, - PM_RET_ERROR_CONFLICT = 2001, - PM_RET_ERROR_ACCESS = 2002, - PM_RET_ERROR_INVALID_NODE = 2003, - PM_RET_ERROR_DOUBLE_REQ = 2004, - PM_RET_ERROR_ABORT_SUSPEND = 2005, - PM_RET_ERROR_TIMEOUT = 2006, - PM_RET_ERROR_NODE_USED = 2007, - PM_RET_ERROR_NO_FEATURE = 2008 + PM_RET_SUCCESS = (0U), + PM_RET_ERROR_ARGS = (1U), + PM_RET_ERROR_NOTSUPPORTED = (4U), + PM_RET_ERROR_NOT_ENABLED = (29U), + PM_RET_ERROR_INTERNAL = (2000U), + PM_RET_ERROR_CONFLICT = (2001U), + PM_RET_ERROR_ACCESS = (2002U), + PM_RET_ERROR_INVALID_NODE = (2003U), + PM_RET_ERROR_DOUBLE_REQ = (2004U), + PM_RET_ERROR_ABORT_SUSPEND = (2005U), + PM_RET_ERROR_TIMEOUT = (2006U), + PM_RET_ERROR_NODE_USED = (2007U), + PM_RET_ERROR_NO_FEATURE = (2008U) }; /** diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c index d88e5fa69..03fa31632 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c +++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c @@ -151,6 +151,8 @@ static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags, 0xffffffff); } + dsb(); + spin_unlock(&inc_lock); if (active_cores == 0) { @@ -203,21 +205,21 @@ err: * Called from sip_svc_setup initialization function with the * rt_svc_init signature. */ -int pm_setup(void) +int32_t pm_setup(void) { - int status, ret; - status = pm_ipi_init(primary_proc); + pm_ipi_init(primary_proc); - ret = pm_get_api_version(&pm_ctx.api_version); + pm_get_api_version(&pm_ctx.api_version); if (pm_ctx.api_version < PM_VERSION) { ERROR("BL31: Platform Management API version error. Expected: " "v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR, PM_VERSION_MINOR, pm_ctx.api_version >> 16, - pm_ctx.api_version & 0xFFFF); + pm_ctx.api_version & 0xFFFFU); return -EINVAL; } + int32_t status = 0, ret = 0; #if ZYNQMP_WDT_RESTART status = pm_wdt_restart_setup(); if (status) @@ -255,17 +257,17 @@ int pm_setup(void) * function with rt_svc_handle signature */ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, - uint64_t x4, void *cookie, void *handle, uint64_t flags) + uint64_t x4, const void *cookie, void *handle, uint64_t flags) { enum pm_ret_status ret; uint32_t payload[PAYLOAD_ARG_CNT]; - uint32_t pm_arg[4]; - uint32_t result[PAYLOAD_ARG_CNT]; + uint32_t pm_arg[5]; + uint32_t result[PAYLOAD_ARG_CNT] = {0}; uint32_t api_id; /* Handle case where PM wasn't initialized properly */ - if (!pm_up) + if (pm_up == 0) SMC_RET1(handle, SMC_UNK); pm_arg[0] = (uint32_t)x1; @@ -291,10 +293,10 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, case PM_REQ_WAKEUP: { /* Use address flag is encoded in the 1st bit of the low-word */ - unsigned int set_addr = pm_arg[1] & 0x1; - uint64_t address = (uint64_t)pm_arg[2] << 32; + uint32_t set_addr = pm_arg[1] & 0x1U; + uint64_t address = (uint64_t)pm_arg[2] << 32U; - address |= pm_arg[1] & (~0x1); + address |= pm_arg[1] & (~0x1U); ret = pm_req_wakeup(pm_arg[0], set_addr, address, pm_arg[3]); SMC_RET1(handle, (uint64_t)ret); @@ -328,7 +330,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, case PM_GET_API_VERSION: /* Check is PM API version already verified */ if (pm_ctx.api_version >= PM_VERSION) { - if (!ipi_irq_flag) { + if (ipi_irq_flag == 0U) { /* * Enable IPI IRQ * assume the rich OS is OK to handle callback IRQs now. @@ -336,7 +338,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, * the GIC. */ pm_ipi_irq_enable(primary_proc); - ipi_irq_flag = 1; + ipi_irq_flag = 1U; } SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | ((uint64_t)pm_ctx.api_version << 32)); @@ -348,7 +350,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, case PM_FPGA_GET_STATUS: { - uint32_t value; + uint32_t value = 0; ret = pm_fpga_get_status(&value); SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); @@ -366,7 +368,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, (uint64_t)result[2] | ((uint64_t)result[3] << 32)); case PM_IOCTL: { - uint32_t value; + uint32_t value = 0; ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], &value); @@ -393,7 +395,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, case PM_CLOCK_GETSTATE: { - uint32_t value; + uint32_t value = 0; ret = pm_clock_getstate(pm_arg[0], &value); SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); @@ -405,7 +407,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, case PM_CLOCK_GETDIVIDER: { - uint32_t value; + uint32_t value = 0; ret = pm_clock_getdivider(pm_arg[0], &value); SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); @@ -419,7 +421,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, case PM_CLOCK_GETRATE: { - uint64_t value; + uint64_t value = 0; ret = pm_clock_getrate(pm_arg[0], &value); SMC_RET2(handle, (uint64_t)ret | @@ -434,15 +436,15 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, case PM_CLOCK_GETPARENT: { - uint32_t value; + uint32_t value = 0; ret = pm_clock_getparent(pm_arg[0], &value); - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); } case PM_GET_TRUSTZONE_VERSION: SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | - ((uint64_t)ZYNQMP_TZ_VERSION << 32)); + ((uint64_t)ZYNQMP_TZ_VERSION << 32U)); case PM_SET_SUSPEND_MODE: ret = pm_set_suspend_mode(pm_arg[0]); @@ -462,25 +464,25 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, { ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], &result[0]); - SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32), + SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U), result[1]); } case PM_FPGA_READ: { - uint32_t value; + uint32_t value = 0; ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], &value); - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); } case PM_SECURE_AES: { - uint32_t value; + uint32_t value = 0; ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value); - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); } case PM_PLL_SET_PARAMETER: @@ -489,10 +491,10 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, case PM_PLL_GET_PARAMETER: { - uint32_t value; + uint32_t value = 0; ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value); - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32)); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32U)); } case PM_PLL_SET_MODE: @@ -501,27 +503,34 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, case PM_PLL_GET_MODE: { - uint32_t mode; + uint32_t mode = 0; ret = pm_pll_get_mode(pm_arg[0], &mode); - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32)); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32U)); } case PM_REGISTER_ACCESS: { - uint32_t value; + uint32_t value = 0; ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], &value); - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); } case PM_EFUSE_ACCESS: { - uint32_t value; + uint32_t value = 0; +#if defined(ZYNQMP_SECURE_EFUSES) + if (is_caller_non_secure(flags)) { + SMC_RET1(handle, + (((uint64_t)PM_RET_ERROR_NOT_ENABLED) << 32U) | + (uint64_t)PM_RET_ERROR_ACCESS); + } +#endif ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value); - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); } case PM_FPGA_GET_VERSION: @@ -532,19 +541,19 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, PM_PACK_PAYLOAD5(payload, smc_fid & FUNCID_NUM_MASK, pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U); - SMC_RET2(handle, (uint64_t)ret | (uint64_t)ret_payload[0] << 32, - (uint64_t)ret_payload[1] | (uint64_t)ret_payload[2] << 32); + SMC_RET2(handle, (uint64_t)ret | (uint64_t)ret_payload[0] << 32U, + (uint64_t)ret_payload[1] | (uint64_t)ret_payload[2] << 32U); } case PM_FEATURE_CHECK: { - uint32_t version; + uint32_t version = 0; uint32_t bit_mask[2] = {0}; ret = pm_feature_check(pm_arg[0], &version, bit_mask, ARRAY_SIZE(bit_mask)); - SMC_RET2(handle, (uint64_t)ret | ((uint64_t)version << 32), - (uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32)); + SMC_RET2(handle, (uint64_t)ret | ((uint64_t)version << 32U), + (uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U)); } default: @@ -553,8 +562,8 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, pm_arg[2], pm_arg[3], pm_arg[4]); ret = pm_ipi_send_sync(primary_proc, payload, result, PAYLOAD_ARG_CNT); - SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32), - (uint64_t)result[1] | ((uint64_t)result[2] << 32)); + SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U), + (uint64_t)result[1] | ((uint64_t)result[2] << 32U)); } } @@ -575,7 +584,7 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, * function with rt_svc_handle signature */ uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, - uint64_t x4, void *cookie, void *handle, uint64_t flags) + uint64_t x4, const void *cookie, void *handle, uint64_t flags) { enum pm_ret_status ret; @@ -586,7 +595,7 @@ uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t value; ret = em_set_action(&value); - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); } case EM_REMOVE_ACTION: @@ -594,7 +603,7 @@ uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t value; ret = em_remove_action(&value); - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); } case EM_SEND_ERRORS: @@ -602,7 +611,7 @@ uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t value; ret = em_send_errors(&value); - SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); } default: diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.h b/plat/xilinx/zynqmp/pm_service/pm_svc_main.h index abadd4065..c1781f3e0 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.h +++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.h @@ -9,12 +9,12 @@ #include "pm_common.h" -int pm_setup(void); +int32_t pm_setup(void); uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, - uint64_t x4, void *cookie, void *handle, + uint64_t x4, const void *cookie, void *handle, uint64_t flags); uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, - uint64_t x4, void *cookie, void *handle, + uint64_t x4, const void *cookie, void *handle, uint64_t flags); #endif /* PM_SVC_MAIN_H */ diff --git a/services/spd/pncd/pncd.mk b/services/spd/pncd/pncd.mk new file mode 100644 index 000000000..0f8eb2514 --- /dev/null +++ b/services/spd/pncd/pncd.mk @@ -0,0 +1,24 @@ +# Copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +PNCD_DIR := services/spd/pncd +SPD_INCLUDES := -Iinclude/bl32/pnc +SPD_INCLUDES += -Iinclude/common/ + +SPD_SOURCES := services/spd/pncd/pncd_common.c \ + services/spd/pncd/pncd_helpers.S \ + services/spd/pncd/pncd_main.c + +NEED_BL32 := yes + +# The following constants need to be defined: +# - SPD_PNCD_NS_IRQ: IRQ number used to notify NS world when SMC_ACTION_FROM_S is received +# - SPD_PNCD_S_IRQ: IRQ number used to notify S world when SMC_ACTION_FROM_NS is received +$(eval $(call assert_numerics, SPD_PNCD_NS_IRQ SPD_PNCD_S_IRQ)) + +$(eval $(call add_defines,\ + $(sort \ + SPD_PNCD_NS_IRQ \ + SPD_PNCD_S_IRQ \ +))) diff --git a/services/spd/pncd/pncd_common.c b/services/spd/pncd/pncd_common.c new file mode 100644 index 000000000..6fdb6293f --- /dev/null +++ b/services/spd/pncd/pncd_common.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <lib/el3_runtime/context_mgmt.h> +#include <lib/utils.h> +#include <plat/common/platform.h> + +#include "pncd_private.h" + +/******************************************************************************* + * Given a secure payload entrypoint info pointer, entry point PC & pointer to a + * context data structure, this function will initialize pnc context and entry + * point info for the secure payload + ******************************************************************************/ +void pncd_init_pnc_ep_state(struct entry_point_info *pnc_entry_point, + uint64_t pc, + pnc_context_t *pnc_ctx) +{ + uint32_t ep_attr; + + /* Passing a NULL context is a critical programming error */ + assert(pnc_ctx); + assert(pnc_entry_point); + assert(pc); + + /* Associate this context with the current cpu */ + pnc_ctx->mpidr = read_mpidr(); + + cm_set_context(&pnc_ctx->cpu_ctx, SECURE); + + /* initialise an entrypoint to set up the CPU context */ + ep_attr = SECURE | EP_ST_ENABLE; + if (read_sctlr_el3() & SCTLR_EE_BIT) { + ep_attr |= EP_EE_BIG; + } + SET_PARAM_HEAD(pnc_entry_point, PARAM_EP, VERSION_1, ep_attr); + + pnc_entry_point->pc = pc; + pnc_entry_point->spsr = SPSR_64(MODE_EL1, + MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + memset(&pnc_entry_point->args, 0, sizeof(pnc_entry_point->args)); +} + +/******************************************************************************* + * This function takes an SP context pointer and: + * 1. Applies the S-EL1 system register context from pnc_ctx->cpu_ctx. + * 2. Saves the current C runtime state (callee saved registers) on the stack + * frame and saves a reference to this state. + * 3. Calls el3_exit() so that the EL3 system and general purpose registers + * from the pnc_ctx->cpu_ctx are used to enter the secure payload image. + ******************************************************************************/ +uint64_t pncd_synchronous_sp_entry(pnc_context_t *pnc_ctx) +{ + assert(pnc_ctx != NULL); + assert(pnc_ctx->c_rt_ctx == 0U); + + /* Apply the Secure EL1 system register context and switch to it */ + assert(cm_get_context(SECURE) == &pnc_ctx->cpu_ctx); + cm_el1_sysregs_context_restore(SECURE); +#if CTX_INCLUDE_FPREGS + fpregs_context_restore(get_fpregs_ctx(cm_get_context(SECURE))); +#endif + cm_set_next_eret_context(SECURE); + + return pncd_enter_sp(&pnc_ctx->c_rt_ctx); +} + + +/******************************************************************************* + * This function takes an SP context pointer and: + * 1. Saves the S-EL1 system register context tp pnc_ctx->cpu_ctx. + * 2. Restores the current C runtime state (callee saved registers) from the + * stack frame using the reference to this state saved in pncd_enter_sp(). + * 3. It does not need to save any general purpose or EL3 system register state + * as the generic smc entry routine should have saved those. + ******************************************************************************/ +void pncd_synchronous_sp_exit(pnc_context_t *pnc_ctx, uint64_t ret) +{ + assert(pnc_ctx != NULL); + /* Save the Secure EL1 system register context */ + assert(cm_get_context(SECURE) == &pnc_ctx->cpu_ctx); + cm_el1_sysregs_context_save(SECURE); +#if CTX_INCLUDE_FPREGS + fpregs_context_save(get_fpregs_ctx(cm_get_context(SECURE))); +#endif + + assert(pnc_ctx->c_rt_ctx != 0); + pncd_exit_sp(pnc_ctx->c_rt_ctx, ret); + + /* Should never reach here */ + panic(); +} diff --git a/services/spd/pncd/pncd_helpers.S b/services/spd/pncd/pncd_helpers.S new file mode 100644 index 000000000..736b30f95 --- /dev/null +++ b/services/spd/pncd/pncd_helpers.S @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include "pncd_private.h" + + .global pncd_enter_sp + /* --------------------------------------------- + * This function is called with SP_EL0 as stack. + * Here we stash our EL3 callee-saved registers + * on to the stack as a part of saving the C + * runtime and enter the secure payload. + * 'x0' contains a pointer to the memory where + * the address of the C runtime context is to be + * saved. + * --------------------------------------------- + */ +func pncd_enter_sp + /* Make space for the registers that we're going to save */ + mov x3, sp + str x3, [x0, #0] + sub sp, sp, #PNCD_C_RT_CTX_SIZE + + /* Save callee-saved registers on to the stack */ + stp x19, x20, [sp, #PNCD_C_RT_CTX_X19] + stp x21, x22, [sp, #PNCD_C_RT_CTX_X21] + stp x23, x24, [sp, #PNCD_C_RT_CTX_X23] + stp x25, x26, [sp, #PNCD_C_RT_CTX_X25] + stp x27, x28, [sp, #PNCD_C_RT_CTX_X27] + stp x29, x30, [sp, #PNCD_C_RT_CTX_X29] + + /* --------------------------------------------- + * Everything is setup now. el3_exit() will + * use the secure context to restore to the + * general purpose and EL3 system registers to + * ERET into the secure payload. + * --------------------------------------------- + */ + b el3_exit +endfunc pncd_enter_sp + + /* --------------------------------------------- + * This function is called 'x0' pointing to a C + * runtime context saved in pncd_enter_sp(). It + * restores the saved registers and jumps to + * that runtime with 'x0' as the new sp. This + * destroys the C runtime context that had been + * built on the stack below the saved context by + * the caller. Later the second parameter 'x1' + * is passed as return value to the caller + * --------------------------------------------- + */ + .global pncd_exit_sp +func pncd_exit_sp + /* Restore the previous stack */ + mov sp, x0 + + /* Restore callee-saved registers on to the stack */ + ldp x19, x20, [x0, #(PNCD_C_RT_CTX_X19 - PNCD_C_RT_CTX_SIZE)] + ldp x21, x22, [x0, #(PNCD_C_RT_CTX_X21 - PNCD_C_RT_CTX_SIZE)] + ldp x23, x24, [x0, #(PNCD_C_RT_CTX_X23 - PNCD_C_RT_CTX_SIZE)] + ldp x25, x26, [x0, #(PNCD_C_RT_CTX_X25 - PNCD_C_RT_CTX_SIZE)] + ldp x27, x28, [x0, #(PNCD_C_RT_CTX_X27 - PNCD_C_RT_CTX_SIZE)] + ldp x29, x30, [x0, #(PNCD_C_RT_CTX_X29 - PNCD_C_RT_CTX_SIZE)] + + /* --------------------------------------------- + * This should take us back to the instruction + * after the call to the last pncd_enter_sp(). + * Place the second parameter to x0 so that the + * caller will see it as a return value from the + * original entry call + * --------------------------------------------- + */ + mov x0, x1 + ret +endfunc pncd_exit_sp diff --git a/services/spd/pncd/pncd_main.c b/services/spd/pncd/pncd_main.c new file mode 100644 index 000000000..99c4aa1b2 --- /dev/null +++ b/services/spd/pncd/pncd_main.c @@ -0,0 +1,471 @@ +/* + * Copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/******************************************************************************* + * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a + * plug-in component to the Secure Monitor, registered as a runtime service. The + * SPD is expected to be a functional extension of the Secure Payload (SP) that + * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting + * the Trusted OS/Applications range to the dispatcher. The SPD will either + * handle the request locally or delegate it to the Secure Payload. It is also + * responsible for initialising and maintaining communication with the SP. + ******************************************************************************/ + +#include <assert.h> +#include <errno.h> +#include <stddef.h> +#include <string.h> + +#include <arch_helpers.h> +#include <bl31/bl31.h> +#include <bl31/interrupt_mgmt.h> +#include <bl_common.h> +#include <common/debug.h> +#include <common/ep_info.h> +#include <drivers/arm/gic_common.h> +#include <lib/el3_runtime/context_mgmt.h> +#include <lib/spinlock.h> +#include <plat/common/platform.h> +#include <pnc.h> +#include "pncd_private.h" +#include <runtime_svc.h> +#include <tools_share/uuid.h> + +/******************************************************************************* + * Structure to keep track of ProvenCore state + ******************************************************************************/ +static pnc_context_t pncd_sp_context; + +static bool ree_info; +static uint64_t ree_base_addr; +static uint64_t ree_length; +static uint64_t ree_tag; + +static bool pnc_initialized; + +static spinlock_t smc_handler_lock; + +static int pncd_init(void); + +static void context_save(unsigned long security_state) +{ + assert(sec_state_is_valid(security_state)); + + cm_el1_sysregs_context_save((uint32_t) security_state); +#if CTX_INCLUDE_FPREGS + fpregs_context_save(get_fpregs_ctx(cm_get_context(security_state))); +#endif +} + +static void *context_restore(unsigned long security_state) +{ + void *handle; + + assert(sec_state_is_valid(security_state)); + + /* Get a reference to the next context */ + handle = cm_get_context((uint32_t) security_state); + assert(handle); + + /* Restore state */ + cm_el1_sysregs_context_restore((uint32_t) security_state); +#if CTX_INCLUDE_FPREGS + fpregs_context_restore(get_fpregs_ctx(cm_get_context(security_state))); +#endif + + cm_set_next_eret_context((uint32_t) security_state); + + return handle; +} + +static uint64_t pncd_sel1_interrupt_handler(uint32_t id, + uint32_t flags, void *handle, void *cookie); + +/******************************************************************************* + * Switch context to the specified security state and return the targeted + * handle. Note that the context may remain unchanged if the switch is not + * allowed. + ******************************************************************************/ +void *pncd_context_switch_to(unsigned long security_state) +{ + unsigned long sec_state_from = + security_state == SECURE ? NON_SECURE : SECURE; + + assert(sec_state_is_valid(security_state)); + + /* Check if this is the first world switch */ + if (!pnc_initialized) { + int rc; + uint32_t flags; + + assert(sec_state_from == SECURE); + + INFO("PnC initialization done\n"); + + /* + * Register an interrupt handler for S-EL1 interrupts + * when generated during code executing in the + * non-secure state. + */ + flags = 0U; + set_interrupt_rm_flag(flags, NON_SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, + pncd_sel1_interrupt_handler, + flags); + if (rc != 0) { + ERROR("Failed to register S-EL1 interrupt handler (%d)\n", + rc); + panic(); + } + + context_save(SECURE); + + pnc_initialized = true; + + /* + * Release the lock before restoring the EL3 context to + * bl31_main. + */ + spin_unlock(&smc_handler_lock); + + /* + * SP reports completion. The SPD must have initiated + * the original request through a synchronous entry + * into the SP. Jump back to the original C runtime + * context. + */ + pncd_synchronous_sp_exit(&pncd_sp_context, (uint64_t) 0x0); + + /* Unreachable */ + ERROR("Returned from pncd_synchronous_sp_exit... Should not happen\n"); + panic(); + } + + /* Check that the world switch is allowed */ + if (read_mpidr() != pncd_sp_context.mpidr) { + if (sec_state_from == SECURE) { + /* + * Secure -> Non-Secure world switch initiated on a CPU where there + * should be no Trusted OS running + */ + WARN("Secure to Non-Secure switch requested on CPU where ProvenCore is not supposed to be running...\n"); + } + + /* + * Secure or Non-Secure world wants to switch world but there is no Secure + * software on this core + */ + return cm_get_context((uint32_t) sec_state_from); + } + + context_save(sec_state_from); + + return context_restore(security_state); +} + +/******************************************************************************* + * This function is the handler registered for S-EL1 interrupts by the PNCD. It + * validates the interrupt and upon success arranges entry into the PNC at + * 'pnc_sel1_intr_entry()' for handling the interrupt. + ******************************************************************************/ +static uint64_t pncd_sel1_interrupt_handler(uint32_t id, + uint32_t flags, + void *handle, + void *cookie) +{ + /* Check the security state when the exception was generated */ + assert(get_interrupt_src_ss(flags) == NON_SECURE); + + /* Sanity check the pointer to this cpu's context */ + assert(handle == cm_get_context(NON_SECURE)); + + /* switch to PnC */ + handle = pncd_context_switch_to(SECURE); + + assert(handle != NULL); + + SMC_RET0(handle); +} + +#pragma weak plat_pncd_setup +int plat_pncd_setup(void) +{ + return 0; +} + +/******************************************************************************* + * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type + * (aarch32/aarch64) if not already known and initialises the context for entry + * into the SP for its initialisation. + ******************************************************************************/ +static int pncd_setup(void) +{ + entry_point_info_t *pnc_ep_info; + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. + * + * TODO: Add support to conditionally include the SPD service + */ + pnc_ep_info = bl31_plat_get_next_image_ep_info(SECURE); + if (!pnc_ep_info) { + WARN("No PNC provided by BL2 boot loader, Booting device without PNC initialization. SMC`s destined for PNC will return SMC_UNK\n"); + return 1; + } + + /* + * If there's no valid entry point for SP, we return a non-zero value + * signalling failure initializing the service. We bail out without + * registering any handlers + */ + if (!pnc_ep_info->pc) { + return 1; + } + + pncd_init_pnc_ep_state(pnc_ep_info, + pnc_ep_info->pc, + &pncd_sp_context); + + /* + * All PNCD initialization done. Now register our init function with + * BL31 for deferred invocation + */ + bl31_register_bl32_init(&pncd_init); + bl31_set_next_image_type(NON_SECURE); + + return plat_pncd_setup(); +} + +/******************************************************************************* + * This function passes control to the Secure Payload image (BL32) for the first + * time on the primary cpu after a cold boot. It assumes that a valid secure + * context has already been created by pncd_setup() which can be directly used. + * It also assumes that a valid non-secure context has been initialised by PSCI + * so it does not need to save and restore any non-secure state. This function + * performs a synchronous entry into the Secure payload. The SP passes control + * back to this routine through a SMC. + ******************************************************************************/ +static int32_t pncd_init(void) +{ + entry_point_info_t *pnc_entry_point; + uint64_t rc = 0; + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. + */ + pnc_entry_point = bl31_plat_get_next_image_ep_info(SECURE); + assert(pnc_entry_point); + + cm_init_my_context(pnc_entry_point); + + /* + * Arrange for an entry into the test secure payload. It will be + * returned via PNC_ENTRY_DONE case + */ + rc = pncd_synchronous_sp_entry(&pncd_sp_context); + + /* + * If everything went well at this point, the return value should be 0. + */ + return rc == 0; +} + +#pragma weak plat_pncd_smc_handler +/******************************************************************************* + * This function is responsible for handling the platform-specific SMCs in the + * Trusted OS/App range as defined in the SMC Calling Convention Document. + ******************************************************************************/ +uintptr_t plat_pncd_smc_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + (void) smc_fid; + (void) x1; + (void) x2; + (void) x3; + (void) x4; + (void) cookie; + (void) flags; + + SMC_RET1(handle, SMC_UNK); +} + +/******************************************************************************* + * This function is responsible for handling all SMCs in the Trusted OS/App + * range as defined in the SMC Calling Convention Document. It is also + * responsible for communicating with the Secure payload to delegate work and + * return results back to the non-secure state. Lastly it will also return any + * information that the secure payload needs to do the work assigned to it. + * + * It should only be called with the smc_handler_lock held. + ******************************************************************************/ +static uintptr_t pncd_smc_handler_unsafe(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + uint32_t ns; + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + + assert(ns != 0 || read_mpidr() == pncd_sp_context.mpidr); + + switch (smc_fid) { + case SMC_CONFIG_SHAREDMEM: + if (ree_info) { + /* Do not Yield */ + SMC_RET0(handle); + } + + /* + * Fetch the physical base address (x1) and size (x2) of the + * shared memory allocated by the Non-Secure world. This memory + * will be used by PNC to communicate with the Non-Secure world. + * Verifying the validity of these values is up to the Trusted + * OS. + */ + ree_base_addr = x1 | (x2 << 32); + ree_length = x3; + ree_tag = x4; + + INFO("IN SMC_CONFIG_SHAREDMEM: addr=%lx, length=%lx, tag=%lx\n", + (unsigned long) ree_base_addr, + (unsigned long) ree_length, + (unsigned long) ree_tag); + + if ((ree_base_addr % 0x200000) != 0) { + SMC_RET1(handle, SMC_UNK); + } + + if ((ree_length % 0x200000) != 0) { + SMC_RET1(handle, SMC_UNK); + } + + ree_info = true; + + /* Do not Yield */ + SMC_RET4(handle, 0, 0, 0, 0); + + break; + + case SMC_GET_SHAREDMEM: + if (ree_info) { + x1 = (1U << 16) | ree_tag; + x2 = ree_base_addr & 0xFFFFFFFF; + x3 = (ree_base_addr >> 32) & 0xFFFFFFFF; + x4 = ree_length & 0xFFFFFFFF; + SMC_RET4(handle, x1, x2, x3, x4); + } else { + SMC_RET4(handle, 0, 0, 0, 0); + } + + break; + + case SMC_ACTION_FROM_NS: + if (ns == 0) { + SMC_RET1(handle, SMC_UNK); + } + + if (SPD_PNCD_S_IRQ < MIN_PPI_ID) { + plat_ic_raise_s_el1_sgi(SPD_PNCD_S_IRQ, + pncd_sp_context.mpidr); + } else { + plat_ic_set_interrupt_pending(SPD_PNCD_S_IRQ); + } + + SMC_RET0(handle); + + break; + + case SMC_ACTION_FROM_S: + if (ns != 0) { + SMC_RET1(handle, SMC_UNK); + } + + if (SPD_PNCD_NS_IRQ < MIN_PPI_ID) { + /* + * NS SGI is sent to the same core as the one running + * PNC + */ + plat_ic_raise_ns_sgi(SPD_PNCD_NS_IRQ, read_mpidr()); + } else { + plat_ic_set_interrupt_pending(SPD_PNCD_NS_IRQ); + } + + SMC_RET0(handle); + + break; + + case SMC_YIELD: + assert(handle == cm_get_context(ns != 0 ? NON_SECURE : SECURE)); + handle = pncd_context_switch_to(ns != 0 ? SECURE : NON_SECURE); + + assert(handle != NULL); + + SMC_RET0(handle); + + break; + + default: + INFO("Unknown smc: %x\n", smc_fid); + break; + } + + return plat_pncd_smc_handler(smc_fid, x1, x2, x3, x4, + cookie, handle, flags); +} + +static uintptr_t pncd_smc_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + uintptr_t ret; + + /* SMC handling is serialized */ + spin_lock(&smc_handler_lock); + ret = pncd_smc_handler_unsafe(smc_fid, x1, x2, x3, x4, cookie, handle, + flags); + spin_unlock(&smc_handler_lock); + + return ret; +} + +/* Define a SPD runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + pncd_fast, + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_FAST, + pncd_setup, + pncd_smc_handler +); + +/* Define a SPD runtime service descriptor for standard SMC calls */ +DECLARE_RT_SVC( + pncd_std, + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_YIELD, + NULL, + pncd_smc_handler +); diff --git a/services/spd/pncd/pncd_private.h b/services/spd/pncd/pncd_private.h new file mode 100644 index 000000000..8c9b634d5 --- /dev/null +++ b/services/spd/pncd/pncd_private.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. + * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PNCD_PRIVATE_H__ +#define __PNCD_PRIVATE_H__ + +#ifndef __ASSEMBLER__ +#include <stdint.h> +#endif /* __ASSEMBLER __ */ + +#include <context.h> +#ifndef __ASSEMBLER__ +#include <lib/cassert.h> +#endif /* __ASSEMBLER __ */ + +#include <platform_def.h> + +/******************************************************************************* + * Constants that allow assembler code to preserve callee-saved registers of the + * C runtime context while performing a security state switch. + ******************************************************************************/ +#define PNCD_C_RT_CTX_X19 U(0x0) +#define PNCD_C_RT_CTX_X20 U(0x8) +#define PNCD_C_RT_CTX_X21 U(0x10) +#define PNCD_C_RT_CTX_X22 U(0x18) +#define PNCD_C_RT_CTX_X23 U(0x20) +#define PNCD_C_RT_CTX_X24 U(0x28) +#define PNCD_C_RT_CTX_X25 U(0x30) +#define PNCD_C_RT_CTX_X26 U(0x38) +#define PNCD_C_RT_CTX_X27 U(0x40) +#define PNCD_C_RT_CTX_X28 U(0x48) +#define PNCD_C_RT_CTX_X29 U(0x50) +#define PNCD_C_RT_CTX_X30 U(0x58) +#define PNCD_C_RT_CTX_SIZE U(0x60) +#define PNCD_C_RT_CTX_ENTRIES (PNCD_C_RT_CTX_SIZE >> DWORD_SHIFT) + +#ifndef __ASSEMBLER__ + +/* AArch64 callee saved general purpose register context structure. */ +DEFINE_REG_STRUCT(c_rt_regs, PNCD_C_RT_CTX_ENTRIES); + +/* + * Compile time assertion to ensure that both the compiler and linker + * have the same double word aligned view of the size of the C runtime + * register context. + */ +CASSERT(sizeof(c_rt_regs_t) == PNCD_C_RT_CTX_SIZE, + assert_spd_c_rt_regs_size_mismatch); + +/******************************************************************************* + * Structure which helps the SPD to maintain the per-cpu state of the SP. + * 'mpidr' - mpidr of the CPU running PNC + * 'c_rt_ctx' - stack address to restore C runtime context from after + * returning from a synchronous entry into the SP. + * 'cpu_ctx' - space to maintain SP architectural state + ******************************************************************************/ +typedef struct pnc_context { + uint64_t mpidr; + uint64_t c_rt_ctx; + cpu_context_t cpu_ctx; +} pnc_context_t; + +/******************************************************************************* + * Function & Data prototypes + ******************************************************************************/ +uint64_t pncd_enter_sp(uint64_t *c_rt_ctx); +void __dead2 pncd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); +uint64_t pncd_synchronous_sp_entry(pnc_context_t *pnc_ctx); +void __dead2 pncd_synchronous_sp_exit(pnc_context_t *pnc_ctx, uint64_t ret); +void pncd_init_pnc_ep_state(struct entry_point_info *pnc_ep, + uint64_t pc, + pnc_context_t *pnc_ctx); +#endif /* __ASSEMBLER__ */ + +#endif /* __PNCD_PRIVATE_H__ */ diff --git a/services/std_svc/drtm/drtm_dma_prot.c b/services/std_svc/drtm/drtm_dma_prot.c new file mode 100644 index 000000000..48317fdc4 --- /dev/null +++ b/services/std_svc/drtm/drtm_dma_prot.c @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * DRTM DMA protection. + * + * Authors: + * Lucian Paul-Trifu <lucian.paultrifu@gmail.com> + * + */ + +#include <stdint.h> +#include <string.h> + +#include <common/debug.h> +#include <drivers/arm/smmu_v3.h> +#include "drtm_dma_prot.h" +#include "drtm_main.h" +#include "drtm_remediation.h" +#include <plat/common/platform.h> +#include <smccc_helpers.h> + +/* + * ________________________ LAUNCH success ________________________ + * | Initial | -------------------> | Prot engaged | + * |````````````````````````| |````````````````````````| + * | request.type == NONE | | request.type != NONE | + * | | <------------------- | | + * `________________________' UNPROTECT_MEM `________________________' + * + * Transitions that are not shown correspond to ABI calls that do not change + * state and result in an error being returned to the caller. + */ +static struct dma_prot active_prot = { + .type = PROTECT_NONE, +}; + +/* Version-independent type. */ +typedef struct drtm_dl_dma_prot_args_v1 struct_drtm_dl_dma_prot_args; + +/* + * This function checks that platform supports complete DMA protection. + * and returns false - if the platform supports complete DMA protection. + * and returns true - if the platform does not support complete DMA protection. + */ +bool drtm_dma_prot_init(void) +{ + bool must_init_fail = false; + const uintptr_t *smmus; + size_t num_smmus = 0; + unsigned int total_smmus; + + /* Warns presence of non-host platforms */ + if (plat_has_non_host_platforms()) { + WARN("DRTM: the platform includes trusted DMA-capable devices" + " (non-host platforms)\n"); + } + + /* + * DLME protection is uncertain on platforms with peripherals whose + * DMA is not managed by an SMMU. DRTM doesn't work on such platforms. + */ + if (plat_has_unmanaged_dma_peripherals()) { + ERROR("DRTM: this platform does not provide DMA protection\n"); + must_init_fail = true; + } + + /* + * Check that the platform reported all SMMUs. + * It is acceptable if the platform doesn't have any SMMUs when it + * doesn't have any DMA-capable devices. + */ + total_smmus = plat_get_total_smmus(); + plat_enumerate_smmus(&smmus, &num_smmus); + if (num_smmus != total_smmus) { + ERROR("DRTM: could not discover all SMMUs\n"); + must_init_fail = true; + } + + return must_init_fail; +} + +/* + * Checks that the DMA protection arguments are valid and that the given + * protected regions are covered by DMA protection. + */ +enum drtm_retc drtm_dma_prot_check_args(const struct_drtm_dl_dma_prot_args *a, + int a_dma_prot_type, + drtm_mem_region_t p) +{ + switch ((enum dma_prot_type)a_dma_prot_type) { + case PROTECT_MEM_ALL: + if (a->dma_prot_table_paddr || a->dma_prot_table_size) { + ERROR("DRTM: invalid launch due to inconsistent" + " DMA protection arguments\n"); + return MEM_PROTECT_INVALID; + } + /* + * Full DMA protection ought to ensure that the DLME and NWd + * DCE regions are protected, no further checks required. + */ + return SUCCESS; + + default: + ERROR("DRTM: invalid launch due to unsupported DMA protection type\n"); + return MEM_PROTECT_INVALID; + } +} + +enum drtm_retc drtm_dma_prot_engage(const struct_drtm_dl_dma_prot_args *a, + int a_dma_prot_type) +{ + const uintptr_t *smmus; + size_t num_smmus = 0; + + if (active_prot.type != PROTECT_NONE) { + ERROR("DRTM: launch denied as previous DMA protection" + " is still engaged\n"); + return DENIED; + } + + if (a_dma_prot_type == PROTECT_NONE) { + return SUCCESS; + /* Only PROTECT_MEM_ALL is supported currently. */ + } else if (a_dma_prot_type != PROTECT_MEM_ALL) { + ERROR("%s(): unimplemented DMA protection type\n", __func__); + panic(); + } + + /* + * Engage SMMUs in accordance with the request we have previously received. + * Only PROTECT_MEM_ALL is implemented currently. + */ + plat_enumerate_smmus(&smmus, &num_smmus); + for (const uintptr_t *smmu = smmus; smmu < smmus+num_smmus; smmu++) { + /* + * TODO: Invalidate SMMU's Stage-1 and Stage-2 TLB entries. This ensures + * that any outstanding device transactions are completed, see Section + * 3.21.1, specification IHI_0070_C_a for an approximate reference. + */ + int rc = smmuv3_ns_set_abort_all(*smmu); + if (rc != 0) { + ERROR("DRTM: SMMU at PA 0x%lx failed to engage DMA protection" + " rc=%d\n", *smmu, rc); + return INTERNAL_ERROR; + } + } + + /* + * TODO: Restrict DMA from the GIC. + * + * Full DMA protection may be achieved as follows: + * + * With a GICv3: + * - Set GICR_CTLR.EnableLPIs to 0, for each GICR; + * GICR_CTLR.RWP == 0 must be the case before finishing, for each GICR. + * - Set GITS_CTLR.Enabled to 0; + * GITS_CTLR.Quiescent == 1 must be the case before finishing. + * + * In addition, with a GICv4: + * - Set GICR_VPENDBASER.Valid to 0, for each GICR; + * GICR_CTLR.RWP == 0 must be the case before finishing, for each GICR. + * + * Alternatively, e.g. if some bit values cannot be changed at runtime, + * this procedure should return an error if the LPI Pending and + * Configuration tables overlap the regions being protected. + */ + + active_prot.type = a_dma_prot_type; + + return SUCCESS; +} + +/* + * Undo what has previously been done in drtm_dma_prot_engage(), or enter + * remediation if it is not possible. + */ +enum drtm_retc drtm_dma_prot_disengage(void) +{ + const uintptr_t *smmus; + size_t num_smmus = 0; + const char *err_str = "cannot undo PROTECT_MEM_ALL SMMU config"; + + if (active_prot.type == PROTECT_NONE) { + return SUCCESS; + /* Only PROTECT_MEM_ALL is supported currently. */ + } else if (active_prot.type != PROTECT_MEM_ALL) { + ERROR("%s(): unimplemented DMA protection type\n", __func__); + panic(); + } + + /* + * For PROTECT_MEM_ALL, undo the SMMU configuration for "abort all" mode + * done during engage(). + */ + /* Simply enter remediation for now. */ + (void)smmus; + (void)num_smmus; + drtm_enter_remediation(1ULL, err_str); + + /* TODO: Undo GIC DMA restrictions. */ + + active_prot.type = PROTECT_NONE; + + return SUCCESS; +} + +uint64_t drtm_unprotect_mem(void *ctx) +{ + enum drtm_retc ret; + + switch (active_prot.type) { + case PROTECT_NONE: + ERROR("DRTM: invalid UNPROTECT_MEM, no DMA protection has" + " previously been engaged\n"); + ret = DENIED; + break; + + case PROTECT_MEM_ALL: + /* + * UNPROTECT_MEM is a no-op for PROTECT_MEM_ALL: DRTM must not touch + * the NS SMMU as it is expected that the DLME has configured it. + */ + active_prot.type = PROTECT_NONE; + + ret = SUCCESS; + break; + + default: + ret = drtm_dma_prot_disengage(); + break; + } + + SMC_RET1(ctx, ret); +} + +void drtm_dma_prot_serialise_table(uint8_t *dst, size_t *size_out) +{ + if (active_prot.type == PROTECT_NONE) { + return; + } else if (active_prot.type != PROTECT_MEM_ALL) { + ERROR("%s(): unimplemented DMA protection type\n", __func__); + panic(); + } + + struct __packed descr_table_1 { + drtm_memory_region_descriptor_table_t header; + drtm_mem_region_t regions[1]; + } prot_table = { + .header = { + .revision = 1, + .num_regions = sizeof(((struct descr_table_1 *)NULL)->regions) / + sizeof(((struct descr_table_1 *)NULL)->regions[0]) + }, + .regions = { + {.region_address = 0, PAGES_AND_TYPE(UINT64_MAX, 0x3)}, + } + }; + + memcpy(dst, &prot_table, sizeof(prot_table)); + *size_out = sizeof(prot_table); +} diff --git a/services/std_svc/drtm/drtm_dma_prot.h b/services/std_svc/drtm/drtm_dma_prot.h new file mode 100644 index 000000000..79dc9cb49 --- /dev/null +++ b/services/std_svc/drtm/drtm_dma_prot.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef DRTM_DMA_PROT_H +#define DRTM_DMA_PROT_H + +#include <stdint.h> +#include <plat/common/platform.h> +#include <services/drtm_svc.h> + +struct __packed drtm_dl_dma_prot_args_v1 { + uint64_t dma_prot_table_paddr; + uint64_t dma_prot_table_size; +}; + +/* Values for DRTM_PROTECT_MEMORY */ +enum dma_prot_type { + PROTECT_NONE = -1, + PROTECT_MEM_ALL = 0, + PROTECT_MEM_REGION = 2, +}; + +struct dma_prot { + enum dma_prot_type type; +}; + +#define DRTM_MEM_REGION_PAGES_AND_TYPE(pages, type) \ + (((uint64_t)(pages) & (((uint64_t)1 << 52) - 1)) \ + | (((uint64_t)(type) & 0x7) << 52)) + +#define PAGES_AND_TYPE(pages, type) \ + .region_size_type = DRTM_MEM_REGION_PAGES_AND_TYPE(pages, type) + +/* Opaque / encapsulated type. */ +typedef struct drtm_dl_dma_prot_args_v1 drtm_dl_dma_prot_args_v1_t; + +bool drtm_dma_prot_init(void); +enum drtm_retc drtm_dma_prot_check_args(const drtm_dl_dma_prot_args_v1_t *a, + int a_dma_prot_type, + drtm_mem_region_t p); +enum drtm_retc drtm_dma_prot_engage(const drtm_dl_dma_prot_args_v1_t *a, + int a_dma_prot_type); +enum drtm_retc drtm_dma_prot_disengage(void); +uint64_t drtm_unprotect_mem(void *ctx); +void drtm_dma_prot_serialise_table(uint8_t *dst, size_t *size_out); + +#endif /* DRTM_DMA_PROT_H */ diff --git a/services/std_svc/drtm/drtm_main.c b/services/std_svc/drtm/drtm_main.c new file mode 100644 index 000000000..3acf6838e --- /dev/null +++ b/services/std_svc/drtm/drtm_main.c @@ -0,0 +1,839 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * DRTM service + * + * Authors: + * Lucian Paul-Trifu <lucian.paultrifu@gmail.com> + * Brian Nezvadovitz <brinez@microsoft.com> 2021-02-01 + */ + +#include <stdint.h> + +#include <arch.h> +#include <arch_helpers.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <common/runtime_svc.h> +#include <drivers/auth/crypto_mod.h> +#include "drtm_main.h" +#include "drtm_measurements.h" +#include "drtm_remediation.h" +#include <lib/el3_runtime/context_mgmt.h> +#include <lib/psci/psci_lib.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> +#include <services/drtm_svc.h> +#include <services/sdei.h> +#include <platform_def.h> + +/* Structure to store DRTM features specific to the platform. */ +static drtm_features_t plat_drtm_features; + +/* DRTM-formatted memory map. */ +static drtm_memory_region_descriptor_table_t *plat_drtm_mem_map; + +/* DLME header */ +struct_dlme_data_header dlme_data_hdr_init; + +/* Minimum data memory requirement */ +uint64_t dlme_data_min_size; + +int drtm_setup(void) +{ + bool rc; + const plat_drtm_tpm_features_t *plat_tpm_feat; + const plat_drtm_dma_prot_features_t *plat_dma_prot_feat; + + INFO("DRTM service setup\n"); + + /* Read boot PE ID from MPIDR */ + plat_drtm_features.boot_pe_id = read_mpidr_el1() & MPIDR_AFFINITY_MASK; + + rc = drtm_dma_prot_init(); + if (rc) { + return INTERNAL_ERROR; + } + + /* + * initialise the platform supported crypto module that will + * be used by the DRTM-service to calculate hash of DRTM- + * implementation specific components + */ + crypto_mod_init(); + + /* Build DRTM-compatible address map. */ + plat_drtm_mem_map = drtm_build_address_map(); + if (plat_drtm_mem_map == NULL) { + return INTERNAL_ERROR; + } + + /* Get DRTM features from platform hooks. */ + plat_tpm_feat = plat_drtm_get_tpm_features(); + if (plat_tpm_feat == NULL) { + return INTERNAL_ERROR; + } + + plat_dma_prot_feat = plat_drtm_get_dma_prot_features(); + if (plat_dma_prot_feat == NULL) { + return INTERNAL_ERROR; + } + + /* + * Add up minimum DLME data memory. + * + * For systems with complete DMA protection there is only one entry in + * the protected regions table. + */ + if (plat_dma_prot_feat->dma_protection_support == + ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE) { + dlme_data_min_size = + sizeof(drtm_memory_region_descriptor_table_t) + + sizeof(drtm_mem_region_t); + dlme_data_hdr_init.dlme_prot_regions_size = dlme_data_min_size; + } else { + /* + * TODO set protected regions table size based on platform DMA + * protection configuration + */ + panic(); + } + + dlme_data_hdr_init.dlme_addr_map_size = drtm_get_address_map_size(); + dlme_data_hdr_init.dlme_tcb_hashes_table_size = + plat_drtm_get_tcb_hash_table_size(); + dlme_data_hdr_init.dlme_impdef_region_size = + plat_drtm_get_imp_def_dlme_region_size(); + + dlme_data_min_size += dlme_data_hdr_init.dlme_addr_map_size + + PLAT_DRTM_EVENT_LOG_MAX_SIZE + + dlme_data_hdr_init.dlme_tcb_hashes_table_size + + dlme_data_hdr_init.dlme_impdef_region_size; + + dlme_data_min_size = page_align(dlme_data_min_size, UP)/PAGE_SIZE; + + /* Fill out platform DRTM features structure */ + /* Only support default PCR schema (0x1) in this implementation. */ + ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(plat_drtm_features.tpm_features, + ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT); + ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(plat_drtm_features.tpm_features, + plat_tpm_feat->tpm_based_hash_support); + ARM_DRTM_TPM_FEATURES_SET_FW_HASH(plat_drtm_features.tpm_features, + plat_tpm_feat->firmware_hash_algorithm); + ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(plat_drtm_features.minimum_memory_requirement, + dlme_data_min_size); + ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(plat_drtm_features.minimum_memory_requirement, + plat_drtm_get_min_size_normal_world_dce()); + ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(plat_drtm_features.dma_prot_features, + plat_dma_prot_feat->max_num_mem_prot_regions); + ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(plat_drtm_features.dma_prot_features, + plat_dma_prot_feat->dma_protection_support); + ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(plat_drtm_features.tcb_hash_features, + plat_drtm_get_tcb_hash_features()); + + return 0; +} + +static inline void invalidate_icache_all(void) +{ + __asm__ volatile("ic ialluis"); + dsb(); + isb(); +} + +static inline uint64_t drtm_features_tpm(void *ctx) +{ + SMC_RET2(ctx, 1ULL, /* TPM feature is supported */ + plat_drtm_features.tpm_features); +} + +static inline uint64_t drtm_features_mem_req(void *ctx) +{ + SMC_RET2(ctx, 1ULL, /* memory req Feature is supported */ + plat_drtm_features.minimum_memory_requirement); +} + +static inline uint64_t drtm_features_boot_pe_id(void *ctx) +{ + SMC_RET2(ctx, 1ULL, /* Boot PE feature is supported */ + plat_drtm_features.boot_pe_id); +} + +static inline uint64_t drtm_features_dma_prot(void *ctx) +{ + SMC_RET2(ctx, 1ULL, /* DMA protection feature is supported */ + plat_drtm_features.dma_prot_features); +} + +static inline uint64_t drtm_features_tcb_hashes(void *ctx) +{ + SMC_RET2(ctx, 1ULL, /* TCB hash feature is supported */ + plat_drtm_features.tcb_hash_features); +} + +static enum drtm_retc drtm_dl_check_caller_el(void *ctx) +{ + uint64_t spsr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3); + uint64_t dl_caller_el; + uint64_t dl_caller_aarch; + + dl_caller_el = spsr_el3 >> MODE_EL_SHIFT & MODE_EL_MASK; + dl_caller_aarch = spsr_el3 >> MODE_RW_SHIFT & MODE_RW_MASK; + + /* Caller's security state is checked from drtm_smc_handle function */ + + /* Caller can be NS-EL2/EL1 */ + if (dl_caller_el == MODE_EL3) { + ERROR("DRTM: invalid launch from EL3\n"); + return DENIED; + } + + if (dl_caller_aarch != MODE_RW_64) { + ERROR("DRTM: invalid launch from non-AArch64 execution state\n"); + return DENIED; + } + + return SUCCESS; +} + +static enum drtm_retc drtm_dl_check_cores(void) +{ + bool running_on_single_core; + uint64_t this_pe_aff_value = read_mpidr_el1() & MPIDR_AFFINITY_MASK; + + if (this_pe_aff_value != plat_drtm_features.boot_pe_id) { + ERROR("DRTM: invalid launch on a non-boot PE\n"); + return DENIED; + } + + running_on_single_core = psci_is_last_on_cpu_safe(); + if (!running_on_single_core) { + ERROR("DRTM: invalid launch due to non-boot PE not being turned off\n"); + return DENIED; + } + + return SUCCESS; +} + +static enum drtm_retc drtm_dl_prepare_dlme_data(const struct_drtm_dl_args *args) +{ + int rc; + uint64_t dlme_data_paddr; + size_t dlme_data_max_size; + uintptr_t dlme_data_mapping; + struct_dlme_data_header *dlme_data_hdr; + uint8_t *dlme_data_cursor; + size_t dlme_data_mapping_bytes; + size_t serialised_bytes_actual; + + dlme_data_paddr = args->dlme_paddr + args->dlme_data_off; + dlme_data_max_size = args->dlme_size - args->dlme_data_off; + + /* + * The capacity of the given DLME data region is checked when + * the other dynamic launch arguments are. + */ + if (dlme_data_max_size < dlme_data_min_size) { + ERROR("%s: assertion failed:" + " dlme_data_max_size (%ld) < dlme_data_total_bytes_req (%ld)\n", + __func__, dlme_data_max_size, dlme_data_min_size); + panic(); + } + + /* Map the DLME data region as NS memory. */ + dlme_data_mapping_bytes = ALIGNED_UP(dlme_data_max_size, DRTM_PAGE_SIZE); + rc = mmap_add_dynamic_region_alloc_va(dlme_data_paddr, + &dlme_data_mapping, + dlme_data_mapping_bytes, + MT_RW_DATA | MT_NS | + MT_SHAREABILITY_ISH); + if (rc != 0) { + WARN("DRTM: %s: mmap_add_dynamic_region() failed rc=%d\n", + __func__, rc); + return INTERNAL_ERROR; + } + dlme_data_hdr = (struct_dlme_data_header *)dlme_data_mapping; + dlme_data_cursor = (uint8_t *)dlme_data_hdr + sizeof(*dlme_data_hdr); + + memcpy(dlme_data_hdr, (const void *)&dlme_data_hdr_init, + sizeof(*dlme_data_hdr)); + + /* Set the header version and size. */ + dlme_data_hdr->version = 1; + dlme_data_hdr->this_hdr_size = sizeof(*dlme_data_hdr); + + /* Prepare DLME protected regions. */ + drtm_dma_prot_serialise_table(dlme_data_cursor, + &serialised_bytes_actual); + assert(serialised_bytes_actual == + dlme_data_hdr->dlme_prot_regions_size); + dlme_data_cursor += serialised_bytes_actual; + + /* Prepare DLME address map. */ + if (plat_drtm_mem_map != NULL) { + memcpy(dlme_data_cursor, plat_drtm_mem_map, + dlme_data_hdr->dlme_addr_map_size); + } else { + WARN("DRTM: DLME address map is not in the cache\n"); + } + dlme_data_cursor += dlme_data_hdr->dlme_addr_map_size; + + /* Prepare DRTM event log for DLME. */ + drtm_serialise_event_log(dlme_data_cursor, &serialised_bytes_actual); + assert(serialised_bytes_actual <= PLAT_DRTM_EVENT_LOG_MAX_SIZE); + dlme_data_hdr->dlme_tpm_log_size = serialised_bytes_actual; + dlme_data_cursor += serialised_bytes_actual; + + /* + * TODO: Prepare the TCB hashes for DLME, currently its size + * 0 + */ + dlme_data_cursor += dlme_data_hdr->dlme_tcb_hashes_table_size; + + /* Implementation-specific region size is unused. */ + dlme_data_cursor += dlme_data_hdr->dlme_impdef_region_size; + + /* + * Prepare DLME data size, includes all data region referenced above + * alongwith the DLME data header + */ + dlme_data_hdr->dlme_data_size = dlme_data_cursor - (uint8_t *)dlme_data_hdr; + + /* Unmap the DLME data region. */ + rc = mmap_remove_dynamic_region(dlme_data_mapping, dlme_data_mapping_bytes); + if (rc != 0) { + ERROR("%s(): mmap_remove_dynamic_region() failed" + " unexpectedly rc=%d\n", __func__, rc); + panic(); + } + + return SUCCESS; +} + +/* + * Note: accesses to the dynamic launch args, and to the DLME data are + * little-endian as required, thanks to TF-A BL31 init requirements. + */ +static enum drtm_retc drtm_dl_check_args(uint64_t x1, + struct_drtm_dl_args *a_out) +{ + uint64_t dlme_start, dlme_end; + uint64_t dlme_img_start, dlme_img_ep, dlme_img_end; + uint64_t dlme_data_start, dlme_data_end; + uintptr_t va_mapping; + size_t va_mapping_size; + struct_drtm_dl_args *a; + struct_drtm_dl_args args_buf; + int rc; + + if (x1 % DRTM_PAGE_SIZE != 0) { + ERROR("DRTM: parameters structure is not " + DRTM_PAGE_SIZE_STR "-aligned\n"); + return INVALID_PARAMETERS; + } + + va_mapping_size = ALIGNED_UP(sizeof(struct_drtm_dl_args), DRTM_PAGE_SIZE); + + /* check DRTM parameters are within NS address region */ + rc = plat_drtm_validate_ns_region(x1, va_mapping_size); + if (rc != 0) { + ERROR("DRTM: parameters lies within secure memory\n"); + return INVALID_PARAMETERS; + } + + rc = mmap_add_dynamic_region_alloc_va(x1, &va_mapping, va_mapping_size, + MT_MEMORY | MT_NS | MT_RO | + MT_SHAREABILITY_ISH); + if (rc != 0) { + WARN("DRTM: %s: mmap_add_dynamic_region() failed rc=%d\n", + __func__, rc); + return INTERNAL_ERROR; + } + a = (struct_drtm_dl_args *)va_mapping; + + /* Sanitize cache of data passed in args by the DCE Preamble. */ + flush_dcache_range(va_mapping, va_mapping_size); + + args_buf = *a; + + rc = mmap_remove_dynamic_region(va_mapping, va_mapping_size); + if (rc) { + ERROR("%s(): mmap_remove_dynamic_region() failed unexpectedly" + " rc=%d\n", __func__, rc); + panic(); + } + a = &args_buf; + + if (!((a->version >= ARM_DRTM_PARAMS_MIN_VERSION) && + (a->version <= ARM_DRTM_PARAMS_MAX_VERSION))) { + ERROR("DRTM: parameters structure version %u is unsupported\n", + a->version); + return NOT_SUPPORTED; + } + + if (!(a->dlme_img_off < a->dlme_size && + a->dlme_data_off < a->dlme_size)) { + ERROR("DRTM: argument offset is outside of the DLME region\n"); + return INVALID_PARAMETERS; + } + dlme_start = a->dlme_paddr; + dlme_end = a->dlme_paddr + a->dlme_size; + dlme_img_start = a->dlme_paddr + a->dlme_img_off; + dlme_img_ep = dlme_img_start + a->dlme_img_ep_off; + dlme_img_end = dlme_img_start + a->dlme_img_size; + dlme_data_start = a->dlme_paddr + a->dlme_data_off; + dlme_data_end = dlme_end; + + /* Check the DLME regions arguments. */ + if ((dlme_start % DRTM_PAGE_SIZE) != 0) { + ERROR("DRTM: argument DLME region is not " + DRTM_PAGE_SIZE_STR "-aligned\n"); + return INVALID_PARAMETERS; + } + + if (!(dlme_start < dlme_end && + dlme_start <= dlme_img_start && dlme_img_start < dlme_img_end && + dlme_start <= dlme_data_start && dlme_data_start < dlme_data_end)) { + ERROR("DRTM: argument DLME region is discontiguous\n"); + return INVALID_PARAMETERS; + } + + if (dlme_img_start < dlme_data_end && dlme_data_start < dlme_img_end) { + ERROR("DRTM: argument DLME regions overlap\n"); + return INVALID_PARAMETERS; + } + + /* Check the DLME image region arguments. */ + if ((dlme_img_start % DRTM_PAGE_SIZE) != 0) { + ERROR("DRTM: argument DLME image region is not " + DRTM_PAGE_SIZE_STR "-aligned\n"); + return INVALID_PARAMETERS; + } + + if (!(dlme_img_start <= dlme_img_ep && dlme_img_ep < dlme_img_end)) { + ERROR("DRTM: DLME entry point is outside of the DLME image region\n"); + return INVALID_PARAMETERS; + } + + if ((dlme_img_ep % 4) != 0) { + ERROR("DRTM: DLME image entry point is not 4-byte-aligned\n"); + return INVALID_PARAMETERS; + } + + /* Check the DLME data region arguments. */ + if ((dlme_data_start % DRTM_PAGE_SIZE) != 0) { + ERROR("DRTM: argument DLME data region is not " + DRTM_PAGE_SIZE_STR "-aligned\n"); + return INVALID_PARAMETERS; + } + + if (dlme_data_end - dlme_data_start < dlme_data_min_size) { + ERROR("DRTM: argument DLME data region is short of %lu bytes\n", + dlme_data_min_size - (size_t)(dlme_data_end - dlme_data_start)); + return INVALID_PARAMETERS; + } + + /* check DLME region (paddr + size) is within a NS address region */ + rc = plat_drtm_validate_ns_region(dlme_start, (size_t)a->dlme_size); + if (rc != 0) { + ERROR("DRTM: DLME region lies within secure memory\n"); + return INVALID_PARAMETERS; + } + + /* Check the Normal World DCE region arguments. */ + if (a->dce_nwd_paddr != 0) { + uint32_t dce_nwd_start = a->dce_nwd_paddr; + uint32_t dce_nwd_end = dce_nwd_start + a->dce_nwd_size; + + if (!(dce_nwd_start < dce_nwd_end)) { + ERROR("DRTM: argument Normal World DCE region is dicontiguous\n"); + return INVALID_PARAMETERS; + } + + if (dce_nwd_start < dlme_end && dlme_start < dce_nwd_end) { + ERROR("DRTM: argument Normal World DCE regions overlap\n"); + return INVALID_PARAMETERS; + } + } + + /* + * Map and sanitize the cache of data range passed by DCE Preamble. This + * is required to avoid / defend against racing with cache evictions + */ + va_mapping_size = ALIGNED_UP((dlme_end - dlme_start), DRTM_PAGE_SIZE); + rc = mmap_add_dynamic_region_alloc_va(dlme_img_start, &va_mapping, va_mapping_size, + MT_MEMORY | MT_NS | MT_RO | + MT_SHAREABILITY_ISH); + if (rc != 0) { + ERROR("DRTM: %s: mmap_add_dynamic_region_alloc_va() failed rc=%d\n", + __func__, rc); + return INTERNAL_ERROR; + } + flush_dcache_range(va_mapping, va_mapping_size); + + rc = mmap_remove_dynamic_region(va_mapping, va_mapping_size); + if (rc) { + ERROR("%s(): mmap_remove_dynamic_region() failed unexpectedly" + " rc=%d\n", __func__, rc); + panic(); + } + + *a_out = *a; + return SUCCESS; +} + +static void drtm_dl_reset_dlme_el_state(enum drtm_dlme_el dlme_el) +{ + uint64_t sctlr; + + /* + * TODO: Set PE state according to the PSCI's specification of the initial + * state after CPU_ON, or to reset values if unspecified, where they exist, + * or define sensible values otherwise. + */ + + switch (dlme_el) { + case DLME_AT_EL1: + sctlr = read_sctlr_el1(); + break; + + case DLME_AT_EL2: + sctlr = read_sctlr_el2(); + break; + + default: /* Not reached */ + ERROR("%s(): dlme_el has the unexpected value %d\n", + __func__, dlme_el); + panic(); + } + + sctlr &= ~(/* Disable DLME's EL MMU, since the existing page-tables are untrusted. */ + SCTLR_M_BIT + | SCTLR_EE_BIT /* Little-endian data accesses. */ + ); + + sctlr |= SCTLR_C_BIT | SCTLR_I_BIT; /* Allow instruction and data caching. */ + + switch (dlme_el) { + case DLME_AT_EL1: + write_sctlr_el1(sctlr); + break; + + case DLME_AT_EL2: + write_sctlr_el2(sctlr); + break; + } +} + +static void drtm_dl_reset_dlme_context(enum drtm_dlme_el dlme_el) +{ + void *ns_ctx = cm_get_context(NON_SECURE); + gp_regs_t *gpregs = get_gpregs_ctx(ns_ctx); + uint64_t spsr_el3 = read_ctx_reg(get_el3state_ctx(ns_ctx), CTX_SPSR_EL3); + + /* Reset all gpregs, including SP_EL0. */ + memset(gpregs, 0, sizeof(*gpregs)); + + /* Reset SP_ELx. */ + switch (dlme_el) { + case DLME_AT_EL1: + write_sp_el1(0); + break; + + case DLME_AT_EL2: + write_sp_el2(0); + break; + } + + /* + * DLME's async exceptions are masked to avoid a NWd attacker's timed + * interference with any state we established trust in or measured. + */ + spsr_el3 |= SPSR_DAIF_MASK << SPSR_DAIF_SHIFT; + + write_ctx_reg(get_el3state_ctx(ns_ctx), CTX_SPSR_EL3, spsr_el3); +} + +static void drtm_dl_prepare_eret_to_dlme(const struct_drtm_dl_args *args, enum drtm_dlme_el dlme_el) +{ + void *ctx = cm_get_context(NON_SECURE); + uint64_t dlme_ep = DL_ARGS_GET_DLME_ENTRY_POINT(args); + uint64_t spsr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3); + + /* Next ERET is to the DLME's EL. */ + spsr_el3 &= ~(MODE_EL_MASK << MODE_EL_SHIFT); + switch (dlme_el) { + case DLME_AT_EL1: + spsr_el3 |= MODE_EL1 << MODE_EL_SHIFT; + break; + + case DLME_AT_EL2: + spsr_el3 |= MODE_EL2 << MODE_EL_SHIFT; + break; + } + + /* Next ERET is to the DLME entry point. */ + cm_set_elr_spsr_el3(NON_SECURE, dlme_ep, spsr_el3); +} + +static uint64_t drtm_dynamic_launch(uint64_t x1, void *handle) +{ + enum drtm_retc ret = SUCCESS; + enum drtm_retc dma_prot_ret; + struct_drtm_dl_args args; + /* DLME should be highest NS exception level */ + enum drtm_dlme_el dlme_el = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; + + /* Ensure that only boot PE is powered on */ + ret = drtm_dl_check_cores(); + if (ret != SUCCESS) { + SMC_RET1(handle, ret); + } + + /* + * Ensure that execution state is AArch64 and the caller + * is highest non-secure exception level + */ + ret = drtm_dl_check_caller_el(handle); + if (ret != SUCCESS) { + SMC_RET1(handle, ret); + } + + ret = drtm_dl_check_args(x1, &args); + if (ret != SUCCESS) { + SMC_RET1(handle, ret); + } + + /* Ensure that there are no SDEI event registered */ +#if SDEI_SUPPORT + if (sdei_get_registered_event_count() != 0) { + SMC_RET1(handle, DENIED); + } +#endif /* SDEI_SUPPORT */ + + /* + * Engage the DMA protections. The launch cannot proceed without the DMA + * protections due to potential TOC/TOU vulnerabilities w.r.t. the DLME + * region (and to the NWd DCE region). + */ + ret = drtm_dma_prot_engage(&args.dma_prot_args, + DL_ARGS_GET_DMA_PROT_TYPE(&args)); + if (ret != SUCCESS) { + SMC_RET1(handle, ret); + } + + /* + * The DMA protection is now engaged. Note that any failure mode that + * returns an error to the DRTM-launch caller must now disengage DMA + * protections before returning to the caller. + */ + + ret = drtm_take_measurements(&args); + if (ret != SUCCESS) { + goto err_undo_dma_prot; + } + + ret = drtm_dl_prepare_dlme_data(&args); + if (ret != SUCCESS) { + goto err_undo_dma_prot; + } + + /* + * Note that, at the time of writing, the DRTM spec allows a successful + * launch from NS-EL1 to return to a DLME in NS-EL2. The practical risk + * of a privilege escalation, e.g. due to a compromised hypervisor, is + * considered small enough not to warrant the specification of additional + * DRTM conduits that would be necessary to maintain OSs' abstraction from + * the presence of EL2 were the dynamic launch only be allowed from the + * highest NS EL. + */ + + dlme_el = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; + + drtm_dl_reset_dlme_el_state(dlme_el); + drtm_dl_reset_dlme_context(dlme_el); + + drtm_dl_prepare_eret_to_dlme(&args, dlme_el); + + /* + * As per DRTM beta0 spec table #28 invalidate the instruction cache + * before jumping to the DLME. This is required to defend against + * potentially-malicious cache contents. + */ + invalidate_icache_all(); + + /* Return the DLME region's address in x0, and the DLME data offset in x1.*/ + SMC_RET2(handle, args.dlme_paddr, args.dlme_data_off); + +err_undo_dma_prot: + dma_prot_ret = drtm_dma_prot_disengage(); + if (dma_prot_ret != SUCCESS) { + ERROR("%s(): drtm_dma_prot_disengage() failed unexpectedly" + " rc=%d\n", __func__, ret); + panic(); + } + + SMC_RET1(handle, ret); +} + +uint64_t drtm_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + /* Check that the SMC call is from the Normal World. */ + if (!is_caller_non_secure(flags)) { + SMC_RET1(handle, NOT_SUPPORTED); + } + + switch (smc_fid) { + case ARM_DRTM_SVC_VERSION: + INFO("DRTM service handler: version\n"); + /* Return the version of current implementation */ + SMC_RET1(handle, ARM_DRTM_VERSION); + break; /* not reached */ + + case ARM_DRTM_SVC_FEATURES: + if (((x1 >> ARM_DRTM_FUNC_SHIFT) & ARM_DRTM_FUNC_MASK) == + ARM_DRTM_FUNC_ID) { + /* Dispatch function-based queries. */ + switch (x1 & FUNCID_MASK) { + case ARM_DRTM_SVC_VERSION: + SMC_RET1(handle, SUCCESS); + break; /* not reached */ + + case ARM_DRTM_SVC_FEATURES: + SMC_RET1(handle, SUCCESS); + break; /* not reached */ + + case ARM_DRTM_SVC_UNPROTECT_MEM: + SMC_RET1(handle, SUCCESS); + break; /* not reached */ + + case ARM_DRTM_SVC_DYNAMIC_LAUNCH: + SMC_RET1(handle, SUCCESS); + break; /* not reached */ + + case ARM_DRTM_SVC_CLOSE_LOCALITY: + WARN("ARM_DRTM_SVC_CLOSE_LOCALITY feature %s", + "is not supported\n"); + SMC_RET1(handle, NOT_SUPPORTED); + break; /* not reached */ + + case ARM_DRTM_SVC_GET_ERROR: + SMC_RET1(handle, SUCCESS); + break; /* not reached */ + + case ARM_DRTM_SVC_SET_ERROR: + SMC_RET1(handle, SUCCESS); + break; /* not reached */ + + case ARM_DRTM_SVC_SET_TCB_HASH: + WARN("ARM_DRTM_SVC_TCB_HASH feature %s", + "is not supported\n"); + SMC_RET1(handle, NOT_SUPPORTED); + break; /* not reached */ + + case ARM_DRTM_SVC_LOCK_TCB_HASH: + WARN("ARM_DRTM_SVC_LOCK_TCB_HASH feature %s", + "is not supported\n"); + SMC_RET1(handle, NOT_SUPPORTED); + break; /* not reached */ + + default: + ERROR("Unknown DRTM service function\n"); + SMC_RET1(handle, NOT_SUPPORTED); + break; /* not reached */ + } + } else { + /* Dispatch feature-based queries. */ + switch (x1 & ARM_DRTM_FEAT_ID_MASK) { + case ARM_DRTM_FEATURES_TPM: + INFO("++ DRTM service handler: TPM features\n"); + return drtm_features_tpm(handle); + break; /* not reached */ + + case ARM_DRTM_FEATURES_MEM_REQ: + INFO("++ DRTM service handler: Min. mem." + " requirement features\n"); + return drtm_features_mem_req(handle); + break; /* not reached */ + + case ARM_DRTM_FEATURES_DMA_PROT: + INFO("++ DRTM service handler: " + "DMA protection features\n"); + return drtm_features_dma_prot(handle); + break; /* not reached */ + + case ARM_DRTM_FEATURES_BOOT_PE_ID: + INFO("++ DRTM service handler: " + "Boot PE ID features\n"); + return drtm_features_boot_pe_id(handle); + break; /* not reached */ + + case ARM_DRTM_FEATURES_TCB_HASHES: + INFO("++ DRTM service handler: " + "TCB-hashes features\n"); + return drtm_features_tcb_hashes(handle); + break; /* not reached */ + + default: + ERROR("Unknown ARM DRTM service feature\n"); + SMC_RET1(handle, NOT_SUPPORTED); + break; /* not reached */ + } + } + + case ARM_DRTM_SVC_UNPROTECT_MEM: + INFO("DRTM service handler: unprotect mem\n"); + return drtm_unprotect_mem(handle); + break; /* not reached */ + + case ARM_DRTM_SVC_DYNAMIC_LAUNCH: + INFO("DRTM service handler: dynamic launch\n"); + return drtm_dynamic_launch(x1, handle); + break; /* not reached */ + + case ARM_DRTM_SVC_CLOSE_LOCALITY: + WARN("DRTM service handler: close locality %s\n", + "is not supported"); + SMC_RET1(handle, NOT_SUPPORTED); + break; /* not reached */ + + case ARM_DRTM_SVC_GET_ERROR: + INFO("DRTM service handler: get error\n"); + drtm_get_error(handle); + break; /* not reached */ + + case ARM_DRTM_SVC_SET_ERROR: + INFO("DRTM service handler: set error\n"); + drtm_set_error(x1, handle); + break; /* not reached */ + + case ARM_DRTM_SVC_SET_TCB_HASH: + WARN("DRTM service handler: set TCB hash %s\n", + "is not supported"); + SMC_RET1(handle, NOT_SUPPORTED); + break; /* not reached */ + + case ARM_DRTM_SVC_LOCK_TCB_HASH: + WARN("DRTM service handler: lock TCB hash %s\n", + "is not supported"); + SMC_RET1(handle, NOT_SUPPORTED); + break; /* not reached */ + + default: + ERROR("Unknown DRTM service function: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); + break; /* not reached */ + } + + /* not reached */ + SMC_RET1(handle, SMC_UNK); +} diff --git a/services/std_svc/drtm/drtm_main.h b/services/std_svc/drtm/drtm_main.h new file mode 100644 index 000000000..60051632e --- /dev/null +++ b/services/std_svc/drtm/drtm_main.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef DRTM_MAIN_H +#define DRTM_MAIN_H + +#include <stdint.h> + +#include <assert.h> +#include <lib/smccc.h> + +#include "drtm_dma_prot.h" + +#define ALIGNED_UP(x, a) __extension__ ({ \ + __typeof__(a) _a = (a); \ + __typeof__(a) _one = 1; \ + assert(IS_POWER_OF_TWO(_a)); \ + ((x) + (_a - _one)) & ~(_a - _one); \ +}) + +#define ALIGNED_DOWN(x, a) __extension__ ({ \ + __typeof__(a) _a = (a); \ + __typeof__(a) _one = 1; \ + assert(IS_POWER_OF_TWO(_a)); \ + (x) & ~(_a - _one); \ +}) + +#define DRTM_PAGE_SIZE (4 * (1 << 10)) +#define DRTM_PAGE_SIZE_STR "4-KiB" + +#define DL_ARGS_GET_DMA_PROT_TYPE(a) (((a)->features >> 3) & 0x7U) +#define DL_ARGS_GET_PCR_SCHEMA(a) (((a)->features >> 1) & 0x3U) +#define DL_ARGS_GET_DLME_ENTRY_POINT(a) \ + (((a)->dlme_paddr + (a)->dlme_img_off + (a)->dlme_img_ep_off)) + +/* + * Range(Min/Max) of DRTM parameter structure versions supported + */ +#define ARM_DRTM_PARAMS_MIN_VERSION U(1) +#define ARM_DRTM_PARAMS_MAX_VERSION U(1) + +enum drtm_dlme_el { + DLME_AT_EL1 = MODE_EL1, + DLME_AT_EL2 = MODE_EL2 +}; + +enum drtm_retc { + SUCCESS = SMC_OK, + NOT_SUPPORTED = SMC_UNK, + INVALID_PARAMETERS = -2, + DENIED = -3, + NOT_FOUND = -4, + INTERNAL_ERROR = -5, + MEM_PROTECT_INVALID = -6, +}; + +typedef struct { + uint64_t tpm_features; + uint64_t minimum_memory_requirement; + uint64_t dma_prot_features; + uint64_t boot_pe_id; + uint64_t tcb_hash_features; +} drtm_features_t; + +struct __packed drtm_dl_args_v1 { + uint16_t version; /* Must be 1. */ + uint8_t __res[2]; + uint32_t features; + uint64_t dlme_paddr; + uint64_t dlme_size; + uint64_t dlme_img_off; + uint64_t dlme_img_ep_off; + uint64_t dlme_img_size; + uint64_t dlme_data_off; + uint64_t dce_nwd_paddr; + uint64_t dce_nwd_size; + drtm_dl_dma_prot_args_v1_t dma_prot_args; +} __aligned(__alignof(uint16_t /* First member's type, `uint16_t version' */)); + +struct __packed dlme_data_header_v1 { + uint16_t version; /* Must be 1. */ + uint16_t this_hdr_size; + uint8_t __res[4]; + uint64_t dlme_data_size; + uint64_t dlme_prot_regions_size; + uint64_t dlme_addr_map_size; + uint64_t dlme_tpm_log_size; + uint64_t dlme_tcb_hashes_table_size; + uint64_t dlme_impdef_region_size; +} __aligned(__alignof(uint16_t /* First member's type, `uint16_t version'. */)); + +typedef struct dlme_data_header_v1 struct_dlme_data_header; + +drtm_memory_region_descriptor_table_t *drtm_build_address_map(void); +uint64_t drtm_get_address_map_size(void); + +/* + * Version-independent type. May be used to avoid excessive line of code + * changes when migrating to new struct versions. + */ +typedef struct drtm_dl_args_v1 struct_drtm_dl_args; + +#endif /* DRTM_MAIN_H */ diff --git a/services/std_svc/drtm/drtm_measurements.c b/services/std_svc/drtm/drtm_measurements.c new file mode 100644 index 000000000..a8f2b3267 --- /dev/null +++ b/services/std_svc/drtm/drtm_measurements.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * DRTM measurements into TPM PCRs. + * + * Authors: + * Lucian Paul-Trifu <lucian.paultrifu@gmail.com> + * + */ +#include <assert.h> + +#include <common/debug.h> +#include <drivers/auth/crypto_mod.h> +#include <drivers/measured_boot/event_log/event_log.h> +#include "drtm_main.h" +#include "drtm_measurements.h" +#include <lib/xlat_tables/xlat_tables_v2.h> + +/* Event Log buffer */ +static uint8_t drtm_event_log[PLAT_DRTM_EVENT_LOG_MAX_SIZE]; + +/* + * Calculate and write hash of various payloads as per DRTM specification + * to Event Log. + * + * @param[in] data_base Address of data + * @param[in] data_size Size of data + * @param[in] event_type Type of Event + * @param[in] event_name Name of the Event + * @return: + * 0 = success + * < 0 = error + */ +static int drtm_event_log_measure_and_record(uintptr_t data_base, + uint32_t data_size, + uint32_t event_type, + const char *event_name, + unsigned int pcr) +{ + int rc; + unsigned char hash_data[CRYPTO_MD_MAX_SIZE]; + event_log_metadata_t metadata = {0}; + + metadata.name = event_name; + metadata.pcr = pcr; + + /* + * Measure the payloads requested by D-CRTM and DCE commponents + * Hash algorithm decided by the Event Log driver at build-time + */ + rc = event_log_measure(data_base, data_size, hash_data); + if (rc != 0) { + return rc; + } + + /* Record the mesasurement in the EventLog buffer */ + event_log_record(hash_data, event_type, &metadata); + + return 0; +} + +/* + * Initialise Event Log global variables, used during the recording + * of various payload measurements into the Event Log buffer + * + * @param[in] event_log_start Base address of Event Log buffer + * @param[in] event_log_finish End address of Event Log buffer, + * it is a first byte past end of the + * buffer + */ +static void drtm_event_log_init(uint8_t *event_log_start, + uint8_t *event_log_finish) +{ + event_log_buf_init(event_log_start, event_log_finish); + event_log_write_specid_event(); +} + +enum drtm_retc drtm_take_measurements(const struct_drtm_dl_args *a) +{ + int rc; + uintptr_t dlme_img_mapping; + uint64_t dlme_img_ep; + size_t dlme_img_mapping_bytes; + uint8_t drtm_null_data = 0U; + uint8_t pcr_schema = DL_ARGS_GET_PCR_SCHEMA(a); + const char *drtm_event_arm_sep_data = "ARM_DRTM"; + + /* Initialise the EventLog driver */ + drtm_event_log_init(drtm_event_log, drtm_event_log + + sizeof(drtm_event_log)); + + /** + * Measurements extended into PCR-17. + * + * PCR-17: Measure the DCE image. Extend digest of (char)0 into PCR-17 + * since the D-CRTM and the DCE are not separate. + */ + rc = drtm_event_log_measure_and_record((uintptr_t)&drtm_null_data, + sizeof(drtm_null_data), + DRTM_EVENT_ARM_DCE, NULL, + PCR_17); + CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_DCE)); + + /* PCR-17: Measure the PCR schema DRTM launch argument. */ + rc = drtm_event_log_measure_and_record((uintptr_t)&pcr_schema, + sizeof(pcr_schema), + DRTM_EVENT_ARM_PCR_SCHEMA, + NULL, PCR_17); + CHECK_RC(rc, + drtm_event_log_measure_and_record(DRTM_EVENT_ARM_PCR_SCHEMA)); + + /* PCR-17: Measure the enable state of external-debug, and trace. */ + /* + * TODO: Measure the enable state of external-debug and trace. This should + * be returned through a platform-specific hook. + */ + + /* PCR-17: Measure the security lifecycle state. */ + /* + * TODO: Measure the security lifecycle state. This is an implementation- + * defined value, retrieved through an implementation-defined mechanisms. + */ + + /* + * PCR-17: Optionally measure the NWd DCE. + * It is expected that such subsequent DCE stages are signed and verified. + * Whether they are measured in addition to signing is implementation + * -defined. + * Here the choice is to not measure any NWd DCE, in favour of PCR value + * resilience to any NWd DCE updates. + */ + + /* PCR-17: End of DCE measurements. */ + rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data, + strlen(drtm_event_arm_sep_data), + DRTM_EVENT_ARM_SEPARATOR, NULL, + PCR_17); + CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR)); + + /** + * Measurements extended into PCR-18. + * + * PCR-18: Measure the PCR schema DRTM launch argument. + */ + rc = drtm_event_log_measure_and_record((uintptr_t)&pcr_schema, + sizeof(pcr_schema), + DRTM_EVENT_ARM_PCR_SCHEMA, + NULL, PCR_18); + CHECK_RC(rc, + drtm_event_log_measure_and_record(DRTM_EVENT_ARM_PCR_SCHEMA)); + + /* + * PCR-18: Measure the public key used to verify DCE image(s) signatures. + * Extend digest of (char)0, since we do not expect the NWd DCE to be + * present. + */ + assert(a->dce_nwd_size == 0); + rc = drtm_event_log_measure_and_record((uintptr_t)&drtm_null_data, + sizeof(drtm_null_data), + DRTM_EVENT_ARM_DCE_PUBKEY, + NULL, PCR_18); + CHECK_RC(rc, + drtm_event_log_measure_and_record(DRTM_EVENT_ARM_DCE_PUBKEY)); + + /* PCR-18: Measure the DLME image. */ + dlme_img_mapping_bytes = page_align(a->dlme_img_size, UP); + rc = mmap_add_dynamic_region_alloc_va(a->dlme_paddr + a->dlme_img_off, + &dlme_img_mapping, + dlme_img_mapping_bytes, MT_RO_DATA | MT_NS); + if (rc) { + WARN("DRTM: %s: mmap_add_dynamic_region() failed rc=%d\n", + __func__, rc); + return INTERNAL_ERROR; + } + + rc = drtm_event_log_measure_and_record(dlme_img_mapping, a->dlme_img_size, + DRTM_EVENT_ARM_DLME, NULL, + PCR_18); + CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_DLME)); + + rc = mmap_remove_dynamic_region(dlme_img_mapping, dlme_img_mapping_bytes); + CHECK_RC(rc, mmap_remove_dynamic_region); + + /* PCR-18: Measure the DLME image entry point. */ + dlme_img_ep = DL_ARGS_GET_DLME_ENTRY_POINT(a); + drtm_event_log_measure_and_record((uintptr_t)&dlme_img_ep, + sizeof(dlme_img_ep), + DRTM_EVENT_ARM_DLME_EP, NULL, + PCR_18); + CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_DLME_EP)); + + /* PCR-18: End of DCE measurements. */ + rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data, + strlen(drtm_event_arm_sep_data), + DRTM_EVENT_ARM_SEPARATOR, NULL, + PCR_18); + CHECK_RC(rc, + drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR)); + /* + * If the DCE is unable to log a measurement because there is no available + * space in the event log region, the DCE must extend a hash of the value + * 0xFF (1 byte in size) into PCR[17] and PCR[18] and enter remediation. + */ + + return SUCCESS; +} + +void drtm_serialise_event_log(uint8_t *dst, size_t *event_log_size_out) +{ + *event_log_size_out = event_log_get_cur_size(drtm_event_log); + memcpy(dst, drtm_event_log, *event_log_size_out); +} diff --git a/services/std_svc/drtm/drtm_measurements.h b/services/std_svc/drtm/drtm_measurements.h new file mode 100644 index 000000000..6d7a84e93 --- /dev/null +++ b/services/std_svc/drtm/drtm_measurements.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef DRTM_MEASUREMENTS_H +#define DRTM_MEASUREMENTS_H + +#include <stdint.h> + +#include "drtm_main.h" +#include <platform_def.h> + +#define DRTM_EVENT_ARM_BASE 0x9000U +#define DRTM_EVENT_TYPE(n) (DRTM_EVENT_ARM_BASE + (unsigned int)(n)) + +#define DRTM_EVENT_ARM_PCR_SCHEMA DRTM_EVENT_TYPE(1) +#define DRTM_EVENT_ARM_DCE DRTM_EVENT_TYPE(2) +#define DRTM_EVENT_ARM_DCE_PUBKEY DRTM_EVENT_TYPE(3) +#define DRTM_EVENT_ARM_DLME DRTM_EVENT_TYPE(4) +#define DRTM_EVENT_ARM_DLME_EP DRTM_EVENT_TYPE(5) +#define DRTM_EVENT_ARM_DEBUG_CONFIG DRTM_EVENT_TYPE(6) +#define DRTM_EVENT_ARM_NONSECURE_CONFIG DRTM_EVENT_TYPE(7) +#define DRTM_EVENT_ARM_DCE_SECONDARY DRTM_EVENT_TYPE(8) +#define DRTM_EVENT_ARM_TZFW DRTM_EVENT_TYPE(9) +#define DRTM_EVENT_ARM_SEPARATOR DRTM_EVENT_TYPE(10) + +#define CHECK_RC(rc, func_call) { \ + if (rc != 0) { \ + ERROR("%s(): " #func_call "failed unexpectedly rc=%d\n", \ + __func__, rc); \ + panic(); \ + } \ +} + +enum drtm_retc drtm_take_measurements(const struct_drtm_dl_args *a); +void drtm_serialise_event_log(uint8_t *dst, size_t *event_log_size_out); + +#endif /* DRTM_MEASUREMENTS_H */ diff --git a/services/std_svc/drtm/drtm_remediation.c b/services/std_svc/drtm/drtm_remediation.c new file mode 100644 index 000000000..696b4ea6a --- /dev/null +++ b/services/std_svc/drtm/drtm_remediation.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * DRTM support for DRTM error remediation. + * + */ +#include <inttypes.h> +#include <stdint.h> + +#include <common/debug.h> +#include <common/runtime_svc.h> +#include "drtm_main.h" +#include <plat/common/platform.h> + +uint64_t drtm_set_error(uint64_t x1, void *ctx) +{ + int rc; + + rc = plat_set_drtm_error(x1); + + if (rc != 0) { + SMC_RET1(ctx, INTERNAL_ERROR); + } + + SMC_RET1(ctx, SUCCESS); +} + +uint64_t drtm_get_error(void *ctx) +{ + uint64_t error_code; + int rc; + + rc = plat_get_drtm_error(&error_code); + + if (rc != 0) { + SMC_RET1(ctx, INTERNAL_ERROR); + } + + SMC_RET2(ctx, SUCCESS, error_code); +} + +void drtm_enter_remediation(uint64_t err_code, const char *err_str) +{ + int rc = plat_set_drtm_error(err_code); + + if (rc != 0) { + ERROR("%s(): drtm_error_set() failed unexpectedly rc=%d\n", + __func__, rc); + panic(); + } + + ERROR("DRTM: entering remediation of error:\n%" PRIu64 "\t\'%s\'\n", + err_code, err_str); + + ERROR("%s(): system reset is not yet supported\n", __func__); + plat_system_reset(); +} diff --git a/services/std_svc/drtm/drtm_remediation.h b/services/std_svc/drtm/drtm_remediation.h new file mode 100644 index 000000000..8f965f1cd --- /dev/null +++ b/services/std_svc/drtm/drtm_remediation.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef DRTM_REMEDIATION_H +#define DRTM_REMEDIATION_H + +uint64_t drtm_set_error(uint64_t x1, void *ctx); +uint64_t drtm_get_error(void *ctx); + +void drtm_enter_remediation(uint64_t error_code, const char *error_str); + +#endif /* DRTM_REMEDIATION_H */ diff --git a/services/std_svc/drtm/drtm_res_address_map.c b/services/std_svc/drtm/drtm_res_address_map.c new file mode 100644 index 000000000..86367061e --- /dev/null +++ b/services/std_svc/drtm/drtm_res_address_map.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <plat/common/platform.h> +#include <services/drtm_svc.h> +#include <platform_def.h> + +/* Address map revision generated by this code. */ +#define DRTM_ADDRESS_MAP_REVISION U(0x0001) + +/* Amount of space needed for address map based on PLAT_DRTM_MMAP_ENTRIES */ +#define DRTM_ADDRESS_MAP_SIZE (sizeof(drtm_memory_region_descriptor_table_t) + \ + (sizeof(drtm_mem_region_t) * \ + PLAT_DRTM_MMAP_ENTRIES)) + +/* Allocate space for DRTM-formatted address map to be constructed. */ +static uint8_t drtm_address_map[DRTM_ADDRESS_MAP_SIZE]; + +static uint64_t drtm_address_map_size; + +drtm_memory_region_descriptor_table_t *drtm_build_address_map(void) +{ + /* Set up pointer to DRTM memory map. */ + drtm_memory_region_descriptor_table_t *map = + (drtm_memory_region_descriptor_table_t *)drtm_address_map; + + /* Get the platform memory map. */ + const mmap_region_t *mmap = plat_get_addr_mmap(); + unsigned int i; + + /* Set up header for address map structure. */ + map->revision = DRTM_ADDRESS_MAP_REVISION; + map->reserved = 0x0000; + + /* Iterate through mmap and generate DRTM address map. */ + for (i = 0U; mmap[i].base_pa != 0UL; i++) { + /* Set PA of region. */ + map->region[i].region_address = mmap[i].base_pa; + + /* Set size of region (in 4kb chunks). */ + map->region[i].region_size_type = 0; + ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM( + map->region[i].region_size_type, + mmap[i].size / PAGE_SIZE_4KB); + + /* Set type and cacheability. */ + switch (MT_TYPE(mmap[i].attr)) { + case MT_DEVICE: + ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE( + map->region[i].region_size_type, + ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE); + break; + case MT_NON_CACHEABLE: + ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE( + map->region[i].region_size_type, + ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR); + ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY( + map->region[i].region_size_type, + ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC); + break; + case MT_MEMORY: + ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE( + map->region[i].region_size_type, + ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL); + break; + default: + return NULL; + } + } + + map->num_regions = i; + + /* Store total size of address map. */ + drtm_address_map_size = sizeof(drtm_memory_region_descriptor_table_t); + drtm_address_map_size += (i * sizeof(drtm_mem_region_t)); + + return map; +} + +uint64_t drtm_get_address_map_size(void) +{ + return drtm_address_map_size; +} diff --git a/services/std_svc/rmmd/rmmd_attest.c b/services/std_svc/rmmd/rmmd_attest.c index 0432ec3a9..25adf502f 100644 --- a/services/std_svc/rmmd/rmmd_attest.c +++ b/services/std_svc/rmmd/rmmd_attest.c @@ -5,6 +5,7 @@ */ #include <stdint.h> #include <string.h> + #include <common/debug.h> #include <lib/spinlock.h> #include <lib/xlat_tables/xlat_tables_v2.h> @@ -56,110 +57,96 @@ static void print_challenge(uint8_t *hash, size_t hash_size) } /* - * TODO: Have different error codes for different errors so that the caller can - * differentiate various error cases. + * Helper function to validate that the buffer base and length are + * within range. */ -int rmmd_attest_get_platform_token(uint64_t buf_pa, uint64_t *buf_len, uint64_t challenge_hash_len) +static int validate_buffer_params(uint64_t buf_pa, uint64_t buf_len) { - int err; - uintptr_t va; - uint8_t temp_buf[SHA512_DIGEST_SIZE]; + unsigned long shared_buf_page; + uintptr_t shared_buf_base; - /* - * TODO: Currently we don't validate incoming buf_pa. This is a - * prototype and we will need to allocate static buffer for EL3-RMM - * communication. - */ + (void)plat_rmmd_get_el3_rmm_shared_mem(&shared_buf_base); - /* We need a page of buffer to pass data */ - if (*buf_len != PAGE_SIZE) { - ERROR("Invalid buffer length\n"); - return RMMD_ERR_INVAL; + shared_buf_page = shared_buf_base & ~PAGE_SIZE_MASK; + + /* Validate the buffer pointer */ + if ((buf_pa & ~PAGE_SIZE_MASK) != shared_buf_page) { + ERROR("Buffer PA out of range\n"); + return E_RMM_BAD_ADDR; } - if ((challenge_hash_len != SHA256_DIGEST_SIZE) && - (challenge_hash_len != SHA384_DIGEST_SIZE) && - (challenge_hash_len != SHA512_DIGEST_SIZE)) { - ERROR("Invalid hash size: %lu\n", challenge_hash_len); - return RMMD_ERR_INVAL; + /* Validate the size of the shared area */ + if (((buf_pa + buf_len - 1UL) & ~PAGE_SIZE_MASK) != shared_buf_page) { + ERROR("Invalid buffer length\n"); + return E_RMM_INVAL; } - spin_lock(&lock); + return 0; /* No error */ +} + +int rmmd_attest_get_platform_token(uint64_t buf_pa, uint64_t *buf_size, + uint64_t c_size) +{ + int err; + uint8_t temp_buf[SHA512_DIGEST_SIZE]; - /* Map the buffer that was provided by the RMM. */ - err = mmap_add_dynamic_region_alloc_va(buf_pa, &va, PAGE_SIZE, - MT_RW_DATA | MT_REALM); + err = validate_buffer_params(buf_pa, *buf_size); if (err != 0) { - ERROR("mmap_add_dynamic_region_alloc_va failed: %d (%p).\n" - , err, (void *)buf_pa); - spin_unlock(&lock); - return RMMD_ERR_NOMEM; + return err; + } + + if ((c_size != SHA256_DIGEST_SIZE) && + (c_size != SHA384_DIGEST_SIZE) && + (c_size != SHA512_DIGEST_SIZE)) { + ERROR("Invalid hash size: %lu\n", c_size); + return E_RMM_INVAL; } - (void)memcpy(temp_buf, (void *)va, challenge_hash_len); + spin_lock(&lock); - print_challenge((uint8_t *)temp_buf, challenge_hash_len); + (void)memcpy(temp_buf, (void *)buf_pa, c_size); + + print_challenge((uint8_t *)temp_buf, c_size); /* Get the platform token. */ - err = plat_get_cca_attest_token(va, - buf_len, (uintptr_t)temp_buf, challenge_hash_len); + err = plat_rmmd_get_cca_attest_token((uintptr_t)buf_pa, + buf_size, (uintptr_t)temp_buf, c_size); if (err != 0) { ERROR("Failed to get platform token: %d.\n", err); - err = RMMD_ERR_UNK; + err = E_RMM_UNK; } - /* Unmap RMM memory. */ - (void)mmap_remove_dynamic_region(va, PAGE_SIZE); spin_unlock(&lock); return err; } -int rmmd_attest_get_signing_key(uint64_t buf_pa, uint64_t *buf_len, +int rmmd_attest_get_signing_key(uint64_t buf_pa, uint64_t *buf_size, uint64_t ecc_curve) { int err; - uintptr_t va; - /* - * TODO: Currently we don't validate incoming buf_pa. This is a - * prototype and we will need to allocate static buffer for EL3-RMM - * communication. - */ - - /* We need a page of buffer to pass data */ - if (*buf_len != PAGE_SIZE) { - ERROR("Invalid buffer length\n"); - return RMMD_ERR_INVAL; + err = validate_buffer_params(buf_pa, *buf_size); + if (err != 0) { + return err; } if (ecc_curve != ATTEST_KEY_CURVE_ECC_SECP384R1) { ERROR("Invalid ECC curve specified\n"); - return RMMD_ERR_INVAL; + return E_RMM_INVAL; } spin_lock(&lock); - /* Map the buffer that was provided by the RMM. */ - err = mmap_add_dynamic_region_alloc_va(buf_pa, &va, PAGE_SIZE, - MT_RW_DATA | MT_REALM); - if (err != 0) { - ERROR("mmap_add_dynamic_region_alloc_va failed: %d (%p).\n" - , err, (void *)buf_pa); - spin_unlock(&lock); - return RMMD_ERR_NOMEM; - } - /* Get the Realm attestation key. */ - err = plat_get_cca_realm_attest_key(va, buf_len, (unsigned int)ecc_curve); + err = plat_rmmd_get_cca_realm_attest_key((uintptr_t)buf_pa, buf_size, + (unsigned int)ecc_curve); if (err != 0) { ERROR("Failed to get attestation key: %d.\n", err); - err = RMMD_ERR_UNK; + err = E_RMM_UNK; } - /* Unmap RMM memory. */ - (void)mmap_remove_dynamic_region(va, PAGE_SIZE); spin_unlock(&lock); return err; diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c index 746419e9c..6bd9fdf30 100644 --- a/services/std_svc/rmmd/rmmd_main.c +++ b/services/std_svc/rmmd/rmmd_main.c @@ -33,6 +33,11 @@ #include "rmmd_private.h" /******************************************************************************* + * RMM boot failure flag + ******************************************************************************/ +static bool rmm_boot_failed; + +/******************************************************************************* * RMM context information. ******************************************************************************/ rmmd_rmm_context_t rmm_context[PLATFORM_CORE_COUNT]; @@ -132,13 +137,10 @@ static void manage_extensions_realm(cpu_context_t *ctx) ******************************************************************************/ static int32_t rmm_init(void) { - - uint64_t rc; - + long rc; rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()]; INFO("RMM init start.\n"); - ctx->state = RMM_STATE_RESET; /* Enable architecture extensions */ manage_extensions_realm(&ctx->cpu_ctx); @@ -147,12 +149,13 @@ static int32_t rmm_init(void) rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx); rc = rmmd_rmm_sync_entry(ctx); - if (rc != 0ULL) { - ERROR("RMM initialisation failed 0x%" PRIx64 "\n", rc); - panic(); + if (rc != E_RMM_BOOT_SUCCESS) { + ERROR("RMM init failed: %ld\n", rc); + /* Mark the boot as failed for all the CPUs */ + rmm_boot_failed = true; + return 0; } - ctx->state = RMM_STATE_IDLE; INFO("RMM init end.\n"); return 1; @@ -163,9 +166,13 @@ static int32_t rmm_init(void) ******************************************************************************/ int rmmd_setup(void) { + size_t shared_buf_size __unused; + uintptr_t shared_buf_base; uint32_t ep_attr; unsigned int linear_id = plat_my_core_pos(); rmmd_rmm_context_t *rmm_ctx = &rmm_context[linear_id]; + rmm_manifest_t *manifest; + int rc; /* Make sure RME is supported. */ assert(get_armv9_2_feat_rme_support() != 0U); @@ -192,6 +199,34 @@ int rmmd_setup(void) MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + shared_buf_size = + plat_rmmd_get_el3_rmm_shared_mem(&shared_buf_base); + + assert((shared_buf_size == SZ_4K) && + ((void *)shared_buf_base != NULL)); + + /* Load the boot manifest at the beginning of the shared area */ + manifest = (rmm_manifest_t *)shared_buf_base; + rc = plat_rmmd_load_manifest(manifest); + if (rc != 0) { + ERROR("Error loading RMM Boot Manifest (%i)\n", rc); + return rc; + } + flush_dcache_range((uintptr_t)shared_buf_base, shared_buf_size); + + /* + * Prepare coldboot arguments for RMM: + * arg0: This CPUID (primary processor). + * arg1: Version for this Boot Interface. + * arg2: PLATFORM_CORE_COUNT. + * arg3: Base address for the EL3 <-> RMM shared area. The boot + * manifest will be stored at the beginning of this area. + */ + rmm_ep_info->args.arg0 = linear_id; + rmm_ep_info->args.arg1 = RMM_EL3_INTERFACE_VERSION; + rmm_ep_info->args.arg2 = PLATFORM_CORE_COUNT; + rmm_ep_info->args.arg3 = shared_buf_base; + /* Initialise RMM context with this entry point information */ cm_setup_context(&rmm_ctx->cpu_ctx, rmm_ep_info); @@ -207,10 +242,12 @@ int rmmd_setup(void) * Forward SMC to the other security state ******************************************************************************/ static uint64_t rmmd_smc_forward(uint32_t src_sec_state, - uint32_t dst_sec_state, uint64_t x0, - uint64_t x1, uint64_t x2, uint64_t x3, - uint64_t x4, void *handle) + uint32_t dst_sec_state, uint64_t x0, + uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *handle) { + cpu_context_t *ctx = cm_get_context(dst_sec_state); + /* Save incoming security state */ cm_el1_sysregs_context_save(src_sec_state); cm_el2_sysregs_context_save(src_sec_state); @@ -221,19 +258,21 @@ static uint64_t rmmd_smc_forward(uint32_t src_sec_state, cm_set_next_eret_context(dst_sec_state); /* - * As per SMCCCv1.1, we need to preserve x4 to x7 unless + * As per SMCCCv1.2, we need to preserve x4 to x7 unless * being used as return args. Hence we differentiate the * onward and backward path. Support upto 8 args in the * onward path and 4 args in return path. + * Register x4 will be preserved by RMM in case it is not + * used in return path. */ if (src_sec_state == NON_SECURE) { - SMC_RET8(cm_get_context(dst_sec_state), x0, x1, x2, x3, x4, - SMC_GET_GP(handle, CTX_GPREG_X5), - SMC_GET_GP(handle, CTX_GPREG_X6), - SMC_GET_GP(handle, CTX_GPREG_X7)); - } else { - SMC_RET4(cm_get_context(dst_sec_state), x0, x1, x2, x3); + SMC_RET8(ctx, x0, x1, x2, x3, x4, + SMC_GET_GP(handle, CTX_GPREG_X5), + SMC_GET_GP(handle, CTX_GPREG_X6), + SMC_GET_GP(handle, CTX_GPREG_X7)); } + + SMC_RET5(ctx, x0, x1, x2, x3, x4); } /******************************************************************************* @@ -241,12 +280,17 @@ static uint64_t rmmd_smc_forward(uint32_t src_sec_state, * either forwarded to the other security state or handled by the RMM dispatcher ******************************************************************************/ uint64_t rmmd_rmi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, - uint64_t x3, uint64_t x4, void *cookie, - void *handle, uint64_t flags) + uint64_t x3, uint64_t x4, void *cookie, + void *handle, uint64_t flags) { - rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()]; uint32_t src_sec_state; + /* If RMM failed to boot, treat any RMI SMC as unknown */ + if (rmm_boot_failed) { + WARN("RMMD: Failed to boot up RMM. Ignoring RMI call\n"); + SMC_RET1(handle, SMC_UNK); + } + /* Determine which security state this SMC originated from */ src_sec_state = caller_sec_state(flags); @@ -271,15 +315,12 @@ uint64_t rmmd_rmi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, } switch (smc_fid) { - case RMMD_RMI_REQ_COMPLETE: - if (ctx->state == RMM_STATE_RESET) { - VERBOSE("RMMD: running rmmd_rmm_sync_exit\n"); - rmmd_rmm_sync_exit(x1); - } + case RMM_RMI_REQ_COMPLETE: { + uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5); return rmmd_smc_forward(REALM, NON_SECURE, x1, - x2, x3, x4, 0, handle); - + x2, x3, x4, x5, handle); + } default: WARN("RMMD: Unsupported RMM call 0x%08x\n", smc_fid); SMC_RET1(handle, SMC_UNK); @@ -293,11 +334,26 @@ uint64_t rmmd_rmi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, ******************************************************************************/ static void *rmmd_cpu_on_finish_handler(const void *arg) { - int32_t rc; + long rc; uint32_t linear_id = plat_my_core_pos(); rmmd_rmm_context_t *ctx = &rmm_context[linear_id]; - ctx->state = RMM_STATE_RESET; + if (rmm_boot_failed) { + /* RMM Boot failed on a previous CPU. Abort. */ + ERROR("RMM Failed to initialize. Ignoring for CPU%d\n", + linear_id); + return NULL; + } + + /* + * Prepare warmboot arguments for RMM: + * arg0: This CPUID. + * arg1 to arg3: Not used. + */ + rmm_ep_info->args.arg0 = linear_id; + rmm_ep_info->args.arg1 = 0ULL; + rmm_ep_info->args.arg2 = 0ULL; + rmm_ep_info->args.arg3 = 0ULL; /* Initialise RMM context with this entry point information */ cm_setup_context(&ctx->cpu_ctx, rmm_ep_info); @@ -309,13 +365,13 @@ static void *rmmd_cpu_on_finish_handler(const void *arg) rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx); rc = rmmd_rmm_sync_entry(ctx); - if (rc != 0) { - ERROR("RMM initialisation failed (%d) on CPU%d\n", rc, - linear_id); - panic(); + + if (rc != E_RMM_BOOT_SUCCESS) { + ERROR("RMM init failed on CPU%d: %ld\n", linear_id, rc); + /* Mark the boot as failed for any other booting CPU */ + rmm_boot_failed = true; } - ctx->state = RMM_STATE_IDLE; return NULL; } @@ -328,15 +384,15 @@ static int gpt_to_gts_error(int error, uint32_t smc_fid, uint64_t address) int ret; if (error == 0) { - return RMMD_OK; + return E_RMM_OK; } if (error == -EINVAL) { - ret = RMMD_ERR_BAD_ADDR; + ret = E_RMM_BAD_ADDR; } else { /* This is the only other error code we expect */ assert(error == -EPERM); - ret = RMMD_ERR_BAD_PAS; + ret = E_RMM_BAD_PAS; } ERROR("RMMD: PAS Transition failed. GPT ret = %d, PA: 0x%"PRIx64 ", FID = 0x%x\n", @@ -354,6 +410,12 @@ uint64_t rmmd_rmm_el3_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint32_t src_sec_state; int ret; + /* If RMM failed to boot, treat any RMM-EL3 interface SMC as unknown */ + if (rmm_boot_failed) { + WARN("RMMD: Failed to boot up RMM. Ignoring RMM-EL3 call\n"); + SMC_RET1(handle, SMC_UNK); + } + /* Determine which security state this SMC originated from */ src_sec_state = caller_sec_state(flags); @@ -363,18 +425,23 @@ uint64_t rmmd_rmm_el3_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, } switch (smc_fid) { - case RMMD_GTSI_DELEGATE: + case RMM_GTSI_DELEGATE: ret = gpt_delegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM); SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1)); - case RMMD_GTSI_UNDELEGATE: + case RMM_GTSI_UNDELEGATE: ret = gpt_undelegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM); SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1)); - case RMMD_ATTEST_GET_PLAT_TOKEN: + case RMM_ATTEST_GET_PLAT_TOKEN: ret = rmmd_attest_get_platform_token(x1, &x2, x3); SMC_RET2(handle, ret, x2); - case RMMD_ATTEST_GET_REALM_KEY: + case RMM_ATTEST_GET_REALM_KEY: ret = rmmd_attest_get_signing_key(x1, &x2, x3); SMC_RET2(handle, ret, x2); + + case RMM_BOOT_COMPLETE: + VERBOSE("RMMD: running rmmd_rmm_sync_exit\n"); + rmmd_rmm_sync_exit(x1); + default: WARN("RMMD: Unsupported RMM-EL3 call 0x%08x\n", smc_fid); SMC_RET1(handle, SMC_UNK); diff --git a/services/std_svc/rmmd/rmmd_private.h b/services/std_svc/rmmd/rmmd_private.h index 73df2b8bc..4954a4353 100644 --- a/services/std_svc/rmmd/rmmd_private.h +++ b/services/std_svc/rmmd/rmmd_private.h @@ -32,11 +32,6 @@ #ifndef __ASSEMBLER__ #include <stdint.h> -typedef enum rmm_state { - RMM_STATE_RESET = 0, - RMM_STATE_IDLE -} rmm_state_t; - /* * Data structure used by the RMM dispatcher (RMMD) in EL3 to track context of * the RMM at R-EL2. @@ -44,7 +39,6 @@ typedef enum rmm_state { typedef struct rmmd_rmm_context { uint64_t c_rt_ctx; cpu_context_t cpu_ctx; - rmm_state_t state; } rmmd_rmm_context_t; /* Functions used to enter/exit the RMM synchronously */ @@ -52,10 +46,10 @@ uint64_t rmmd_rmm_sync_entry(rmmd_rmm_context_t *ctx); __dead2 void rmmd_rmm_sync_exit(uint64_t rc); /* Functions implementing attestation utilities for RMM */ -int rmmd_attest_get_platform_token(uint64_t buf_pa, uint64_t *buf_len, - uint64_t challenge_hash_len); -int rmmd_attest_get_signing_key(uint64_t buf_pa, uint64_t *buf_len, - uint64_t ecc_curve); +int rmmd_attest_get_platform_token(uint64_t buf_pa, uint64_t *buf_size, + uint64_t c_size); +int rmmd_attest_get_signing_key(uint64_t buf_pa, uint64_t *buf_size, + uint64_t ecc_curve); /* Assembly helpers */ uint64_t rmmd_rmm_enter(uint64_t *c_rt_ctx); diff --git a/services/std_svc/rmmd/trp/trp.mk b/services/std_svc/rmmd/trp/trp.mk index a4f6e03e0..44bbf226f 100644 --- a/services/std_svc/rmmd/trp/trp.mk +++ b/services/std_svc/rmmd/trp/trp.mk @@ -1,11 +1,12 @@ # -# Copyright (c) 2021 Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2022 Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # -RMM_SOURCES += services/std_svc/rmmd/trp/trp_entry.S \ - services/std_svc/rmmd/trp/trp_main.c +RMM_SOURCES += services/std_svc/rmmd/trp/trp_entry.S \ + services/std_svc/rmmd/trp/trp_main.c \ + services/std_svc/rmmd/trp/trp_helpers.c RMM_LINKERFILE := services/std_svc/rmmd/trp/linker.lds diff --git a/services/std_svc/rmmd/trp/trp_entry.S b/services/std_svc/rmmd/trp/trp_entry.S index 1b03c9fbc..47c1df14d 100644 --- a/services/std_svc/rmmd/trp/trp_entry.S +++ b/services/std_svc/rmmd/trp/trp_entry.S @@ -6,6 +6,8 @@ #include <asm_macros.S> #include <services/rmmd_svc.h> + +#include <platform_def.h> #include "trp_private.h" .global trp_head @@ -31,6 +33,28 @@ * --------------------------------------------- */ trp_head: + /* + * Stash arguments from previous boot stage + */ + mov x20, x0 + mov x21, x1 + mov x22, x2 + mov x23, x3 + + /* + * Validate CPUId before allocating a stack. + */ + cmp x20, #PLATFORM_CORE_COUNT + b.lo 1f + + mov_imm x0, RMM_BOOT_COMPLETE + mov_imm x1, E_RMM_BOOT_CPU_ID_OUT_OF_RANGE + smc #0 + + /* EL3 should never return back here, so panic if it does */ + b trp_panic + +1: bl plat_set_my_stack /* @@ -45,7 +69,6 @@ trp_head: adr x2, cold_boot_flag str xzr, [x2] - /* --------------------------------------------- * Zero out BSS section * --------------------------------------------- @@ -54,15 +77,21 @@ trp_head: ldr x1, =__BSS_SIZE__ bl zeromem + mov x0, x20 + mov x1, x21 + mov x2, x22 + mov x3, x23 bl trp_setup - bl trp_main warm_boot: - mov_imm x0, RMMD_RMI_REQ_COMPLETE - mov x1, xzr + mov_imm x0, RMM_BOOT_COMPLETE + mov x1, xzr /* RMM_BOOT_SUCCESS */ smc #0 b trp_handler +trp_panic: + no_ret plat_panic_handler + /* * Flag to mark if it is a cold boot. * 1: cold boot, 0: warmboot. diff --git a/services/std_svc/rmmd/trp/trp_helpers.c b/services/std_svc/rmmd/trp/trp_helpers.c new file mode 100644 index 000000000..159f3a551 --- /dev/null +++ b/services/std_svc/rmmd/trp/trp_helpers.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#include <plat/common/platform.h> +#include <services/rmmd_svc.h> +#include "trp_private.h" + +/* + * Per cpu data structure to populate parameters for an SMC in C code and use + * a pointer to this structure in assembler code to populate x0-x7 + */ +static trp_args_t trp_smc_args[PLATFORM_CORE_COUNT]; + +/* + * Set the arguments for SMC call + */ +trp_args_t *set_smc_args(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id; + trp_args_t *pcpu_smc_args; + + /* + * Return to Secure Monitor by raising an SMC. The results of the + * service are passed as an arguments to the SMC + */ + linear_id = plat_my_core_pos(); + pcpu_smc_args = &trp_smc_args[linear_id]; + write_trp_arg(pcpu_smc_args, TRP_ARG0, arg0); + write_trp_arg(pcpu_smc_args, TRP_ARG1, arg1); + write_trp_arg(pcpu_smc_args, TRP_ARG2, arg2); + write_trp_arg(pcpu_smc_args, TRP_ARG3, arg3); + write_trp_arg(pcpu_smc_args, TRP_ARG4, arg4); + write_trp_arg(pcpu_smc_args, TRP_ARG5, arg5); + write_trp_arg(pcpu_smc_args, TRP_ARG6, arg6); + write_trp_arg(pcpu_smc_args, TRP_ARG7, arg7); + + return pcpu_smc_args; +} + +/* + * Abort the boot process with the reason given in err. + */ +__dead2 void trp_boot_abort(uint64_t err) +{ + (void)trp_smc(set_smc_args(RMM_BOOT_COMPLETE, err, 0, 0, 0, 0, 0, 0)); + panic(); +} diff --git a/services/std_svc/rmmd/trp/trp_main.c b/services/std_svc/rmmd/trp/trp_main.c index 2e3f07634..5a56af043 100644 --- a/services/std_svc/rmmd/trp/trp_main.c +++ b/services/std_svc/rmmd/trp/trp_main.c @@ -7,58 +7,63 @@ #include <common/debug.h> #include <plat/common/platform.h> +#include <services/rmm_core_manifest.h> #include <services/rmmd_svc.h> #include <services/trp/platform_trp.h> +#include <trp_helpers.h> +#include "trp_private.h" #include <platform_def.h> -#include "trp_private.h" -/******************************************************************************* - * Per cpu data structure to populate parameters for an SMC in C code and use - * a pointer to this structure in assembler code to populate x0-x7 - ******************************************************************************/ -static trp_args_t trp_smc_args[PLATFORM_CORE_COUNT]; +/* Parameters received from the previous image */ +static unsigned int trp_boot_abi_version; +static uintptr_t trp_shared_region_start; + +/* Parameters received from boot manifest */ +uint32_t trp_boot_manifest_version; /******************************************************************************* - * Set the arguments for SMC call + * Setup function for TRP. ******************************************************************************/ -static trp_args_t *set_smc_args(uint64_t arg0, - uint64_t arg1, - uint64_t arg2, - uint64_t arg3, - uint64_t arg4, - uint64_t arg5, - uint64_t arg6, - uint64_t arg7) +void trp_setup(uint64_t x0, + uint64_t x1, + uint64_t x2, + uint64_t x3) { - uint32_t linear_id; - trp_args_t *pcpu_smc_args; - /* - * Return to Secure Monitor by raising an SMC. The results of the - * service are passed as an arguments to the SMC + * Validate boot parameters. + * + * According to the Boot Interface ABI v.0.1, the + * parameters recived from EL3 are: + * x0: CPUID (verified earlier so not used) + * x1: Boot Interface version + * x2: PLATFORM_CORE_COUNT + * x3: Pointer to the shared memory area. */ - linear_id = plat_my_core_pos(); - pcpu_smc_args = &trp_smc_args[linear_id]; - write_trp_arg(pcpu_smc_args, TRP_ARG0, arg0); - write_trp_arg(pcpu_smc_args, TRP_ARG1, arg1); - write_trp_arg(pcpu_smc_args, TRP_ARG2, arg2); - write_trp_arg(pcpu_smc_args, TRP_ARG3, arg3); - write_trp_arg(pcpu_smc_args, TRP_ARG4, arg4); - write_trp_arg(pcpu_smc_args, TRP_ARG5, arg5); - write_trp_arg(pcpu_smc_args, TRP_ARG6, arg6); - write_trp_arg(pcpu_smc_args, TRP_ARG7, arg7); - - return pcpu_smc_args; -} -/******************************************************************************* - * Setup function for TRP. - ******************************************************************************/ -void trp_setup(void) -{ + (void)x0; + + if (TRP_RMM_EL3_VERSION_GET_MAJOR(x1) != TRP_RMM_EL3_ABI_VERS_MAJOR) { + trp_boot_abort(E_RMM_BOOT_VERSION_MISMATCH); + } + + if ((void *)x3 == NULL) { + trp_boot_abort(E_RMM_BOOT_INVALID_SHARED_BUFFER); + } + + if (x2 > TRP_PLATFORM_CORE_COUNT) { + trp_boot_abort(E_RMM_BOOT_CPUS_OUT_OF_RANGE); + } + + trp_boot_abi_version = x1; + trp_shared_region_start = x3; + flush_dcache_range((uintptr_t)&trp_boot_abi_version, + sizeof(trp_boot_abi_version)); + flush_dcache_range((uintptr_t)&trp_shared_region_start, + sizeof(trp_shared_region_start)); + /* Perform early platform-specific setup */ - trp_early_platform_setup(); + trp_early_platform_setup((rmm_manifest_t *)trp_shared_region_start); } /* Main function for TRP */ @@ -66,9 +71,19 @@ void trp_main(void) { NOTICE("TRP: %s\n", version_string); NOTICE("TRP: %s\n", build_message); + NOTICE("TRP: Supported RMM-EL3 Interface ABI: v.%u.%u\n", + TRP_RMM_EL3_ABI_VERS_MAJOR, TRP_RMM_EL3_ABI_VERS_MINOR); + NOTICE("TRP: Boot Manifest Version : v.%u.%u\n", + RMMD_GET_MANIFEST_VERSION_MAJOR(trp_boot_manifest_version), + RMMD_GET_MANIFEST_VERSION_MINOR(trp_boot_manifest_version)); INFO("TRP: Memory base : 0x%lx\n", (unsigned long)RMM_BASE); + INFO("TRP: Base address for the shared region : 0x%lx\n", + (unsigned long)trp_shared_region_start); INFO("TRP: Total size : 0x%lx bytes\n", (unsigned long)(RMM_END - RMM_BASE)); + INFO("TRP: RMM-EL3 Interface ABI reported by EL3: v.%u.%u\n", + TRP_RMM_EL3_VERSION_GET_MAJOR(trp_boot_abi_version), + TRP_RMM_EL3_VERSION_GET_MINOR(trp_boot_abi_version)); } /******************************************************************************* @@ -78,7 +93,7 @@ static trp_args_t *trp_ret_rmi_version(void) { VERBOSE("RMM version is %u.%u\n", RMI_ABI_VERSION_MAJOR, RMI_ABI_VERSION_MINOR); - return set_smc_args(RMMD_RMI_REQ_COMPLETE, RMI_ABI_VERSION, + return set_smc_args(RMM_RMI_REQ_COMPLETE, RMI_ABI_VERSION, 0, 0, 0, 0, 0, 0); } @@ -90,13 +105,13 @@ static trp_args_t *trp_asc_mark_realm(unsigned long long x1) unsigned long long ret; VERBOSE("Delegating granule 0x%llx\n", x1); - ret = trp_smc(set_smc_args(RMMD_GTSI_DELEGATE, x1, 0, 0, 0, 0, 0, 0)); + ret = trp_smc(set_smc_args(RMM_GTSI_DELEGATE, x1, 0, 0, 0, 0, 0, 0)); if (ret != 0ULL) { ERROR("Granule transition from NON-SECURE type to REALM type " "failed 0x%llx\n", ret); } - return set_smc_args(RMMD_RMI_REQ_COMPLETE, ret, 0, 0, 0, 0, 0, 0); + return set_smc_args(RMM_RMI_REQ_COMPLETE, ret, 0, 0, 0, 0, 0, 0); } /******************************************************************************* @@ -107,13 +122,13 @@ static trp_args_t *trp_asc_mark_nonsecure(unsigned long long x1) unsigned long long ret; VERBOSE("Undelegating granule 0x%llx\n", x1); - ret = trp_smc(set_smc_args(RMMD_GTSI_UNDELEGATE, x1, 0, 0, 0, 0, 0, 0)); + ret = trp_smc(set_smc_args(RMM_GTSI_UNDELEGATE, x1, 0, 0, 0, 0, 0, 0)); if (ret != 0ULL) { ERROR("Granule transition from REALM type to NON-SECURE type " "failed 0x%llx\n", ret); } - return set_smc_args(RMMD_RMI_REQ_COMPLETE, ret, 0, 0, 0, 0, 0, 0); + return set_smc_args(RMM_RMI_REQ_COMPLETE, ret, 0, 0, 0, 0, 0, 0); } /******************************************************************************* diff --git a/services/std_svc/rmmd/trp/trp_private.h b/services/std_svc/rmmd/trp/trp_private.h index 43a4a4bfd..945ae1c89 100644 --- a/services/std_svc/rmmd/trp/trp_private.h +++ b/services/std_svc/rmmd/trp/trp_private.h @@ -7,48 +7,39 @@ #ifndef TRP_PRIVATE_H #define TRP_PRIVATE_H -/* Definitions to help the assembler access the SMC/ERET args structure */ -#define TRP_ARGS_SIZE TRP_ARGS_END -#define TRP_ARG0 0x0 -#define TRP_ARG1 0x8 -#define TRP_ARG2 0x10 -#define TRP_ARG3 0x18 -#define TRP_ARG4 0x20 -#define TRP_ARG5 0x28 -#define TRP_ARG6 0x30 -#define TRP_ARG7 0x38 -#define TRP_ARGS_END 0x40 +#include <services/rmmd_svc.h> +#include <trp_helpers.h> + +/* Definitions for RMM-EL3 Interface ABI VERSION */ +#define TRP_RMM_EL3_ABI_VERS_MAJOR RMM_EL3_IFC_VERSION_MAJOR +#define TRP_RMM_EL3_ABI_VERS_MINOR RMM_EL3_IFC_VERSION_MINOR +#define TRP_RMM_EL3_ABI_VERS (((TRP_RMM_EL3_ABI_VERS_MAJOR & 0x7FFF) << 16) | \ + (TRP_RMM_EL3_ABI_VERS_MINOR & 0xFFFF)) + +#define TRP_PLATFORM_CORE_COUNT PLATFORM_CORE_COUNT #ifndef __ASSEMBLER__ #include <stdint.h> -/* Data structure to hold SMC arguments */ -typedef struct trp_args { - uint64_t regs[TRP_ARGS_END >> 3]; -} __aligned(CACHE_WRITEBACK_GRANULE) trp_args_t; - #define write_trp_arg(args, offset, val) (((args)->regs[offset >> 3]) \ = val) - -/* RMI handled by TRP */ -#define RMI_FNUM_VERSION_REQ U(0x150) - -#define RMI_FNUM_GRANULE_DELEGATE U(0x151) -#define RMI_FNUM_GRANULE_UNDELEGATE U(0x152) - -#define RMI_RMM_REQ_VERSION RMM_FID(SMC_64, RMI_FNUM_VERSION_REQ) - -#define RMI_RMM_GRANULE_DELEGATE RMM_FID(SMC_64, \ - RMI_FNUM_GRANULE_DELEGATE) -#define RMI_RMM_GRANULE_UNDELEGATE RMM_FID(SMC_64, \ - RMI_FNUM_GRANULE_UNDELEGATE) +/* RMI SMC64 FIDs handled by the TRP */ +#define RMI_RMM_REQ_VERSION SMC64_RMI_FID(U(0)) +#define RMI_RMM_GRANULE_DELEGATE SMC64_RMI_FID(U(1)) +#define RMI_RMM_GRANULE_UNDELEGATE SMC64_RMI_FID(U(2)) /* Definitions for RMI VERSION */ #define RMI_ABI_VERSION_MAJOR U(0x0) #define RMI_ABI_VERSION_MINOR U(0x0) -#define RMI_ABI_VERSION ((RMI_ABI_VERSION_MAJOR << 16) | \ - RMI_ABI_VERSION_MINOR) +#define RMI_ABI_VERSION (((RMI_ABI_VERSION_MAJOR & 0x7FFF) \ + << 16) | \ + (RMI_ABI_VERSION_MINOR & 0xFFFF)) + +#define TRP_RMM_EL3_VERSION_GET_MAJOR(x) \ + RMM_EL3_IFC_VERSION_GET_MAJOR((x)) +#define TRP_RMM_EL3_VERSION_GET_MINOR(x) \ + RMM_EL3_IFC_VERSION_GET_MAJOR_MINOR((x)) /* Helper to issue SMC calls to BL31 */ uint64_t trp_smc(trp_args_t *); @@ -57,7 +48,10 @@ uint64_t trp_smc(trp_args_t *); void trp_main(void); /* Setup TRP. Executed only by Primary CPU */ -void trp_setup(void); +void trp_setup(uint64_t x0, + uint64_t x1, + uint64_t x2, + uint64_t x3); #endif /* __ASSEMBLER__ */ #endif /* TRP_PRIVATE_H */ diff --git a/services/std_svc/sdei/sdei_event.c b/services/std_svc/sdei/sdei_event.c index 0b608e1b6..e0c7971ac 100644 --- a/services/std_svc/sdei/sdei_event.c +++ b/services/std_svc/sdei/sdei_event.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -99,3 +99,24 @@ sdei_ev_map_t *find_event_map(int ev_num) return NULL; } + +/* + * Return the total number of currently registered SDEI events. + */ +int sdei_get_registered_event_count(void) +{ + const sdei_mapping_t *mapping; + sdei_ev_map_t *map; + unsigned int i; + unsigned int j; + int count = 0; + + /* Add up reg counts for each mapping. */ + for_each_mapping_type(i, mapping) { + iterate_mapping(mapping, j, map) { + count += map->reg_count; + } + } + + return count; +} diff --git a/services/std_svc/spm/el3_spmc/spmc.h b/services/std_svc/spm/el3_spmc/spmc.h index d62be91eb..523365002 100644 --- a/services/std_svc/spm/el3_spmc/spmc.h +++ b/services/std_svc/spm/el3_spmc/spmc.h @@ -9,6 +9,7 @@ #include <stdint.h> +#include <common/bl_common.h> #include <lib/psci/psci.h> #include <lib/spinlock.h> #include <services/el3_spmc_logical_sp.h> diff --git a/services/std_svc/spm/el3_spmc/spmc.mk b/services/std_svc/spm/el3_spmc/spmc.mk index aa591d9f3..c674e7161 100644 --- a/services/std_svc/spm/el3_spmc/spmc.mk +++ b/services/std_svc/spm/el3_spmc/spmc.mk @@ -24,3 +24,21 @@ SPMC_SOURCES += $(SPMC_LP_SOURCES) # Let the top-level Makefile know that we intend to include a BL32 image NEED_BL32 := yes + +ifndef BL32 +# The SPMC is paired with a Test Secure Payload source and we intend to +# build the Test Secure Payload if no other image has been provided +# for BL32. +# +# In cases where an associated Secure Payload lies outside this build +# system/source tree, the dispatcher Makefile can either invoke an external +# build command or assume it is pre-built. + +BL32_ROOT := bl32/tsp + +# Conditionally include SP's Makefile. The assumption is that the TSP's build +# system is compatible with that of Trusted Firmware, and it'll add and populate +# necessary build targets and variables. + +include ${BL32_ROOT}/tsp.mk +endif diff --git a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c index 4a24108e0..89d7b3177 100644 --- a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c +++ b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c @@ -72,13 +72,23 @@ spmc_shmem_obj_alloc(struct spmc_shmem_obj_state *state, size_t desc_size) { struct spmc_shmem_obj *obj; size_t free = state->data_size - state->allocated; + size_t obj_size; if (state->data == NULL) { ERROR("Missing shmem datastore!\n"); return NULL; } - if (spmc_shmem_obj_size(desc_size) > free) { + obj_size = spmc_shmem_obj_size(desc_size); + + /* Ensure the obj size has not overflowed. */ + if (obj_size < desc_size) { + WARN("%s(0x%zx) desc_size overflow\n", + __func__, desc_size); + return NULL; + } + + if (obj_size > free) { WARN("%s(0x%zx) failed, free 0x%zx\n", __func__, desc_size, free); return NULL; @@ -88,7 +98,7 @@ spmc_shmem_obj_alloc(struct spmc_shmem_obj_state *state, size_t desc_size) obj->desc_size = desc_size; obj->desc_filled = 0; obj->in_use = 0; - state->allocated += spmc_shmem_obj_size(desc_size); + state->allocated += obj_size; return obj; } @@ -260,6 +270,34 @@ spmc_shmem_obj_ffa_constituent_size(struct spmc_shmem_obj *obj, return comp_mrd->address_range_count * sizeof(struct ffa_cons_mrd); } +/** + * spmc_shmem_obj_validate_id - Validate a partition ID is participating in + * a given memory transaction. + * @sp_id: Partition ID to validate. + * @desc: Descriptor of the memory transaction. + * + * Return: true if ID is valid, else false. + */ +bool spmc_shmem_obj_validate_id(const struct ffa_mtd *desc, uint16_t sp_id) +{ + bool found = false; + + /* Validate the partition is a valid participant. */ + for (unsigned int i = 0U; i < desc->emad_count; i++) { + size_t emad_size; + struct ffa_emad_v1_0 *emad; + + emad = spmc_shmem_obj_get_emad(desc, i, + MAKE_FFA_VERSION(1, 1), + &emad_size); + if (sp_id == emad->mapd.endpoint_id) { + found = true; + break; + } + } + return found; +} + /* * Compare two memory regions to determine if any range overlaps with another * ongoing memory transaction. @@ -302,10 +340,9 @@ overlapping_memory_regions(struct ffa_comp_mrd *region1, PAGE_SIZE_4KB; region2_end = region2_start + region2_size; - if ((region1_start >= region2_start && - region1_start < region2_end) || - (region1_end > region2_start - && region1_end < region2_end)) { + /* Check if regions are not overlapping. */ + if (!((region2_end <= region1_start) || + (region1_end <= region2_start))) { WARN("Overlapping mem regions 0x%lx-0x%lx & 0x%lx-0x%lx\n", region1_start, region1_end, region2_start, region2_end); @@ -858,9 +895,6 @@ static long spmc_ffa_fill_desc(struct mailbox *mbox, goto err_arg; } - memcpy((uint8_t *)&obj->desc + obj->desc_filled, - (uint8_t *) mbox->tx_buffer, fragment_length); - if (fragment_length > obj->desc_size - obj->desc_filled) { WARN("%s: bad fragment size %u > %zu remaining\n", __func__, fragment_length, obj->desc_size - obj->desc_filled); @@ -868,6 +902,9 @@ static long spmc_ffa_fill_desc(struct mailbox *mbox, goto err_arg; } + memcpy((uint8_t *)&obj->desc + obj->desc_filled, + (uint8_t *) mbox->tx_buffer, fragment_length); + /* Ensure that the sender ID resides in the normal world. */ if (ffa_is_secure_world_id(obj->desc.sender_id)) { WARN("%s: Invalid sender ID 0x%x.\n", @@ -990,7 +1027,7 @@ static long spmc_ffa_fill_desc(struct mailbox *mbox, /* Calculate the size that the v1.1 descriptor will required. */ size_t v1_1_desc_size = spmc_shm_get_v1_1_descriptor_size((void *) &obj->desc, - fragment_length); + obj->desc_size); if (v1_1_desc_size == 0U) { ERROR("%s: cannot determine size of descriptor.\n", @@ -1002,7 +1039,7 @@ static long spmc_ffa_fill_desc(struct mailbox *mbox, v1_1_obj = spmc_shmem_obj_alloc(&spmc_shmem_obj_state, v1_1_desc_size); - if (!obj) { + if (!v1_1_obj) { ret = FFA_ERROR_NO_MEMORY; goto err_arg; } @@ -1319,7 +1356,8 @@ spmc_ffa_mem_retrieve_req(uint32_t smc_fid, if (req->emad_count == 0U) { WARN("%s: unsupported attribute desc count %u.\n", __func__, obj->desc.emad_count); - return -EINVAL; + ret = FFA_ERROR_INVALID_PARAMETER; + goto err_unlock_mailbox; } /* Determine the appropriate minimum descriptor size. */ @@ -1403,6 +1441,14 @@ spmc_ffa_mem_retrieve_req(uint32_t smc_fid, } } + /* Validate the caller is a valid participant. */ + if (!spmc_shmem_obj_validate_id(&obj->desc, sp_ctx->sp_id)) { + WARN("%s: Invalid endpoint ID (0x%x).\n", + __func__, sp_ctx->sp_id); + ret = FFA_ERROR_INVALID_PARAMETER; + goto err_unlock_all; + } + /* Validate that the provided emad offset and structure is valid.*/ for (size_t i = 0; i < req->emad_count; i++) { size_t emad_size; @@ -1657,6 +1703,7 @@ int spmc_ffa_mem_relinquish(uint32_t smc_fid, struct mailbox *mbox = spmc_get_mbox_desc(secure_origin); struct spmc_shmem_obj *obj; const struct ffa_mem_relinquish_descriptor *req; + struct secure_partition_desc *sp_ctx = spmc_get_current_sp_ctx(); if (!secure_origin) { WARN("%s: unsupported relinquish direction.\n", __func__); @@ -1694,36 +1741,31 @@ int spmc_ffa_mem_relinquish(uint32_t smc_fid, goto err_unlock_all; } - if (obj->desc.emad_count != req->endpoint_count) { - WARN("%s: mismatch of endpoint count %u != %u\n", __func__, - obj->desc.emad_count, req->endpoint_count); + /* + * Validate the endpoint ID was populated correctly. We don't currently + * support proxy endpoints so the endpoint count should always be 1. + */ + if (req->endpoint_count != 1U) { + WARN("%s: unsupported endpoint count %u != 1\n", __func__, + req->endpoint_count); ret = FFA_ERROR_INVALID_PARAMETER; goto err_unlock_all; } - /* Validate requested endpoint IDs match descriptor. */ - for (size_t i = 0; i < req->endpoint_count; i++) { - bool found = false; - size_t emad_size; - struct ffa_emad_v1_0 *emad; - - for (unsigned int j = 0; j < obj->desc.emad_count; j++) { - emad = spmc_shmem_obj_get_emad(&obj->desc, j, - MAKE_FFA_VERSION(1, 1), - &emad_size); - if (req->endpoint_array[i] == - emad->mapd.endpoint_id) { - found = true; - break; - } - } + /* Validate provided endpoint ID matches the partition ID. */ + if (req->endpoint_array[0] != sp_ctx->sp_id) { + WARN("%s: invalid endpoint ID %u != %u\n", __func__, + req->endpoint_array[0], sp_ctx->sp_id); + ret = FFA_ERROR_INVALID_PARAMETER; + goto err_unlock_all; + } - if (!found) { - WARN("%s: Invalid endpoint ID (0x%x).\n", - __func__, req->endpoint_array[i]); - ret = FFA_ERROR_INVALID_PARAMETER; - goto err_unlock_all; - } + /* Validate the caller is a valid participant. */ + if (!spmc_shmem_obj_validate_id(&obj->desc, sp_ctx->sp_id)) { + WARN("%s: Invalid endpoint ID (0x%x).\n", + __func__, req->endpoint_array[0]); + ret = FFA_ERROR_INVALID_PARAMETER; + goto err_unlock_all; } if (obj->in_use == 0U) { @@ -1795,6 +1837,13 @@ int spmc_ffa_mem_reclaim(uint32_t smc_fid, goto err_unlock; } + if (obj->desc_filled != obj->desc_size) { + WARN("%s: incomplete object desc filled %zu < size %zu\n", + __func__, obj->desc_filled, obj->desc_size); + ret = FFA_ERROR_INVALID_PARAMETER; + goto err_unlock; + } + /* Allow for platform specific operations to be performed. */ ret = plat_spmc_shmem_reclaim(&obj->desc); if (ret != 0) { diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c index e38878432..7e6c89df3 100644 --- a/services/std_svc/spmd/spmd_main.c +++ b/services/std_svc/spmd/spmd_main.c @@ -803,6 +803,14 @@ uint64_t spmd_smc_handler(uint32_t smc_fid, break; /* not reached */ case FFA_MSG_SEND_DIRECT_REQ_SMC32: + case FFA_MSG_SEND_DIRECT_REQ_SMC64: + if (!secure_origin) { + /* Validate source endpoint is non-secure for non-secure caller. */ + if (ffa_is_secure_world_id(ffa_endpoint_source(x1))) { + return spmd_ffa_error_return(handle, + FFA_ERROR_INVALID_PARAMETER); + } + } if (secure_origin && spmd_is_spmc_message(x1)) { ret = spmd_handle_spmc_message(x3, x4, SMC_GET_GP(handle, CTX_GPREG_X5), @@ -862,7 +870,6 @@ uint64_t spmd_smc_handler(uint32_t smc_fid, /* Fall through to forward the call to the other world */ case FFA_MSG_SEND: - case FFA_MSG_SEND_DIRECT_REQ_SMC64: case FFA_MSG_SEND_DIRECT_RESP_SMC64: case FFA_MEM_DONATE_SMC32: case FFA_MEM_DONATE_SMC64: diff --git a/services/std_svc/spmd/spmd_private.h b/services/std_svc/spmd/spmd_private.h index 07fecb66c..d21a622fd 100644 --- a/services/std_svc/spmd/spmd_private.h +++ b/services/std_svc/spmd/spmd_private.h @@ -7,6 +7,7 @@ #ifndef SPMD_PRIVATE_H #define SPMD_PRIVATE_H +#include <common/bl_common.h> #include <context.h> /******************************************************************************* diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c index 84402706d..495783e7d 100644 --- a/services/std_svc/std_svc_setup.c +++ b/services/std_svc/std_svc_setup.c @@ -13,6 +13,7 @@ #include <lib/pmf/pmf.h> #include <lib/psci/psci.h> #include <lib/runtime_instr.h> +#include <services/drtm_svc.h> #include <services/pci_svc.h> #include <services/rmmd_svc.h> #include <services/sdei.h> @@ -73,7 +74,16 @@ static int32_t std_svc_setup(void) sdei_init(); #endif +#if TRNG_SUPPORT + /* TRNG initialisation */ trng_setup(); +#endif /* TRNG_SUPPORT */ + +#if DRTM_SUPPORT + if (drtm_setup() != 0) { + ret = 1; + } +#endif /* DRTM_SUPPORT */ return ret; } @@ -165,7 +175,8 @@ static uintptr_t std_svc_smc_handler(uint32_t smc_fid, return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); } -#endif +#endif /* TRNG_SUPPORT */ + #if ENABLE_RME if (is_rmmd_el3_fid(smc_fid)) { @@ -186,6 +197,13 @@ static uintptr_t std_svc_smc_handler(uint32_t smc_fid, } #endif +#if DRTM_SUPPORT + if (is_drtm_fid(smc_fid)) { + return drtm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, + flags); + } +#endif /* DRTM_SUPPORT */ + switch (smc_fid) { case ARM_STD_SVC_CALL_COUNT: /* diff --git a/services/std_svc/trng/trng_entropy_pool.c b/services/std_svc/trng/trng_entropy_pool.c index ac13b1d7a..30105b3a3 100644 --- a/services/std_svc/trng/trng_entropy_pool.c +++ b/services/std_svc/trng/trng_entropy_pool.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,7 +18,7 @@ * 192 bits of entropy, we don't have to throw out the leftover 1-63 bits of * entropy. */ -#define WORDS_IN_POOL (4) +#define WORDS_IN_POOL (4) static uint64_t entropy[WORDS_IN_POOL]; /* index in bits of the first bit of usable entropy */ static uint32_t entropy_bit_index; @@ -27,14 +27,14 @@ static uint32_t entropy_bit_size; static spinlock_t trng_pool_lock; -#define BITS_PER_WORD (sizeof(entropy[0]) * 8) -#define BITS_IN_POOL (WORDS_IN_POOL * BITS_PER_WORD) -#define ENTROPY_MIN_WORD (entropy_bit_index / BITS_PER_WORD) -#define ENTROPY_FREE_BIT (entropy_bit_size + entropy_bit_index) -#define _ENTROPY_FREE_WORD (ENTROPY_FREE_BIT / BITS_PER_WORD) -#define ENTROPY_FREE_INDEX (_ENTROPY_FREE_WORD % WORDS_IN_POOL) +#define BITS_PER_WORD (sizeof(entropy[0]) * 8) +#define BITS_IN_POOL (WORDS_IN_POOL * BITS_PER_WORD) +#define ENTROPY_MIN_WORD (entropy_bit_index / BITS_PER_WORD) +#define ENTROPY_FREE_BIT (entropy_bit_size + entropy_bit_index) +#define _ENTROPY_FREE_WORD (ENTROPY_FREE_BIT / BITS_PER_WORD) +#define ENTROPY_FREE_INDEX (_ENTROPY_FREE_WORD % WORDS_IN_POOL) /* ENTROPY_WORD_INDEX(0) includes leftover bits in the lower bits */ -#define ENTROPY_WORD_INDEX(i) ((ENTROPY_MIN_WORD + i) % WORDS_IN_POOL) +#define ENTROPY_WORD_INDEX(i) ((ENTROPY_MIN_WORD + i) % WORDS_IN_POOL) /* * Fill the entropy pool until we have at least as many bits as requested. @@ -65,12 +65,12 @@ static bool trng_fill_entropy(uint32_t nbits) */ bool trng_pack_entropy(uint32_t nbits, uint64_t *out) { - bool success = true; + bool ret = true; spin_lock(&trng_pool_lock); if (!trng_fill_entropy(nbits)) { - success = false; + ret = false; goto out; } @@ -82,9 +82,8 @@ bool trng_pack_entropy(uint32_t nbits, uint64_t *out) for (word_i = 0; word_i < to_fill; word_i++) { /* * Repack the entropy from the pool into the passed in out - * buffer. This takes the lower bits from the valid upper bits - * of word_i and the upper bits from the lower bits of - * (word_i + 1). + * buffer. This takes lesser bits from the valid upper bits + * of word_i and more bits from the lower bits of (word_i + 1). * * I found the following diagram useful. note: `e` represents * valid entropy, ` ` represents invalid bits (not entropy) and @@ -136,7 +135,7 @@ bool trng_pack_entropy(uint32_t nbits, uint64_t *out) out: spin_unlock(&trng_pool_lock); - return success; + return ret; } void trng_entropy_pool_setup(void) diff --git a/services/std_svc/trng/trng_main.c b/services/std_svc/trng/trng_main.c index 38aa64997..90098a8f2 100644 --- a/services/std_svc/trng/trng_main.c +++ b/services/std_svc/trng/trng_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,9 +23,9 @@ static const uuid_t uuid_null; static uintptr_t trng_rnd32(uint32_t nbits, void *handle) { uint32_t mask = ~0U; - uint64_t ent[2]; + uint64_t ent[2] = {0}; - if (nbits == 0U || nbits > 96U) { + if (nbits == 0U || nbits > TRNG_RND32_ENTROPY_MAXBITS) { SMC_RET1(handle, TRNG_E_INVALID_PARAMS); } @@ -59,9 +59,9 @@ static uintptr_t trng_rnd32(uint32_t nbits, void *handle) static uintptr_t trng_rnd64(uint32_t nbits, void *handle) { uint64_t mask = ~0ULL; - uint64_t ent[3]; + uint64_t ent[3] = {0}; - if (nbits == 0U || nbits > 192U) { + if (nbits == 0U || nbits > TRNG_RND64_ENTROPY_MAXBITS) { SMC_RET1(handle, TRNG_E_INVALID_PARAMS); } @@ -117,9 +117,9 @@ uintptr_t trng_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, switch (smc_fid) { case ARM_TRNG_VERSION: SMC_RET1(handle, MAKE_SMCCC_VERSION( - TRNG_VERSION_MAJOR, TRNG_VERSION_MINOR - )); + TRNG_VERSION_MAJOR, TRNG_VERSION_MINOR)); break; /* unreachable */ + case ARM_TRNG_FEATURES: if (is_trng_fid((uint32_t)x1)) { SMC_RET1(handle, TRNG_E_SUCCESS); @@ -127,16 +127,19 @@ uintptr_t trng_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, SMC_RET1(handle, TRNG_E_NOT_SUPPORTED); } break; /* unreachable */ + case ARM_TRNG_GET_UUID: SMC_UUID_RET(handle, plat_trng_uuid); break; /* unreachable */ + case ARM_TRNG_RND32: return trng_rnd32((uint32_t)x1, handle); + case ARM_TRNG_RND64: return trng_rnd64((uint32_t)x1, handle); + default: - WARN("Unimplemented TRNG Service Call: 0x%x\n", - smc_fid); + WARN("Unimplemented TRNG Service Call: 0x%x\n", smc_fid); SMC_RET1(handle, TRNG_E_NOT_IMPLEMENTED); break; /* unreachable */ } diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile index ca548b836..042e84462 100644 --- a/tools/cert_create/Makefile +++ b/tools/cert_create/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -9,12 +9,12 @@ V ?= 0 DEBUG := 0 CRTTOOL ?= cert_create${BIN_EXT} BINARY := $(notdir ${CRTTOOL}) -OPENSSL_DIR := /usr COT := tbbr MAKE_HELPERS_DIRECTORY := ../../make_helpers/ include ${MAKE_HELPERS_DIRECTORY}build_macros.mk include ${MAKE_HELPERS_DIRECTORY}build_env.mk +include ${MAKE_HELPERS_DIRECTORY}defaults.mk ifneq (${PLAT},none) TF_PLATFORM_ROOT := ../../plat/ @@ -35,6 +35,8 @@ ifeq (${COT},tbbr) include src/tbbr/tbbr.mk else ifeq (${COT},dualroot) include src/dualroot/cot.mk +else ifeq (${COT},cca) + include src/cca/cot.mk else $(error Unknown chain of trust ${COT}) endif @@ -43,6 +45,10 @@ ifneq (,$(wildcard ${PLAT_CERT_CREATE_HELPER_MK})) include ${PLAT_CERT_CREATE_HELPER_MK} endif +# Select OpenSSL version flag according to the OpenSSL build selected +# from setting the OPENSSL_DIR path. +$(eval $(call SELECT_OPENSSL_API_VERSION)) + HOSTCCFLAGS := -Wall -std=c99 ifeq (${DEBUG},1) @@ -58,6 +64,9 @@ else endif HOSTCCFLAGS += ${DEFINES} +# USING_OPENSSL3 flag will be added to the HOSTCCFLAGS variable with the proper +# computed value. +HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3) # Make soft links and include from local directory otherwise wrong headers # could get pulled in from firmware tree. @@ -74,11 +83,11 @@ LIB := -lssl -lcrypto HOSTCC ?= gcc -.PHONY: all clean realclean +.PHONY: all clean realclean --openssl all: ${BINARY} -${BINARY}: ${OBJECTS} Makefile +${BINARY}: --openssl ${OBJECTS} Makefile @echo " HOSTLD $@" @echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__; \ const char platform_msg[] = "${PLAT_MSG}";' | \ @@ -89,6 +98,11 @@ ${BINARY}: ${OBJECTS} Makefile @echo " HOSTCC $<" ${Q}${HOSTCC} -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@ +--openssl: +ifeq ($(DEBUG),1) + @echo "Selected OpenSSL version: ${OPENSSL_CURRENT_VER}" +endif + clean: $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS}) diff --git a/tools/cert_create/include/cca/cca_cot.h b/tools/cert_create/include/cca/cca_cot.h new file mode 100644 index 000000000..56585fbf1 --- /dev/null +++ b/tools/cert_create/include/cca/cca_cot.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CCA_COT_H +#define CCA_COT_H + +/* Certificates. */ +enum { + /* Certificates owned by the silicon provider. */ + CCA_CONTENT_CERT, + CORE_SWD_KEY_CERT, + SPMC_CONTENT_CERT, + SIP_SECURE_PARTITION_CONTENT_CERT, + + /* Certificates owned by the platform owner. */ + PLAT_KEY_CERT, + PLAT_SECURE_PARTITION_CONTENT_CERT, + NON_TRUSTED_FW_CONTENT_CERT, +}; + +/* Certificate extensions. */ +enum { + /* Extensions used in certificates owned by the silicon provider. */ + TRUSTED_FW_NVCOUNTER_EXT, + TRUSTED_BOOT_FW_HASH_EXT, + TRUSTED_BOOT_FW_CONFIG_HASH_EXT, + HW_CONFIG_HASH_EXT, + FW_CONFIG_HASH_EXT, + SWD_ROT_PK_EXT, + CORE_SWD_PK_EXT, + SOC_AP_FW_HASH_EXT, + SOC_FW_CONFIG_HASH_EXT, + RMM_HASH_EXT, + TRUSTED_OS_FW_HASH_EXT, + TRUSTED_OS_FW_CONFIG_HASH_EXT, + SP_PKG1_HASH_EXT, + SP_PKG2_HASH_EXT, + SP_PKG3_HASH_EXT, + SP_PKG4_HASH_EXT, + + /* Extensions used in certificates owned by the platform owner. */ + PROT_PK_EXT, + PLAT_PK_EXT, + SP_PKG5_HASH_EXT, + SP_PKG6_HASH_EXT, + SP_PKG7_HASH_EXT, + SP_PKG8_HASH_EXT, + NON_TRUSTED_FW_NVCOUNTER_EXT, + NON_TRUSTED_WORLD_BOOTLOADER_HASH_EXT, + NON_TRUSTED_FW_CONFIG_HASH_EXT, +}; + +/* Keys. */ +enum { + /* Keys owned by the silicon provider. */ + ROT_KEY, + SWD_ROT_KEY, + CORE_SWD_KEY, + + /* Keys owned by the platform owner. */ + PROT_KEY, + PLAT_KEY, +}; + +#endif /* CCA_COT_H */ diff --git a/tools/cert_create/include/cert.h b/tools/cert_create/include/cert.h index e63b4740a..5d39a885a 100644 --- a/tools/cert_create/include/cert.h +++ b/tools/cert_create/include/cert.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -54,6 +54,7 @@ int cert_new( int days, int ca, STACK_OF(X509_EXTENSION) * sk); +void cert_cleanup(void); /* Macro to register the certificates used in the CoT */ #define REGISTER_COT(_certs) \ diff --git a/tools/cert_create/include/ext.h b/tools/cert_create/include/ext.h index e900a6dc4..0e7f3be94 100644 --- a/tools/cert_create/include/ext.h +++ b/tools/cert_create/include/ext.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -72,6 +72,7 @@ X509_EXTENSION *ext_new_hash(int nid, int crit, const EVP_MD *md, unsigned char *buf, size_t len); X509_EXTENSION *ext_new_nvcounter(int nid, int crit, int value); X509_EXTENSION *ext_new_key(int nid, int crit, EVP_PKEY *k); +void ext_cleanup(void); /* Macro to register the extensions used in the CoT */ #define REGISTER_EXTENSIONS(_ext) \ diff --git a/tools/cert_create/include/key.h b/tools/cert_create/include/key.h index 128e7f7b4..312575b44 100644 --- a/tools/cert_create/include/key.h +++ b/tools/cert_create/include/key.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,7 +22,9 @@ enum { enum { KEY_ALG_RSA, /* RSA PSS as defined by PKCS#1 v2.1 (default) */ #ifndef OPENSSL_NO_EC - KEY_ALG_ECDSA, + KEY_ALG_ECDSA_NIST, + KEY_ALG_ECDSA_BRAINPOOL_R, + KEY_ALG_ECDSA_BRAINPOOL_T, #endif /* OPENSSL_NO_EC */ KEY_ALG_MAX_NUM }; @@ -42,7 +44,9 @@ enum{ static const unsigned int KEY_SIZES[KEY_ALG_MAX_NUM][KEY_SIZE_MAX_NUM] = { { 2048, 1024, 3072, 4096 }, /* KEY_ALG_RSA */ #ifndef OPENSSL_NO_EC - {} /* KEY_ALG_ECDSA */ + {}, /* KEY_ALG_ECDSA_NIST */ + {}, /* KEY_ALG_ECDSA_BRAINPOOL_R */ + {} /* KEY_ALG_ECDSA_BRAINPOOL_T */ #endif /* OPENSSL_NO_EC */ }; @@ -66,10 +70,13 @@ typedef struct key_s { /* Exported API */ int key_init(void); key_t *key_get_by_opt(const char *opt); +#if !USING_OPENSSL3 int key_new(key_t *key); +#endif int key_create(key_t *key, int type, int key_bits); int key_load(key_t *key, unsigned int *err_code); int key_store(key_t *key); +void key_cleanup(void); /* Macro to register the keys used in the CoT */ #define REGISTER_KEYS(_keys) \ diff --git a/tools/cert_create/src/cca/cot.c b/tools/cert_create/src/cca/cot.c new file mode 100644 index 000000000..5a35ff606 --- /dev/null +++ b/tools/cert_create/src/cca/cot.c @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "cca/cca_cot.h" + +#include <cca_oid.h> + +#include "cert.h" +#include "ext.h" +#include "key.h" + +/* + * Certificates used in the chain of trust. + * + * All certificates are self-signed so the issuer certificate field points to + * itself. + */ +static cert_t cot_certs[] = { + [CCA_CONTENT_CERT] = { + .id = CCA_CONTENT_CERT, + .opt = "cca-cert", + .help_msg = "CCA Content Certificate (output file)", + .cn = "CCA Content Certificate", + .key = ROT_KEY, + .issuer = CCA_CONTENT_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + SOC_AP_FW_HASH_EXT, + SOC_FW_CONFIG_HASH_EXT, + RMM_HASH_EXT, + TRUSTED_BOOT_FW_HASH_EXT, + TRUSTED_BOOT_FW_CONFIG_HASH_EXT, + HW_CONFIG_HASH_EXT, + FW_CONFIG_HASH_EXT, + }, + .num_ext = 8 + }, + + [CORE_SWD_KEY_CERT] = { + .id = CORE_SWD_KEY_CERT, + .opt = "core-swd-cert", + .help_msg = "Core Secure World Key Certificate (output file)", + .cn = "Core Secure World Key Certificate", + .key = SWD_ROT_KEY, + .issuer = CORE_SWD_KEY_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + SWD_ROT_PK_EXT, + CORE_SWD_PK_EXT, + }, + .num_ext = 3 + }, + + [SPMC_CONTENT_CERT] = { + .id = SPMC_CONTENT_CERT, + .opt = "tos-fw-cert", + .help_msg = "SPMC Content Certificate (output file)", + .cn = "SPMC Content Certificate", + .key = CORE_SWD_KEY, + .issuer = SPMC_CONTENT_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + TRUSTED_OS_FW_HASH_EXT, + TRUSTED_OS_FW_CONFIG_HASH_EXT, + }, + .num_ext = 3 + }, + + [SIP_SECURE_PARTITION_CONTENT_CERT] = { + .id = SIP_SECURE_PARTITION_CONTENT_CERT, + .opt = "sip-sp-cert", + .help_msg = "SiP owned Secure Partition Content Certificate (output file)", + .cn = "SiP owned Secure Partition Content Certificate", + .key = CORE_SWD_KEY, + .issuer = SIP_SECURE_PARTITION_CONTENT_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + SP_PKG1_HASH_EXT, + SP_PKG2_HASH_EXT, + SP_PKG3_HASH_EXT, + SP_PKG4_HASH_EXT, + }, + .num_ext = 5 + }, + + [PLAT_KEY_CERT] = { + .id = PLAT_KEY_CERT, + .opt = "plat-key-cert", + .help_msg = "Platform Key Certificate (output file)", + .cn = "Platform Key Certificate", + .key = PROT_KEY, + .issuer = PLAT_KEY_CERT, + .ext = { + NON_TRUSTED_FW_NVCOUNTER_EXT, + PROT_PK_EXT, + PLAT_PK_EXT, + }, + .num_ext = 3 + }, + + [PLAT_SECURE_PARTITION_CONTENT_CERT] = { + .id = PLAT_SECURE_PARTITION_CONTENT_CERT, + .opt = "plat-sp-cert", + .help_msg = "Platform owned Secure Partition Content Certificate (output file)", + .cn = "Platform owned Secure Partition Content Certificate", + .key = PLAT_KEY, + .issuer = PLAT_SECURE_PARTITION_CONTENT_CERT, + .ext = { + NON_TRUSTED_FW_NVCOUNTER_EXT, + SP_PKG5_HASH_EXT, + SP_PKG6_HASH_EXT, + SP_PKG7_HASH_EXT, + SP_PKG8_HASH_EXT, + }, + .num_ext = 5 + }, + + [NON_TRUSTED_FW_CONTENT_CERT] = { + .id = NON_TRUSTED_FW_CONTENT_CERT, + .opt = "nt-fw-cert", + .help_msg = "Non-Trusted Firmware Content Certificate (output file)", + .cn = "Non-Trusted Firmware Content Certificate", + .key = PLAT_KEY, + .issuer = NON_TRUSTED_FW_CONTENT_CERT, + .ext = { + NON_TRUSTED_FW_NVCOUNTER_EXT, + NON_TRUSTED_WORLD_BOOTLOADER_HASH_EXT, + NON_TRUSTED_FW_CONFIG_HASH_EXT, + }, + .num_ext = 3 + }, +}; + +REGISTER_COT(cot_certs); + + +/* Certificate extensions. */ +static ext_t cot_ext[] = { + [TRUSTED_FW_NVCOUNTER_EXT] = { + .oid = TRUSTED_FW_NVCOUNTER_OID, + .opt = "tfw-nvctr", + .help_msg = "Trusted Firmware Non-Volatile counter value", + .sn = "TrustedWorldNVCounter", + .ln = "Trusted World Non-Volatile counter", + .asn1_type = V_ASN1_INTEGER, + .type = EXT_TYPE_NVCOUNTER, + .attr.nvctr_type = NVCTR_TYPE_TFW + }, + + [TRUSTED_BOOT_FW_HASH_EXT] = { + .oid = TRUSTED_BOOT_FW_HASH_OID, + .opt = "tb-fw", + .help_msg = "Trusted Boot Firmware image file", + .sn = "TrustedBootFirmwareHash", + .ln = "Trusted Boot Firmware hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + + [TRUSTED_BOOT_FW_CONFIG_HASH_EXT] = { + .oid = TRUSTED_BOOT_FW_CONFIG_HASH_OID, + .opt = "tb-fw-config", + .help_msg = "Trusted Boot Firmware Config file", + .sn = "TrustedBootFirmwareConfigHash", + .ln = "Trusted Boot Firmware Config hash", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + + [HW_CONFIG_HASH_EXT] = { + .oid = HW_CONFIG_HASH_OID, + .opt = "hw-config", + .help_msg = "HW Config file", + .sn = "HWConfigHash", + .ln = "HW Config hash", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + + [FW_CONFIG_HASH_EXT] = { + .oid = FW_CONFIG_HASH_OID, + .opt = "fw-config", + .help_msg = "Firmware Config file", + .sn = "FirmwareConfigHash", + .ln = "Firmware Config hash", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + + [SWD_ROT_PK_EXT] = { + .oid = SWD_ROT_PK_OID, + .sn = "SWDRoTKey", + .ln = "Secure World Root of Trust Public Key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .attr.key = SWD_ROT_KEY + }, + + [CORE_SWD_PK_EXT] = { + .oid = CORE_SWD_PK_OID, + .sn = "CORESWDKey", + .ln = "Core Secure World Public Key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .attr.key = CORE_SWD_KEY + }, + + [SOC_AP_FW_HASH_EXT] = { + .oid = SOC_AP_FW_HASH_OID, + .opt = "soc-fw", + .help_msg = "SoC AP Firmware image file", + .sn = "SoCAPFirmwareHash", + .ln = "SoC AP Firmware hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + + [SOC_FW_CONFIG_HASH_EXT] = { + .oid = SOC_FW_CONFIG_HASH_OID, + .opt = "soc-fw-config", + .help_msg = "SoC Firmware Config file", + .sn = "SocFirmwareConfigHash", + .ln = "SoC Firmware Config hash", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + + [RMM_HASH_EXT] = { + .oid = RMM_HASH_OID, + .opt = "rmm-fw", + .help_msg = "RMM Firmware image file", + .sn = "RMMFirmwareHash", + .ln = "RMM Firmware hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + + [TRUSTED_OS_FW_HASH_EXT] = { + .oid = TRUSTED_OS_FW_HASH_OID, + .opt = "tos-fw", + .help_msg = "Trusted OS image file", + .sn = "TrustedOSHash", + .ln = "Trusted OS hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + + [TRUSTED_OS_FW_CONFIG_HASH_EXT] = { + .oid = TRUSTED_OS_FW_CONFIG_HASH_OID, + .opt = "tos-fw-config", + .help_msg = "Trusted OS Firmware Config file", + .sn = "TrustedOSFirmwareConfigHash", + .ln = "Trusted OS Firmware Config hash", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + + [SP_PKG1_HASH_EXT] = { + .oid = SP_PKG1_HASH_OID, + .opt = "sp-pkg1", + .help_msg = "Secure Partition Package1 file", + .sn = "SPPkg1Hash", + .ln = "SP Pkg1 hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + [SP_PKG2_HASH_EXT] = { + .oid = SP_PKG2_HASH_OID, + .opt = "sp-pkg2", + .help_msg = "Secure Partition Package2 file", + .sn = "SPPkg2Hash", + .ln = "SP Pkg2 hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + [SP_PKG3_HASH_EXT] = { + .oid = SP_PKG3_HASH_OID, + .opt = "sp-pkg3", + .help_msg = "Secure Partition Package3 file", + .sn = "SPPkg3Hash", + .ln = "SP Pkg3 hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + [SP_PKG4_HASH_EXT] = { + .oid = SP_PKG4_HASH_OID, + .opt = "sp-pkg4", + .help_msg = "Secure Partition Package4 file", + .sn = "SPPkg4Hash", + .ln = "SP Pkg4 hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + + [PROT_PK_EXT] = { + .oid = PROT_PK_OID, + .sn = "PlatformRoTKey", + .ln = "Platform Root of Trust Public Key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .attr.key = PROT_KEY + }, + + [PLAT_PK_EXT] = { + .oid = PLAT_PK_OID, + .sn = "PLATKey", + .ln = "Platform Public Key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .attr.key = PLAT_KEY + }, + + [SP_PKG5_HASH_EXT] = { + .oid = SP_PKG5_HASH_OID, + .opt = "sp-pkg5", + .help_msg = "Secure Partition Package5 file", + .sn = "SPPkg5Hash", + .ln = "SP Pkg5 hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + [SP_PKG6_HASH_EXT] = { + .oid = SP_PKG6_HASH_OID, + .opt = "sp-pkg6", + .help_msg = "Secure Partition Package6 file", + .sn = "SPPkg6Hash", + .ln = "SP Pkg6 hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + [SP_PKG7_HASH_EXT] = { + .oid = SP_PKG7_HASH_OID, + .opt = "sp-pkg7", + .help_msg = "Secure Partition Package7 file", + .sn = "SPPkg7Hash", + .ln = "SP Pkg7 hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + [SP_PKG8_HASH_EXT] = { + .oid = SP_PKG8_HASH_OID, + .opt = "sp-pkg8", + .help_msg = "Secure Partition Package8 file", + .sn = "SPPkg8Hash", + .ln = "SP Pkg8 hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + + [NON_TRUSTED_FW_NVCOUNTER_EXT] = { + .oid = NON_TRUSTED_FW_NVCOUNTER_OID, + .opt = "ntfw-nvctr", + .help_msg = "Non-Trusted Firmware Non-Volatile counter value", + .sn = "NormalWorldNVCounter", + .ln = "Non-Trusted Firmware Non-Volatile counter", + .asn1_type = V_ASN1_INTEGER, + .type = EXT_TYPE_NVCOUNTER, + .attr.nvctr_type = NVCTR_TYPE_NTFW + }, + + [NON_TRUSTED_WORLD_BOOTLOADER_HASH_EXT] = { + .oid = NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID, + .opt = "nt-fw", + .help_msg = "Non-Trusted World Bootloader image file", + .sn = "NonTrustedWorldBootloaderHash", + .ln = "Non-Trusted World hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + + [NON_TRUSTED_FW_CONFIG_HASH_EXT] = { + .oid = NON_TRUSTED_FW_CONFIG_HASH_OID, + .opt = "nt-fw-config", + .help_msg = "Non Trusted OS Firmware Config file", + .sn = "NonTrustedOSFirmwareConfigHash", + .ln = "Non-Trusted OS Firmware Config hash", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, +}; + +REGISTER_EXTENSIONS(cot_ext); + +/* Keys used to establish the chain of trust. */ +static key_t cot_keys[] = { + [ROT_KEY] = { + .id = ROT_KEY, + .opt = "rot-key", + .help_msg = "Root Of Trust key (input/output file)", + .desc = "Root Of Trust key" + }, + + [SWD_ROT_KEY] = { + .id = SWD_ROT_KEY, + .opt = "swd-rot-key", + .help_msg = "Secure World Root of Trust key", + .desc = "Secure World Root of Trust key" + }, + + [CORE_SWD_KEY] = { + .id = CORE_SWD_KEY, + .opt = "core-swd-key", + .help_msg = "Core Secure World key", + .desc = "Core Secure World key" + }, + + [PROT_KEY] = { + .id = PROT_KEY, + .opt = "prot-key", + .help_msg = "Platform Root of Trust key", + .desc = "Platform Root of Trust key" + }, + + [PLAT_KEY] = { + .id = PLAT_KEY, + .opt = "plat-key", + .help_msg = "Platform key", + .desc = "Platform key" + }, +}; + +REGISTER_KEYS(cot_keys); diff --git a/tools/cert_create/src/cca/cot.mk b/tools/cert_create/src/cca/cot.mk new file mode 100644 index 000000000..d0c80bbdd --- /dev/null +++ b/tools/cert_create/src/cca/cot.mk @@ -0,0 +1,10 @@ +# +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +PLAT_MSG := Confidential Compute Architecture root of trust +PLAT_INCLUDE := ../../include/tools_share + +OBJECTS += src/cca/cot.o diff --git a/tools/cert_create/src/cert.c b/tools/cert_create/src/cert.c index 67ae1d6ee..2513213a6 100644 --- a/tools/cert_create/src/cert.c +++ b/tools/cert_create/src/cert.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,7 +39,11 @@ int rand_serial(BIGNUM *b, ASN1_INTEGER *ai) if (!btmp) return 0; +#if USING_OPENSSL3 if (!BN_rand(btmp, SERIAL_RAND_BITS, 0, 0)) +#else + if (!BN_pseudo_rand(btmp, SERIAL_RAND_BITS, 0, 0)) +#endif goto error; if (ai && !BN_to_ASN1_INTEGER(btmp, ai)) goto error; @@ -272,3 +276,19 @@ cert_t *cert_get_by_opt(const char *opt) return NULL; } + +void cert_cleanup(void) +{ + unsigned int i; + + for (i = 0; i < num_certs; i++) { + if (certs[i].fn != NULL) { + void *ptr = (void *)certs[i].fn; + + certs[i].fn = NULL; + free(ptr); + } + } + free(certs); +} + diff --git a/tools/cert_create/src/ext.c b/tools/cert_create/src/ext.c index 28821238f..acf57a476 100644 --- a/tools/cert_create/src/ext.c +++ b/tools/cert_create/src/ext.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -315,3 +315,20 @@ ext_t *ext_get_by_opt(const char *opt) return NULL; } + +void ext_cleanup(void) +{ + unsigned int i; + + for (i = 0; i < num_extensions; i++) { + if (extensions[i].arg != NULL) { + void *ptr = (void *)extensions[i].arg; + + extensions[i].arg = NULL; + free(ptr); + } + } + free(extensions); + X509V3_EXT_cleanup(); +} + diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c index 2857a3b07..487777b67 100644 --- a/tools/cert_create/src/key.c +++ b/tools/cert_create/src/key.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,7 @@ key_t *keys; unsigned int num_keys; +#if !USING_OPENSSL3 /* * Create a new key container */ @@ -37,9 +38,11 @@ int key_new(key_t *key) return 1; } +#endif static int key_create_rsa(key_t *key, int key_bits) { +#if USING_OPENSSL3 EVP_PKEY *rsa = EVP_RSA_gen(key_bits); if (rsa == NULL) { printf("Cannot generate RSA key\n"); @@ -47,26 +50,128 @@ static int key_create_rsa(key_t *key, int key_bits) } key->key = rsa; return 1; +#else + BIGNUM *e; + RSA *rsa = NULL; + + e = BN_new(); + if (e == NULL) { + printf("Cannot create RSA exponent\n"); + return 0; + } + + if (!BN_set_word(e, RSA_F4)) { + printf("Cannot assign RSA exponent\n"); + goto err2; + } + + rsa = RSA_new(); + if (rsa == NULL) { + printf("Cannot create RSA key\n"); + goto err2; + } + + if (!RSA_generate_key_ex(rsa, key_bits, e, NULL)) { + printf("Cannot generate RSA key\n"); + goto err; + } + + if (!EVP_PKEY_assign_RSA(key->key, rsa)) { + printf("Cannot assign RSA key\n"); + goto err; + } + + BN_free(e); + return 1; + +err: + RSA_free(rsa); +err2: + BN_free(e); + return 0; +#endif } #ifndef OPENSSL_NO_EC -static int key_create_ecdsa(key_t *key, int key_bits) +#if USING_OPENSSL3 +static int key_create_ecdsa(key_t *key, int key_bits, const char *curve) { - EVP_PKEY *ec = EVP_EC_gen("prime256v1"); + EVP_PKEY *ec = EVP_EC_gen(curve); if (ec == NULL) { printf("Cannot generate EC key\n"); return 0; } + key->key = ec; return 1; } + +static int key_create_ecdsa_nist(key_t *key, int key_bits) +{ + return key_create_ecdsa(key, key_bits, "prime256v1"); +} + +static int key_create_ecdsa_brainpool_r(key_t *key, int key_bits) +{ + return key_create_ecdsa(key, key_bits, "brainpoolP256r1"); +} + +static int key_create_ecdsa_brainpool_t(key_t *key, int key_bits) +{ + return key_create_ecdsa(key, key_bits, "brainpoolP256t1"); +} +#else +static int key_create_ecdsa(key_t *key, int key_bits, const int curve_id) +{ + EC_KEY *ec; + + ec = EC_KEY_new_by_curve_name(curve_id); + if (ec == NULL) { + printf("Cannot create EC key\n"); + return 0; + } + if (!EC_KEY_generate_key(ec)) { + printf("Cannot generate EC key\n"); + goto err; + } + EC_KEY_set_flags(ec, EC_PKEY_NO_PARAMETERS); + EC_KEY_set_asn1_flag(ec, OPENSSL_EC_NAMED_CURVE); + if (!EVP_PKEY_assign_EC_KEY(key->key, ec)) { + printf("Cannot assign EC key\n"); + goto err; + } + + return 1; + +err: + EC_KEY_free(ec); + return 0; +} + +static int key_create_ecdsa_nist(key_t *key, int key_bits) +{ + return key_create_ecdsa(key, key_bits, NID_X9_62_prime256v1); +} + +static int key_create_ecdsa_brainpool_r(key_t *key, int key_bits) +{ + return key_create_ecdsa(key, key_bits, NID_brainpoolP256r1); +} + +static int key_create_ecdsa_brainpool_t(key_t *key, int key_bits) +{ + return key_create_ecdsa(key, key_bits, NID_brainpoolP256t1); +} +#endif /* USING_OPENSSL3 */ #endif /* OPENSSL_NO_EC */ typedef int (*key_create_fn_t)(key_t *key, int key_bits); static const key_create_fn_t key_create_fn[KEY_ALG_MAX_NUM] = { - key_create_rsa, /* KEY_ALG_RSA */ + [KEY_ALG_RSA] = key_create_rsa, #ifndef OPENSSL_NO_EC - key_create_ecdsa, /* KEY_ALG_ECDSA */ + [KEY_ALG_ECDSA_NIST] = key_create_ecdsa_nist, + [KEY_ALG_ECDSA_BRAINPOOL_R] = key_create_ecdsa_brainpool_r, + [KEY_ALG_ECDSA_BRAINPOOL_T] = key_create_ecdsa_brainpool_t, #endif /* OPENSSL_NO_EC */ }; @@ -194,3 +299,20 @@ key_t *key_get_by_opt(const char *opt) return NULL; } + +void key_cleanup(void) +{ + unsigned int i; + + for (i = 0; i < num_keys; i++) { + EVP_PKEY_free(keys[i].key); + if (keys[i].fn != NULL) { + void *ptr = keys[i].fn; + + free(ptr); + keys[i].fn = NULL; + } + } + free(keys); +} + diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c index b39378ca9..2ab6bcfd9 100644 --- a/tools/cert_create/src/main.c +++ b/tools/cert_create/src/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -84,7 +84,9 @@ static char *strdup(const char *str) static const char *key_algs_str[] = { [KEY_ALG_RSA] = "rsa", #ifndef OPENSSL_NO_EC - [KEY_ALG_ECDSA] = "ecdsa" + [KEY_ALG_ECDSA_NIST] = "ecdsa", + [KEY_ALG_ECDSA_BRAINPOOL_R] = "ecdsa-brainpool-regular", + [KEY_ALG_ECDSA_BRAINPOOL_T] = "ecdsa-brainpool-twisted", #endif /* OPENSSL_NO_EC */ }; @@ -106,7 +108,7 @@ static void print_help(const char *cmd, const struct option *long_opt) printf("\n\n"); printf("The certificate generation tool loads the binary images and\n" - "optionally the RSA keys, and outputs the key and content\n" + "optionally the RSA or ECC keys, and outputs the key and content\n" "certificates properly signed to implement the chain of trust.\n" "If keys are provided, they must be in PEM format.\n" "Certificates are generated in DER format.\n"); @@ -267,7 +269,8 @@ static const cmd_opt_t common_cmd_opt[] = { }, { { "key-alg", required_argument, NULL, 'a' }, - "Key algorithm: 'rsa' (default)- RSAPSS scheme as per PKCS#1 v2.1, 'ecdsa'" + "Key algorithm: 'rsa' (default)- RSAPSS scheme as per PKCS#1 v2.1, " \ + "'ecdsa', 'ecdsa-brainpool-regular', 'ecdsa-brainpool-twisted'" }, { { "key-size", required_argument, NULL, 'b' }, @@ -430,10 +433,12 @@ int main(int argc, char *argv[]) /* Load private keys from files (or generate new ones) */ for (i = 0 ; i < num_keys ; i++) { +#if !USING_OPENSSL3 if (!key_new(&keys[i])) { ERROR("Failed to allocate key container\n"); exit(1); } +#endif /* First try to load the key from disk */ if (key_load(&keys[i], &err_code)) { @@ -594,9 +599,7 @@ int main(int argc, char *argv[]) /* If we got here, then we must have filled the key array completely. * We can then safely call free on all of the keys in the array */ - for (i = 0; i < num_keys; i++) { - EVP_PKEY_free(keys[i].key); - } + key_cleanup(); #ifndef OPENSSL_NO_ENGINE ENGINE_cleanup(); @@ -605,30 +608,10 @@ int main(int argc, char *argv[]) /* We allocated strings through strdup, so now we have to free them */ - for (i = 0; i < num_keys; i++) { - if (keys[i].fn != NULL) { - void *ptr = keys[i].fn; - - keys[i].fn = NULL; - free(ptr); - } - } - for (i = 0; i < num_extensions; i++) { - if (extensions[i].arg != NULL) { - void *ptr = (void *)extensions[i].arg; - extensions[i].arg = NULL; - free(ptr); - } - } - for (i = 0; i < num_certs; i++) { - if (certs[i].fn != NULL) { - void *ptr = (void *)certs[i].fn; + ext_cleanup(); - certs[i].fn = NULL; - free(ptr); - } - } + cert_cleanup(); return 0; } diff --git a/tools/cert_create/src/sha.c b/tools/cert_create/src/sha.c index 06ef3601b..bb750d4e3 100644 --- a/tools/cert_create/src/sha.c +++ b/tools/cert_create/src/sha.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,16 @@ #include <stdio.h> #include "debug.h" #include "key.h" +#if USING_OPENSSL3 #include <openssl/evp.h> #include <openssl/obj_mac.h> +#else +#include <openssl/sha.h> +#endif #define BUFFER_SIZE 256 +#if USING_OPENSSL3 static int get_algorithm_nid(int hash_alg) { int nids[] = {NID_sha256, NID_sha384, NID_sha512}; @@ -20,16 +25,22 @@ static int get_algorithm_nid(int hash_alg) } return nids[hash_alg]; } +#endif int sha_file(int md_alg, const char *filename, unsigned char *md) { FILE *inFile; + int bytes; + unsigned char data[BUFFER_SIZE]; +#if USING_OPENSSL3 EVP_MD_CTX *mdctx; const EVP_MD *md_type; - int bytes; int alg_nid; unsigned int total_bytes; - unsigned char data[BUFFER_SIZE]; +#else + SHA256_CTX shaContext; + SHA512_CTX sha512Context; +#endif if ((filename == NULL) || (md == NULL)) { ERROR("%s(): NULL argument\n", __func__); @@ -42,6 +53,8 @@ int sha_file(int md_alg, const char *filename, unsigned char *md) return 0; } +#if USING_OPENSSL3 + mdctx = EVP_MD_CTX_new(); if (mdctx == NULL) { fclose(inFile); @@ -74,5 +87,32 @@ err: fclose(inFile); EVP_MD_CTX_free(mdctx); return 0; + +#else + + if (md_alg == HASH_ALG_SHA384) { + SHA384_Init(&sha512Context); + while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { + SHA384_Update(&sha512Context, data, bytes); + } + SHA384_Final(md, &sha512Context); + } else if (md_alg == HASH_ALG_SHA512) { + SHA512_Init(&sha512Context); + while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { + SHA512_Update(&sha512Context, data, bytes); + } + SHA512_Final(md, &sha512Context); + } else { + SHA256_Init(&shaContext); + while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { + SHA256_Update(&shaContext, data, bytes); + } + SHA256_Final(md, &shaContext); + } + + fclose(inFile); + return 1; + +#endif } diff --git a/tools/conventional-changelog-tf-a/package.json b/tools/conventional-changelog-tf-a/package.json index 0008b535c..3dd98774a 100644 --- a/tools/conventional-changelog-tf-a/package.json +++ b/tools/conventional-changelog-tf-a/package.json @@ -1,6 +1,6 @@ { "name": "conventional-changelog-tf-a", - "version": "2.7.0", + "version": "2.8.0", "license": "BSD-3-Clause", "private": true, "main": "index.js", diff --git a/tools/encrypt_fw/Makefile b/tools/encrypt_fw/Makefile index 60bd8ea74..2939b142b 100644 --- a/tools/encrypt_fw/Makefile +++ b/tools/encrypt_fw/Makefile @@ -11,15 +11,21 @@ ENCTOOL ?= encrypt_fw${BIN_EXT} BINARY := $(notdir ${ENCTOOL}) OPENSSL_DIR := /usr + +MAKE_HELPERS_DIRECTORY := ../../make_helpers/ +include ${MAKE_HELPERS_DIRECTORY}build_macros.mk +include ${MAKE_HELPERS_DIRECTORY}build_env.mk +include ${MAKE_HELPERS_DIRECTORY}defaults.mk + OBJECTS := src/encrypt.o \ src/cmd_opt.o \ src/main.o HOSTCCFLAGS := -Wall -std=c99 -MAKE_HELPERS_DIRECTORY := ../../make_helpers/ -include ${MAKE_HELPERS_DIRECTORY}build_macros.mk -include ${MAKE_HELPERS_DIRECTORY}build_env.mk +# Select OpenSSL version flag according to the OpenSSL build selected +# from setting the OPENSSL_DIR path. +$(eval $(call SELECT_OPENSSL_API_VERSION)) ifeq (${DEBUG},1) HOSTCCFLAGS += -g -O0 -DDEBUG -DLOG_LEVEL=40 @@ -36,6 +42,12 @@ else Q := endif +HOSTCCFLAGS += ${DEFINES} +# USING_OPENSSL3 flag will be added to the HOSTCCFLAGS variable with the proper +# computed value. +HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3) + + # Make soft links and include from local directory otherwise wrong headers # could get pulled in from firmware tree. INC_DIR := -I ./include -I ../../include/tools_share -I ${OPENSSL_DIR}/include @@ -51,11 +63,11 @@ LIB := -lssl -lcrypto HOSTCC ?= gcc -.PHONY: all clean realclean +.PHONY: all clean realclean --openssl all: ${BINARY} -${BINARY}: ${OBJECTS} Makefile +${BINARY}: --openssl ${OBJECTS} Makefile @echo " HOSTLD $@" @echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__;' | \ ${HOSTCC} -c ${HOSTCCFLAGS} -xc - -o src/build_msg.o @@ -65,6 +77,11 @@ ${BINARY}: ${OBJECTS} Makefile @echo " HOSTCC $<" ${Q}${HOSTCC} -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@ +--openssl: +ifeq ($(DEBUG),1) + @echo "Selected OpenSSL version: ${OPENSSL_CURRENT_VER}" +endif + clean: $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS}) diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile index e6aeba95b..d7e0fe5be 100644 --- a/tools/fiptool/Makefile +++ b/tools/fiptool/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -7,6 +7,7 @@ MAKE_HELPERS_DIRECTORY := ../../make_helpers/ include ${MAKE_HELPERS_DIRECTORY}build_macros.mk include ${MAKE_HELPERS_DIRECTORY}build_env.mk +include ${MAKE_HELPERS_DIRECTORY}defaults.mk FIPTOOL ?= fiptool${BIN_EXT} PROJECT := $(notdir ${FIPTOOL}) @@ -23,6 +24,15 @@ else HOSTCCFLAGS += -O2 endif +# Select OpenSSL version flag according to the OpenSSL build selected +# from setting the OPENSSL_DIR path. +$(eval $(call SELECT_OPENSSL_API_VERSION)) + +HOSTCCFLAGS += ${DEFINES} +# USING_OPENSSL3 flag will be added to the HOSTCCFLAGS variable with the proper +# computed value. +HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3) + # Include library directories where OpenSSL library files are located. # For a normal installation (i.e.: when ${OPENSSL_DIR} = /usr or # /usr/local), binaries are located under the ${OPENSSL_DIR}/lib/ @@ -51,11 +61,11 @@ ifneq (,$(wildcard ${PLAT_FIPTOOL_HELPER_MK})) include ${PLAT_FIPTOOL_HELPER_MK} endif -.PHONY: all clean distclean +.PHONY: all clean distclean --openssl all: ${PROJECT} -${PROJECT}: ${OBJECTS} Makefile +${PROJECT}: --openssl ${OBJECTS} Makefile @echo " HOSTLD $@" ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} @${ECHO_BLANK_LINE} @@ -66,5 +76,11 @@ ${PROJECT}: ${OBJECTS} Makefile @echo " HOSTCC $<" ${Q}${HOSTCC} -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@ +--openssl: +ifeq ($(DEBUG),1) + @echo "Selected OpenSSL version: ${OPENSSL_CURRENT_VER}" +endif + + clean: $(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS}) diff --git a/tools/fiptool/tbbr_config.c b/tools/fiptool/tbbr_config.c index 4998bb2c2..cdbf38959 100644 --- a/tools/fiptool/tbbr_config.c +++ b/tools/fiptool/tbbr_config.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -172,6 +172,21 @@ toc_entry_t toc_entries[] = { .cmdline_name = "plat-sp-cert" }, { + .name = "CCA Content Certificate", + .uuid = UUID_CCA_CONTENT_CERT, + .cmdline_name = "cca-cert" + }, + { + .name = "Core Secure World Key Certificate", + .uuid = UUID_CORE_SWD_KEY_CERT, + .cmdline_name = "core-swd-cert" + }, + { + .name = "Platform Key Certificate", + .uuid = UUID_PLAT_KEY_CERT, + .cmdline_name = "plat-key-cert" + }, + { .name = NULL, .uuid = { {0} }, .cmdline_name = NULL, diff --git a/tools/sptool/sp_mk_generator.py b/tools/sptool/sp_mk_generator.py index f4045d340..f3af584af 100644 --- a/tools/sptool/sp_mk_generator.py +++ b/tools/sptool/sp_mk_generator.py @@ -90,7 +90,7 @@ def get_sp_pkg(sp, args :dict): def is_line_in_sp_gen(line, args :dict): with open(args["sp_gen_mk"], "r") as f: sppkg_rule = [l for l in f if line in l] - return len(sppkg_rule) is not 0 + return len(sppkg_rule) != 0 def get_file_from_layout(node): ''' Helper to fetch a file path from sp_layout.json. ''' @@ -145,7 +145,7 @@ def gen_sptool_args(sp_layout, sp, args :dict): sptool_args += f" --img-offset {image_offset}" if image_offset is not None else "" sptool_args += f" -o {sp_pkg}" sppkg_rule = f''' -{sp_pkg}: +{sp_pkg}: {sp_dtb} \t$(Q)echo Generating {sp_pkg} \t$(Q)$(PYTHON) $(SPTOOL) {sptool_args} ''' @@ -196,11 +196,11 @@ def gen_fiptool_args(sp_layout, sp, args :dict): ''' Generate arguments for the FIP Tool. ''' if "uuid" in sp_layout[sp]: # Extract the UUID from the JSON file if the SP entry has a 'uuid' field - uuid_std = uuid.UUID(data[key]['uuid']) + uuid_std = uuid.UUID(sp_layout[sp]['uuid']) else: with open(get_sp_manifest_full_path(sp_layout[sp], args), "r") as pm_f: uuid_lines = [l for l in pm_f if 'uuid' in l] - assert(len(uuid_lines) is 1) + assert(len(uuid_lines) == 1) # The uuid field in SP manifest is the little endian representation # mapped to arguments as described in SMCCC section 5.3. # Convert each unsigned integer value to a big endian representation |
