[dev][interrupt] Move gic registers to separate include

Bug: 138743238
Change-Id: I76a0d1724219d0eeb27c358f3e6b3a4e7f4771e6

2 files changed, 76 insertions, 42 deletions

diff --git a/dev/interrupt/arm_gic/arm_gic.c b/dev/interrupt/arm_gic/arm_gic.c
index 1a5bb133..2366445e 100644
--- a/dev/interrupt/arm_gic/arm_gic.c
+++ b/dev/interrupt/arm_gic/arm_gic.c
@@ -40,15 +40,15 @@
 #include <lib/sm/sm_err.h>
 #endif
 
+#include "arm_gic_common.h"
+
 #define LOCAL_TRACE 0
 
 #if ARCH_ARM
-#include <arch/arm.h>
 #define iframe arm_iframe
 #define IFRAME_PC(frame) ((frame)->pc)
 #endif
 #if ARCH_ARM64
-#include <arch/arm64.h>
 #define iframe arm64_iframe_short
 #define IFRAME_PC(frame) ((frame)->elr)
 #endif
@@ -126,46 +126,6 @@ void register_int_handler(unsigned int vector, int_handler handler, void *arg)
     spin_unlock_restore(&gicd_lock, state, GICD_LOCK_FLAGS);
 }
 
-#define GICCREG_READ(gic, reg) (*REG32(GICBASE(gic) + (reg)))
-#define GICCREG_WRITE(gic, reg, val) (*REG32(GICBASE(gic) + (reg)) = (val))
-/* main cpu regs */
-#define GICC_CTLR               (GICC_OFFSET + 0x0000)
-#define GICC_PMR                (GICC_OFFSET + 0x0004)
-#define GICC_BPR                (GICC_OFFSET + 0x0008)
-#define GICC_IAR                (GICC_OFFSET + 0x000c)
-#define GICC_EOIR               (GICC_OFFSET + 0x0010)
-#define GICC_RPR                (GICC_OFFSET + 0x0014)
-#define GICC_HPPIR              (GICC_OFFSET + 0x0018)
-#define GICC_APBR               (GICC_OFFSET + 0x001c)
-#define GICC_AIAR               (GICC_OFFSET + 0x0020)
-#define GICC_AEOIR              (GICC_OFFSET + 0x0024)
-#define GICC_AHPPIR             (GICC_OFFSET + 0x0028)
-#define GICC_APR(n)             (GICC_OFFSET + 0x00d0 + (n) * 4)
-#define GICC_NSAPR(n)           (GICC_OFFSET + 0x00e0 + (n) * 4)
-#define GICC_IIDR               (GICC_OFFSET + 0x00fc)
-#define GICC_DIR                (GICC_OFFSET + 0x1000)
-
-#define GICDREG_READ(gic, reg) (*REG32(GICBASE(gic) + (reg)))
-#define GICDREG_WRITE(gic, reg, val) (*REG32(GICBASE(gic) + (reg)) = (val))
-/* distribution regs */
-#define GICD_CTLR               (GICD_OFFSET + 0x000)
-#define GICD_TYPER              (GICD_OFFSET + 0x004)
-#define GICD_IIDR               (GICD_OFFSET + 0x008)
-#define GICD_IGROUPR(n)         (GICD_OFFSET + 0x080 + (n) * 4)
-#define GICD_ISENABLER(n)       (GICD_OFFSET + 0x100 + (n) * 4)
-#define GICD_ICENABLER(n)       (GICD_OFFSET + 0x180 + (n) * 4)
-#define GICD_ISPENDR(n)         (GICD_OFFSET + 0x200 + (n) * 4)
-#define GICD_ICPENDR(n)         (GICD_OFFSET + 0x280 + (n) * 4)
-#define GICD_ISACTIVER(n)       (GICD_OFFSET + 0x300 + (n) * 4)
-#define GICD_ICACTIVER(n)       (GICD_OFFSET + 0x380 + (n) * 4)
-#define GICD_IPRIORITYR(n)      (GICD_OFFSET + 0x400 + (n) * 4)
-#define GICD_ITARGETSR(n)       (GICD_OFFSET + 0x800 + (n) * 4)
-#define GICD_ICFGR(n)           (GICD_OFFSET + 0xc00 + (n) * 4)
-#define GICD_NSACR(n)           (GICD_OFFSET + 0xe00 + (n) * 4)
-#define GICD_SGIR               (GICD_OFFSET + 0xf00)
-#define GICD_CPENDSGIR(n)       (GICD_OFFSET + 0xf10 + (n) * 4)
-#define GICD_SPENDSGIR(n)       (GICD_OFFSET + 0xf20 + (n) * 4)
-
 #define GIC_REG_COUNT(bit_per_reg) DIV_ROUND_UP(MAX_INT, (bit_per_reg))
 #define DEFINE_GIC_SHADOW_REG(name, bit_per_reg, init_val, init_from) \
     uint32_t (name)[GIC_REG_COUNT(bit_per_reg)] = { \
diff --git a/dev/interrupt/arm_gic/arm_gic_common.h b/dev/interrupt/arm_gic/arm_gic_common.h
new file mode 100644
index 00000000..4c20d7c3
--- /dev/null
+++ b/dev/interrupt/arm_gic/arm_gic_common.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2012-2019 LK Trusty Authors. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#pragma once
+
+#include <stdint.h>
+#include <platform/gic.h>
+#include <reg.h>
+
+#if ARCH_ARM
+#include <arch/arm.h>
+#endif
+#if ARCH_ARM64
+#include <arch/arm64.h>
+#endif
+
+#define GICCREG_READ(gic, reg) (*REG32(GICBASE(gic) + (reg)))
+#define GICCREG_WRITE(gic, reg, val) (*REG32(GICBASE(gic) + (reg)) = (val))
+/* main cpu regs */
+#define GICC_CTLR               (GICC_OFFSET + 0x0000)
+#define GICC_PMR                (GICC_OFFSET + 0x0004)
+#define GICC_BPR                (GICC_OFFSET + 0x0008)
+#define GICC_IAR                (GICC_OFFSET + 0x000c)
+#define GICC_EOIR               (GICC_OFFSET + 0x0010)
+#define GICC_RPR                (GICC_OFFSET + 0x0014)
+#define GICC_HPPIR              (GICC_OFFSET + 0x0018)
+#define GICC_APBR               (GICC_OFFSET + 0x001c)
+#define GICC_AIAR               (GICC_OFFSET + 0x0020)
+#define GICC_AEOIR              (GICC_OFFSET + 0x0024)
+#define GICC_AHPPIR             (GICC_OFFSET + 0x0028)
+#define GICC_APR(n)             (GICC_OFFSET + 0x00d0 + (n) * 4)
+#define GICC_NSAPR(n)           (GICC_OFFSET + 0x00e0 + (n) * 4)
+#define GICC_IIDR               (GICC_OFFSET + 0x00fc)
+#define GICC_DIR                (GICC_OFFSET + 0x1000)
+
+#define GICDREG_READ(gic, reg) (*REG32(GICBASE(gic) + (reg)))
+#define GICDREG_WRITE(gic, reg, val) (*REG32(GICBASE(gic) + (reg)) = (val))
+/* distribution regs */
+#define GICD_CTLR               (GICD_OFFSET + 0x000)
+#define GICD_TYPER              (GICD_OFFSET + 0x004)
+#define GICD_IIDR               (GICD_OFFSET + 0x008)
+#define GICD_IGROUPR(n)         (GICD_OFFSET + 0x080 + (n) * 4)
+#define GICD_ISENABLER(n)       (GICD_OFFSET + 0x100 + (n) * 4)
+#define GICD_ICENABLER(n)       (GICD_OFFSET + 0x180 + (n) * 4)
+#define GICD_ISPENDR(n)         (GICD_OFFSET + 0x200 + (n) * 4)
+#define GICD_ICPENDR(n)         (GICD_OFFSET + 0x280 + (n) * 4)
+#define GICD_ISACTIVER(n)       (GICD_OFFSET + 0x300 + (n) * 4)
+#define GICD_ICACTIVER(n)       (GICD_OFFSET + 0x380 + (n) * 4)
+#define GICD_IPRIORITYR(n)      (GICD_OFFSET + 0x400 + (n) * 4)
+#define GICD_ITARGETSR(n)       (GICD_OFFSET + 0x800 + (n) * 4)
+#define GICD_ICFGR(n)           (GICD_OFFSET + 0xc00 + (n) * 4)
+#define GICD_NSACR(n)           (GICD_OFFSET + 0xe00 + (n) * 4)
+#define GICD_SGIR               (GICD_OFFSET + 0xf00)
+#define GICD_CPENDSGIR(n)       (GICD_OFFSET + 0xf10 + (n) * 4)
+#define GICD_SPENDSGIR(n)       (GICD_OFFSET + 0xf20 + (n) * 4)