aboutsummaryrefslogtreecommitdiff
path: root/dev/interrupt
AgeCommit message (Expand)Author
2024-04-18dev: interrupt: arm_gic: Fix ubsan errorArve Hjønnevåg
2024-03-25trusty:mmu: Make writable mappings non-executableMike McTernan
2023-10-26dev: interrupt: arm_gic: Add init checkArve Hjønnevåg
2023-10-16dev: interrupt: x86_lapic: Fix PIC interrupt deliveryArve Hjønnevåg
2023-08-24Update irq vector assert from > 32 to >= 32. 32 is a valid irq vector.Serena Zhou
2023-08-17trusty:gic: allow building with v4 and fix GICR per CPU offsetMike McTernan
2023-07-21[dev][interrupt] Fix compile error when GIC_VERSION <= 2Nick Bray
2023-07-21[dev][interrupt] Remove support for FIQ debuggingNick Bray
2023-06-19lk:arm_gic: save 1 instruction in sm_intc_fiq_enter()Mike McTernan
2022-10-18Fixup a format specifiers for muslDaniel Houck
2022-09-28Switch to PRIxPTR format specifier macrosAyrton Munoz
2022-08-22[dev][interrupt][arm_gic] Move assert to allow doorbell usageDonnie Pollitz
2022-08-12[GICv3] Poll for RWP bit after updating GICD_ICENABLER<n>Michael Ryleev
2022-02-01[dev][interrupt][arm_gic] Fix GICD_* offsets for v3Andrei Homescu
2022-02-01[dev][interrupt][arm_gic] Fix arm_gic_init for GICv3Andrei Homescu
2022-01-29[dev][interrupt][arm_gic] Get GIC base addresses at runtimeAndrei Homescu
2021-02-08[dev][interrupt][arm_gic] Add DSB after igrpen writeArve Hjønnevåg
2020-03-18[dev][interrupt][arm_gic/x86_lapic]: Include missing dependenciesWenhao Wang
2020-03-16Fix no-SMP builds with GICv3Matthew Maurer
2020-03-16arm_gic: Trigger SGIs with GICv3 affinity routingMatthew Maurer
2020-03-13arm_gic: Enable SGIs when registering handlerMatthew Maurer
2020-01-31Make GIC FIQ suspend/resume UBSan cleanMatthew Maurer
2019-12-04[dev][interrupt] Add suspend/resume hooks for GICv3Michael Ryleev
2019-11-26[dev][interrupt][x86_lapic] Add sm_intc_enable_interrupts stubZhong,Fangjian
2019-11-21[dev][interrupt][arm_gic] gicv3 doorbell interrupt supportArve Hjønnevåg
2019-11-21[dev][interrupt] Add initial support for GICv3Michael Ryleev
2019-11-21[dev][interrupt] Add definition of GICv3 registersMichael Ryleev
2019-11-21[dev][interrupt] Move gic registers to separate includeMichael Ryleev
2019-11-21[arch][arm64] Modify GIC interface to read/writeHaoran.Wang
2019-11-19[dev][interrupt] Rename "smc32_args_t" to "struct smc32_args"Nick Bray
2019-09-27[dev][interrupt] Add x86 interrupt handling supportZhong,Fangjian
2019-09-25[dev][interrupt][x86_lapic] Bug fix on X1 Local APIC write registerZhong,Fangjian
2019-06-27[arch][arm/arm64] Add ARM_MERGE_FIQ_IRQ build flagArve Hjønnevåg
2019-04-18[dev][interrupt] Add x86 Local APIC supportZhong,Fangjian
2019-04-11Use unsigned flagsMatthew Maurer
2018-12-20[dev][interrupt] Add x86 interrupt call stubZhong,Fangjian
2018-10-08Remove unneeded architecture-specific files.Nick Bray
2018-03-02[include][shared][lk][macros] Move DIV_ROUND_UP to macros.hRoberto Pereira
2017-12-01[dev][interrupt][arm_gic] Fix fiq suspend/resumeArve Hjønnevåg
2016-02-14[vim] remove vim expandtab comments on most of the filesTravis Geiselbrecht
2016-02-14[style] mass reformat all the non external code to 4 space indentsTravis Geiselbrecht
2015-10-19[make] remove the need for a module to manually add $(LOCAL_DIR)/include to t...Travis Geiselbrecht
2015-09-20[arch][or1k] get working after SMP changesM1cha
2015-09-20[dev][arm_gic] fix warning in arm64 by adding arm/arm64 specific iframe codeTravis Geiselbrecht
2015-05-13[dev][interrupt][arm_gic] Fix fiq code to get cpu number from arch_curr_cpu_numArve Hjønnevåg
2015-05-13[dev][interrupt][arm_gic] Call sm_handle_fiq from platform_fiqArve Hjønnevåg
2015-05-13[dev][interrupt][arm_gic] Enable ns interrupts if WITH_LIB_SM is setArve Hjønnevåg
2015-05-13[dev][interrupt][arm_gic] Add trace printf for irq numbers returned to nsArve Hjønnevåg
2015-03-27[init][smp] have secondary init run in arch code up to threading, and complet...Travis Geiselbrecht
2015-03-27[dev][arm_gic] call the appropriate init routine for secondary cpus coming ou...Travis Geiselbrecht
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-11 18:41:55 +0000