diff options
author | Sricharan R <r.sricharan@ti.com> | 2013-05-28 10:58:25 +0530 |
---|---|---|
committer | Lokesh Vutla <lokeshvutla@ti.com> | 2013-05-29 15:04:57 +0530 |
commit | 25051b53364c510dc24da274f180424a2a2dd27a (patch) | |
tree | aff11e605adba129d544038591cd1bbba67bbf56 | |
parent | 21d6e010f1de9453a8b6f31eaa1f46cab8490f30 (diff) | |
download | jacinto6evm-25051b53364c510dc24da274f180424a2a2dd27a.tar.gz |
ARM: DRA7xx: Correct SRAM END address
NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
-rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 7 | ||||
-rw-r--r-- | include/configs/dra7xx_evm.h | 3 | ||||
-rw-r--r-- | include/configs/omap5_uevm.h | 3 |
3 files changed, 6 insertions, 7 deletions
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index df8222aaf5..15d429f4f9 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -159,13 +159,6 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ -#define NON_SECURE_SRAM_START 0x40300000 -#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index b0b0bdacf6..fc35f2f9a8 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -42,4 +42,7 @@ /* Clock Defines */ #define V_OSCK 20000000 /* Clock output from T2 */ +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ + #endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 4f2d4253c7..96c5955b62 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -61,5 +61,8 @@ /* Clock Defines */ #define V_OSCK 19200000 /* Clock output from T2 */ +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ + #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 #endif /* __CONFIG_OMAP5_EVM_H */ |