diff options
author | Praneeth Bajjuri <praneeth@ti.com> | 2017-08-28 18:05:10 -0500 |
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committer | Praneeth Bajjuri <praneeth@ti.com> | 2017-08-28 18:05:10 -0500 |
commit | 897c50416cb47553fd149ae95ede41149ae8fbaa (patch) | |
tree | 862d462158291cbd41102d541554304ed42a4eaa /arch/arm/cpu/armv7/omap5/hw_data.c | |
parent | 28c2b55c045daa86413fe9fa73299b1d47564615 (diff) | |
parent | 50becb1a9d088359a55d6068a47ed3fc8605253c (diff) | |
download | jacinto6evm-6AM.1.3-rvc-video-j6e-aug.tar.gz |
Merge branch 'p-ti-u-boot-2016.05' of git://git.omapzoom.org/repo/u-boot into 6AM.1.3-rvc-video6AM.1.3-rvc-video-j6e-aug6AM.1.3-rvc-video
* 'p-ti-u-boot-2016.05' of git://git.omapzoom.org/repo/u-boot: (62 commits)
am57x: android: add vendor partition
arm: omap: enable high speed mode support in SPL for the eMMC on DRA76x
ARM: dts: dra76-evm: add higher speed MMC/SD modes
ARM: dts: dra76-evm: shift to using common IOdelay data
ARM: dts: dra76x: create a common file with MMC/SD IOdelay data
ARM: DRA72x: Add support for detection of DRA71x SR 2.1
dra7xx: android: add vendor partition
fastboot: sparse: remove session-id logic
ARM: dts: dra76-evm: Add initial support
ARM: dts: dra7-evm: sync DT with Linux
configs: ti_omap5_common: Select dtb name for dra76
board: ti: dra76-evm: Add support for powering on mmc ldo
board: ti: dra76-evm: Add the pinmux data
board: ti: dra76-evm: Add DDR data
board: ti: dra76-evm: Add the pmic data
board: ti: dra76-evm: Add epprom support
arm: dra76: Add support for ES1.0 detection
configs: dra7xx: Enable LP87565 related configs
power: regulator: palmas: Add smps12 dual regulator for tps65917
power: regulator: lp87565: add regulator support
...
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
-rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 105 |
1 files changed, 50 insertions, 55 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 0716f51931..06b0414469 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -28,17 +28,6 @@ struct vcores_data const **omap_vcores = struct omap_sys_ctrl_regs const **ctrl = (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; -/* OPP HIGH FREQUENCY for ES2.0 */ -static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { - {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - /* OPP NOM FREQUENCY for ES1.0 */ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -50,28 +39,6 @@ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -/* OPP LOW FREQUENCY for ES1.0 */ -static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { - {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* OPP LOW FREQUENCY for ES2.0 */ -static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { - {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -116,28 +83,6 @@ static const struct dpll_params {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ }; -static const struct dpll_params - core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { - {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */ - {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */ - {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = { - {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */ - {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */ - {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */ -}; - static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -168,6 +113,16 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ }; +static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = { + {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */ + {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */ + {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -188,6 +143,7 @@ static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ }; +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK /* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { @@ -199,11 +155,14 @@ static const struct dpll_params {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +#endif +#ifndef CONFIG_SYS_OMAP_ABE_SYSCK /* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = { 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 }; +#endif /* ABE M & N values with sysclk2(22.5792 MHz) as input */ static const struct dpll_params @@ -285,6 +244,17 @@ struct dplls omap5_dplls_es2 = { .ddr = NULL }; +struct dplls dra76x_dplls = { + .mpu = mpu_dpll_params_1ghz, + .core = core_dpll_params_2128mhz_dra7xx, + .per = per_dpll_params_768mhz_dra76x, + .abe = abe_dpll_params_sysclk2_361267khz, + .iva = iva_dpll_params_2330mhz_dra7xx, + .usb = usb_dpll_params_1920mhz, + .ddr = ddr_dpll_params_2664mhz, + .gmac = gmac_dpll_params_2000mhz, +}; + struct dplls dra7xx_dplls = { .mpu = mpu_dpll_params_1ghz, .core = core_dpll_params_2128mhz_dra7xx, @@ -336,6 +306,22 @@ struct pmic_data tps659038 = { .gpio_en = 0, }; +/* The LP87565*/ +struct pmic_data lp87565 = { + .base_offset = LP873X_BUCK_BASE_VOLT_UV, + .step = 5000, /* 5 mV represented in uV */ + /* + * Offset codes 0 - 0x13 Invalid. + * Offset codes 0x14 0x17 give 10mV steps + * Offset codes 0x17 through 0x9D give 5mV steps + * So let us start with our operating range from .73V + */ + .start_code = 0x17, + .i2c_slave_addr = 0x60, + .pmic_bus_init = gpi2c_init, + .pmic_write = palmas_i2c_write_u8, +}; + /* The LP8732 and LP8733 are software-compatible, use common struct */ struct pmic_data lp8733 = { .base_offset = LP873X_BUCK_BASE_VOLT_UV, @@ -753,6 +739,12 @@ void __weak hw_data_init(void) *ctrl = &omap5_ctrl; break; + case DRA762_ES1_0: + *prcm = &dra7xx_prcm; + *dplls_data = &dra76x_dplls; + *ctrl = &dra7xx_ctrl; + break; + case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: @@ -763,6 +755,7 @@ void __weak hw_data_init(void) case DRA722_ES1_0: case DRA722_ES2_0: + case DRA722_ES2_1: *prcm = &dra7xx_prcm; *dplls_data = &dra72x_dplls; *ctrl = &dra7xx_ctrl; @@ -791,12 +784,14 @@ void get_ioregs(const struct ctrl_ioregs **regs) case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: + case DRA762_ES1_0: *regs = &ioregs_dra7xx_es1; break; case DRA722_ES1_0: *regs = &ioregs_dra72x_es1; break; case DRA722_ES2_0: + case DRA722_ES2_1: *regs = &ioregs_dra72x_es2; break; |