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AgeCommit message (Expand)Author
2017-10-14AMDGPU: Bring HSA metadata on par with the specificationKonstantin Zhuravlyov
2017-10-14Pull out repeated calls to VT.getVectorNumElements(). NFCI.Simon Pilgrim
2017-10-14Use DAG::getBitcast() helper. NFCI.Simon Pilgrim
2017-10-14AMDGPU: Improve note directive verification in assemblerKonstantin Zhuravlyov
2017-10-14AMDGPU: Do not emit deprecated notes for code object v3Konstantin Zhuravlyov
2017-10-14AMDGPU: Add support for isa version noteKonstantin Zhuravlyov
2017-10-14[X86][SSE] Support combining AND(EXTRACT(SHUF(X)), C) -> EXTRACT(SHUF(X))Simon Pilgrim
2017-10-14[X86] Add patterns for vzmovl+cvtpd2dq/cvttpd2dq with a load.Craig Topper
2017-10-14[X86] Add AVX512 versions of VCVTPD2PS to load folding tables.Craig Topper
2017-10-14[X86] Add patterns for vzmovl+cvtpd2ps with a load.Craig Topper
2017-10-14[X86] Remove some patterns for bitcasted alignednonedtemporalloads.Craig Topper
2017-10-14[X86] Remove unnecessary bitconverts as the root of patterns for zero extende...Craig Topper
2017-10-14[X86] Add additional patterns for folding loads with 128-bit VCVTDQ2PD and VC...Craig Topper
2017-10-14[X86] Add AVX512 flavors of VCVTDQ2PD plus VCVTUDQ2PD to the load folding tab...Craig Topper
2017-10-14[X86] Remove TB_NO_REVERSE from VCVTDQ2PDYrr and VCVTPS2PDYrr in the load fol...Craig Topper
2017-10-14[X86] Add an additional isel pattern to CVTDQ2PDrm/VCVTDQ2PDrm to enable load...Craig Topper
2017-10-14Fix assembler for alloca of multiple elements in non-zero addr spaceYaxun Liu
2017-10-14[AArch64][RegisterBankInfo] Use the statically computed mappings for COPYQuentin Colombet
2017-10-13Revert r315763: "[Hexagon] Rangify some loops, NFC"Krzysztof Parzyszek
2017-10-13[X86] Use X86ISD::VBROADCAST in place of v2f64 X86ISD::MOVDDUP when AVX2 is a...Craig Topper
2017-10-13[Hexagon] Rangify some loops, NFCKrzysztof Parzyszek
2017-10-13[InstCombine] use m_Neg() to reduce code; NFCISanjay Patel
2017-10-13[globalisel][tablegen] Add support for fpimm and import of APInt/APFloat base...Daniel Sanders
2017-10-13[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings;...Eugene Zelenko
2017-10-13[RegisterBankInfo] Cache the getMinimalPhysRegClass informationQuentin Colombet
2017-10-13[Legalizer] Use SmallSetVector instead of SetVector.Quentin Colombet
2017-10-13[LegalizerInfo] Don't evaluate end boundary every time through the loopQuentin Colombet
2017-10-13[Legalizer] Only allocate the SetVectors once per function.Quentin Colombet
2017-10-13AMDGPU: Implement hasBitPreservingFPLogicMatt Arsenault
2017-10-13LowerTypeTests: Give imported symbols a type with size 0 so that they are not...Peter Collingbourne
2017-10-13[Hexagon] Avoid unused variable warnings in release builds.Benjamin Kramer
2017-10-13AMDGPU: Look for src mods before fp_extendMatt Arsenault
2017-10-13[aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 us...Daniel Sanders
2017-10-13[SmallPtrSet] Add iterator epoch tracking.Benjamin Kramer
2017-10-13[InstCombine] move code to remove repeated constant check; NFCISanjay Patel
2017-10-13AMDGPU: Implement isFPExtFoldableMatt Arsenault
2017-10-13[InstCombine] recycle adds for better efficiencySanjay Patel
2017-10-13DAG: Add opcode and source type to isFPExtFreeMatt Arsenault
2017-10-13[Hexagon] Minimize number of repeated constant extendersKrzysztof Parzyszek
2017-10-13[InstCombine] use local var to reduce code duplication; NFCISanjay Patel
2017-10-13[X86] Add initial skeleton support for knm cpuCraig Topper
2017-10-13[IPSCCP] Move common functions to ValueLatticeUtils (NFC)Matthew Simpson
2017-10-13[InstCombine] add hasOneUse check to add-zext-add fold to prevent increasing ...Sanjay Patel
2017-10-13[SCEV] Maintain and use a loop->loop invalidation dependencySanjoy Das
2017-10-13[InstCombine] use AddOne helper to reduce code; NFCSanjay Patel
2017-10-13[InstCombine] rearrange code to remove repeated constant check; NFCISanjay Patel
2017-10-13[InstCombine] allow zext(bool) + C --> select bool, C+1, C for vector typesSanjay Patel
2017-10-13[X86] Fix some inconsistent formatting in the processor feature lists.Craig Topper
2017-10-13[X86] Add ProcIntelBDW to BroadwellProc class not BDWFeatures class.Craig Topper
2017-10-13[RS4GC] Look through vector bitcasts when looking for base pointerDaniel Neilson
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